DS50003319C-13 Ethernet HDMI TX IP
HDMI TX IP Ta'iala mo Tagata Fa'aoga
Folasaga (Fai se Fesili)
O le Microchip's High-Definition Multimedia Interface (HDMI) transmitter IP e lagolagoina le faʻasalalauina o faʻamatalaga ata vitio ma leo o loʻo faʻamatalaina i le HDMI tulaga faʻapitoa.
O lo'o fa'aogaina e le HDMI le Transition Minimized Differential Signaling (TMDS) e fa'amanino lelei ai le tele o voluma o fa'amatalaga fa'afuainumera i luga o mamao mamao fa'alautele, fa'amautinoa le fa'asalalauina o fa'ailoga fa'afuainumera maualuga, fa'asologa, ma fa'atuatuaina. O se feso'ota'iga TMDS e aofia ai se alalaupapa uati e tasi ma laina fa'amaumauga e tolu. O le uati pika vitio o loʻo tuʻuina atu i luga o le alalaupapa TMDS uati, lea e fesoasoani e faʻamautu faʻailoga i le faʻamaopoopoina. O faʻamatalaga vitio o loʻo faʻaaogaina e pei o 24-bit pixels i luga o alalaupapa faʻamaumauga e tolu o le TMDS, lea e faʻavasegaina ai faʻamaumauga taʻitasi mo vaega lanu mumu, lanumeamata, ma le lanumoana. O fa'amaumauga fa'alogo o lo'o feavea'i e pei o 8-bit pepa i luga o le TMDS lanu meamata ma le lanu mumu.
TMDS encoder e mafai ai ona tuʻuina atu faʻamatalaga faʻasologa i se saoasaoa maualuga, aʻo faʻaitiitia le gafatia mo le Electro-magnetic Interference (EMI) i luga o uaea kopa e ala i le faʻaitiitia o le numera o suiga (faʻaitiitia le faʻalavelave i le va o alalaupapa), ma ausia le paleni Direct Current (DC), i luga o uaea. , e ala i le tausia o le numera o tasi ma zeros i luga o le laina toeitiiti tutusa.
HDMI TX IP ua mamanuina e faʻaoga faʻatasi ma PolarFire® SoC ma PolarFire masini transceivers. O le IP e fetaui ma HDMI 1.4 ma HDMI 2.0, lea e lagolagoina e oʻo atu i le 60 faʻavaa i le sekone, faʻatasi ai ma le bandwidth maualuga o le 18 Gbps. O le IP o loʻo faʻaogaina le TMDS encoder e faʻaliliuina ai le 8-bit faʻamatalaga vitio i le alalaupapa ma le pusa leo i le 10-bit DC-paleni, ma faʻaitiitia le suiga. Ona tu'uina atu lea fa'asolosolo ile fua ole 10-bits ile pika, ile alalaupapa. I le taimi o le fa'aogaina o ata vitio, e fa'asalalau fa'ailoga fa'atonu. O nei faʻailoga e faʻavaeina i luga o faʻailoga hsync ma vsync. I le vaitaimi o motu fa'amatalaga, o le pa'u leo e tu'uina atu e pei o 10-bit pepa i luga o le ala mumu ma le lanu meamata.
Fa'aoga Taiala
DS50003319C – 1
© 2024 Microchip Technology Inc. ma ona lala
Aotelega
O le laulau o loʻo i lalo o loʻo tuʻuina atu ai se aotelega o uiga HDMI TX IP.
Laulau 1. HDMI TX IP uiga
|
Autu Version |
O lenei taiala fa'aoga e lagolagoina le HDMI TX IP v5.2.0 |
|
Lagolagoina Aiga masini |
• PolarFire® SoC • PolarFire |
|
Lagolago Meafaigaluega tafe |
Manaomia Libero® SoC v11.4 po'o fa'asalalauga mulimuli ane |
|
Lagolagoina Fa'afeso'ota'i |
Interfaces e lagolagoina e le HDMI TX IP o: • AXI4-Amata - O lenei autu e lagolagoina le AXI4-Stream i ports ulufale. A fa'atulagaina i lenei faiga, e ave e IP le AXI4 Stream fa'ailoga masani fa'asea e fai ma fa'aoga. • AXI4-Lite Configuration Interface - O lenei Core e lagolagoina le AXI4-Lite fetuutuunaiga faʻaoga mo le 4Kp60 manaʻoga. I lenei faiga, o fa'aoga IP e sau mai le SoftConsole. • Tagatanuu - Pe a faʻatulagaina i lenei faiga, e ave e le IP le ata vitio ma faʻalogo leo e fai ma faʻaoga. |
|
Laisene |
HDMI TX IP o loʻo tuʻuina atu ma avanoa laisene e lua: • Fa'ailoga: O loʻo tuʻuina atu le faʻailoga faʻailoga RTL atoa mo le autu. E avanoa mo le leai o se totogi ma soʻo se laisene Libero, e mafai ai ona faʻapipiʻi le autu ma SmartDesign. E mafai ona e faia le Simulation, Synthesis, Layout, ma polokalame le FPGA silicon e faʻaaoga ai le Libero design suite. • RTL: O le RTL source code atoa o lo'o loka laisene, lea e mana'omia ona fa'atau eseese. |
Vaega
HDMI TX IP o loʻo i ai uiga nei:
• E fetaui mo HDMI 2.0 ma le 1.4b
• Lagolagoina le tasi pe fa fa'ailoga/piksel i le uati
• Lagolago i iugafono e oo atu ile 3840 x 2160 ile 60 fps
• Lagolago 8, 10, 12, ma le 16-bit le loloto o lanu
• Lagolagoina faatulagaga lanu e pei o le RGB, YUV 4:2:2, ma le YUV 4:4:4
• Lagolago leo e oo atu i le 32 auala
• Lagolagoina Fa'ailoga Fa'ailoga - TMDS
• Lagolagoina Native ma le AXI4 Stream Vitio ma Audio Fa'amatalaga fa'amatalaga
• Lagolagoina le Native ma le AXI4-Lite Configuration interface mo le suiga o parakalafa
Fa'atonuga fa'apipi'i
O le IP autu e tatau ona faʻapipiʻi i le IP Catalog of Libero® SoC software e otometi lava e ala i le IP Catalog update function i le Libero SoC software, pe sii mai ma le lima mai le lisi. O le taimi lava e faʻapipiʻi ai le IP core i le Libero SoC software IP Catalog, e faʻapipiʻiina, faʻatupuina, ma faʻapipiʻiina i totonu o SmartDesign mo le faʻaofiina i totonu o le poloketi Libero.
Fa'aoga Taiala
DS50003319C – 2
© 2024 Microchip Technology Inc. ma ona lala
Fa'aaogaina o Punaoa (Fai se Fesili)
HDMI TX IP o loʻo faʻatinoina i PolarFire® FPGA (MPF300T – 1FCG1152I Package).
Ole siata o lo'o i lalo o lo'o lisiina ai punaoa fa'aaogaina pe a g_PIXELS_PER_CLK = 1PXL.
Laulau 2. Fa'aogaina o Punaoa mo le 1PXL
|
|
g_COLOR_FORMAT g_BITS_PER_COMPONENT (Bits) |
g_AUX_CHANNEL_ENABLE g_4K60_SUPPORT Ie |
|
4LUT |
ie DFF |
Fa'aoga 4LUT |
Fa'aoga DFF |
uSRAM (64×12) |
|
RGB |
8 |
Fa'amalo |
Fa'agata |
787 |
514 |
108 |
108 |
9 |
|
Fa'agata |
Fa'agata |
819 |
502 |
108 |
108 |
9 |
||
|
10 |
Fa'agata |
Fa'agata |
1070 |
849 |
156 |
156 |
13 |
|
|
12 |
Fa'agata |
Fa'agata |
1084 |
837 |
156 |
156 |
13 |
|
|
16 |
Fa'agata |
Fa'agata |
1058 |
846 |
156 |
156 |
13 |
|
|
YCbCr422 |
8 |
Fa'agata |
Fa'agata |
696 |
473 |
96 |
96 |
8 |
|
YCbCr444 |
8 |
Fa'agata |
Fa'agata |
819 |
513 |
108 |
108 |
9 |
|
10 |
Fa'agata |
Fa'agata |
1068 |
849 |
156 |
156 |
13 |
|
|
12 |
Fa'agata |
Fa'agata |
1017 |
837 |
156 |
156 |
13 |
|
|
16 |
Fa'agata |
Fa'agata |
1050 |
845 |
156 |
156 |
13 |
Ole siata o lo'o i lalo o lo'o lisiina ai punaoa fa'aaogaina pe a g_PIXELS_PER_CLK = 4PXL.
Laulau 3. Fa'aogaina o Punaoa mo le 4PXL
|
|
g_COLOR_FORMAT g_BITS_PER_COMPONENT (Bits) |
g_AUX_CHANNEL_ENABLE g_4K60_SUPPORT Ie |
|
4LUT |
ie DFF |
Fa'aoga 4LUT |
Fa'aoga DFF |
uSRAM (64×12) |
|
RGB |
8 |
Fa'agata |
Fa'amalo |
4078 |
2032 |
144 |
144 |
12 |
|
Fa'amalo |
Fa'agata |
1475 |
2269 |
144 |
144 |
12 |
||
|
Fa'agata |
Fa'agata |
1393 |
1092 |
144 |
144 |
12 |
||
|
10 |
Fa'agata |
Fa'agata |
2151 |
1635 |
264 |
264 |
22 |
|
|
12 |
Fa'agata |
Fa'agata |
1909 |
1593 |
264 |
264 |
22 |
|
|
16 |
Fa'agata |
Fa'agata |
1645 |
1284 |
264 |
264 |
22 |
|
|
YCbCr422 |
8 |
Fa'agata |
Fa'agata |
1265 |
922 |
144 |
144 |
12 |
|
YCbCr444 |
8 |
Fa'agata |
Fa'agata |
1119 |
811 |
144 |
144 |
12 |
|
10 |
Fa'agata |
Fa'agata |
2000 |
1627 |
264 |
264 |
22 |
|
|
12 |
Fa'agata |
Fa'agata |
1909 |
1585 |
264 |
264 |
22 |
|
|
16 |
Fa'agata |
Fa'agata |
1604 |
1268 |
264 |
264 |
22 |
Fa'aoga Taiala
DS50003319C – 3
© 2024 Microchip Technology Inc. ma ona lala
HDMI TX IP Configurator
1. HDMI TX IP Configurator (Fai se Fesili)
O lenei vaega o loʻo tuʻuina atu se faʻaopoopogaview o le HDMI TX Configurator interface ma ona vaega eseese.
O le HDMI TX Configurator e tuʻuina atu se faʻataʻitaʻiga faʻataʻitaʻiga e faʻatutu ai le HDMI TX autu mo manaʻoga faʻasalalauga faʻapitoa. O lenei configurator e mafai ai e le tagata faʻaoga ona filifili faʻamaufaʻailoga e pei ole Bits Per Component, Color Form, Number of Pixels, Audio Mode, Interface, Testbench, ma Laisene. E taua tele le fetuutuuna'i sa'o o nei fa'atulagaga ina ia mautinoa le lelei o le tu'uina atu o fa'amatalaga vitio i luga ole HDMI.
O le atina'e o le HDMI TX Configurator e aofia ai lisi fa'alalo ma filifiliga e mafai ai e tagata fa'aoga ona fa'avasega le fa'aogaina o le HDMI. O fetuutuunaiga autu o loʻo faʻamatalaina i totonu Laulau 3-1.
O le ata o loʻo i lalo o loʻo tuʻuina mai ai se auiliiliga view ole fa'aoga HDMI TX Configurator.
Ata 1-1. HDMI TX IP Configurator
O lo'o iai fo'i i le fa'aoga fa'amau o OK ma Fa'aleaogaina mo le fa'amaonia po'o le lafoa'iina o fa'atonuga na faia.
Fa'aoga Taiala
DS50003319C – 5
© 2024 Microchip Technology Inc. ma ona lala
Fa'atinoga o Meafaigaluega
2. Fa'atinoga o Meafaigaluega (Fai se Fesili)
HDMI Transmitter (TX) e aofia ai le lua stage:
• Ose fa'agaioiga XOR/XNOR, e fa'aitiitia ai le aofa'i o suiga
• Se INV/NONINV, e fa'aiti'itia ai le va'aiga (paleni DC). O isi pito e lua ua fa'aopoopoina i lenei stagu o le faagaoioiga. Fa'atonuga fa'amaumauga (hsync ma vsync) o lo'o fa'ailogaina i le 10 bits i fa'apotopotoga e fa e mafai ai ona fesoasoani i le tagata e talia fa'atasi lana uati ma le uati transmitter. E tatau ona fa'aoga se transceiver fa'atasi ma le HDMI TX IP e fa'avasega ai le 10 bits (1 pixel mode) po'o le 40 bits (4 pixels mode).
O loʻo faʻaalia foʻi e le tagata faʻapipiʻi se faʻataʻitaʻiga o le HDMI Tx core, faʻaigoaina HDMI_TX_0, e faʻaalia ai le tele o fesoʻotaʻiga ma fesoʻotaʻiga e fesoʻotaʻi ma le autu. E tolu auala mo le HDMI TX interface ma o loʻo faʻamatalaina faʻapea:
Faiga Fa'asologa o Lanu RGB
O ports o HDMI TX IP mo le tasi pika i le uati pe a mafai le faʻalogo leo ma le lanu lanu o le RGB mo PolarFire® masini o lo'o fa'aalia i le ata o lo'o i lalo. O se ata vaaia o ports o le HDMI Tx core e pei ona taua i lalo:
• O fa'ailoga uati fa'atonutonu o le R_CLK_LOCK, G_CLK_LOCK, ma le B_CLK_LOCK. O faailoilo o le Uati o le R_CLK_I, G_CLK_I, ma le B_CLK_I.
• Fa'amatalaga auala e aofia ai DATA_R_I, DATA_G_I, ma DATA_B_I.
• Fa'ailoga Fesoasoani o AUX_DATA_R_I ma AUX_DATA_G_I.
Ata 2-1. HDMI TX IP Block Ata (RGB Lanu Fa'asologa)
Mo nisi fa'amatalaga e uiga i fa'ailoga I/O mo le fa'atulagaina o lanu RGB, va'ai Laulau 3-2.
YCbCr444 Lanu Fa'asologa Fa'asologa
O ports o HDMI TX IP mo le tasi pika i le uati pe a mafai le faʻalogo leo ma le lanu lanu o le YCbCr444 o loʻo faʻaalia i le ata o loʻo i lalo. O se ata vaaia o ports o le HDMI Tx core e pei ona taua i lalo:
• O faailoilo fa'atonutonu o Y_CLK_LOCK, Cb_CLK_LOCK, ma Cr_CLK_LOCK.
• O faailoilo o le Uati o Y_CLK_I, Cb_CLK_I, ma Cr_CLK_I.
Fa'aoga Taiala
DS50003319C – 6
© 2024 Microchip Technology Inc. ma ona lala
Fa'atinoga o Meafaigaluega
• Fa'amatalaga auala e aofia ai DATA_Y_I, DATA_Cb_I, ma DATA_Cr_I.
• Fa'ailo fa'aoga o Fa'amatalaga Fesoasoani o AUX_DATA_Y_I ma AUX_DATA_C_I.
Ata 2-2. HDMI TX IP Poloka Ata (YCbCr444 Fa'asologa Lanu)
Mo nisi fa'amatalaga e uiga i fa'ailoga I/O mo YCbCr444 fa'asologa lanu, va'ai Laulau 3-6. YCbCr422 Lanu Fa'asologa Fa'asologa
O ports o HDMI TX IP mo le tasi pika i le uati pe a mafai le faʻalogo leo ma le lanu lanu o le YCbCr422 o loʻo faʻaalia i le ata o loʻo i lalo. O se ata vaaia o ports o le HDMI Tx core e pei ona taua i lalo:
• Fa'ailoga fa'atonutonu o LANE1_CLK_LOCK, LANE2_CLK_LOCK, ma LANE3_CLK_LOCK. • O faailo o le Uati o LANE1_CLK_I, LANE2_CLK_I, ma LANE3_CLK_I.
• Fa'amatalaga auala e aofia ai DATA_Y_I ma DATA_C_I.
Fa'aoga Taiala
DS50003319C – 7
© 2024 Microchip Technology Inc. ma ona lala
Fa'atinoga o Meafaigaluega
Ata 2-3. HDMI TX IP Poloka Ata (YCbCr422 Fa'asologa Lanu)
Mo nisi fa'amatalaga e uiga i fa'ailoga I/O mo YCbCr422 fa'asologa lanu, va'ai Laulau 3-7 Fa'aoga Taiala
DS50003319C – 8
© 2024 Microchip Technology Inc. ma ona lala
HDMI TX Parameters ma Fa'ailoga Fa'amatalaga
3. HDMI TX Parameters ma Fa'ailoga Fa'amatalaga (Fai se Fesili)
O lenei vaega o loʻo talanoaina ai faʻamaufaʻailoga i le HDMI TX GUI configurator ma faʻailoga I/O. 3.1 Fa'atutuga Parata (Fai se Fesili)
O le laulau o loʻo i lalo o loʻo lisiina ai faʻamaufaʻailoga i le HDMI TX IP.
Laulau 3-1. Fa'atutuga Parata
|
Igoa Parameter |
Fa'amatalaga |
|
Fa'ailoga lanu |
Fa'amatala le avanoa lanu. Lagolagoina fa'asologa lanu nei: • RGB • YCbCr422 • YCbCr444 |
|
Numera o biti i le vaega |
Fa'ailoa mai le aofa'i o pa'u ile vaega lanu. Lagolago 8, 10, 12, ma 16 bits i vaega taitasi. |
|
Numera o Pixel |
Fa'ailoa le aofa'i o pika ile fa'aulu ile uati: • Piki ile uati = 1 • Piki ile uati = 4 |
|
4Kp60 Lagolago |
Lagolago mo le 4K iugafono ile 60 fa'avaa ile sekone: • A mafai le lagolago 1, 4Kp60 • Pe a 0, 4Kp60 lagolago ua le atoatoa |
|
Faʻalogo Audio |
Fa'atonu le faiga fa'asalalau leo. Fa'amatalaga fa'alogo mo le ala R ma le G: • Fa'aaga • Fa'aletonu |
|
Fa'afeso'ota'i |
Native ma AXI stream |
|
Su'ega Su'ega |
Fa'ataga le filifiliga o se siosiomaga su'esu'e. Lagolagoina filifiliga o lo'o i lalo: • Tagata fa'aoga • Leai |
|
Laisene |
Fa'ailoa mai le ituaiga laisene. Tuuina atu avanoa laisene e lua: • RTL • Fa'ailoga |
3.2 Taulaga (Fai se Fesili)
O le laulau o lo'o i lalo o lo'o lisiina ai ports o lo'o tu'uina atu ma fa'aulufalega o le HDMI TX IP mo le fa'aoga Fa'a-Native pe a fa'agaoioi le fa'alogo leo ma le lanu o le RGB.
Laulau 3-2. Fa'ailoga Ulufale ma Fa'ailoga
|
Igoa Faailoga |
Fa'atonuga |
Lautele |
Fa'amatalaga |
|
SYS_CLK_I |
Ulufale |
1-bit |
Uati faiga, e masani lava o le uati tutusa ma le fa'aaliga fa'atonu |
|
RESET_N_I |
Ulufale |
1-bit |
Asynchronous active-low reset signal |
|
VIDEO_DATA_VALID_I |
Ulufale |
1-bit |
Fa'amatalaga vitiō fa'aoga aoga |
|
AUDIO_DATA_VALID_I |
Ulufale |
1-bit |
Fa'amatalaga fa'amatalaga fa'alogo fa'aoga aoga |
|
R_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "R" mai le XCVR |
|
R_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo R alalaupapa mai le XCVR |
|
G_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "G" mai XCVR |
|
G_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo le ala G mai le XCVR |
|
B_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "B" mai le XCVR |
Fa'aoga Taiala
DS50003319C – 9
© 2024 Microchip Technology Inc. ma ona lala
HDMI TX Parameters ma Fa'ailoga Fa'amatalaga
|
………..faaauau Fa'ailoga Igoa Fa'asinoga Lautele Fa'amatalaga |
|||
|
B_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo ala B mai le XCVR |
|
H_SYNC_I |
Ulufale |
1-bit |
Fa'asa'o fa'asaga i pulupulu |
|
V_SYNC_I |
Ulufale |
1-bit |
Pusa fa'atasi tu'usa'o |
|
PACKET_HEADER_I |
Ulufale |
PIXELS_PER_CLK*1 |
Ulutala pusa mo faʻamatalaga pusa leo |
|
DATA_R_I |
Ulufale |
PIXELS_PER_CLK*8 |
Fa'aulu fa'amaumauga "R". |
|
DATA_G_I |
Ulufale |
PIXELS_PER_CLK*8 |
Tu'u fa'amaumauga "G". |
|
DATA_B_I |
Ulufale |
PIXELS_PER_CLK*8 |
Tu'u fa'amaumauga "B". |
|
AUX_DATA_R_I |
Ulufale |
PIXELS_PER_CLK*4 |
Fa'amatalaga alaala o le paketi leo "R". |
|
AUX_DATA_G_I |
Ulufale |
PIXELS_PER_CLK*4 |
Fa'amatalaga alaala o le pusa leo "G". |
|
TMDS_R_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "R" fa'amaumauga |
|
TMDS_G_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "G" fa'amaumauga |
|
TMDS_B_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "B" fa'amaumauga |
O le laulau o lo'o i lalo o lo'o lisiina ai ports mo le AXI4 Stream interface ma le Audio Enable.
Laulau 3-3. Ulufale ma Taulaga Fa'aulu mo le AXI4 Stream Interface
|
Ituaiga Igoa o le Taulaga |
|
Lautele |
Fa'amatalaga |
|
TDATA_I |
Ulufale |
3*g_BITS_PER_COMPONENT*g_PIXELS_PER_CLK Fa'atumu fa'amatalaga vitiō |
|
|
TVALID_I |
Ulufale |
1-bit |
Fa'aoga vitio aoga |
|
TREADY_O Fa'asologa 1-bit |
|
|
Fa'ailoga ua sauni le pologa |
|
TUSER_I |
Ulufale |
PIXELS_PER_CLK*9 + 5 |
bit 0 = le fa'aaogaina bit 1 = VSYNC bit 2 = HSYNC bit 3 = le fa'aaogaina fasi [3 + g_PIXELS_PER_CLK: 4] = Fa'aulu ulutala fasi [4 + g_PIXELS_PER_CLK] = Fa'amatalaga fa'alogo e aoga bit [(5 * g_PIXELS_PER_CLK) + 4: (1*g_PIXELS_PER_CLK) + 5] = Fa'amatalaga G Audio bit [(9 * g_PIXELS_PER_CLK) + 4: (5*g_PIXELS_PER_CLK) + 5] = Fa'amatalaga R Audio |
O le laulau o lo'o i lalo o lo'o lisi ai ports o lo'o tu'uina atu ma fa'aulufalega o le HDMI TX IP mo le fa'aoga Fa'a-Native pe a fa'aletonu le fa'alogo.
Laulau 3-4. Fa'ailoga Ulufale ma Fa'ailoga
|
Igoa Faailoga |
Fa'atonuga |
Lautele |
Fa'amatalaga |
|
SYS_CLK_I |
Ulufale |
1-bit |
Uati faiga, e masani lava o le uati tutusa ma le fa'aaliga fa'atonu |
|
RESET_N_I |
Ulufale |
1-bit |
Asynchronous malosi -maualalo toe seti faailoilo |
|
VIDEO_DATA_VALID_I |
Ulufale |
1-bit |
Fa'amatalaga vitiō fa'aoga aoga |
|
R_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "R" mai le XCVR |
|
R_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo R alalaupapa mai le XCVR |
|
G_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "G" mai XCVR |
|
G_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo le ala G mai le XCVR |
|
B_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "B" mai le XCVR |
|
B_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo ala B mai le XCVR |
|
H_SYNC_I |
Ulufale |
1-bit |
Fa'asa'o fa'asaga i pulupulu |
|
V_SYNC_I |
Ulufale |
1-bit |
Pusa fa'atasi tu'usa'o |
|
DATA_R_I |
Ulufale |
PIXELS_PER_CLK*8 |
Fa'aulu fa'amaumauga "R". |
Fa'aoga Taiala
DS50003319C – 10
© 2024 Microchip Technology Inc. ma ona lala
HDMI TX Parameters ma Fa'ailoga Fa'amatalaga
|
………..faaauau Fa'ailoga Igoa Fa'asinoga Lautele Fa'amatalaga |
|||
|
DATA_G_I |
Ulufale |
PIXELS_PER_CLK*8 |
Tu'u fa'amaumauga "G". |
|
DATA_B_I |
Ulufale |
PIXELS_PER_CLK*8 |
Tu'u fa'amaumauga "B". |
|
TMDS_R_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "R" fa'amaumauga |
|
TMDS_G_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "G" fa'amaumauga |
|
TMDS_B_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "B" fa'amaumauga |
O le laulau o loʻo i lalo o loʻo lisiina ai ports mo le AXI4 Stream interface.
Laulau 3-5. Ulufale ma Taulaga Fa'aulu mo le AXI4 Stream Interface
|
Igoa o le Taulaga |
Ituaiga |
Lautele |
Fa'amatalaga |
|
TDATA_I_VIDEO |
Ulufale |
3*g_BITS_PER_COMPONENT*g_PIXELS_PER_CLK |
Fa'aofi fa'amaumauga vitiō |
|
TVALID_I_VIDEO |
Ulufale |
1-bit |
Fa'aoga vitio aoga |
|
TREADY_O_VIDEO |
Tuuina atu |
1-bit |
Fa'ailoga ua sauni le pologa |
|
TUSER_I_VIDEO |
Ulufale |
4 pito |
bit 0 = le fa'aaogaina bit 1 = VSYNC bit 2 = HSYNC bit 3 = le fa'aaogaina |
O le laulau o lo'o i lalo o lo'o lisiina ai ports mo le YCbCr444 mode pe a fa'aogaina le leo.
Laulau 3-6. Ulufale ma Fa'aulufalega mo le YCbCr444 Faiga ma Fa'alogo leo Fa'aagaoioi
|
Igoa Faailoga |
Itulau Lautele |
|
Fa'amatalaga |
|
SYS_CLK_I |
Ulufale |
1-bit |
Uati faiga, e masani lava o le uati tutusa ma le fa'aaliga fa'atonu |
|
RESET_N_I |
Ulufale |
1-bit |
Asynchronous active-low reset signal |
|
VIDEO_DATA_VALID_I Ulufale |
|
1-bit |
Fa'amatalaga vitiō fa'aoga aoga |
|
AUDIO_DATA_VALID_I Ulufale |
|
1-bit |
Fa'amatalaga fa'amatalaga fa'alogo fa'aoga aoga |
|
Y_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "Y" mai le XCVR |
|
Y_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo Y alaala mai le XCVR |
|
Cb_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "Cb" mai XCVR |
|
Cb_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo Cb alaala mai le XCVR |
|
Cr_CLK_I |
Ulufale |
1-bit |
Uati TX mo le ala "Cr" mai XCVR |
|
Cr_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo Cr alavai mai le XCVR |
|
H_SYNC_I |
Ulufale |
1-bit |
Fa'asa'o fa'asaga i pulupulu |
|
V_SYNC_I |
Ulufale |
1-bit |
Pusa fa'atasi tu'usa'o |
|
PACKET_HEADER_I |
Ulufale |
PIXELS_PER_CLK*1 |
Ulutala pusa mo faʻamatalaga pusa leo |
|
FA'AMATALAGA_Y_I |
Ulufale |
PIXELS_PER_CLK*8 |
Tu'u fa'amaumauga "Y". |
|
DATA_Cb_I |
Ulufale |
PIXELS_PER_CLK*DATA_WIDTH Ulufale “Cb” fa'amaumauga |
|
|
DATA_Cr_I |
Ulufale |
PIXELS_PER_CLK*DATA_WIDTH Ulufale “Cr” fa'amaumauga |
|
|
AUX_DATA_Y_I |
Ulufale |
PIXELS_PER_CLK*4 |
Fa'amatalaga o alalaupapa leo "Y". |
|
AUX_DATA_C_I |
Ulufale |
PIXELS_PER_CLK*4 |
Fa'amatalaga alaala o le paketi leo "C". |
|
TMDS_R_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "Cb" fa'amaumauga |
|
TMDS_G_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "Y" fa'amaumauga |
|
TMDS_B_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "Cr" fa'amaumauga |
O le laulau o lo'o i lalo o lo'o lisiina ai ports mo le YCbCr422 mode pe a fa'aogaina le leo.
Fa'aoga Taiala
DS50003319C – 11
© 2024 Microchip Technology Inc. ma ona lala
HDMI TX Parameters ma Fa'ailoga Fa'amatalaga
Laulau 3-7. Ulufale ma Fa'aulufalega mo le YCbCr422 Faiga ma Fa'alogo leo Fa'aagaoioi
|
Igoa Faailoga |
Itulau Lautele |
|
Fa'amatalaga |
|
SYS_CLK_I |
Ulufale |
1-bit |
Uati faiga, e masani lava o le uati tutusa ma le fa'aaliga fa'atonu |
|
RESET_N_I |
Ulufale |
1-bit |
Asynchronous Active-Low reset signal |
|
VIDEO_DATA_VALID_I Ulufale |
|
1-bit |
Fa'amatalaga vitiō fa'aoga aoga |
|
LANE1_CLK_I |
Ulufale |
1-bit |
Uati TX mo le "lane mai le XCVE lane 1" auala mai le XCVR |
|
LANE1_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo le laina mai le XCVE laina 1 |
|
LANE2_CLK_I |
Ulufale |
1-bit |
Uati TX mo le "lane mai le XCVE lane 2" auala mai le XCVR |
|
LANE2_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo le laina mai le XCVE laina 2 |
|
LANE3_CLK_I |
Ulufale |
1-bit |
Uati TX mo le "lane mai le XCVE lane 3" auala mai le XCVR |
|
LANE3_CLK_LOCK |
Ulufale |
1-bit |
TX_CLK_STABLE mo le laina mai le XCVE laina 3 |
|
H_SYNC_I |
Ulufale |
1-bit |
Fa'asa'o fa'asaga i pulupulu |
|
V_SYNC_I |
Ulufale |
1-bit |
Pusa fa'atasi tu'usa'o |
|
PACKET_HEADER_I |
Ulufale |
PIXELS_PER_CLK*1 |
Ulutala pusa mo faʻamatalaga pusa leo |
|
FA'AMATALAGA_Y_I |
Ulufale |
PIXELS_PER_CLK*DATA_WIDTH Ulufale “Y” fa'amaumauga |
|
|
DATA_C_I |
Ulufale |
PIXELS_PER_CLK*DATA_WIDTH Ulufale “C” fa'amaumauga |
|
|
AUX_DATA_Y_I |
Ulufale |
PIXELS_PER_CLK*4 |
Fa'amatalaga o alalaupapa leo "Y". |
|
AUX_DATA_C_I |
Ulufale |
PIXELS_PER_CLK*4 |
Fa'amatalaga alaala o le paketi leo "C". |
|
TMDS_R_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "C" fa'amaumauga |
|
TMDS_G_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga "Y" fa'amaumauga |
|
TMDS_B_O |
Tuuina atu |
PIXELS_PER_CLK*10 |
Fa'ailoga fa'ailoga e feso'ota'i ma fa'amatalaga sync |
Fa'aoga Taiala
DS50003319C – 12
© 2024 Microchip Technology Inc. ma ona lala
Resitala Fa'afanua ma Fa'amatalaga
4. Resitala Fa'afanua ma Fa'amatalaga (Fai se Fesili)
|
Offset |
Igoa |
Bit Pos. |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x00 |
SCRAMBLER_IP_EN |
7:0 |
|
|
|
|
|
|
|
AMATA |
|
15:8 |
|
|
|
|
|
|
|
|
||
|
23:16 |
|
|
|
|
|
|
|
|
||
|
31:24 |
|
|
|
|
|
|
|
|
||
|
0x04 |
XCVR_DATA_LANE_ 0_SEL |
7:0 |
|
|
|
|
|
|
AMATA[1:0] |
|
|
15:8 |
|
|
|
|
|
|
|
|
||
|
23:16 |
|
|
|
|
|
|
|
|
||
|
31:24 |
|
|
|
|
|
|
|
|
||
Fa'aoga Taiala
DS50003319C – 13
© 2024 Microchip Technology Inc. ma ona lala
Resitala Fa'afanua ma Fa'amatalaga
4.1 SCRAMBLER_IP_EN (Fai se Fesili)
Igoa: SCRAMBLER_IP_EN
Offset: 0x000
Toe setiina: 0x0
Meatotino: Tusi-na'o
Scrambler Enable Control Register. O lenei tusi resitala e tatau ona tusia e maua ai le 4kp60 Lagolago mo le HDMI TX IP
Bit 31 30 29 28 27 26 25 24
Avanoa
Toe setiina
Bit 23 22 21 20 19 18 17 16
Avanoa
Toe setiina
Bit 15 14 13 12 11 10 9 8
Avanoa
Toe setiina
Bit 7 6 5 4 3 2 1 0
|
|
|
|
|
|
|
|
AMATA |
Avanoa W Toe setiina 0
Bit 0 – AMATA Tusia le “1” i le vaega lea e amata ai le fa'aliliuina o fa'amatalaga Scrambler ua mafai. O le HDMI 2.0 o lo'o fa'aaogaina se ituaiga o su'ega e ta'ua o le 8b/10b encoding. O lenei faiga fa'ailoga e fa'aogaina e tu'uina atu fa'amatalaga i luga o le fa'aoga HDMI ma le fa'atuatuaina ma le lelei.
Fa'aoga Taiala
DS50003319C – 14
© 2024 Microchip Technology Inc. ma ona lala
Resitala Fa'afanua ma Fa'amatalaga
4.2 XCVR_DATA_LANE_0_SEL (Fai se Fesili)
Igoa: XCVR_DATA_LANE_0_SEL
Offset: 0x004
Toe setiina: 0x1
Meatotino: Tusi-na'o
XCVR_DATA_LANE_0_SEL resitala filifilia le faʻamatalaga e manaʻomia e faʻafeiloaʻi i le XCVR mai HDMI TX IP mo le mauaina o le uati mo Full HD, 4kp30, 4kp60.
Bit 31 30 29 28 27 26 25 24
|
|
|
|
|
|
|
|
|
Avanoa
Toe setiina
Bit 23 22 21 20 19 18 17 16
|
|
|
|
|
|
|
|
|
Avanoa
Toe setiina
Bit 15 14 13 12 11 10 9 8
|
|
|
|
|
|
|
|
|
Avanoa
Toe setiina
Bit 7 6 5 4 3 2 1 0
|
|
|
|
|
|
|
AMATA[1:0] |
Avanoa WW Toe Seti 0 1
Bits 1:0 – AMATA[1:0] O le tusiaina o le “10” i ia vaega e amata ai le 4KP60 ua mafai ma o le XCVR data-rate ua tuuina atu o le FFFFF_00000.
Fa'aoga Taiala
DS50003319C – 15
© 2024 Microchip Technology Inc. ma ona lala
Testbench Simulation
5. Testbench Simulation (Fai se Fesili)
Ua tuʻuina atu le Testbench e siaki ai le faʻatinoga o le HDMI TX autu. O le Testbench e galue na'o le atina'e fa'ale-aganu'u ma le 1 pika i le uati ma fa'aoga leo.
O le laulau o loʻo i lalo o loʻo lisiina ai faʻasologa o loʻo faʻatulagaina e tusa ai ma le talosaga.
Laulau 5-1. Testbench Parameter Configuration
|
Igoa |
Fa'ailoga Fa'atonu |
|
Fa'ailoga lanu (g_COLOR_FORMAT) |
RGB |
|
Biti i le vaega (g_BITS_PER_COMPONENT) |
8 |
|
Numera o Piki (g_PIXELS_PER_CLK) |
1 |
|
4Kp60 Lagolago (g_4K60_SUPPORT) |
0 |
|
Faiga Fa'alogo (g_AUX_CHANNEL_ENABLE) |
1 (Fa'aaga) |
|
Fa'amatalaga (G_FORMAT) |
0 (Tape) |
Ina ia faʻataʻitaʻiina le autu e faʻaaoga ai le testbench, fai laasaga nei:
1. I le fa'amalama o le Fuafuaga Fuafuaga, fa'alautele le Fausiaina o Fuafuaga.
2. Kiliki taumatau Fausia SmartDesign Testbench, ona kiliki lea o le Run, e pei ona faʻaalia i le ata o loʻo i lalo. Ata 5-1. Fausia SmartDesign Testbench
3. Ulufale se igoa mo le SmartDesign testbench, ona kiliki lea o le OK.
Ata 5-2. Fa'aigoa SmartDesign Testbench
SmartDesign testbench ua faia, ma o se tapoleni e aliali i le itu taumatau o le Design Flow pane.
Fa'aoga Taiala
DS50003319C – 16
© 2024 Microchip Technology Inc. ma ona lala
Testbench Simulation
4. Fa'asaga i Libero® SoC Catalog, filifili View > Pupuni > IP Catalog, ona fa'alautele lea o Fofo Vitio. Kiliki faalua HDMI TX IP (v5.2.0), ona kiliki lea o le OK.
5. I le faamalama Parameter Configurator, filifili le numera manaʻomia o Pixels tau, e pei ona faʻaalia i le ata o loʻo i lalo.
Ata 5-3. Fa'atulagaina o Parameter
6. Filifili uma ports, kiliki-matau ma filifili Promote to Top Level.
7. I luga o le SmartDesign toolbar, kiliki Fausia Vaega.
8. I luga o le Stimulus Hierarchy tab, kiliki-matau HDMI_TX_TB testbench file, ona kiliki lea Simulate Pre-Synth Design > Open Interactively.
Le ModelSim® e tatala le meafaigaluega i le suʻega, e pei ona faʻaalia i le ata o loʻo i lalo. Ata 5-4. ModelSim Tool ma HDMI TX Testbench File
Taua: Afai e faʻalavelaveina le faʻataʻitaʻiga ona o le taimi faʻatapulaʻa taʻavale ua faʻamaonia i le DO file, fa'aaoga le tamoe -uma poloaiga e faʻamaeʻa le faʻataʻitaʻiga.
Fa'aoga Taiala
DS50003319C – 17
© 2024 Microchip Technology Inc. ma ona lala
Testbench Simulation
5.1 Ata o Taimi (Fai se Fesili)
O le ata o loʻo mulimuli mai mo le HDMI TX IP o loʻo faʻaalia ai faʻamatalaga vitio ma faʻatonu taimi faʻamaumauga mo le 1 pika i le uati.
Ata 5-5. HDMI TX IP Taimi Taimi o Fa'amatalaga Vitio mo le 1 Pixel i le Uati
O le ata o loʻo i lalo o loʻo faʻaalia ai faʻatasiga e fa o faʻamaumauga faʻatonutonu.
Ata 5-6. HDMI TX IP Taimi Taimi o Fa'amatalaga Pulea mo le 1 Pixel i le Uati
Fa'aoga Taiala
DS50003319C – 18
© 2024 Microchip Technology Inc. ma ona lala
System Integration
6. System Integration (Fai se Fesili)
O lenei vaega o loʻo faʻaalia e pei oample faʻamatalaga mamanu.
O le laulau o loʻo i lalo o loʻo lisiina ai faʻasalalauga o PF XCVR, PF TX PLL, ma PF CCC.
Laulau 6-1. PF XCVR, PF TX PLL, ma PF CCC Configurations
|
I'ugafono |
|
Bit Width PF XCVR Configuration |
PF TX PLL Fa'atonuga |
PF CCC Configuration |
||||
|
TX Fa'amatalaga Fa'atatau |
TX Uati Vaevaega Fa'ailoga |
TX PCS ie Lautele |
Mana'omia Uati Bit Output |
Fa'asinomaga Uati Fa'atele |
Ulufale Fa'atele |
Tuuina atu Fa'atele |
||
|
1PXL (1080p60) 8 |
|
1485 |
4 |
10 |
5940 |
148.5 |
NA |
NA |
|
1PXL (1080p30) 10 |
|
925 |
4 |
10 |
3700 |
148.5 |
92.5 |
74 |
|
12 |
1113.75 |
4 |
10 |
4455 |
148.5 |
111.375 |
74.25 |
|
|
16 |
1485 |
4 |
10 |
5940 |
148.5 |
148.5 |
74.25 |
|
|
4PXL (1080p60) 10 |
|
1860 |
4 |
40 |
7440 |
148.5 |
46.5 |
37.2 |
|
12 |
2229 |
4 |
40 |
8916 |
148.5 |
55.725 |
37.15 |
|
|
16 |
2970 |
2 |
40 |
5940 |
148.5 |
74.25 |
37.125 |
|
|
4PXL (4kp30) |
8 |
2970 |
2 |
40 |
5940 |
148.5 |
NA |
NA |
|
10 |
3712.5 |
2 |
40 |
7425 |
148.5 |
92.812 |
74.25 |
|
|
12 |
4455 |
1 |
40 |
4455 |
148.5 |
111.375 |
74.25 |
|
|
16 |
5940 |
1 |
40 |
5940 |
148.5 |
148.5 |
74.25 |
|
|
4PXL (4Kp60) |
8 |
5940 |
1 |
40 |
5940 |
148.5 |
NA |
NA |
HDMI TX Sample Design, pe a configured i g_BITS_PER_COMPONENT = 8-bit ma
g_PIXELS_PER_CLK = 1 PXL mode, o loʻo faʻaalia i le ata o loʻo i lalo.
Ata 6-1. HDMI TX Sample Lisiina
HDMI_TX_C0_0
PF_INIT_MONITOR_C0_0
|
FABRIC_POR_N PCIE_INIT_FAIA USRAM_INIT_FAIA SRAM_INIT_FAIA MEVICE_INIT_FAIA XCVR_INIT_FAIA USRAM_INIT_FROM_SNVM_FAIA USRAM_INIT_FROM_UPROM_FAIA USRAM_INIT_FROM_SPI_FAIA SRAM_INIT_FROM_SNVM_FAIA SRAM_INIT_FROM_UPROM_FAIA SRAM_INIT_FROM_SPI_FAIA AUTOCALIB_FAIA |
PF_INIT_MONITOR_C0
CORERESET_PF_C0_0
|
CLK EXT_RST_N BANK_x_VDDI_STATUS BANK_y_VDDI_STATUS PLL_POWERDOWN_B PLL_LOCK FABRIC_RESET_N SS_BUSY INIT_FAIA FF_US_RESTORE FPGA_POR_N |
CORERESET_PF_C0
Fa'aaliga_Pule_C0_0
|
FRAME_END_O H_SYNC_O RESETN_I V_SYNC_O SYS_CLK_I V_ACTIVE_O ENABLE_I DATA_TRIGGER_O S_RES_O[15:0] V_RES_O[15:0] |
Fa'aaliga_Pule_C0
pattern_generator_verilog_pattern_0
|
DATA_VALID_O SYS_CLK_I FRAME_END_O RESET_N_I LINE_END_O FA'AMATALAGA_EN_I MULA_O[7:0] FRAME_END_I MATUA_O[7:0] PATTERN_SEL_I[2:0] BLUE_O[7:0] BAYER_O[7:0] |
Test_Pattern_Generator_C1
PF_XCVR_REF_CLK_C0_0
|
RESET_N_I SYS_CLK_I VIDEO_DATA_VALID_I R_CLK_I R_CLK_LOCK G_CLK_I G_CLK_LOCK TMDS_R_O[9:0] B_CLK_I TMDS_G_O[9:0] B_CLK_LOCK TMDS_B_O[9:0] V_SYNC_I XCVR_LANE_0_DATA_O[9:0] H_SYNC_I
FAAMATALAGA_R_I[7:0]
FA'AMATALAGA_G_I[7:0]
FA'amatalaga_B_I[7:0] |
HDMI_TX_C0
PF_TX_PLL_C0_0
PF_XCVR_ERM_C0_0
|
PADs_OUT LANE3_TXD_N CLKS_FROM_TXPLL_0 LANE3_TXD_P LANE0_IN LANE2_TXD_N LANE0_PCS_ARST_N LANE2_TXD_P LANE0_PMA_ARST_N LANE1_TXD_N LANE0_TX_DATA[9:0] LANE1_TXD_P LANE1_IN LANE0_TXD_N LANE1_PCS_ARST_N LANE0_TXD_P LANE1_PMA_ARST_N LANE0_OUT LANE1_TX_DATA[9:0] LANE0_TX_CLK_R LANE2_IN LANE0_TX_CLK_STABLE LANE2_PCS_ARST_N LANE1_OUT LANE2_PMA_ARST_N LANE1_TX_CLK_R LANE2_TX_DATA[9:0] LANE1_TX_CLK_STABLE LANE3_IN LANE2_OUT LANE3_PCS_ARST_N LANE2_TX_CLK_R LANE3_PMA_ARST_N LANE2_TX_CLK_STABLE LANE3_TX_DATA[9:0] LANE3_OUT LANE3_TX_CLK_STABLE |
PF_XCVR_ERM_C0
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P
PATTERN_SEL_I[2:0] REF_CLK_PAD_P REF_CLK_PAD_N
|
REF_CLK_PAD_P REF_CLK_PAD_NREF_CLK |
|
REF_CLKPLL_LOCKCLKS_TO_XCVR |
PF_XCVR_REF_CLK_C0
PF_TX_PLL_C0
Mo Example, i 8-bit configurations, o vaega nei o le vaega o le mamanu: • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ua configured mo le fua faatatau o faamatalaga o 1485 Mbps i le PMA mode mo TX na o, faatasi ai ma le lautele o faamatalaga configured 10 bit mo 1pxl mode ma 148.5 MHz fa'asino uati, fa'atatau i le fa'atulagaina o laulau muamua
• LANE0_TX_CLK_R output o le PF_XCVR_ERM_C0_0 o lo'o fa'atupuina ile 148.5 MHz uati, fa'atatau ile fa'atulagaina o le laulau muamua.
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, ma le PF_INIT_MONITOR_C0) o loʻo faʻatautaia e LANE0_TX_CLK_R, o le 148.5 MHz.
• R_CLK_I, G_CLK_I, ma B_CLK_I o lo'o tulia e LANE3_TX_CLK_R, LANE2_TX_CLK_R, ma LANE1_TX_CLK_R.
Fa'aoga Taiala
DS50003319C – 19
© 2024 Microchip Technology Inc. ma ona lala
System Integration
Sample tu'ufa'atasiga mo, g_BITS_PER_COMPONENT = 8 ma g_PIXELS_PER_CLK = 4. Mo Example, i 8-bit configurations, o vaega nei o le vaega o le mamanu: • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) ua configured mo faamatalaga fua faatatau o le 2970 Mbps i le PMA mode mo
TX naʻo, faʻatasi ai ma le lautele o faʻamatalaga ua faʻatulagaina e pei o le 40-bit mo le 1pxl mode ma le 148.5 MHz reference clock e faʻavae i luga o le laulau muamua.
• LANE0_TX_CLK_R output o le PF_XCVR_ERM_C0_0 o lo'o fa'atupuina ile 74.25 MHz uati, fa'atatau ile fa'atulagaina o le laulau muamua.
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, ma le PF_INIT_MONITOR_C0) o loʻo faʻatautaia e LANE0_TX_CLK_R, o le 148.5 MHz.
• R_CLK_I, G_CLK_I, ma B_CLK_I o lo'o tulia e LANE3_TX_CLK_R, LANE2_TX_CLK_R, ma LANE1_TX_CLK_R.
HDMI TX Sample Design, pe a faʻapipiʻiina i le g_BITS_PER_COMPONENT = 12 Bit ma g_PIXELS_PER_CLK = 1 PXL mode, faʻaalia i le ata o loʻo i lalo.
Ata 6-2. HDMI TX Sample Lisiina
PF_XCVR_ERM_C0_0
PATTERN_SEL_I[2:0]
REF_CLK_PAD_P REF_CLK_PAD_N
PF_CCC_C1_0
|
REF_CLK_0 OUT0_FABCLK_0PLL_LOCK_0 |
PF_CCC_C1
PF_INIT_MONITOR_C0_0
CORERESET_PF_C0_0
|
CLK EXT_RST_N BANK_x_VDDI_STATUS BANK_y_VDDI_STATUS PLL_POWERDOWN_B PLL_LOCK FABRIC_RESET_N SS_BUSY INIT_FAIA FF_US_RESTORE FPGA_POR_N |
CORERESET_PF_C0
Fa'aaliga_Pule_C0_0
|
FRAME_END_O H_SYNC_O RESETN_I V_SYNC_O SYS_CLK_I V_ACTIVE_O ENABLE_I DATA_TRIGGER_O S_RES_O[15:0] V_RES_O[15:0] |
Fa'aaliga_Pule_C0
pattern_generator_verilog_pattern_0
|
DATA_VALID_O SYS_CLK_I FRAME_END_O RESET_N_I LINE_END_O FA'AMATALAGA_EN_I MULA_O[7:0] FRAME_END_I MATUA_O[7:0] PATTERN_SEL_I[2:0] BLUE_O[7:0] BAYER_O[7:0] |
Test_Pattern_Generator_C0
PF_XCVR_REF_CLK_C0_0
|
REF_CLK_PAD_P REF_CLK_PAD_NREF_CLK |
PF_XCVR_REF_CLK_C0
HDMI_TX_0
|
RESET_N_I SYS_CLK_I VIDEO_DATA_VALID_I R_CLK_I R_CLK_LOCK G_CLK_I G_CLK_LOCK TMDS_R_O[9:0] B_CLK_I TMDS_G_O[9:0] B_CLK_LOCK TMDS_B_O[9:0] V_SYNC_I XCVR_LANE_0_DATA_O[9:0] H_SYNC_I
FAAMATALAGA_R_I[11:4]
FA'AMATALAGA_G_I[11:4]
FA'amatalaga_B_I[11:4] |
HDMI_TX_C0
PF_TX_PLL_C0_0
|
PADs_OUT CLKS_FROM_TXPLL_0 LANE3_TXD_N LANE0_IN LANE3_TXD_P LANE0_PCS_ARST_N LANE2_TXD_N LANE0_PMA_ARST_N LANE2_TXD_P LANE0_TX_DATA[9:0] LANE1_TXD_N LANE1_IN LANE1_TXD_P LANE1_PCS_ARST_N LANE0_TXD_N LANE1_PMA_ARST_N LANE0_TXD_P LANE1_TX_DATA[9:0] LANE0_OUT LANE2_IN LANE1_OUT LANE2_PCS_ARST_N LANE1_TX_CLK_R LANE2_PMA_ARST_N LANE1_TX_CLK_STABLE LANE2_TX_DATA[9:0] LANE2_OUT LANE2_TX_CLK_R LANE3_PCS_ARST_N LANE2_TX_CLK_STABLE LANE3_PMA_ARST_N LANE3_OUT LANE3_TX_DATA[9:0] LANE3_TX_CLK_R LANE3_TX_CLK_STABLE |
PF_XCVR_ERM_C0
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P
|
FABRIC_POR_N PCIE_INIT_FAIA USRAM_INIT_FAIA SRAM_INIT_FAIA MEVICE_INIT_FAIA XCVR_INIT_FAIA USRAM_INIT_FROM_SNVM_FAIA USRAM_INIT_FROM_UPROM_FAIA USRAM_INIT_FROM_SPI_FAIA SRAM_INIT_FROM_SNVM_FAIA SRAM_INIT_FROM_UPROM_FAIA SRAM_INIT_FROM_SPI_FAIA AUTOCALIB_FAIA |
|
REF_CLKPLL_LOCKCLKS_TO_XCVR |
PF_INIT_MONITOR_C0
PF_TX_PLL_C0
Sample tu'ufa'atasiga mo, g_BITS_PER_COMPONENT > 8 ma g_PIXELS_PER_CLK = 1. Mo Example, i 12-bit configurations, o vaega nei o le vaega o le mamanu:
• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) o loʻo faʻatulagaina mo faʻamaumauga o le 111.375 Mbps i le PMA mode mo TX naʻo, faʻatasi ai ma le lautele o faʻamatalaga faʻapipiʻiina e pei o le 10 bit mo le 1pxl mode ma le 1113.75 Mbps reference clock, faʻavae i luga o le Laulau 6-1 faatulagaga
• LANE1_TX_CLK_R output o le PF_XCVR_ERM_C0_0 e fa'atupuina ile 111.375 MHz uati, fa'atatau ile Laulau 6-1 faatulagaga
• R_CLK_I, G_CLK_I, ma B_CLK_I o lo'o tulia e LANE3_TX_CLK_R, LANE2_TX_CLK_R, ma LANE1_TX_CLK_R.
• PF_CCC_C0 e fa'atupuina se uati e ta'ua OUT0_FABCLK_0, e 74.25 MHz le tele o taimi, pe a o'o i le 111.375 MHz le uati ulufale, lea e fa'aola e LANE1_TX_CLK_R.
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, ma le PF_INIT_MONITOR_C0) o loʻo faʻatautaia e OUT0_FABCLK_0, o le 74.25 MHz.
Sample tu'ufa'atasiga mo, g_BITS_PER_COMPONENT > 8 ma g_PIXELS_PER_CLK = 4. Mo Example, i 12-bit configurations, o vaega nei o le vaega o le mamanu:
• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) o loʻo faʻatulagaina mo faʻamaumauga o le 4455 Mbps i le PMA mode mo TX naʻo, faʻatasi ai ma le lautele o faʻamatalaga e faʻapipiʻiina e pei o le 40 bit mo le 4pxl mode ma le 111.375 MHz reference clock, faʻavae i luga o le Laulau 6-1 faatulagaga
• LANE1_TX_CLK_R output o le PF_XCVR_ERM_C0_0 e fa'atupuina ile 111.375 MHz uati, fa'atatau ile Laulau 6-1 faatulagaga
Fa'aoga Taiala
DS50003319C – 20
© 2024 Microchip Technology Inc. ma ona lala
System Integration
• R_CLK_I, G_CLK_I, ma B_CLK_I o lo'o tulia e LANE3_TX_CLK_R, LANE2_TX_CLK_R, ma LANE1_TX_CLK_R.
• PF_CCC_C0 e fa'atupuina se uati e ta'ua OUT0_FABCLK_0, e 74.25 MHz le tele o taimi, pe a o'o i le 111.375 MHz le uati ulufale, lea e fa'aola e LANE1_TX_CLK_R.
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, ma le PF_INIT_MONITOR_C0) o loʻo faʻatautaia e OUT0_FABCLK_0, o le 74.25 MHz.
Fa'aoga Taiala
DS50003319C – 21
© 2024 Microchip Technology Inc. ma ona lala
Toe Iloilo Tala'aga
7. Toe Iloilo Tala'aga (Fai se Fesili)
O le tala fa'asolopito o lo'o fa'amatalaina suiga na fa'atinoina i le pepa. O suiga o lo'o lisiina e ala i toe iloiloga, amata i le lomiga aupito lata mai.
Laulau 7-1. Toe Iloilo Tala'aga
|
Toe Iloiloga |
Aso |
Fa'amatalaga |
|
C |
05/2024 |
Ole lisi lea o suiga ile toe teuteuga C ole pepa: • Fa'afouina Folasaga vaega • Aveese laulau fa'aoga punaoa mo le tasi pika ma le fa pika ma fa'aopoopo Laulau 2 ma Laulau 3 in 1. Fa'aaogaina o Punaoa vaega • Fa'afouina Laulau 3-1 i le 3.1. Fa'atutuga Parata vaega • Faaopoopo Laulau 3-6 ma Laulau 3-7 i le 3.2. Taulaga vaega • Faaopoopo 6. Tuufaatasiga Faiga vaega |
|
B |
|
09/2022 Ole lisi lea o suiga ile toe teuteuga B ole pepa: • Fa'afouina mea o lo'o i totonu o Features ma Folasaga • Faaopoopo Ata 2-2 mo le le atoatoa leo Mode • Faaopoopo Laulau 3-4 ma Laulau 3-5 • Fa'afouina le Laulau 3-2 ma Laulau 3-3 • Fa'afouina Laulau 3-1 • Fa'afouina 1. Fa'aaogaina o Punaoa • Fa'afouina Ata 1-1 • Fa'afouina Ata 5-3 |
|
A |
|
04/2022 Ole lisi lea o suiga ile toe teuteuga A ole pepa: • O le pepa na ave i le mamanu Microchip • O le numera o le pepa na fa'afouina i le DS50003319 mai le 50200863 |
|
2.0 |
— |
O lo'o i lalo le aotelega o suiga na faia i lenei toe iloiloga. • Vaega Faaopoopo ma Aiga Lagolagoina |
|
1.0 |
|
08/2021 Toe iloilo muamua |
Fa'aoga Taiala
DS50003319C – 22
© 2024 Microchip Technology Inc. ma ona lala
Microchip FPGA Lagolago
Microchip FPGA products group backs its products with various support services, including Customer Service, Customer Technical Support Center, a webnofoaga, ma ofisa faatau i le lalolagi atoa. E fautuaina tagata fa'atau e asiasi i Microchip i luga ole laiga a'o le'i fa'afeso'ota'i le lagolago ona e foliga mai ua uma ona tali a latou fesili.
Fa'afeso'ota'i le Nofoaga Autu Lagolago Fa'apitoa e ala ile webnofoaga i www.microchip.com/support. Ta'u le numera o le Vaega o Meafaigaluega FPGA, filifili le vaega o mataupu talafeagai, ma fa'apipi'i le mamanu files a'o faia se mataupu lagolago fa'apitoa.
Fa'afeso'ota'i Auaunaga Fa'atau mo le lagolago o oloa e le fa'apitoa, e pei o le tau o oloa, fa'aleleia o oloa, fa'afouga fa'amatalaga, tulaga oka, ma le fa'atagaina.
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• Fax, mai so'o se mea o le lalolagi, 650.318.8044
Microchip Fa'amatalaga
Le Microchip Webnofoaga
Microchip e maua le lagolago i luga ole laiga e ala i la matou webnofoaga i www.microchip.com/. Lenei web'upega tafa'ilagi e fa'aoga e fai ai files ma fa'amatalaga faigofie ona maua e tagata fa'atau. O nisi o mea e maua e aofia ai:
• Lagolago oloa - Pepa faʻamatalaga ma mea sese, faʻamatalaga talosaga ma samppolokalame, punaoa mamanu, ta'iala a le tagata fa'aoga ma pepa lagolago mo meafaigaluega, fa'asalalauga fou fa'akomepiuta ma polokalama fa'amaumauga
• Lagolago Fa'atekinisi Lautele - Fesili e masani ona fesiligia (FAQs), talosaga lagolago faʻapitoa, vaega faʻatalanoaga i luga ole laiga, Microchip design paaga polokalame lisi sui auai
• Pisinisi a Microchip - Filifilia oloa ma taʻiala faʻatonu, faʻasalalauga lata mai a Microchip, lisi o semina ma mea tutupu, lisi o ofisa faʻatau Microchip, tufatufaina ma sui fale gaosi oloa
Au'aunaga Fa'asilasilaga Suiga o Mea
O le auaunaga fa'asilasilaga suiga o oloa a Microchip e fesoasoani e fa'amautu ai tagata fa'atau i oloa Microchip. O le a maua e le au fai saofaga le faʻamatalaga imeli i soʻo se taimi e iai suiga, faʻafouga, toe teuteuga poʻo mea sese e fesoʻotaʻi ma se aiga o oloa faʻapitoa poʻo meafaigaluega atinaʻe e fiafia i ai.
Ina ia lesitala, alu i www.microchip.com/pcn ma mulimuli i faatonuga o le resitalaina. Lagolago Tagata Fa'atau
E mafai ona maua e tagata fa'aoga oloa Microchip le fesoasoani e ala i le tele o auala: • Fa'asoa po'o Sui
• Ofisa Fa'atauga Fa'alotoifale
• Embedded Solutions Engineer (ESE)
• Lagolago Fa'atekinisi
E tatau i tagata fa'atau ona fa'afeso'ota'i le latou tufatufaina, sui po'o le ESE mo le lagolago. O loʻo avanoa foʻi ofisa faʻatau i le lotoifale e fesoasoani i tagata faʻatau. O lo'o iai se lisi o ofisa fa'atau ma nofoaga i totonu o lenei pepa.
E maua le lagolago fa'apitoa e ala ile webnofoaga i: www.microchip.com/support Fa'ailoga Puipuiga o Fa'ailoga Fa'atonu a Microchip
Manatua faʻamatalaga o loʻo i lalo o le faʻaogaina o le puipuiga o tulafono i luga o oloa Microchip:
Fa'aoga Taiala
DS50003319C – 23
© 2024 Microchip Technology Inc. ma ona lala
• O oloa Microchip e fetaui ma fa'amatalaga o lo'o i totonu o latou Pepa Fa'amatalaga Microchip.
• E talitonu le Microchip o lona aiga o oloa e malupuipuia pe a faʻaaogaina i le auala faʻamoemoeina, i totonu o faʻamatalaga faʻaogaina, ma i lalo o tulaga masani.
• Fa'ataua Microchip ma puipuia fa'amalosi ana aia tatau tau meatotino. O le taumafai e soli le tulafono o le puipuiga o le oloa Microchip e matua fa'asaina ma e ono solia ai le Digital Millennium Copyright Act.
• E le mafai e le Microchip po'o se isi mea gaosi semiconductor ona fa'amaonia le saogalemu o lana code. O le puipuiga o tulafono laiti e le o lona uiga tatou te faʻamautinoa o le oloa e "le mafai ona motusia". O le puipuiga o tulafono laiti o lo'o fa'asolosolo pea. Microchip ua tuuto atu i le faʻaauauina pea o le faʻaleleia atili o uiga puipuia o tulafono a tatou oloa.
Faasilasilaga Faaletulafono
O lenei lomiga ma faʻamatalaga o loʻo i totonu e mafai ona faʻaaogaina naʻo oloa Microchip, e aofia ai le mamanu, suʻega, ma tuʻufaʻatasia oloa Microchip ma lau talosaga. O le fa'aogaina o nei fa'amatalaga i so'o se isi lava faiga e solia ai nei aiaiga. O fa'amatalaga e uiga i le fa'aogaina o masini e tu'uina atu mo na'o lou fa'amalieina ma e ono suia i fa'afouga. O lau matafaioi le faʻamautinoa o lau talosaga e fetaui ma au faʻamatalaga. Fa'afeso'ota'i lou ofisa fa'atau Microchip fa'apitonu'u mo se lagolago fa'aopoopo pe, maua se lagolago fa'aopoopo ile www.microchip.com/en-us/support/design-help/client-support-services.
O LENEI FAʻAMATALAGA E TUUINA E MICROCHIP "AS IS". E LEAI FAIA e le MICROCHIP ni sui po'o se fa'amaoniga o so'o se ituaiga pe fa'aalia pe fa'aali, tusia pe tugutu, tulāfono po'o se isi mea, e feso'ota'i ma fa'amatalaga e aofia ai ae le tapula'a i so'o se fa'amaoniaga fa'amaonia, fa'amaonia, ma le fa'amaoniaina. FAAMOEMOEGA, POO WARRANTY E FAI I ONA TULAGA, TULAGA, POO LE FAIGALUEGA.
E LEAI SE MEA E TATAU AI MICROCHIP MO SO'O SE FA'AMATALAGA, FA'AMATALAGA, FA'ASA'OGA, FA'AMATALAGA, PO'O LE FA'A'ALI'AGA MA'U'U, FA'AFIA, TAU, PO'O LE TU'U'UINA O SO'O SE I'UGA SO'O SE FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA, PE'O LE MEA NA FA'AUPUNA'I, E tusa lava pe fa'aletonu. FA'ATONU POO LE FA'AFIA E FA'AVAEINA. I LE AGATOGA FA'AALIGA E LE TULAFONO, O LE UMA AOFA'IGA A MICROCHIP I TOTOGI UMA I SO'O SE AUALA E FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA E LE'A LOLOA I LE TOTOGI O TOTOGI, AFAI E IAI, NA E TOTOGI SA'O I LE MICROCHIP MO LE FA'AMATALAGA.
O le fa'aogaina o masini Microchip i le tausiga o le ola ma/po'o le saogalemu o lo'o i le tulaga lamatia o le tagata fa'atau, ma e malie le tagata fa'atau e puipuia, fa'aleaga ma taofia Microchip le afaina mai so'o se mea leaga, tagi, suti, po'o tupe alu e mafua mai i lea fa'aoga. E leai ni laisene e tu'uina atu, fa'aalia po'o se isi mea, i lalo o so'o se Microchip aia tatau tau le atamai se'i vagana ua ta'ua.
Fa'ailoga Fa'ailoga
Le igoa Microchip ma le logo, le Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ma XMEGA o fa'ailoga fa'amaufa'ailoga a Microchip Technology Incorporated i Amerika ma isi atunu'u.
AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, ma ZL o faʻailoga resitalaina o Microchip Technology Incorporated i Amerika.
Taofi Fa'aigoa Fa'atasi, AKS, Analog-for-the-Digital Age, So'o se Capacitor, So'o se In, So'o'Out, Fa'aopoopoina Suiga, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic.
Fa'aoga Taiala
DS50003319C – 24
© 2024 Microchip Technology Inc. ma ona lala
Fa'afetauiga Tulaga, DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Parallel, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, MarginLink, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Faʻamaonia logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PureSilicon , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Aofa'i Tumau , Taimi Fa'atuatuaina, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ma ZENA o fa'ailoga fa'ailoga a Microchip Technology Incorporated i Amerika ma isi atunu'u.
SQTP ose fa'ailoga tautua a Microchip Technology Incorporated i Amerika
O le logo Adaptec, Frequency on Demand, Silicon Storage Technology, ma Symmcom o fa'ailoga fa'amaufa'ailoga a Microchip Technology Inc. i isi atunu'u.
GestIC ose fa'ailoga fa'amaufa'ailoga a Microchip Technology Germany II GmbH & Co. KG, ose lala o Microchip Technology Inc., i isi atunu'u.
O isi fa'ailoga tau fefa'ataua'iga uma o lo'o ta'ua ii o meatotino a latou kamupani. © 2024, Microchip Technology Incorporated ma ona lala. Ua Taofia Aia Tatau Uma. ISBN:
Faiga Fa'atonuga
Mo faʻamatalaga e uiga i Microchip's Quality Management Systems, faʻamolemole asiasi www.microchip.com/quality.
Fa'aoga Taiala
DS50003319C – 25
© 2024 Microchip Technology Inc. ma ona lala
Fa'atauga ma Au'aunaga i le Lalolagi Atoa
AMERIKA ASIA/ PASIFIK ASIA/ PASIFIK EUROPE
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Korea – Daegu
Telefoni: 82-53-744-4301
Korea – Seoul
Telefoni: 82-2-554-7200
Meleisia – Kuala Lumpur Telefoni: 60-3-7651-7906
Meleisia – Penang
Telefoni: 60-4-227-8870
Filipaina – Manila
Telefoni: 63-2-634-9065
Singapore
Telefoni: 65-6334-8870
Taiuani – Hsin Chu
Telefoni: 886-3-577-8366
Taiuani – Kaohsiung
Telefoni: 886-7-213-7830
Taiuani – Taipei
Telefoni: 886-2-2508-8600
Taialani – Bangkok
Telefoni: 66-2-694-1351
Vietnam – Ho Chi Minh
Telefoni: 84-28-5448-2100
Fa'aoga Taiala
Ausetalia – Uelese
Telefoni: 43-7242-2244-39
Fax: 43-7242-2244-393
Tenimaka – Copenhagen
Telefoni: 45-4485-5910
Fax: 45-4485-2829
Finelani – Espoo
Telefoni: 358-9-4520-820
Farani – Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Siamani – Garching
Telefoni: 49-8931-9700
Siamani – Haan
Telefoni: 49-2129-3766400
Siamani – Heilbronn
Telefoni: 49-7131-72400
Siamani – Karlsruhe
Telefoni: 49-721-625370
Siamani – Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Siamani – Rosenheim
Telefoni: 49-8031-354-560
Isaraelu – Hod Hasaron
Telefoni: 972-9-775-5100
Italia – Milan
Telefoni: 39-0331-742611
Fax: 39-0331-466781
Italia – Padova
Telefoni: 39-049-7625286
Netherlands – Drunen
Telefoni: 31-416-690399
Fax: 31-416-690340
Nouei – Trondheim
Telefoni: 47-72884388
Polani – Warsaw
Telefoni: 48-22-3325737
Romania – Bucharest
Tel: 40-21-407-87-50
Sepania - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Suetena – Gothenberg
Tel: 46-31-704-60-40
Suetena - Stockholm
Telefoni: 46-8-5090-4654
Peretania - Wokingham
Telefoni: 44-118-921-5800
Fax: 44-118-921-5820
DS50003319C – 26
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