intel UG-20094 Cyclone 10 GX Native Fixed Point DSP IP Core
Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide
Iyo Intel Cyclone® 10 GX Native Fixed Point DSP IP musimboti inosimbisa uye inodzora imwechete Intel Cyclone 10 GX Variable Precision Digital Signal Processing (DSP) block. Iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inowanikwa chete kune Intel Cyclone 10 GX zvishandiso.
Cyclone 10 GX Native Fixed Point DSP IP Core Functional Block Diagram
Related Information
Nhanganyaya kuIntel FPGA IP Cores.
Cyclone 10 GX Native Fixed Point DSP IP Core Features
Iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inotsigira zvinotevera maficha:
- Kushanda kwepamusoro-soro, kukwidziridzwa kwesimba, uye kunyoreswa kwakazara mashandiro ekuwanza
- 18-bit uye 27-bit izwi kureba
- Vaviri 18 × 19 vanowedzera kana imwe 27 × 27 kuwedzera paDSP block
- Yakavakwa-mukuwedzera, kubvisa, uye 64-bit kaviri kuunganidza rejisita kuti ubatanidze mibairo yekuwanza
- Cascading 19-bit kana 27-bit kana pre-adder yaremara uye ichidonha 18-bit kana pre-adder inoshandiswa kugadzira tap-inononoka mutsara wekusefa application.
- Cascading 64-bit inobuda bhazi kuparadzira zvinobuda kubva kune rimwe bhuroko kuenda kune rinotevera bhuroko pasina ekunze logic rutsigiro.
- Hard pre-adder inotsigirwa mune 19-bit uye 27-bit modhi yemasefa esymmetric
- Yemukati coefficient rejista bhangi mune ese 18-bit uye 27-bit modhi yekusefa kuita
- 18-bit uye 27-bit systolic finite impulse mhinduro (FIR) mafirita ane akagovaniswa adder
Kutanga
Chitsauko ichi chinopa general overview yeIntel FPGA IP yepakati dhizaini inoyerera kuti ikubatsire nekukurumidza kutanga neCyclone 10 GX Native Fixed Point DSP IP musimboti. Iyo Intel FPGA IP Library yakaiswa sechikamu cheIntel Quartus® Prime yekuisa maitiro. Iwe unogona kusarudza uye parameterize chero Intel FPGA IP musimboti kubva muraibhurari. Intel inopa yakasanganiswa paramende dhizaini iyo inokutendera iwe kugadzirisa iyo Intel FPGA DSP IP musimboti kutsigira akasiyana siyana ekushandisa. Iyo parameter mupepeti inotungamira iwe kuburikidza nekumisikidzwa kweiyo parameter kukosha uye kusarudzwa kwesarudzo ports.
Related Information
- Nhanganyaya kuIntel FPGA IP Cores
Inopa ruzivo rwese nezvese Intel FPGA IP cores, kusanganisira parameterizing, kugadzira, kusimudzira, uye kutevedzera IP cores. - Kugadzira Shanduro-Yakazvimirira IP uye Platform Mugadziri (Standard) Simulatio Scripts
Gadzira zvinyorwa zvekunyepedzera zvisingade zvigadziriso zvemanyorero zvesoftware kana IP vhezheni kusimudzira. - Project Management Best Practices
Nhungamiro yekutonga kwakanaka uye kutakurika kweprojekiti yako uye IP files.
Cyclone 10 GX Native Fixed Point DSP IP Core Parameter Settings
Iwe unogona kugadzirisa iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti nekutsanangura maparamita uchishandisa parameter mupepeti muIntel Quartus Prime software.
Operation Mode Tab
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| Ndapota sarudza maitiro ekushanda | operation_mode | m18×18_full m18×18_sumof2 m18×18_plus36 m18×18_systolic m27×27 | Sarudza yaunoda kushanda mode. |
| Multiplier Configuration | |||
| Representation format yepamusoro multiplier x operand | sign_max | akasaina asina kusainwa | Rondedzera chimiro chekumiririra chepamusoro multiplier x operand. |
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| Representation fomati ye top multiplier y operand | sign_may | akasaina asina kusainwa | Taura chimiro chekumiririra chepamusoro wedzera y operand. |
| Representation fomati yepasi multiplier x operand | sign_mbx | akasaina asina kusainwa | Rondedzera chimiro chekumiririra chepasi multiplier x operand. |
| Representation fomati yepazasi kuwandisa y operand | sign_mby | akasaina asina kusainwa | Rondedzera chimiro chekumiririra chepasi multiplier y operand.
Nguva dzose sarudza asina kusaina nokuti m18×18_plus36 . |
| Gonesa 'sub' port | enable_sub | Aihwa Ehe | Sarudza Ehe kugonesa
sub port. |
| Nyoresa kuisa 'sub' yekuwanda | sub_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda ye sub registration. |
| Input Cascade | |||
| Gonesa kuisa cascade kuti 'ay' inyore | ay_shandisa_scan_in | Aihwa Ehe | Sarudza Ehe kugonesa yekuisa cascade module kune chero data yekuisa.
Kana iwe uchigonesa yekuisa cascade module, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inoshandisa masaini ekuisa scanin sekuisa panzvimbo yeay masaini ekuisa. |
| Gonesa kuisa cascade kuti 'by' kuisa | by_use_scan_in | Aihwa Ehe | Sarudza Ehe kugonesa yekuisa cascade module yekuisa data.
Kana iwe uchigonesa yekuisa cascade module, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inoshandisa iyo ay yekupinza masaini sekuisa panzvimbo yemasaini ekuisa. |
| Gonesa data ay kunonoka rejista | delay_scan_out_ay | Aihwa Ehe | Sarudza Ehe kugonesa kunonoka kunyoresa pakati peay uye nemarejista ekuisa.
Ichi chimiro hachishandiswe mukati m18×18_plus36 uye m27x27 kushanda mode. |
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| Gonesa data nekunonoka rejista | delay_scan_out_by | Aihwa Ehe | Sarudza Ehe kugonesa kunonoka rejista pakati pemareji ekuisa uye scanout inobuda bhazi.
Ichi chimiro hachishandiswe mukati m18×18_plus36 uye m27x27 kushanda mode. |
| Shandisa scanout port | gui_scanout_enable | Aihwa Ehe | Sarudza Ehe kugonesa
scanout inobuda bhazi. |
| 'scanout' inobuda bhazi upamhi | scan_out_width | 1–27 | Taura hupamhi hwe
scanout inobuda bhazi. |
| Data 'x' Configuration | |||
| 'demo' kuisa upamhi hwebhazi | ax_width | 1–27 | Taura hupamhi hwe
bhazi rekuisa nedemo.(1) |
| Nyoresa 'demo' rekuwedzera | ax_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yerejista yekuisa demo.
regisita yekupinza nedemo haipo kana ukaseta 'demo' operand source ku 'coef'. |
| 'bx' kuisa upamhi hwebhazi | bx_width | 1–18 | Taura hupamhi hwe
bx bhazi rekuisa.(1) |
| Nyoresa kuisa 'bx' yevanowedzera | bx_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yebx regisita yekupinda.
bx register yekupinza haisi kuwanikwa kana iwe ukaseta 'bx' operand source ku 'coef'. |
| Data 'y' Configuration | |||
| 'ay' kana 'scanin' upamhi hwebhazi | ay_scan_in_width | 1–27 | Taura hupamhi hwebhazi rekuisa ay kana scanin.(1) |
| Nyoresa kuisa 'ay' kana kuisa 'scanin' yekuwanda | ay_scan_in_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yeay kana scanin yekuisa regisheni. |
| 'by' kuisa upamhi hwebhazi | ne_upamhi | 1–19 | Taura hupamhi hwebhazi rekupinda.(1) |
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| Nyoresa kuisa 'ne' yevanowedzera | by_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda kana scanin
rejista yekupinda.(1) |
| Output 'result' Configuration | |||
| 'resulta' yakabuda bhazi upamhi | mhedzisiro_a_upamhi | 1–64 | Taura hupamhi hwe
resulta kubuda bhazi. |
| 'resultb' yakabuda bhazi upamhi | mhedzisiro_b_upamhi | 1–64 | Taura hupamhi hwebhazi rinobuda. resultb inowanikwa chete kana uchishandisa operation_mode m18×18_yakazara. |
| Shandisa register yekubuda | output_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yemhedzisiro uye mhedzisiro inobuda marejista. |
Pre-adder Tab
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| 'ay' operand source | operand_source_may | kuisa preadder | tsanangura iyo operand source yeay input. Sarudza preadder kugonesa pre-adder module yekuwedzeredza yepamusoro. Settings yeay uye neye operand sosi inofanira kunge yakafanana. |
| 'by' operand source | operand_source_mby | kuisa preadder | Nyatsotsanangura operand kwakabva nekupinza. Sarudza preadder kugonesa pre-adder module yekuwedzeredza pasi. Settings yeay uye neye operand sosi inofanira kunge yakafanana. |
| Seta pre-adder oparesheni yekubvisa | preadder_subtract_a | Aihwa Ehe | Sarudza Ehe kudoma mashandiro ekubvisa epre-adder module yekuwedzeredza yepamusoro. Pre-adder marongero epamusoro nepasi pekuwedzera anofanirwa kunge akafanana. |
| Seta pre-adder b operation yekubvisa | preadder_bvisa_b | Aihwa Ehe | Sarudza Ehe kudoma mashandiro ekubvisa epre-adder module yekuwandisa pasi. Pre-adder marongero epamusoro nepasi pekuwedzera anofanirwa kunge akafanana. |
| Data 'z' Configuration | |||
| 'az' kuisa hupamhi hwebhazi | az_width | 1–26 | Taura hupamhi hwebhazi rekuisa reaz.(1) |
| Nyoresa kuisa 'az' yevanowedzera | az_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yeaz marejista ekuisa. Zvirongwa zvewachi zveay uye az marejista ekuisa anofanira kunge akafanana. |
| 'bz' kuisa hupamhi hwebhazi | bz_width | 1–18 | Taura hupamhi hwebhazi rekuisa bz.(1) |
| Nyoresa kuisa 'bz' kwemuwedzere | bz_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yebz marejista ekuisa. Zvirongwa zvewachi zve by uye bz marejista ekuisa anofanirwa kufanana. |
Internal Coefficient Tab
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| 'demo' operand source | operand_source_max | input coef | Nyatsotsanangura nzvimbo yebhazi rekuisa demo. Sarudza coef kugonesa yemukati coefficient module yekuwedzeredza yepamusoro.
Sarudza Aihwa nokuti Nyoresa 'demo' rekuwedzera parameter paunogonesa iyo yemukati coefficient chimiro. |
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| Settings yedemo uye bx operand sosi inofanira kunge yakafanana. | |||
| 'bx' operand source | operand_source_mbx | input coef | tsanangura iyo operand sosi yebhazi rekuisa bx. Sarudza coef kugonesa yemukati coefficient module yekuwedzeredza yepamusoro.
Sarudza Aihwa nokuti Nyoresa kuisa 'bx' yevanowedzera parameter paunogonesa iyo yemukati coefficient chimiro. Settings yedemo uye bx operand sosi inofanira kunge yakafanana. |
| 'coefsel' Input Register Configuration | |||
| Nyoresa kuisa 'coefsela' yekuwandisa | coef_sel_a_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yemarejista ekuisa ecoefsela. |
| Nyoresa kuisa 'coefselb' yekuwanda | coef_sel_b_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinza yemarejista ekuisa coefselb. |
| Coefficient Storage Configuration | |||
| coef_a_0–7 | coef_a_0–7 | Integer | Taura makoefficients ebhazi rekuisa demo.
Kune 18-bit maitiro ekushanda, iyo yakawanda yekuisa kukosha ndeye 218 - 1. Pakuita 27-bit, iyo yakanyanya kukosha ndeye 227 - 1. |
| coef_b_0–7 | coef_b_0–7 | Integer | Taura makoefficients ebhazi rekuisa bx. |
Accumulator/Output Cascade Tab
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| Gonesa 'kuunganidza' port | enable_accumulate | Aihwa Ehe | Sarudza Ehe kugonesa
accumulator port. |
| Gonesa 'negate' port | enable_negate | Aihwa Ehe | Sarudza Ehe kugonesa
negate port. |
| Gonesa 'loadconst' port | enable_loadconst | Aihwa Ehe | Sarudza Ehe kugonesa
loadconst port. |
| Kunyoresa kupinza 'kuunganidza' kweiyo accumulator | accumulate_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0 , Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yeaunganidza marejista ekuisa. |
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| Kunyoresa kupinza 'loadconst' yeaccumulator | load_const_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yeloadconst marejista ekuisa. |
| Nyoresa kuisa 'negate' yeadder unit | negate_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yerejista yekuisa yekuramba. |
| Gonesa kaviri accumulator | gonesa_double_acum | Aihwa Ehe | Sarudza Ehe kugonesa kaviri accumulator chimiro. |
| N kukosha kwe preset yekugara | load_const_value | 0-63 | Taura preset inoramba ichikosha.
Kukosha uku kunogona kuva 2N kupi N ndiyo preset inoramba ichikosha. |
| Gonesa chainin port | use_chainad | Aihwa Ehe | Sarudza Ehe kugonesa kuburitsa cascade module uye iyo chainin yekupinza bhazi.
Output cascade feature haitsigirwe mukati m18×18_yakazara maitiro ekushanda. |
| Vhura chainout port | gui_chainout_enable | Aihwa Ehe | Sarudza Ehe kugonesa iyo chainout inobuda bhazi. Output cascade feature haitsigirwe mukati
m18×18_yakazara maitiro ekushanda. |
Pipelining Tab
| Parameter | IP Yakagadzirwa Parameter | Value | Tsanangudzo |
| Wedzera rejista yepombi yekupinza kune yekuisa data chiratidzo (x/y/z/coefsel) | input_pipeline_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa nekutsanangura chiratidzo chewachi yekupinda ye x, y, z, coefsela uye marejista ekuisa pombi yecoefselb. |
| Wedzera rejista yekupinza pombi kune iyo 'sub' data chiratidzo | sub_pipeline_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinza ye sub pipeline yekuisa register. (2) |
| Wedzera rejista yepombi yekupinza kune iyo 'unganidza' data chiratidzo | accum_pipeline_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekuunganidza yekuunganidza pombi yekuisa regisheni.(2) |
| Wedzera rejista yepombi yekupinza kune iyo 'loadconst' data chiratidzo | load_const_pipeline_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yeloadconst pombi yekuisa regisheni.(2) |
| Wedzera rejista yekupinza pombi kune iyo 'negate' data chiratidzo | negate_pipeline_clock | Aihwa Clock0 Clock1 Clock2 | Sarudza Wachi0, Wachi1, kana Wachi2 kugonesa uye kutsanangura chiratidzo chewachi yekupinda yerejista yekuregedza pombi yekupinda.(2) |
Maximum Input Data Width Per Operation Mode
Iwe unogona kugadzirisa hupamhi hwe data ye x, y, uye z mapikisi sekutsanangurwa kwazvino patafura.
Ese marejista ekuisa mapaipi emagetsi ekudzora masiginecha anofanirwa kunge aine wachi imwe chete.
| Operation Mode | Maximum Input Data Width | |||||
| ax | ay | az | bx | by | bz | |
| Pasina Pre-adder kana Internal Coefficient | ||||||
| m18×18_yakazara | 18 (yakasaina)
18 (isina kusaina) |
19 (yakasaina)
18 (isina kusaina) |
Haina kushandiswa | 18 (yakasaina)
18 (isina kusaina) |
19 (yakasaina)
18 (isina kusaina) |
Haina kushandiswa |
| m18×18_sumof2 | ||||||
| m18×18_systolic | ||||||
| m18×18_plus36 | ||||||
| m27×27 | 27 (yakasaina)
27 (isina kusaina) |
Haina kushandiswa | ||||
| Ne Pre-adder Feature Chete | ||||||
| m18×18_yakazara | 18 (yakasaina)
18 (isina kusaina) |
|||||
| m18×18_sumof2 | ||||||
| m18×18_systolic | ||||||
| m27×27 | 27 (yakasaina)
27 (isina kusaina) |
26 (yakasaina)
26 (isina kusaina) |
Haina kushandiswa | |||
| NeInternal Coefficient Feature chete | ||||||
| m18×18_yakazara | Haina kushandiswa | 19 (yakasaina)
18 (isina kusaina) |
Haina kushandiswa | 19 (yakasaina)
18 (isina kusaina) |
Haina kushandiswa | |
| m18×18_sumof2 | ||||||
| m18×18_systolic | ||||||
| m27×27 | 27 (yakasaina)
27 (isina kusaina) |
Haina kushandiswa | ||||
Tsanangudzo Yekushanda
The Cyclone 10 GX Native Fixed Point DSP IP musimboti ine 2 zvivakwa; 18 × 18 kuwanda uye 27 × 27 kuwedzera. Imwe neimwe instantiation yeCyclone 10 GX Native Fixed Point DSP IP musimboti inoburitsa chete 1 yezvivakwa zviviri zvinoenderana nemaitiro akasarudzwa ekushanda. Iwe unogona kugonesa sarudzo dzemodule kune yako application.
Related Information
Variable Precision DSP Blocks muIntel Cyclone 10 GX Devices chitsauko, Intel Cyclone 10 GX Core Fabric uye General Purpose I/Os Handbook.
Operational Modes
Iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inotsigira 5 maitiro ekushanda:
- Iyo 18 × 18 Yakazara Modhi
- Iyo 18 × 18 Sum ye2 Mode
- Iyo 18 × 18 Plus 36 Modhi
- Iyo 18 × 18 Systolic Modhi
- Iyo 27 × 27 Modhi
Iyo 18 × 18 Yakazara Modhi
Kana yakagadziriswa se 18 × 18 yakazara modhi, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti unoshanda seaviri akazvimiririra 18 (akasaina / asina kusaina) × 19 (akasaina) kana gumi nemasere.
(yakasaina/isina kusaina) × 18 (isina kusaina) inowandisa ine 37-bit kubuda. Iyi modhi inoshandisa zvinotevera equations:
- resulta = demo * ay
- resultb = bx * by
Iyo 18 × 18 Yakazara Mode Architecture
Iyo 18 × 18 Sum ye2 Mode
Mune 18 × 18 Sum ye2 modes, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inogonesa kumusoro uye pasi vawedzere uye inogadzira mhedzisiro kubva pakuwedzera kana kubvisa pakati pevaviri vanowedzera. Iyo sub-dynamic control siginecha inodzora adder kuti iite yekuwedzera kana kubvisa mashandiro. Mhedzisiro yekubuda kwehupamhi hweCyclone 2 GX Native Fixed Point DSP IP musimboti inogona kutsigira kusvika makumi matanhatu nemana mabhiti paunogonesa accumulator/output cascade. Iyi modhi inoshandisa equation yemhedzisiro =[±(ax * ay) + (bx * by)].
Iyo 18 × 18 Sum ye2 Mode Architecture
Iyo 18 × 18 Plus 36 Modhi
Kana yakagadziriswa se 18 × 18 Plus 36 modhi, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inogonesa chete pamusoro pekuwedzera. Iyi modhi inoshandisa equation yemhedzisiro = (ax * ay) + concatenate(bx[17:0],by[17:0]).
Iyo 18 × 18 Plus 36 Mode Architecture
Iwe unofanirwa kuseta iyo Representation fomati yepasi kuwanda y operand kune isina kusaina kana uchishandisa iyi modhi. Kana bhazi rekuisa risingasviki 36-bit mune iyi modhi, iwe unofanirwa kupa inodiwa yakasainwa yekuwedzera kuzadza iyo 36-bit yekupinda.
Kushandisa isingasviki 36-bit Operand Mu 18 × 18 Plus 36 Mode
Ex uyuample inoratidza magadzirirwo eCyclone 10 GX Native Fixed Point DSP IP musimboti wekushandisa 18 × 18 Plus 36 maitiro ekushanda ane yakasainwa 12-bit yekupinda data ye101010101010 (binary) pachinzvimbo che36-bit operand.
- Seta Representation fomati yepazasi multiplier x operand: kusaina.
- Seta Representation fomati yepazasi kuwandisa y operand: kune isina kusaina.
- Isa 'bx' hupamhi hwebhazi kusvika 18.
- Gadzirisa 'by' kuisa hupamhi hwebhazi kusvika 18.
- Ipa data re'111111111111111111' kune bx bhazi rekuisa.
- Ipa data re'111111101010101010' kune nebhazi rekupinza.
Iyo 18 × 18 Systolic Modhi
Mune 18 × 18 systolic mashandiro emodhi, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inogonesa kumusoro uye pasi vawandisa, yekuisa systolic rejista yekuwedzeredza yepamusoro, uye cheni systolic rejista yecheni mumasaini ekuisa. Paunogonesa kubuda kwekaseti, iyi modhi inotsigira mhedzisiro yekubuda kwehupamhi hwe44 bits. Kana iwe uchigonesa iyo accumulator ficha isina inobuda cascade, unogona kugadzirisa mhedzisiro yekubuda kwehupamhi kusvika 64 bits.
Iyo 18 × 18 Systolic Mode Architecture
Iyo 27 × 27 Modhi
Kana yagadziriswa se 27 × 27 modes, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inogonesa 27(yakasaina/isina kusaina) × 27(yakasaina/isina kusaina) kuwedzera. Bhazi rinobuda rinogona kutsigira kusvika ku64 bits ine accumulator/output cascade inogoneswa. Iyi modhi inoshandisa equation yemhedzisiro = ax * ay.
Iyo 27 × 27 Mode Architecture
Maitiro Ekusarudza
Iwo esarudzo ma modules anowanikwa muCyclone 10 GX Native Fixed Point DSP IP Core ndeaya:
- Input cascade
- Pre-adder
- Internal Coefficient
- Accumulator uye goho cascade
- Pipeline register
Input Cascade
Input cascade feature inotsigirwa neay uye nebhazi rekuisa. Paunoseta Gonesa kupinza cascade ye'ay' yekuisa kuHongu, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inotora mapinjiro kubva kumasaini ekupinza masaini pane ay bhazi rekuisa. Paunoseta Inogonesa kupinza cascade ye'by' yekupinda kuHongu, iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inotora zvinopinza kubva kune ay bhazi rekuisa pane nebhazi rekuisa.
Zvinokurudzirwa kugonesa marejista ekuisa ay uye/kana chero pese painoiswa cascade inogoneswa kuitira iko iko kushanda.
Iwe unogona kugonesa marejista ekunonoka kuti aenderane nezvinodiwa latency pakati perejista yekupinza uye rejista yekubuda. Pane 2 marejista ekunonoka mukati mepakati. Iyo yepamusoro yekunonoka rejista inoshandiswa kune ay kana scan-in yekuisa madoko nepo yepasi yekunonoka rejista inoshandiswa kune scanout inobuda ports. Aya marejista ekunonoka anotsigirwa mu18 × 18 yakazara modhi, 18 × 18 sums ye2 modes, uye 18 × 18 systolic modes.
Pre-adder
Iyo pre-adder inogona kugadzirwa mune zvinotevera zvigadziriso:
- Vaviri vakazvimiririra 18-bit (vakasaina / vasina kusaina) pre-adders.
- Imwe 26-bit pre-adder.
Kana wagonesa pre-adder mu 18 × 18 modhi yekuwanza, ay uye az anoshandiswa sebhazi rekupinza kuenda kumusoro pre-adder nepo by na bz richishandiswa sebhazi rekupinza kuenda kuzasi pre-adder. Paunogonesa pre-adder mu 27 × 27 kuwandisa modhi, ay uye az dzinoshandiswa sebhazi rekuisa kune pre-adder. Pre-adder inotsigira zvose kuwedzera nekubvisa. Kana ese ari maviri e-pre-adhi mukati meDSP block akashandiswa, anofanirwa kugovera mhando yekushanda yakafanana (kuwedzeredza kana kubvisa).
Internal Coefficient
Iyo yemukati coefficient inogona kutsigira anosvika masere anoramba aripo coefficients eakawanda mu 18-bit uye 27-bit modes. Kana iwe uchigonesa iyo yemukati coefficient chimiro, maviri ekuisa mabhazi ekudzora kusarudzwa kweiyo coefficient multiplexer anogadzirwa. Bhazi rekuisa coefsela rinoshandiswa kusarudza macoefficient afanotsanangurwa emupupuri wepamusoro uye bhazi rekuisa zano rinoshandiswa kusarudza macoefficient afanotsanangurwa emupupuri wepasi.
Iyo yemukati coefficient yekuchengetedza haitsigire dynamically controllable coefficient values uye yekunze coefficient kuchengetedza inodiwa kuita basa rakadaro.
Accumulator uye Output Cascade
Iyo accumulator module inogona kugoneswa kuita zvinotevera mashandiro:
- Kuwedzera kana kubvisa kushanda
- Yakarerekera kutenderedza mashandiro uchishandisa kukosha kwakagara kwe2N
- Dual channel accumulation
Kuti uite zvine simba kuwedzera kana kubvisa mashandiro eiyo accumulator, dzora chiratidzo chekuisa chekuramba. Pakutenderera kwakarerekera kuvhiya, unogona kutsanangura uye kurodha preset ye2N isati accumulator module isati yagoneswa nekutsanangura nhamba kune parameter N kukosha kweiyo preset yekugara. Nhamba N inofanira kuva isingasviki 64. Unogona kugonesa zvine simba kana kudzima kushandiswa kweiyo preset yekugara nekudzora chiratidzo cheloadconst. Iwe unogona kushandisa ichi chiitiko sechinoshanda muxing cheiyo kutenderera kukosha mune accumulator mhinduro nzira. Mutengo wakatakurwa uye mashandisirwo echiratidzo akaunganidzwa anongoenderana.
Iwe unogona kugonesa iyo kaviri accumulator rejista uchishandisa parameter Gonesa kaviri accumulator kuita kuunganidza kaviri. Iyo accumulator module inogona kutsigira kuvharirwa kweakawanda DSP mabhuroki ekuwedzera kana kubvisa mashandiro nekugonesa cheni yekupinza chiteshi uye cheni-kunze yekubuda chiteshi. Mune 18 × 18 systolic modhi, chete 44-bit yecheni yekupinza bhazi uye cheni kunze kwekubuda bhazi ichashandiswa. Nekudaro, ese 64-bit cheni mubhazi rekupinza anofanirwa kuve akabatana neketani-kunze inobuda bhazi kubva kune yakapfuura DSP block.
Pipeline Register
Iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti inotsigira imwe nhanho yerejista yepombi. Iyo pombi rejisita inotsigira anosvika matatu masosi masosi uye imwe asynchronous yakajeka chiratidzo chekuseta patsva marejista epombi. Pane marejista mashanu epaipi:
- data kupinza bhazi pombi regisita
- sub dynamic control signal pipeline register
- ramba dynamic control chiratidzo chepipeline register
- kuunganidza dynamic control signal pipeline register
- loadconst dynamic control pipeline register
Iwe unogona kusarudza kugonesa yega yega data yekuisa pombi marejista uye iyo ine simba yekudzora chiratidzo pombi inonyoresa yakazvimirira. Nekudaro, ese akagoneswa mapaipi marejista anofanirwa kushandisa imwechete wachi sosi.
Clock Scheme
Iyo yekupinza, pombi, uye inobuda marejista muCyclone 10 GX Native Fixed Point DSP IP musimboti inotsigira matatu wachi masosi / inogonesa uye maviri asynchronous clears. Ese marejista ekuisa anoshandisa aclr[0] uye ese pombi uye anobuda marejista anoshandisa aclr[1]. Imwe neimwe mhando yerejista inogona kusarudza imwe yeawa matatu masosi uye wachi inogonesa masaini. Paunogadzirisa iyo Cyclone 10 GX Native Fixed Point DSP IP musimboti kusvika 18 × 18 systolic mashandiro modhi, iyo Intel Quartus Prime software inoisa yekuisa systolic rejista uye ketani systolic rejista wachi sosi kune imwecheteyo wachi sosi seyakabuda rejista mukati.
Kana iwe uchigonesa iyo kaviri accumulator chimiro, iyo Intel Quartus Prime software inoisa iyo kaviri accumulator rejista wachi sosi kune imwechete wachi sosi seyakabuditsa rejista mukati.
Kuvhara Scheme Constraints
Iyi tebhu inoratidza zvipingamupinyi zvaunofanirwa kunyorera kune ese marejitari wachi wachi zvirongwa.
| Condition | Constraint |
| Kana pre-adder yabatidzwa | Wachi sosi yeay uye az marejista ekuisa anofanira kunge akafanana. |
| Wachi sosi ye by uye bz marejista ekuisa anofanira kunge akafanana. | |
| Kana marejista epaipi akabatidzwa | Chibviro chewachi yeese marejista epaipi anofanira kunge akafanana. |
| Kana chero ipi zvayo yekupinda inonyoresa kune dynamic control zviratidzo | Wachi sosi yemareji ekuisa e sub, acumulate, loadconst, uye negate inofanira kufanana. |
Cyclone 10 GX Native Fixed Point DSP IP Core Signals
Iyi inotevera nhamba inoratidza yekupinda uye yekubuda masaini eCyclone 10 GX Native Fixed Point DSP IP musimboti.
Cyclone 10 GX Native Fixed Point DSP IP Core Signals
Data Input Signals
| Zita rechiratidzo | Type | Upamhi | Tsanangudzo |
| demo[] | Input | 27 | Isa dhata bhazi pamusoro pekuwedzera. |
| ay[] | Input | 27 | Isa dhata bhazi pamusoro pekuwedzera.
Kana pre-adder yagoneswa, masaini aya anopihwa masaini ekuisa kune yepamusoro pre-adder. |
| az[] | Input | 26 | Aya masaini masaini ekuisa kumusoro pre-adder.
Aya masaini anongowanikwa kana pre-adder yagoneswa. Aya masaini haawanikwe mukati m18×18_plus36 kushanda mode. |
| bx[] | Input | 18 | Isa data bhasi kusvika pasi muwedzere.
Aya masaini haawanikwe mukati m27×27 kushanda mode. |
| ne[] | Input | 19 | Isa data bhasi kusvika pasi muwedzere.
Kana pre-adder yagoneswa, masaini aya anoshanda sezviratidzo zvekupinza kuzasi pre-adder. Aya masaini haawanikwe mukati m27×27 kushanda mode. |
| bz[] | Input | 18 | Aya masaini masaini ekuisa kuzasi pre-adder. Aya masaini anongowanikwa kana pre-adder yagoneswa. Aya masaini haawanikwe mukati m27×27 uye m18×18_plus36 maitiro ekushanda. |
Data Output Signals
| Zita rechiratidzo | Type | Upamhi | Decsription |
| mhinduro[] | Output | 64 | Kuburitsa data bhazi kubva kumusoro kuwandisa.
Aya masaini anotsigira anosvika makumi matatu nemanomwe mabhiti m18×18_yakazara kushanda mode. |
| mhedzisiro[] | Output | 37 | Output data bhazi kubva pazasi multiplier.
Aya masaini anongowanikwa mukati m18×18_yakazara kushanda mode. |
Clock, Gonesa, uye Zvakajeka Zviratidzo
| Zita rechiratidzo | Type | Upamhi | Tsanangudzo |
| clk[] | Input | 3 | Isa masaini ewachi pamarejista ese.
Aya masaini ewachi anongowanikwa chete kana chero regiyo rekuisa, marejista epombi, kana regita rekubuda rakaiswa Wachi0, Wachi1, kana Wachi2. • clk[0] = Wachi0 • clk[1] = Wachi1 • clk[2] = Wachi2 |
| ena[] | Input | 3 | Wachi inogonesa clk[2:0]. Ichi chiratidzo chiri kushanda-Pamusoro.
• ena[0] ndeye Wachi0 • ena[1] ndeye Wachi1 • ena[2] ndeye Wachi2 |
| aclr[] | Input | 2 | Asynchronous yakajeka yekupinza masaini kune ese marejista. Ichi chiratidzo chiri kushanda-Pamusoro.
Shandisa aclr[0] kune ese marejista ekuisa uye kushandiswa aclr[1] kune ese marejista epaipi uye regista yekubuda. Nekusagadzikana, chiratidzo ichi hachina kusimbiswa. |
Dynamic Control Signals
| Zita rechiratidzo | Type | Upamhi | Tsanangudzo |
| sub | Input | 1 | Input chiratidzo chekuwedzera kana kubvisa chinobuda chepamusoro chekuwedzera nekubuda kwepasi rekuwedzera.
• Dessert chiratidzo ichi kuti utaure kuwedzera kushanda. • Nyora chiratidzo ichi kuti utaure basa rekubvisa. Nekusagadzikana, chiratidzo ichi chinobviswa. Unogona kutaura kana dessert chiratidzo ichi panguva yekumhanya-nguva.(3) |
| negate | Input | 1 | Input chiratidzo chekuwedzera kana kubvisa huwandu hwepamusoro nepasi vawedzere nedata kubva kumasaini echainin.
• Dessert chiratidzo ichi kuti utaure kuwedzera kushanda. • Nyora chiratidzo ichi kuti utaure basa rekubvisa. Nekusagadzikana, chiratidzo ichi chinobviswa. Unogona kutaura kana dessert chiratidzo ichi panguva yekumhanya-nguva.(3) |
| kuunganidza | Input | 1 | Input chiratidzo kugonesa kana kudzima iyo accumulator chimiro.
• Dessert chiratidzo ichi kudzima accumulator chimiro. • Rongedza chiratidzo ichi kugonesa accumulator chimiro. Nekusagadzikana, chiratidzo ichi chinobviswa. Unogona kutaura kana dessert chiratidzo ichi panguva yekumhanya-nguva.(3) |
| loadconst | Input | 1 | Input sign yekugonesa kana kudzima kurodha nguva dzose chimiro.
• Deassert chiratidzo ichi kuti uvhare mutoro unogara uripo. • Rongedza chiratidzo ichi kuti ugonese basa rinogara riripo. Nekusagadzikana, chiratidzo ichi chinobviswa. Unogona kutaura kana dessert chiratidzo ichi panguva yekumhanya-nguva.(3) |
Internal Coeficient Signals
| Zita rechiratidzo | Type | Upamhi | Tsanangudzo |
| coefsela[] | Input | 3 | Sarudzo yekupinza masiginecha ye8 coefficient values inotsanangurwa nemushandisi kune yekumusoro inowandisa. Iyo coefficient values inochengetwa mundangariro yemukati uye inotsanangurwa neparameter coef_a_0 ku coef_a_7.
• coefsela[2:0] = 000 inoreva coef_a_0 • coefsela[2:0] = 001 inoreva coef_a_1 • coelsela[2:0] = 010 inoreva coef_a_2 • … zvichingodaro. Aya masaini anongowanikwa kana iyo yemukati coefficient ficha yakagoneswa. |
| coefselb[] | Input | 3 | Sarudzo yekupinza masiginecha ye8 coefficient values inotsanangurwa nemushandisi kune yepasi pekuwedzera. Iyo coefficient values inochengetwa mundangariro yemukati uye inotsanangurwa neparameter coef_b_0 ku coef_b_7.
• coefselb[2:0] = 000 inoreva coef_b_0 • coefselb[2:0] = 001 inoreva coef_b_1 • coelselb[2:0] = 010 inoreva coef_b_2 • … zvichingodaro. Aya masaini anongowanikwa kana iyo yemukati coefficient ficha yakagoneswa. |
Isa maSignals eCascade
| Zita rechiratidzo | Type | Upamhi | Tsanangudzo |
| scanin[] | Input | 27 | Pinza data bhasi rekuisa cascade module.
Batanidza masaini aya kune scanout masiginecha kubva kune yakapfuura DSP musimboti. |
| scanout[] | Ouput | 27 | Kuburitsa data bhazi reiyo yekuisa cascade module.
Batanidza aya masaini kune scanin masiginecha eiyo inotevera DSP musimboti. |
Kubuda Cascade Signals
| Zita rechiratidzo | Type | Upamhi | Tsanangudzo |
| chain[] | Input | 64 | Pinza data bhasi rekubuda cascade module.
Batanidza masaini aya kune masaini masaini kubva kune yakapfuura DSP musimboti. |
| chainout[] | Output | 64 | Kuburitsa data bhazi reinobuda cascade module.
Batanidza masaini aya kune masaini masaini eiyo inotevera DSP musimboti. |
Gwaro rekudzokorora Nhoroondo yeCyclone 10 GX Native Fixed Point DSP IP Core User Guide
| Date | Version | Kuchinja |
| Mbudzi 2017 | 2017.11.06 | Kusunungurwa kwekutanga. |
Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumira kushanda kweFPGA yayo uye semiconductor zvigadzirwa kune zvazvino zvakatemwa zvinoenderana neIntel yakajairwa waranti asi inochengeta kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
Mamwe mazita nemhando anogona kunzi zvinhu zvevamwe.
Zvinyorwa / Zvishandiso
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intel UG-20094 Cyclone 10 GX Native Fixed Point DSP IP Core [pdf] Bhuku reMushandisi UG-20094 Cyclone 10 GX Native Fixed Point DSP IP Core, UG-20094, Cyclone 10 GX Native Fixed Point DSP IP Core, Native Fixed Point DSP IP Core, Fixed Point DSP IP Core, DSP IP Core |
