Intel UG-20094 Cyclone 10 GX Native Fixed Point DSP IP Core

Intel® Cyclone® 10 GX Native Fixed Point DSP IP Core User Guide

Intel Cyclone® 10 GX Native Fixed Point DSP IP core imalimbitsa ndikuwongolera chipika chimodzi cha Intel Cyclone 10 GX Variable Precision Digital Signal Processing (DSP). Cyclone 10 GX Native Fixed Point DSP IP core imapezeka pazida za Intel Cyclone 10 GX zokha.

Cyclone 10 GX Native Fixed Point DSP IP Core Functional Block Diagram

Zambiri Zogwirizana
Chiyambi cha Intel FPGA IP Cores.

Cyclone 10 GX Native Fixed Point DSP IP Core Features

Cyclone 10 GX Native Fixed Point DSP IP core imathandizira izi:

• Kuchita bwino kwambiri, kukhathamiritsa mphamvu, komanso kulembetsa kwathunthu kuchulutsa
• 18-bit ndi 27-bit mawu kutalika
• Awiri 18 × 19 ochulukitsa kapena 27 × 27 kuchulukitsa pa chipika cha DSP
• Zowonjezera, kuchotsa, ndi regista ya 64-bit yophatikiza kawiri kuti iphatikize zotsatira zochulutsa
• Kutaya 19-bit kapena 27-bit pamene pre-adder yayimitsidwa ndikutsika 18-bit pamene pre-adder imagwiritsidwa ntchito kupanga mzere wochedwetsapo kuti usefe.
• Kutulutsa mabasi a 64-bit kuti afalitse zotsatira kuchokera pa block imodzi kupita ku block ina popanda thandizo lakunja.
• Pre-adder yolimba imathandizidwa mumitundu ya 19-bit ndi 27-bit pazosefera zofananira
• Internal coefficient registry banki mumitundu yonse ya 18-bit ndi 27-bit pakukhazikitsa zosefera
• Zosefera za 18-bit ndi 27-bit systolic finite impulse response (FIR) zokhala ndi chowonjezera chogawa

Kuyambapo

Mutuwu umapereka chidziwitso chambiriview ya Intel FPGA IP core design flow kukuthandizani kuti muyambe mwachangu ndi Cyclone 10 GX Native Fixed Point DSP IP core. Intel FPGA IP Library imayikidwa ngati gawo la Intel Quartus® Prime install process. Mutha kusankha ndikusintha mtundu uliwonse wa Intel FPGA IP kuchokera ku library. Intel imapereka mkonzi wophatikizira womwe umakulolani kuti musinthe makonda anu a Intel FPGA DSP IP kuti muthandizire ntchito zosiyanasiyana. Mkonzi wa parameter amakuwongolerani pakusintha kwamitengo ndikusankha madoko osankha.

Zambiri Zogwirizana

• Chiyambi cha Intel FPGA IP Cores
  Amapereka zambiri za Intel FPGA IP cores, kuphatikiza parameterizing, kupanga, kukweza, ndi kuyerekezera ma IP cores.
• Kupanga Zolemba Zodziyimira pawokha za IP ndi Platform Designer (Standard) Simulatio Scripts
  Pangani zolemba zofananira zomwe sizikufuna kusinthidwa pamanja pamapulogalamu kapena kukweza mtundu wa IP.
• Ntchito Zabwino Kwambiri Zoyang'anira Ntchito
  Malangizo oyendetsera bwino komanso kusuntha kwa polojekiti yanu ndi IP files.

Cyclone 10 GX Native Fixed Point DSP IP Core Parameter Settings

Mutha kusintha makonda a Cyclone 10 GX Native Fixed Point DSP IP pofotokoza magawowo pogwiritsa ntchito pulogalamu ya Intel Quartus Prime.

Operation Mode Tab

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
Chonde sankhani mawonekedwe opangira	operation_mode	m18×18_full m18×18_sumof2 m18×18_plus36 m18×18_systolic m27×27	Sankhani ankafuna ntchito akafuna.
Kusintha kwa Multiplier
Mtundu woyimira wochulukira kwambiri x operand	sign_max	osayinidwa osasainidwa	Tchulani mtundu woyimira wochulukira pamwamba x operand.

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
Mawonekedwe oyimira a ochulutsa y apamwamba kwambiri	sign_may	osayinidwa osasainidwa	Tchulani mtundu woyimira wa ochulutsa y apamwamba.
Mtundu woyimira pansi wochulukitsa x operand	sign_mbx	osayinidwa osasainidwa	Tchulani mawonekedwe oyimira pansi ochulukitsa x operand.
Mtundu woyimira pansi wochulukitsa y operand	sign_mby	osayinidwa osasainidwa	Tchulani mawonekedwe oyimira pansi ochulukitsa y operand. Nthawi zonse sankhani osasainidwa za m18×18_plus36 .
Yambitsani doko la 'sub'	athe_sub	Ayi Inde	Sankhani Inde kuti athe sub port.
Lembani zolowetsa za 'sub' za zochulukitsa	sub_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kufotokoza chizindikiro cha wotchi yolowera pa regista yaing'ono.
Lowetsani Cascade
Yambitsani zolowetsa za 'ay'	ay_use_scan_in	Ayi Inde	Sankhani Inde kuti mutsegule moduli ya cascade pakulowetsa kwa data iliyonse. Mukayatsa gawo lolowera la cascade, Cyclone 10 GX Native Fixed Point DSP IP core imagwiritsa ntchito ma siginoni olowetsamo ngati cholowa m'malo mwa ma siginali ay.
Yambitsani zolowetsa za 'by'	mwa_use_scan_in	Ayi Inde	Sankhani Inde kuti mutsegule moduli ya cascade yolowetsa polowetsa deta. Mukayatsa gawo lolowera la cascade, Cyclone 10 GX Native Fixed Point DSP IP core imagwiritsa ntchito ma siginolo a ay monga kulowetsa m'malo motengera ma siginali.
Yambitsani kaundula wa data	delay_scan_out_ay	Ayi Inde	Sankhani Inde kuti mutsegule kaundula wochedwa pakati pa ay ndi kaundula wolowera. Izi sizikugwira ntchito m18×18_plus36 ndi m27x27 ntchito mode.

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
Yambitsani deta polembetsa mochedwa	delay_scan_out_by	Ayi Inde	Sankhani Inde kuti muzitha kulembetsa kuchedwa pakati pa zolembera zolowera ndi mabasi a scanout. Izi sizikugwira ntchito m18×18_plus36 ndi m27x27 ntchito mode.
Yambitsani scanout port	gui_scanout_enable	Ayi Inde	Sankhani Inde kuti athe scanout zotuluka basi.
'scanout' m'lifupi mwa basi	scan_out_width	1-27	Tchulani m'lifupi mwake scanout zotuluka basi.
Kukonzekera kwa Data 'x'
'ax' m'lifupi mwa basi	ax_width	1-27	Tchulani m'lifupi mwake basi yolowetsa nkhwangwa.(1)
Lembani 'nkhwangwa' yochulukitsa	ax_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowera pa regista ya nkhwangwa. kaundula wa nkhwangwa palibe ngati mukhazikitsa 'ax' ntchito source ku 'ng'ombe'.
'bx' m'lifupi mwa basi	bx_width	1-18	Tchulani m'lifupi mwake bx lolowera basi.(1)
Lembani zolowetsa za 'bx' za ochulukitsa	bx_wotchi	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowera pa regista ya bx. bx kaundula sapezeka ngati mukhazikitsa 'bx' gwero la ntchito ku 'ng'ombe'.
Kusintha kwa Data 'y'
'ay' kapena 'scanin' m'lifupi mwa basi	ay_scan_in_width	1-27	Tchulani m'lifupi mwa basi ya ay kapena scanin.(1)
Lembani zolowetsa 'ay' kapena lowetsani 'scanin' pazochulukitsa	ayi_scan_in_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi ya ay kapena kaundula wa scanin.
'by' m'lifupi mwa basi	mwa_m'lifupi	1-19	Tchulani m'lifupi mwa basi yolowera.(1)

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
Lembetsani zolowetsa 'ndi' zochulukitsa	pa_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kufotokoza chizindikiro cha wotchi yolowera kapena scanin kaundula.(1)
Kukonzekera kwa 'zotsatira'
'zotsatira' m'lifupi mwa bus	zotsatira_a_width	1-64	Tchulani m'lifupi mwake resulta zotuluka basi.
'resultb' m'lifupi mwa bus	zotsatira_b_width	1-64	Tchulani m'lifupi mwa basi yotulutsa zotsatira. resultb imapezeka mukamagwiritsa ntchito operation_mode m18×18_zonse.
Gwiritsani ntchito registry yotulutsa	output_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowera pazotsatira ndi zolembera zotuluka.

Pre-adder Tab

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
'ay' gwero la ntchito	operand_source_may	input pread	Tchulani gwero la ntchito ya ay. Sankhani preadder kuti athe pre-adder module kuti achulukitse pamwamba. Zokonda pa ay ndi gwero la operand ziyenera kukhala zofanana.
'by' operand source	operand_source_mby	input pread	Tchulani gwero la operand polowetsa. Sankhani preadder kuti athe pre-adder module kuti achulukitse pansi. Zokonda pa ay ndi gwero la operand ziyenera kukhala zofanana.
Khazikitsani pre-adder ntchito yochotsa	pread_subtract_a	Ayi Inde	Sankhani Inde kutchula ntchito yochotsa kwa pre-adder module yochulukitsira pamwamba. Zokonda za Pre-adder zochulutsa pamwamba ndi pansi ziyenera kukhala zofanana.
Khazikitsani ntchito ya pre-adder b kuti ichotse	pread_subtract_b	Ayi Inde	Sankhani Inde kutchulapo ntchito yochotsa kwa pre-adder module kwa ochulukitsa pansi. Zokonda za Pre-adder zochulutsa pamwamba ndi pansi ziyenera kukhala zofanana.
Kusintha kwa Data 'z'
'az' m'lifupi mwa basi	az_width	1-26	Tchulani m'lifupi mwa basi ya az.(1)
Lembetsani zolowetsa 'az' za zochulukitsa	az_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowera pamakaundula a az. Zokonda pa wotchi ya ay ndi az zolembera ziyenera kukhala zofanana.
'bz' m'lifupi mwa basi	bz_width	1-18	Tchulani m'lifupi mwa basi yolowetsa ya bz.(1)
Lembetsani zolowetsa 'bz' za zochulukitsa	bz_koloko	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kufotokoza chizindikiro cha wotchi yolowera pamarejista olowetsa a bz. Zokonda pa wotchi ya by ndi bz zolembera ziyenera kukhala zofanana.

Internal Coefficient Tab

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
'ax' ntchito source	operand_source_max	kulowa khofi	Tchulani kumene operand akuchokera. Sankhani khofi kuti mulole gawo lamkati la coefficient kuti muwonjezere zambiri. Sankhani Ayi za Lembani 'nkhwangwa' yochulukitsa parameter mukatsegula gawo lamkati la coefficient.

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
			Zokonda pa nkhwangwa ndi bx operand source ziyenera kukhala zofanana.
'bx' gwero la ntchito	operand_source_mbx	kulowa khofi	Tchulani komwe kumayambira mabasi olowera a bx. Sankhani khofi kuti mulole gawo lamkati la coefficient kuti muwonjezere zambiri. Sankhani Ayi za Lembani zolowetsa za 'bx' za ochulukitsa parameter mukatsegula gawo lamkati la coefficient. Zokonda pa nkhwangwa ndi bx operand source ziyenera kukhala zofanana.
'coefsel' Input Register Configuration
Lembani zolowetsa za 'coefsela' za zochulukitsa	coef_sel_a_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowetsa m'kaundula wa coefsela.
Lembani zolowetsa za 'coefselb' za zochulukitsa	coef_sel_b_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowera pamakaundula a coefselb.
Kusintha kwa Coefficient Storage
coef_a_0-7	coef_a_0-7	Nambala	Tchulani ma coefficient a mabasi olowetsa khwangwala. Kwa mawonekedwe a 18-bit, mtengo wolowera kwambiri ndi 218 - 1. Pa ntchito ya 27-bit, mtengo wapamwamba ndi 227 - 1.
coef_b_0-7	coef_b_0-7	Nambala	Tchulani ma coefficient a basi ya bx.

Accumulator/Output Cascade Tab

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
Yambitsani doko la 'accumulate'	athe_kusonkhanitsa	Ayi Inde	Sankhani Inde kuti athe accumulator port.
Yambitsani doko la 'negate'	athe_negate	Ayi Inde	Sankhani Inde kuti athe negate port.
Yambitsani doko la 'loadconst'	enable_loadconst	Ayi Inde	Sankhani Inde kuti athe doko laloadconst.
Kulembetsa zolowetsa 'kusonkhanitsa' kwa accumulator	acumulate_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0 , Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowetsamo zolembera zolembera.

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
Lembani zolowetsa za 'loadconst' za accumulator	load_const_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kufotokoza chizindikiro cha wotchi yolowera pamakaundula olowetsa a loadconst.
Lembani zolowetsa za 'negate' za adder unit	negate_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowera pamakaundula oletsa zolowetsa.
Yambitsani kuchulukitsa kawiri	enable_double_accum	Ayi Inde	Sankhani Inde kuti athe pawiri accumulator Mbali.
N mtengo wokhazikika	load_const_value	0-63	Tchulani mtengo wokhazikika wokhazikika. Mtengo uwu ukhoza kukhala 2N ku N ndiye mtengo wokhazikika wokhazikika.
Yambitsani doko la chainin	use_chainadder	Ayi Inde	Sankhani Inde kuti athe kutulutsa gawo la cascade ndi mabasi olowera chachainin. Zotulutsa zotulutsa sizimatheka m18×18_zonse ntchito mode.
Yambitsani doko la chainout	gui_chainout_enable	Ayi Inde	Sankhani Inde kuti athe kutulutsa chainout bus. Zotulutsa zotulutsa sizimatheka m18×18_zonse ntchito mode.

Pipelining Tab

Parameter	IP Yopangidwa ndi Parameter	Mtengo	Kufotokozera
Onjezani kaundula wa mapaipi olowera ku siginali ya data (x/y/z/coefsel)	input_pipeline_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi ya x, y, z, coefsela ndi kaundula wa mapaipi a coefselb.
Onjezani kaundula wa mapaipi olowera ku sigino ya data ya 'sub'	sub_pipeline_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowetsa m'kaundula wa sub pipeline. (2)
Onjezani kaundula wa mapaipi olowera ku siginecha ya 'acumulate'	accum_pipeline_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowetsamo regista yolowetsa mapaipi.(2)
Onjezani kaundula wa mapaipi olowera ku sigino ya data ya 'loadconst'	load_const_pipeline_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowera pa regista yolowetsa mapaipi a loadconst.(2)
Onjezani kaundula wa mapaipi olowera ku siginecha ya 'negate'	negate_pipeline_clock	Ayi Clock0 Clock1 Clock2	Sankhani Koloko0, Koloko1, kapena Koloko2 kuyatsa ndi kutchula chizindikiro cha wotchi yolowera pa regista yoletsa mapaipi.(2)

M'lifupi Lalikulu Lalikulu Lalikulu Pamachitidwe Ogwiritsa Ntchito
Mutha kusintha makulidwe a data pazolowetsa za x, y, ndi z monga zafotokozedwera patebulo.

Ma regista onse olowetsa mapaipi azizindikiro zowongolera ayenera kukhala ndi wotchi yofanana.

Operation Mode	M'lifupi Lalikulu la Data
	ax	ay	az	bx	by	bz
Popanda Pre-adder kapena Internal Coefficient
m18×18_zonse	18 (yosaina) 18 (osasainidwa)	19 (yosaina) 18 (osasainidwa)	Osagwiritsidwa ntchito	18 (yosaina) 18 (osasainidwa)	19 (yosaina) 18 (osasainidwa)	Osagwiritsidwa ntchito
m18×18_sumof2
m18×18_systolic
m18×18_plus36
m27 × 27	27 (yosaina) 27 (osasainidwa)		Osagwiritsidwa ntchito
Ndi Pre-adder Mbali Yokha
m18×18_zonse	18 (yosaina) 18 (osasainidwa)
m18×18_sumof2
m18×18_systolic
m27 × 27	27 (yosaina) 27 (osasainidwa)	26 (yosaina) 26 (osasainidwa)		Osagwiritsidwa ntchito
Ndi Internal Coefficient Mbali Yokha
m18×18_zonse	Osagwiritsidwa ntchito	19 (yosaina) 18 (osasainidwa)	Osagwiritsidwa ntchito		19 (yosaina) 18 (osasainidwa)	Osagwiritsidwa ntchito
m18×18_sumof2
m18×18_systolic
m27 × 27		27 (yosaina) 27 (osasainidwa)			Osagwiritsidwa ntchito

Kufotokozera Kwantchito

Cyclone 10 GX Native Fixed Point DSP IP core imakhala ndi zomangamanga za 2; 18 × 18 kuchulukitsa ndi 27 × 27 kuchulukitsa. Kukhazikika kulikonse kwa Cyclone 10 GX Native Fixed Point DSP IP pachimake kumapanga 1 yokha mwa 2 zomanga kutengera njira zosankhidwa. Mutha kuyatsa ma modules kuti mugwiritse ntchito.

Zambiri Zogwirizana
Ma Block Precision DSP osinthika mu mutu wa Intel Cyclone 10 GX Devices, Intel Cyclone 10 GX Core Fabric ndi General Purpose I/Os Handbook.

Njira Zogwirira Ntchito

Cyclone 10 GX Native Fixed Point DSP IP core imathandizira njira zisanu zogwirira ntchito:

• 18 × 18 Full Mode
• 18 × 18 Sum ya 2 Mode
• Njira ya 18 × 18 Plus 36
• 18 × 18 Systolic Mode
• 27 × 27 Mode

18 × 18 Full Mode
Ikasinthidwa kukhala 18 × 18 mode wathunthu, Cyclone 10 GX Native Fixed Point DSP IP core imagwira ntchito ngati awiri odziyimira pawokha 18 (osayinidwa / osasainidwa) × 19 (osayinidwa) kapena 18
(osaina / osasainidwa) × 18 (osayinidwa) ochulukitsa omwe ali ndi 37-bit. Njira iyi imagwiritsa ntchito ma equation awa:

• resulta = nkhwangwa * ayi
• resultb = bx * ndi

18 × 18 Full Mode Zomangamanga

18 × 18 Sum ya 2 Mode
Mu 18 × 18 Sum of 2 modes, Cyclone 10 GX Native Fixed Point DSP IP core imathandiza ochulukitsa apamwamba ndi pansi ndipo amapanga zotsatira kuchokera kuonjezera kapena kuchotsa pakati pa ochulukitsa 2. Chizindikiro cha sub-dynamic control chimawongolera adder kuti achite ntchito zowonjezera kapena zochotsa. Kuchuluka kwa zotsatira za Cyclone 10 GX Native Fixed Point DSP IP core kumatha kuthandizira mpaka ma bits 64 mukamatsegula accumulator/output cascade. Mchitidwewu umagwiritsa ntchito equation ya resulta =[±(ax * ay) + (bx * by)].

18 × 18 Sum of 2 Mode Architecture

Njira ya 18 × 18 Plus 36
Ikakonzedwa ngati 18 × 18 Plus 36 mode, Cyclone 10 GX Native Fixed Point DSP IP core imathandiza ochulutsa pamwamba okha. Mchitidwewu umagwiritsa ntchito equation ya resulta = (ax * ay) + concatenate(bx[17:0],by[17:0]).

Zomangamanga za 18 × 18 Plus 36 Mode

Muyenera kuyika mawonekedwe a Representation kwa ochulukitsa pansi ochulukitsa y operand kuti asasainidwe mukamagwiritsa ntchito njirayi. Pamene mabasi olowera ndi ochepera 36-bit mwanjira iyi, mukuyenera kupereka zowonjezera zomwe zasaina kuti mudzaze zolowetsa za 36-bit.

Kugwiritsa Ntchito Pang'ono ndi 36-bit Operand Mu 18 × 18 Plus 36 Mode
Ex iziample akuwonetsa momwe mungasinthire maziko a Cyclone 10 GX Native Fixed Point DSP IP kuti agwiritse ntchito 18 × 18 Plus 36 mode ndi data yolowetsa 12-bit yosainidwa ya 101010101010 (binary) m'malo mwa 36-bit operand.

1. Khazikitsani mtundu woyimilira wa ochulukitsa pansi x operand: kuti asayinidwe.
2. Khazikitsani mtundu woyimilira wa ochulukitsa ochulukitsa pansi: mpaka osasainidwa.
3. Khazikitsani 'bx' m'lifupi mwa basi kukhala 18.
4. Khazikitsani 'by' m'lifupi mwa basi kufika 18.
5. Perekani zidziwitso za '111111111111111111' ku bx lolowera basi.
6. Perekani zidziwitso za '111111101010101010' podutsa basi.

18 × 18 Systolic Mode
Mumayendedwe a 18 × 18 systolic, Cyclone 10 GX Native Fixed Point DSP IP pachimake imathandizira ochulutsa pamwamba ndi pansi, kaundula wa systolic wochulukitsa, ndi kaundula wa systolic wa unyolo mumasinthidwe olowera. Pamene mutsegula kutuluka kwa cascade, njirayi imathandizira zotsatira zotuluka mu 44 bits. Mukatsegula gawo la accumulator popanda kutulutsa, mutha kusintha kuchuluka kwa zotsatirazo kukhala ma bits 64.

18 × 18 Systolic Mode Architecture

27 × 27 Mode
Mukakonzedwa ngati 27 × 27 modes, Cyclone 10 GX Native Fixed Point DSP IP core imathandiza 27 (osayinidwa / osayinidwa) × 27 (osayinidwa / osayinidwa) ochulukitsa. Basi yotulutsa imatha kuthandizira mpaka ma bits 64 ndi accumulator/output cascade wothandizidwa. Njira iyi imagwiritsa ntchito equation ya resulta = ax * ay.

27 × 27 Mode Zomangamanga

Zosankha Zosankha

Ma module omwe akupezeka mu Cyclone 10 GX Native Fixed Point DSP IP Core ndi awa:

• Lowetsani cascade
• Owonjezera
• Internal Coefficient
• Accumulator ndi linanena bungwe cascacade
• Kaundula wa mapaipi

Lowetsani Cascade
Zolowetsa za cascade zimathandizidwa ndi ay ndi mabasi olowetsa. Mukakhazikitsa Enable input cascade kuti 'ay' alowe ku Inde, Cyclone 10 GX Native Fixed Point DSP IP core itenga zolowa kuchokera ku siginecha zolowetsa m'malo molowetsa basi. Mukakhazikitsa Enable input cascade kuti 'by' alowe ku Inde, Cyclone 10 GX Native Fixed Point DSP IP core itenga zolowa kuchokera ku mabasi olowera m'malo molowera basi.

Ndikoyenera kuti mutsegule zolembera za ay ndi/kapena nthawi iliyonse ikatsegulidwa kuti pulogalamuyo ikhale yolondola.

Mutha kuloleza zolembetsa zochedwetsa kuti zigwirizane ndi kufunikira kwa latency pakati pa zolembera zolembera ndi zolembera zotulutsa. Pali 2 zolembera zochedwa pachimake. Kaundula wapamwamba wochedwa amagwiritsidwa ntchito polowera ma ay kapena scan-in input pomwe zolembera zochedwa zapansi zimagwiritsidwa ntchito pamadoko otuluka. Zolembera zochedwa izi zimathandizidwa mu 18 × 18 mode, 18 × 18 sums of 2 modes, ndi 18 × 18 systolic modes.

Pre-adder

Pre-adder ikhoza kukhazikitsidwa muzosintha zotsatirazi:

• Owonjezera awiri odziyimira pawokha a 18-bit (osayinidwa / osasainidwa).
• Mmodzi wa 26-bit pre-adder.

Mukayatsa pre-adder mu 18 × 18 modes kuchulutsa, ay ndi az amagwiritsidwa ntchito ngati mabasi olowera pamwamba pa adder pomwe by ndi bz amagwiritsidwa ntchito ngati mabasi olowera pansi pa adder. Mukayatsa pre-adder mu 27 × 27 kuchulukitsa, ay ndi az amagwiritsidwa ntchito ngati basi yolowera ku pre-adder. Pre-adder imathandizira kuwonjezera ndi kuchotsa. Zowonjezera zonse ziwiri zomwe zili mkati mwa chipika cha DSP chimodzi zimagwiritsidwa ntchito, ziyenera kugawana mtundu womwewo wa opareshoni (mwina kuwonjezera kapena kuchotsa).

Internal Coefficient
Coefficient yamkati imatha kuthandizira mpaka ma coefficient asanu ndi atatu osasinthika a ma multiplicands mu 18-bit ndi 27-bit modes. Mukayatsa mawonekedwe amkati, mabasi awiri olowera kuti aziwongolera kusankha kwa coefficient multiplexer adzapangidwa. Basi yolowetsa ya coefsela imagwiritsidwa ntchito posankha ma coefficients ofotokozedweratu a chochulukitsira pamwamba ndipo basi yolowetsa uphungu imagwiritsidwa ntchito kusankha ma coefficients omwe afotokozedweratu a ochulukitsira pansi.

Zosungirako zamkati zamkati sizigwirizana ndi ma dynamically controllable coefficient values ​​ndipo kusungirako kwakunja kumafunika kuti muchite ntchitoyi.

Accumulator ndi Output Cascade

The accumulator module imatha kuthandizidwa kuchita izi:

• Ntchito yowonjezera kapena kuchotsa
• Kuzungulira mokondera pogwiritsa ntchito mtengo wokhazikika wa 2N
• Kuwunjika kwanjira ziwiri

Kuti mugwire ntchito yowonjezeretsa kapena yochotsa, yang'anirani chizindikiro cha negate. Kuti mugwire ntchito mokondera, mutha kufotokozera ndikuyika zokhazikika za 2N gawo la accumulator lisanatsegulidwe pofotokoza chiwerengero cha nambala ya N mtengo wanthawi zonse. Nambala ya N iyenera kukhala yochepera 64. Mutha kuloleza kapena kuletsa kugwiritsa ntchito nthawi zonse zomwe zakhazikitsidwa poyang'anira chizindikiro cha loadconst. Mutha kugwiritsa ntchito ntchitoyi ngati muxing wokhazikika wamtengo wozungulira munjira yoyankhira accumulator. Mtengo wonyamula komanso kugwiritsa ntchito ma siginecha zomwe zasonkhanitsidwa zimayenderana.

Mutha kuloleza kulembetsa kophatikiza kawiri pogwiritsa ntchito chizindikiro Yambitsani kusonkhanitsa kawiri kuti mupange kusonkhanitsa kawiri. Gawo la accumulator limatha kuthandizira kulumikizidwa kwa midadada yambiri ya DSP kuti muwonjezere kapena kuchotsa ntchito pothandizira doko lolowera unyolo ndi doko lotulutsa unyolo. Mu 18 × 18 systolic mode, 44-bit yokha ya mabasi olowetsa unyolo ndi ma chain out bus adzagwiritsidwa ntchito. Komabe, maunyolo onse a 64-bit mu basi yolowetsa ayenera kulumikizidwa ndi mabasi otuluka kuchokera ku block ya DSP yapitayi.

Regista ya Pipeline

Cyclone 10 GX Native Fixed Point DSP IP core imathandizira gawo limodzi la kaundula wa mapaipi. Kaundula wa mapaipi amathandizira mpaka mawotchi atatu ndi chizindikiro chimodzi chowoneka bwino chokhazikitsanso kaundula wa mapaipi. Pali ma regista asanu a mapaipi:

• kaundula wa mapaipi a mabasi a data
• sub dynamic control sign registry
• negate dynamic control sign pipeline registry
• sonkhanitsani kaundula wa mapaipi owongolera amphamvu
• loadconst dynamic control pipeline register

Mutha kusankha kuti mulembetse kaundula wa mapaipi a mabasi aliwonse ndi ma siginolo a dynamic control pipeline amalembetsa paokha. Komabe, zolembetsa zonse zamapaipi zoyatsidwa ziyenera kugwiritsa ntchito wotchi yomweyo.

Clock Scheme

Zolowetsa, mapaipi, ndi zolembera zotuluka mu Cyclone 10 GX Native Fixed Point DSP IP pachimake zimathandizira mawotchi / mawotchi atatu ndi zowunikira ziwiri zosasinthika. Ma regista onse olowetsa amagwiritsa ntchito aclr[0] ndipo zolembera zonse za mapaipi ndi zotulutsa zimagwiritsa ntchito aclr[1]. Mtundu uliwonse wolembetsa ukhoza kusankha chimodzi mwazinthu zitatu za mawotchi ndi mawotchi amathandizira ma sign. Mukakonza Cyclone 10 GX Native Fixed Point DSP IP pachimake kukhala 18 × 18 systolic systolic mode, Intel Quartus Prime software imayika kaundula wa systolic ndi chain systolic register wotchi gwero la wotchi yomweyo monga zolembera zotuluka mkati.

Mukatsegula chowonjezera chapawiri, pulogalamu ya Intel Quartus Prime imayika gwero la wotchi yophatikizira pawiri ku gwero la wotchi yomweyo monga zolembera zotulutsa mkati.

Zoletsa za Clock Scheme
Tsambali likuwonetsa zopinga zomwe muyenera kuyika pamakina onse owonera mawotchi.

Mkhalidwe	Kukakamiza
Pamene pre-adder yayatsidwa	Gwero la wotchi ya zolembera za ay ndi az ziyenera kukhala zofanana.

	Gwero la wotchi ya by ndi bz zolembera ziyenera kukhala zofanana.
Pamene zolembera za mapaipi zimayatsidwa	Gwero la mawotchi pamakaundula onse a mapaipi ayenera kukhala ofanana.
Pamene aliyense wa kulowa m'kaundula kwa zosintha ulamuliro zizindikiro	Gwero la wotchi yolembera zolembera za sub, accumulate, loadconst, ndi negate ziyenera kukhala zofanana.

Cyclone 10 GX Native Fixed Point DSP IP Core Signals

Chithunzi chotsatira chikuwonetsa zolowetsa ndi zotuluka za Cyclone 10 GX Native Fixed Point DSP IP pachimake.

Cyclone 10 GX Native Fixed Point DSP IP Core Signals

Zizindikiro Zolowetsa Data

Dzina la Signal	Mtundu	M'lifupi	Kufotokozera
nkhwangwa[]	Zolowetsa	27	Lowetsani basi ya data kuti muchulukitse.
ayi[]	Zolowetsa	27	Lowetsani basi ya data kuti muchulukitse. Pamene pre-adder yayatsidwa, ma siginowa amatumizidwa ngati ma siginoloji olowera pamwamba pa pre-adder.
azi[]	Zolowetsa	26	Zizindikirozi ndi zizindikiro zolowera ku pre-adder yapamwamba. Zizindikirozi zimapezeka kokha pamene pre-adder yayatsidwa. Zizindikirozi sizikupezeka mkati m18×18_plus36 ntchito mode.
bx[]	Zolowetsa	18	Lowetsani basi ya data kupita kuchulukitsira pansi. Zizindikirozi sizikupezeka mkati m27 × 27 ntchito mode.
ndi[]	Zolowetsa	19	Lowetsani basi ya data kupita kuchulukitsira pansi. Pamene pre-adder yayatsidwa, zizindikirozi zimakhala ngati zizindikiro zolowera pansi pa pre-adder. Zizindikirozi sizikupezeka mkati m27 × 27 ntchito mode.
bz[]	Zolowetsa	18	Zizindikirozi ndi zizindikiro zolowera pansi pa pre-adder. Zizindikirozi zimapezeka kokha pamene pre-adder yayatsidwa. Zizindikirozi sizikupezeka mkati m27 × 27 ndi m18×18_plus36 modes ntchito.

Zizindikiro Zotulutsa Data

Dzina la Signal	Mtundu	M'lifupi	Kutumiza
zotsatira[]	Zotulutsa	64	Mabasi otulutsa deta kuchokera ku ochulukitsa apamwamba. Zizindikirozi zimathandizira mpaka ma bits 37 m18×18_zonse ntchito mode.
zotsatira[]	Zotulutsa	37	Mabasi otulutsa data kuchokera pansi ochulukitsa. Zizindikirozi zimapezeka kokha mkati m18×18_zonse ntchito mode.

Wotchi, Yambitsani, ndi Zizindikiro Zomveka

Dzina la Signal	Mtundu	M'lifupi	Kufotokozera
clk[]	Zolowetsa	3	Lowetsani chizindikiro cha wotchi pamarejista onse. Zizindikiro za wotchizi zimapezeka pokhapokha ngati zolembera zilizonse, zolembera zamapaipi, kapena zolembera zotulutsa zakhazikitsidwa Koloko0, Koloko1, kapena Koloko2. • clk[0] = Koloko0 • clk[1] = Koloko1 • clk[2] = Koloko2
ena[]	Zolowetsa	3	Wotchi imathandizira clk[2:0]. Chizindikiro ichi ndi chogwira-Pamwamba. • ena[0] ndi ya Koloko0 • ena[1] ndi ya Koloko1 • ena[2] ndi ya Koloko2
aclr[]	Zolowetsa	2	Asynchronous zomveka bwino zolembera zolembera zonse. Chizindikiro ichi ndi chogwira-Pamwamba. Gwiritsani ntchito aclr[0] pa zolembera zonse zolowetsa ndikugwiritsa ntchito aclr[1] kwa zolembera zonse za mapaipi ndi zotuluka. Mwachikhazikitso, chizindikiro ichi sichitsimikiziridwa.

Zizindikiro za Dynamic Control

Dzina la Signal	Mtundu	M'lifupi	Kufotokozera
gawo	Zolowetsa	1	Lowetsani chizindikiro kuti muwonjezere kapena kuchotsa zotulutsa zochulukira pamwamba ndi zochulukitsa zapansi. • Chotsani chizindikiro ichi kuti mutchule ntchito yowonjezera. • Nenani chizindikiro ichi kuti mutchule ntchito yochotsera. Mwachikhazikitso, chizindikiro ichi chimachotsedwa. Mutha kunena kapena kutsitsa chizindikirochi panthawi yothamanga.(3)
negate	Zolowetsa	1	Lowetsani chizindikiro kuti muwonjezere kapena kuchotsa kuchuluka kwa ochulutsa pamwamba ndi pansi ndi data kuchokera ku siginecha za chain. • Chotsani chizindikiro ichi kuti mutchule ntchito yowonjezera. • Nenani chizindikiro ichi kuti mutchule ntchito yochotsera. Mwachikhazikitso, chizindikiro ichi chimachotsedwa. Mutha kunena kapena kutsitsa chizindikirochi panthawi yothamanga.(3)
sonkhanitsa	Zolowetsa	1	Lowetsani chizindikiro kuti mutsegule kapena kuletsa mawonekedwe a accumulator. • Deassert chizindikiro ichi kuti zimitsani accumulator Mbali. • Limbikitsani chizindikiro ichi kuti mutsegule gawo la accumulator. Mwachikhazikitso, chizindikiro ichi chimachotsedwa. Mutha kunena kapena kutsitsa chizindikirochi panthawi yothamanga.(3)
loadconst	Zolowetsa	1	Lowetsani chizindikiro kuti mutsegule kapena kuyimitsa mawonekedwe osasintha. • Chotsani chizindikiro ichi kuti muyimitse mawonekedwe osasintha. • Limbikitsani chizindikiro ichi kuti mutsegule nthawi zonse. Mwachikhazikitso, chizindikiro ichi chimachotsedwa. Mutha kunena kapena kutsitsa chizindikirochi panthawi yothamanga.(3)

Zizindikiro za Internal Coeficient

Dzina la Signal	Mtundu	M'lifupi	Kufotokozera
coefsela[]	Zolowetsa	3	Zosankha zolowetsa zamtengo 8 wofotokozedwa ndi wogwiritsa ntchito pazochulukitsa zapamwamba. Ma coefficient values ​​amasungidwa mu kukumbukira kwamkati ndikufotokozedwa ndi magawo ndalama_a_0 ku ndalama_a_7. • coefsela[2:0] = 000 amatanthauza ndalama_a_0 • coefsela[2:0] = 001 amatanthauza ndalama_a_1 • coelsela[2:0] = 010 amatanthauza ndalama_a_2 • … ndi zina zotero. Zizindikirozi zimapezeka kokha pamene gawo la mkati layatsidwa.
coefselb[]	Zolowetsa	3	Zosankha zolowetsa zamtengo 8 wofotokozedwa ndi wogwiritsa ntchito pakuchulukitsa pansi. Ma coefficient values ​​amasungidwa mu kukumbukira kwamkati ndikufotokozedwa ndi magawo ndalama_b_0 ku ndalama_b_7. • coefselb[2:0] = 000 amatanthauza ndalama_b_0 • coefselb[2:0] = 001 amatanthauza ndalama_b_1 • coelselb[2:0] = 010 amatanthauza ndalama_b_2 • … ndi zina zotero. Zizindikirozi zimapezeka kokha pamene gawo la mkati layatsidwa.

Lowetsani Zizindikiro za Cascade

Dzina la Signal	Mtundu	M'lifupi	Kufotokozera
scanin[]	Zolowetsa	27	Lowetsani basi ya data yolowera gawo la cascade. Lumikizani ma siginecha awa ku siginecha kuchokera pakatikati pa DSP.
scanout[]	Kutuluka	27	Basi ya data yotuluka ya module yolowera ya cascade. Lumikizani ma siginecha awa ku ma sikelo a scanin a core ya DSP yotsatira.

Kutulutsa kwa Cascade Signals

Dzina la Signal	Mtundu	M'lifupi	Kufotokozera
unyolo[]	Zolowetsa	64	Lowetsani basi ya data yotulutsa gawo la cascade. Lumikizani ma siginecha awa ku ma siginecha a chainout kuchokera pakatikati pa DSP.
chainout[]	Zotulutsa	64	Mabasi otulutsa amtundu wa cascade module. Lumikizani ma siginecha awa ku ma signinin amtundu wotsatira wa DSP.

Mbiri Yokonzanso Zolemba za Cyclone 10 GX Native Fixed Point DSP IP Core User Guide

Tsiku	Baibulo	Zosintha
Novembala 2017	2017.11.06	Kutulutsidwa koyamba.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imalola kuti FPGA yake ndi zinthu zopangira semiconductor ziziwoneka bwino malinga ndi chitsimikizo cha Intel koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.

Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Zolemba / Zothandizira

Intel UG-20094 Cyclone 10 GX Native Fixed Point DSP IP Core [pdf] Buku Logwiritsa Ntchito UG-20094 Cyclone 10 GX Native Fixed Point DSP IP Core, UG-20094, Cyclone 10 GX Native Fixed Point DSP IP Core, Native Fixed Point DSP IP Core, Fixed Point DSP IP Core, DSP IP Core

Maumboni

• Buku Logwiritsa Ntchito