AN 795 Fa'atinoga o Ta'iala mo le 10G
Ethernet Subsystem Fa'aaoga Latency Low 10G MAC
Fa'aoga Taiala
AN 795 Fa'atinoga o Ta'iala mo le 10G Ethernet Subsystem Fa'aaogaina le Latency Low Latency 10G MAC
AN 795: Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaogaina le Latency Low 10G MAC Intel FPGA® IP i Intel ® Arria® 10 Devices
Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaogaina le Latency Low 10G MAC Intel ® FPGA IP i Intel ® Arria® 10 Devices
O ta'iala fa'atino e fa'aali atu ia te oe le fa'aogaina ole Intel's Low Latency 10G Media Access Controller (MAC) ma PHY IPs.
Ata 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC System
Laulau 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC Designs
O lenei laulau o lo'o lisiina uma ai Intel ® Arria® 10 mamanu mo Low Latency Ethernet 10G MAC Intel FPGA IP.
| Design Example | MAC Variant | PHY | Pusa Atina'e |
| 10GBase-R Ethernet | 10G | Tagatanuu PHY | Intel Arria 10 GX Transceiver SI |
| 10GBase-R Faiga Resitala Ethernet |
10G | Tagatanuu PHY | Intel Arria 10 GX Transceiver SI |
| XAUI Ethernet | 10G | XAUI PHY | Intel Arria 10 GX FPGA |
| 1G/10G Ethernet | 1G/10G | 1G/10GbE ma le 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/10G Ethernet ma le 1588 | 1G/10G | 1G/10GbE ma le 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M/100M/1G/10G Ethernet | 10M/100M/1G/10G | 1G/10GbE ma le 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M/100M/1G/10G Ethernet ma le 1588 |
10M/100M/1G/10G | 1G/10GbE ma le 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet | 1G/2.5G | 1G/2.5G/5G/10G Uiga tele Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet ma le 1588 | 1G/2.5G | 1G/2.5G/5G/10G Uiga tele Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G/10G Ethernet | 1G/2.5G/10G | 1G/2.5G/5G/10G Uiga tele Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 10G USXGMII Ethernet | 1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G Uiga tele Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
*O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
1. Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaogaina le Latency Low Latency 10G MAC Intel® FPGA IP i Intel® Arria® 10 Devices
683347 | 2020.10.28
Fa'aaliga:
E mafai ona e mauaina uma mamanu lisi e ala i le Low Latency Ethernet 10G MAC Intel® FPGA IP editor parameter i le Intel Quartus Prime software, vagana ai le XAUI Ethernet reference design. E mafai ona e mauaina le XAUI Ethernet reference design mai le Design Store.
Intel ofo atu MAC ma PHY IP eseese mo le 10M i le 1G Multi-rate Ethernet subsystems ina ia mautinoa fetuutuunai faatinoga. E mafai ona e vave fa'aalia le Low Latency Ethernet 10G MAC Intel FPGA IP ma le 1G/2.5G/5G/10G Multi-rate Ethernet PHY, Intel Arria 10 1G/10GbE ma le 10GBASE-KR PHY, po'o le XAUI PHY ma le Intel Arria 10 Transceiver Native PHY i fa'amalieina mana'oga mamanu eseese.
Fa'amatalaga Fa'atatau
- Low Latency Ethernet 10G MAC Intel FPGA IP Taiala Tagata Fa'aoga
Tuuina atu faʻamatalaga auʻiliʻili e uiga i le faʻatulagaina ma le faʻavasegaina o le MAC IP. - Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide
Tuuina atu faʻamatalaga auʻiliʻili e uiga i le faʻavaveina ma le faʻavasegaina o le MAC design examples. - Intel Arria 10 Transceiver PHY User Guide
Tuuina atu faʻamatalaga auiliili e uiga i le vave faʻatulagaina ma le faʻavasegaina o le PHY IP. - Low Latency Ethernet 10G MAC Debug Checklist
- AN 699: Fa'aaogaina o le Altera Ethernet Design Toolkit
O lenei mea faigaluega e fesoasoani ia te oe e faʻapipiʻi ma faʻatautaia mamanu faʻasinomaga Ethernet faʻapea foʻi ma le debug soʻo se mataupu e fesoʻotaʻi ma Ethernet. - Su'esu'ega La'au Sese mo le Latency Low 10G MAC Fa'amatalaga Pi'opi'o Fa'amatalaga
- Arria 10 Low Latency Ethernet 10G MAC ma XAUI PHY Reference Design
Tuuina mai le files mo le mamanu faasinomaga.
1.1. Maualalo Latency Ethernet 10G MAC ma Intel Arria 10 Transceiver Native PHY Intel FPGA IPs
E mafai ona e fa'atulagaina le Intel Arria 10 Transceiver Native PHY Intel FPGA IP e fa'atino ai le 10GBASE-R PHY fa'atasi ai ma le Ethernet fa'apitoa fa'apitoa fa'apitoa o lo'o fa'agasolo i le 10.3125 Gbps fa'amaumauga e pei ona fa'amatalaina i le Fuaiupu 49 o le IEEE 802.3-2008 fa'amatalaga.
O lenei faʻatulagaga e tuʻuina atu ai le XGMII i le Low Latency Ethernet 10G MAC Intel FPGA IP ma faʻaaogaina se alalaupapa tasi 10.3 Gbps PHY e tuʻuina atu ai se fesoʻotaʻiga tuusaʻo i se SFP + opitika module e faʻaaoga ai le SFI eletise faʻamatalaga.
Intel ofo atu lua 10GBASE-R Ethernet subsystem design examples ma e mafai ona e fa'atupuina nei mamanu ma le malosi e fa'aaoga ai le Low Latency Ethernet 10G MAC Intel FPGA IP editor parameter. O mamanu e lagolagoina le faʻataʻitaʻiga faʻatinoga ma suʻega meafaigaluega i luga o pusa faʻapitoa a le Intel.
Ata 2. Uati ma Toe Seti Fuafuaga mo Low Latency Ethernet 10G MAC ma Intel Arria 10 Transceiver Native PHY i le 10GBASE-R Design Examalumalu
Ata 3. Uati ma Toe Seti Fuafuaga mo Low Latency Ethernet 10G MAC ma Intel Arria 10 Transceiver Native PHY i le 10GBASE-R Design Example ma Resitala Faiga Fa'aagaoi
Fa'amatalaga Fa'atatau
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide
Tuuina atu faʻamatalaga auʻiliʻili e uiga i le faʻavaveina ma le faʻavasegaina o le MAC design examples.
1.2. Low Latency Ethernet 10G MAC ma XAUI PHY Intel FPGA IPs
O le XAUI PHY Intel FPGA IP e maua ai le XGMII i le Low Latency Ethernet 10G MAC Intel FPGA IP ma faʻaaogaina laina e fa i le 3.125 Gbps i le PMD interface.
O le XAUI PHY o se faʻatinoga faʻapitoa faʻapitoa o le 10 Gigabit Ethernet soʻotaga faʻamatalaina i le IEEE 802.3ae-2008 faʻamatalaga.
E mafai ona e mauaina le mamanu faʻasino mo le 10GbE subsystem faʻatinoina e faʻaaoga ai le Low Latency Ethernet 10G MAC ma XAUI PHY Intel FPGA IPs mai Design Store. O le mamanu e lagolagoina le faʻataʻitaʻiga faʻatino ma suʻega meafaigaluega i luga o le Intel development kit.
Ata 4. Uati ma Toe Seti Fuafuaga mo Low Latency Ethernet 10G MAC ma XAUI PHY Reference Design 
Fa'amatalaga Fa'atatau
- Arria 10 Low Latency Ethernet 10G MAC ma XAUI PHY Reference Design
Tuuina mai le files mo le mamanu faasinomaga. - AN 794: Arria 10 Low Latency Ethernet 10G MAC ma XAUI PHY Reference Design
1.3. Maualalo Latency Ethernet 10G MAC ma 1G/10GbE ma 10GBASEKR PHY Intel Arria 10 FPGA IPs
O le 1G/10GbE ma le 10GBASE-KR PHY Intel Arria 10 FPGA IP e maua ai le MII, GMII ma le XGMII i le Low Latency Ethernet 10G MAC Intel FPGA IP.
O le 1G / 10GbE ma le 10GBASE-KR PHY Intel Arria 10 FPGA IP faʻaaogaina se laina tasi 10Mbps / 100Mbps / 1Gbps / 10Gbps serial PHY. O mamanu e maua ai se fesoʻotaʻiga tuusaʻo i le 1G / 10GbE lua saoasaoa SFP + pluggable modules, 10M-10GbE 10GBASE-T ma le 10M / 100M / 1G / 10GbE 1000BASE-T kopa fafo PHY masini, poʻo fesoʻotaʻiga chip-to-chip. O nei IP cores e lagolagoina reconfigurable 10Mbps/100Mbps/1Gbps/10Gbps fua faatatau o faamatalaga.
Intel ofo atu lua-saoasaoa 1G/10GbE ma tele-saoasaoa 10Mb/100Mb/1Gb/10GbE mamanu examples ma e mafai ona e gaosia nei mamanu ma le malosi e faʻaaoga ai le Low Latency
Ethernet 10G MAC Intel FPGA IP fa'atonu fa'atonu. O mamanu e lagolagoina le faʻataʻitaʻiga faʻatinoga ma suʻega meafaigaluega i luga o le Intel development kit.
O le tele-saosaoa Ethernet subsystem faʻatinoga e faʻaaoga ai le 1G/10GbE poʻo le 10GBASE-KR PHY Intel Arria 10 FPGA IP mamanu e manaʻomia ai le SDC faʻatonuga mo le PHY IP i totonu ma le faʻaogaina o le kolosi o le uati. Va'ai ile altera_eth_top.sdc file i le mamanu exampLe iloa atili e uiga i le mea e manaʻomia create_generated_clock, set_clock_groups ma seti_false_path SDC tapulaʻa.
Ata 5. Uati ma Toe Seti Fuafuaga mo Low Latency Ethernet 10G MAC ma Intel Arria 10 1G/10GbE ma 10GBASE-KR Design Example (1G/10GbE Mode)
Ata 6. Uati ma Toe Seti Fuafuaga mo Low Latency Ethernet 10G MAC ma Intel Arria 10 1G/10GbE ma 10GBASE-KR Design Example (10Mb/100Mb/1Gb/10GbE Mode)
Fa'amatalaga Fa'atatau
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide
Tuuina atu faʻamatalaga auʻiliʻili e uiga i le faʻavaveina ma le faʻavasegaina o le MAC design examples.
1.4. Uta'i Latency Low 10G MAC ma le 1G/2.5G/5G/10G TeleRate Ethernet PHY Intel FPGA IPs
O le 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP mo Intel Arria 10 masini e maua ai le GMII ma le XGMII i le Low Latency Ethernet 10G MAC Intel FPGA IP.
O le 1G / 2.5G / 5G / 10G Tele-Rate Ethernet PHY Intel FPGA IP mo Intel Arria 10 masini faʻaaogaina se tasi-auala 1G / 2.5G / 5G / 10Gbps serial PHY. O le mamanu e maua ai se fesoʻotaʻiga tuusaʻo i le 1G / 2.5GbE lua saoasaoa SFP + faʻapipiʻi modules, MGBASE-T ma NBASE-T kopa fafo PHY masini, poʻo fesoʻotaʻiga chip-to-chip. O nei IP e lagolagoina le toe fa'afouina 1G/2.5G/5G/10Gbps fua faatatau o fa'amaumauga.
Intel ofo atu le lua-saoasaoa 1G/2.5GbE, tele-saosaoa 1G/2.5G/10GbE MGBASE-T, ma multispeed 1G/2.5G/5G/10GbE MGBASE-T mamanu examples ma e mafai ona e fa'atupuina nei mamanu ma le malosi e fa'aaoga ai le Low Latency Ethernet 10G MAC Intel FPGA IP editor parameter. O mamanu e lagolagoina le faʻataʻitaʻiga faʻatinoga ma suʻega meafaigaluega i luga o le Intel development kit.
Ata 7. Uati ma Toe Seti Fuafuaga mo le Low Latency Ethernet 10G MAC ma le 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G Mode)
Mo le tele-saosaoa 1G/2.5GbE ma le 1G/2.5G/10GbE MBASE-T Ethernet subsystem fa'atinoga e fa'aaoga ai le 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP, ua fautuaina oe e Intel e kopi le module reconfiguration transceiver (alt_mge_rcfg_a10. sv) tu'uina atu ma le mamanu example. O lenei module e toe faʻaleleia le saoasaoa o le alalaupapa transceiver mai le 1G i le 2.5G, poʻo le 10G, ma le isi itu.
O le tele-saosaoa 1G/2.5GbE ma le 1G/2.5G/10GbE MBASE-T Ethernet subsystem fa'atinoga e mana'omia ai fo'i fa'atonuga SDC tusi lesona mo uati PHY IP totonu.
ma le fa'aogaina ole kolosi ole uati. Va'ai ile altera_eth_top.sdc file i le mamanu exampLe iloa atili e uiga i le mea e manaʻomia create_generated_clock, set_clock_groups ma seti_false_path SDC tapulaʻa.
Ata 8. Uati ma Toe Seti Fuafuaga mo le Low Latency Ethernet 10G MAC ma le 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/10GbE MBASE-T Mode) 
Ata 9. Uati ma Toe Seti Fuafuaga mo le Low Latency Ethernet 10G MAC ma le 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/5G/10GbE NBASE-T Mode)
Fa'amatalaga Fa'atatau
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide Tuuina atu faʻamatalaga auʻiliʻili e uiga i le faʻavaveina ma le faʻavasegaina o le mamanu MAC examples.
1.5. Fa'amatalaga Toe Iloiloga o Fa'amaumauga mo AN 795: Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaogaina le Latency Low 10G MAC Intel FPGA IP i Intel Arria 10 Devices
| Fa'amatalaga Fa'amaumauga | Suiga |
| 2020.10.28 | • Toe fa'ailogaina o le Intel. • Toe fa'aigoaina le pepa o le AN 795: Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaoga le Latency Low 10G MAC Intel FPGA IP i Intel Arria 10 Devices. |
| Aso | Fa'aliliuga | Suiga |
| Fepuari-17 | 2017.02.01 | Fa'asalalauga muamua. |
AN 795: Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaoga Low
Latency 10G MAC Intel ® FPGA IP i Intel® Arria® 10 Masini
Faʻasinomaga Faʻainitaneti
Lauina Manatu
ID: 683347
Fa'aliliuga: 2020.10.28
Pepa / Punaoa
 |
intel AN 795 Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaogaina le Latency Low Latency 10G MAC [pdf] Taiala mo Tagata Fa'aoga AN 795 Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaogaina le Latency Low Latency 10G MAC, AN 795, Fa'atinoina o Ta'iala mo le 10G Ethernet Subsystem Fa'aaoga le Latency Low Latency 10G MAC, Ethernet Subsystem Fa'aaoga Latency Low Latency 10G MAC, Low Latency 10G MAC |
