intel UG-20094 Cyclone 10 GX Kafaffen Ma'anar DSP IP Core

Intel® Cyclone® 10 GX Kafaffen Mahimman Bayani DSP IP Core User Guide

Intel Cyclone® 10 GX Native Fixed Point DSP IP core core yana nan take kuma yana sarrafa toshewar Intel Cyclone 10 GX Canza Daidaitaccen Siginar Dijital (DSP). Cyclone 10 GX Native Fixed Point DSP IP core yana samuwa kawai don na'urorin Intel Cyclone 10 GX.

Cyclone 10 GX Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararriyar IP

Bayanai masu alaƙa
Gabatarwa zuwa Intel FPGA IP Cores.

Cyclone 10 GX Ƙwararren Ƙwararren Ƙwararren Ƙwararren DSP IP Core Features

Cyclone 10 GX Native Fixed Point DSP IP core yana goyan bayan fasalulluka masu zuwa:

• Babban aiki, ingantaccen iko, da cikakken ayyukan ninkawa masu rijista
• Tsawon kalmomin 18-bit da 27-bit
• Masu haɓaka 18 × 19 guda biyu ko ɗaya 27 × 27 multiplier kowane toshe DSP
• Bugu da kari, ragi, da 64-bit rijiyoyin tarawa biyu don hada sakamakon ninkawa.
• Cascading 19-bit ko 27-bit lokacin da pre-adder ya naƙasa da kuma zubar da 18-bit lokacin da ake amfani da pre-adder don samar da layin jinkiri don tacewa aikace-aikacen.
• Cascading bas ɗin fitarwa 64-bit don yada sakamakon fitarwa daga toshe ɗaya zuwa toshe na gaba ba tare da tallafin dabaru na waje ba.
• Hard pre-adder yana goyan bayan yanayin 19-bit da 27-bit don masu tacewa
• Bankin rajista na coefficient na ciki a cikin yanayin 18-bit da 27-bit don aiwatar da tacewa
• 18-bit da 27-bit systolic iyakacin karfin amsawa (FIR) masu tacewa tare da rarraba kayan fitarwa

Farawa

Wannan babin yana ba da cikakken bayaniview na Intel FPGA IP core design flow don taimaka muku da sauri farawa tare da Cyclone 10 GX Native Fixed Point DSP IP core. An shigar da Laburaren IP na Intel FPGA azaman wani ɓangare na tsarin shigarwa na Intel Quartus® Prime. Kuna iya zaɓar da daidaita kowane Intel FPGA IP core daga ɗakin karatu. Intel yana ba da haɗe-haɗe da editan sigina wanda ke ba ku damar keɓance ainihin Intel FPGA DSP IP don tallafawa aikace-aikace iri-iri. Editan siga yana jagorantar ku ta hanyar saitin ƙimar sigina da zaɓin tashar jiragen ruwa na zaɓi.

Bayanai masu alaƙa

• Gabatarwa zuwa Intel FPGA IP Cores
  Yana ba da cikakken bayani game da duk na'urorin IP na Intel FPGA, gami da daidaitawa, haɓakawa, haɓakawa, da kwaikwaiyon bayanan IP.
• Ƙirƙirar Rubutun Simulatio Mai Zaman Kansu na IP da Platform Designer (Standard).
  Ƙirƙirar rubutun kwaikwaiyo waɗanda baya buƙatar ɗaukakawar hannu don haɓaka software ko sigar IP.
• Mafi kyawun Ayyukan Gudanarwa
  Jagorori don ingantaccen gudanarwa da ɗaukar nauyin aikin ku da IP files.

Cyclone 10 GX Kafaffen Mahimman Bayanai DSP IP Core Siga Saituna

Kuna iya keɓance ainihin madaidaicin Cyclone 10 GX Native Fixed Point DSP IP ta hanyar ƙididdige sigogi ta amfani da editan siga a cikin software na Intel Quartus Prime.

Yanayin Aiki Tab

Siga	IP Generated Parameter	Daraja	Bayani
Da fatan za a zaɓi yanayin aiki	yanayin aiki	m18×18_full m18×18_sumof2 m18×18_plus36 m18×18_systolic m27×27	Zaɓi yanayin aiki da ake so.
Kanfigareshan Multiplier
Tsarin wakilci don babban mai ninka x operand	sanya hannu_max	sanya hannu ba a sanya hannu ba	Ƙayyade tsarin wakilci don babban mai ninka x operand.

Siga	IP Generated Parameter	Daraja	Bayani
Tsarin wakilci don babban mai yawa y operand	sanya hannu_mayu	sanya hannu ba a sanya hannu ba	Ƙayyade tsarin wakilci don babban mai ninka y operand.
Tsarin wakilci na ƙasa mai yawa x operand	sanya hannu_mbx	sanya hannu ba a sanya hannu ba	Ƙayyade tsarin wakilci don mai ninka x na ƙasa.
Tsarin wakilci na ƙasa mai yawa y operand	sanya hannu_mby	sanya hannu ba a sanya hannu ba	Ƙayyade tsarin wakilci na ƙasa mai yawa y operand. Koyaushe zaɓi ba a sanya hannu ba domin m18×18_plus36 .
Kunna tashar tashar 'sub'	kunna_sub	A'a Ee	Zaɓi Ee don kunna sub port.
Yi rijistar shigar da 'sub' na mai ninkawa	sub_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar sub.
Shigar da Cascade
Kunna shigar da cascade don shigarwar 'ay'	ay_use_scan_in	A'a Ee	Zaɓi Ee don ba da damar shigar da cascade module don shigar da bayanan ay. Lokacin da kuka kunna tsarin shigar da cascade, Cyclone 10 GX Native Fixed Point DSP IP core yana amfani da siginar shigarwar scanin azaman shigarwa maimakon siginar shigar ay.
Kunna shigar da cascade don shigarwar 'by'	ta_amfani_scan_in	A'a Ee	Zaɓi Ee don ba da damar shigar da cascade module don ta hanyar shigar da bayanai. Lokacin da kuka kunna tsarin shigar cascade, Cyclone 10 GX Native Fixed Point DSP IP core yana amfani da siginar shigarwar ay azaman shigarwa maimakon ta siginar shigarwa.
Kunna rijistar ayyana jinkiri	jinkirta_scan_out_ay	A'a Ee	Zaɓi Ee don ba da damar yin rajista tsakanin ay da ta shigar da rajista. Ba a tallafawa wannan fasalin a ciki m18×18_plus36 kuma cika27 yanayin aiki.

Siga	IP Generated Parameter	Daraja	Bayani
Kunna bayanai ta rijistar jinkiri	jinkirta_scan_out_by	A'a Ee	Zaɓi Ee don ba da damar yin rijistar jinkirta tsakanin ta rajistar shigarwar da bas ɗin fitarwa. Ba a tallafawa wannan fasalin a ciki m18×18_plus36 kuma cika27 yanayin aiki.
Kunna tashar jiragen ruwa na scanout	gui_scanout_enable	A'a Ee	Zaɓi Ee don kunna bas ɗin fitarwa.
Faɗin bas ɗin fitarwa na 'scanout'	duban_nisa	1-27	Ƙayyade faɗin bas ɗin fitarwa.
Bayanan 'x' Kanfigareshan
Faɗin shigar bas 'ax'	fadi_tashi	1-27	Ƙayyade faɗin bas shigar ax.(1)
Yi rijistar shigar da 'ax' na mai ninkawa	ax_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar gatari. Babu rajistan shigar da gatari idan kun saita 'ax' operand source ku 'kofi'.
'bx' shigar da faɗin bas	bx_nisa	1-18	Ƙayyade faɗin bx tashar bas.(1)
Yi rijistar shigar 'bx' na mai yawa	bx_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙayyade siginar shigarwar agogo don rajistar shigarwar bx. Babu rajistar shigarwar bx idan kun saita 'bx' tushen operand ku 'kofi'.
Tsarin 'y' Data
'ay' ko 'scanin' fadin bas	ay_scan_in_nisa	1-27	Ƙayyade faɗin ay ko na'urar shigar da bas ɗin scanin.(1)
Yi rijista shigar 'ay' ko shigar da 'scanin' na mai ninka	ay_scan_in_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar ay ko scanin.
'by' shigar da fadin bas	ta_fadi	1-19	Ƙayyade faɗin ta hanyar bas ɗin shigarwa.(1)

Siga	IP Generated Parameter	Daraja	Bayani
Yi rijistar shigarwa 'ta' na mai ninkawa	da karfe_	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo ta ta ko scanin shigar da rajista.(1)
Fitar 'sakamakon' Kanfigareshan
'sakamakon' fadin bas ɗin fitarwa	sakamakon_nisa_	1-64	Ƙayyade faɗin resulta fitarwa bas.
'resultb' fadin bas ɗin fitarwa	sakamako_b_nisa	1-64	Ƙayyade faɗin bas ɗin fitarwa na sakamako. sakamako yana samuwa kawai lokacin amfani da operation_mode m18×18_cikakken.
Yi amfani da rajistar fitarwa	fitarwa_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogon don sakamakon da rikodin fitarwa na sakamako.

Pre-Adder Tab

Siga	IP Generated Parameter	Daraja	Bayani
'ay' operand source	operand_source_may	shigar da mai gabatarwa	Ƙayyade tushen operand don shigarwar ay. Zaɓi mai gabatarwa don ba da damar pre-adder module don babban mai yawa. Saitunan ay da ta hanyar operand dole ne su kasance iri ɗaya.
'by' operand source	operand_source_mby	shigar da mai gabatarwa	Ƙayyade tushen operand ta hanyar shigarwa. Zaɓi mai gabatarwa don kunna pre-adder module don ƙasa mai yawa. Saitunan ay da ta hanyar operand dole ne su kasance iri ɗaya.
Saita pre-adder aiki don ragewa	prereader_rauni_a	A'a Ee	Zaɓi Ee don ƙididdige aikin ragi don ƙirar riga-kafi don babban mai yawa. Saitunan ƙararrawa na sama da ƙasa dole ne su kasance iri ɗaya.
Saita pre-adder b aiki zuwa ragi	prereader_sauke_b	A'a Ee	Zaɓi Ee don ƙididdige aikin ragi don ƙirar pre-adder don mai yawa na ƙasa. Saitunan ƙararrawa na sama da ƙasa dole ne su kasance iri ɗaya.
Data 'z' Kanfigareshan
Faɗin shigar bas 'az'	az_nisa	1-26	Ƙayyade faɗin bas ɗin shigarwar az.(1)
Yi rijistar shigar da 'az' na mai ninkawa	az_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙayyade siginar shigarwar agogo don rajistar shigarwar az. Saitunan agogo don rajistar shigarwar ay da az dole ne su kasance iri ɗaya.
'bz' shigar da fadin bas	bz_nisa	1-18	Ƙayyade faɗin bus ɗin shigarwar bz.(1)
Yi rijistar shigar 'bz' na mai ninkawa	bz_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar bz. Saitunan agogo na by da bz rajistar shigarwa dole ne su kasance iri ɗaya.

Tabbatacce na ciki

Siga	IP Generated Parameter	Daraja	Bayani
'ax' operand source	operand_source_max	shigarwa kofa	Ƙayyade tushen operand don bas ɗin shigar da gatari. Zaɓi kofa don ba da damar ƙididdiga na ciki na ciki don babban mai yawa. Zaɓi A'a domin Yi rijistar shigar da 'ax' na mai ninkawa siga lokacin da ka kunna fasalin haɗin kai na ciki.

Siga	IP Generated Parameter	Daraja	Bayani
			Saituna don gatari da tushen bx operand dole ne su kasance iri ɗaya.
'bx' tushen operand	operand_source_mbx	shigarwa kofa	Ƙayyade tushen operand don shigar da bas ɗin bx. Zaɓi kofa don ba da damar ƙididdiga na ciki na ciki don babban mai yawa. Zaɓi A'a domin Yi rijistar shigar 'bx' na mai yawa siga lokacin da ka kunna fasalin haɗin kai na ciki. Saituna don gatari da tushen bx operand dole ne su kasance iri ɗaya.
Kanfigareshan Rijistar Shigar 'coefsel'
Yi rijistar shigar da 'coefsela' na mai ninkawa	agogon_sel_a_	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar coefsela.
Yi rijistar shigar 'coefselb' na mai ninkawa	agogon_sel_b_	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar coefselb.
Kanfigareshan Ma'ajiyar Haɗaɗɗiyya
coef_a_0-7	coef_a_0-7	lamba	Ƙayyade ƙimar ƙima don shigar da gatari. Don yanayin aiki 18-bit, matsakaicin ƙimar shigarwa shine 218 - 1. Don aiki na 27-bit, matsakaicin ƙimar shine 227 - 1.
coef_b_0-7	coef_b_0-7	lamba	Ƙayyade ƙididdiga masu ƙima don shigar da bas ɗin bx.

Accumulator/Fitarwa Cascade Tab

Siga	IP Generated Parameter	Daraja	Bayani
Kunna tashar jiragen ruwa 'tattara'	kunna_tara	A'a Ee	Zaɓi Ee don kunna accumulator tashar jiragen ruwa.
Kunna tashar tashar 'negate'	kunna_negate	A'a Ee	Zaɓi Ee don kunna tashar jirgin ruwa.
Kunna tashar 'loadconst'	kunna_loadconst	A'a Ee	Zaɓi Ee don kunna tashar jiragen ruwa loadconst.
Yi rijistar shigar da 'tara' na mai tarawa	tara_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0 , Agogo1, ko Agogo2 don kunna da ƙididdige siginar agogon shigarwa don tara rijistar shigarwar.

Siga	IP Generated Parameter	Daraja	Bayani
Yi rijistar shigar da 'loadconst' na mai tarawa	load_const_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar agogon shigarwa don rajistar shigarwar loadconst.
Yi rijistar shigar da 'negate' na rukunin ƙara	negate_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar negate.
Kunna tara tara biyu	kunna_biyu_accum	A'a Ee	Zaɓi Ee don kunna fasalin tarawa biyu.
N darajar da aka saita akai akai	load_const_darajar	0-63	Ƙimar da aka saita akai akai. Wannan darajar na iya zama 2N ina N shine ƙimar da aka saita akai akai.
Kunna tashar tashar tashar chainin	amfani_chainadder	A'a Ee	Zaɓi Ee don ba da damar fitowar cascade module da kuma bas shigar da chainin. Ba a samun goyan bayan fasalin cascade a ciki m18×18_cikakken yanayin aiki.
Kunna tashar tashar sarkar	gui_chainout_enable	A'a Ee	Zaɓi Ee don kunna bas ɗin fitarwa na chainout. Ba a samun goyan bayan fasalin cascade a ciki m18×18_cikakken yanayin aiki.

Tabbar bututun mai

Siga	IP Generated Parameter	Daraja	Bayani
Ƙara rajistar bututun shigarwa zuwa siginar bayanan shigarwa (x/y/z/coefsel)	shigar da bututun_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogon x, y, z, coefsela da rajistar shigar bututun coefselb.
Ƙara rijistar bututun shigarwa zuwa siginar bayanan 'sub'	sub_pipeline_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigar da bututun da ke ƙasa. (2)
Ƙara rajistar bututun shigarwa zuwa siginar 'tattara' bayanai	accum_pipeline_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar agogon shigarwa don rijistar shigar bututun mai tarawa.(2)
Ƙara rajistar bututun shigarwa zuwa siginar bayanai na 'loadconst'	load_const_pipeline_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar bututun loadconst.(2)
Ƙara rijistar bututun shigarwa zuwa siginar bayanan 'negate'	negate_pipeline_clock	A'a Clock0 Clock1 Clock2	Zaɓi Agogo0, Agogo1, ko Agogo2 don kunna da ƙididdige siginar shigarwar agogo don rajistar shigarwar bututun negate.(2)

Matsakaicin Nisa Bayanan shigarwa a kowane Yanayin Aiki
Kuna iya tsara faɗin bayanai don abubuwan shigar x, y, da z kamar yadda aka ƙayyade a cikin tebur.

Duk rajistar shigar bututun don siginar sarrafawa mai ƙarfi dole ne su kasance da saitin agogo iri ɗaya.

Yanayin Aiki	Matsakaicin Nisa Bayanan shigarwa
	ax	ay	az	bx	by	bz
Ba tare da Pre-Adder ko Internal Coefficient
m18×18_cikakken	18 (sa hannu) 18 (ba a sanya hannu ba)	19 (sa hannu) 18 (ba a sanya hannu ba)	Ba a yi amfani da shi ba	18 (sa hannu) 18 (ba a sanya hannu ba)	19 (sa hannu) 18 (ba a sanya hannu ba)	Ba a yi amfani da shi ba
m18×18_sumof2
m18×18_systolic
m18×18_plus36
m27×27	27 (sa hannu) 27 (ba a sanya hannu ba)		Ba a yi amfani da shi ba
Tare da Pre-Adder Feature Only
m18×18_cikakken	18 (sa hannu) 18 (ba a sanya hannu ba)
m18×18_sumof2
m18×18_systolic
m27×27	27 (sa hannu) 27 (ba a sanya hannu ba)	26 (sa hannu) 26 (ba a sanya hannu ba)		Ba a yi amfani da shi ba
Tare da Fasalin Ƙarfafawar Ciki Kawai
m18×18_cikakken	Ba a yi amfani da shi ba	19 (sa hannu) 18 (ba a sanya hannu ba)	Ba a yi amfani da shi ba		19 (sa hannu) 18 (ba a sanya hannu ba)	Ba a yi amfani da shi ba
m18×18_sumof2
m18×18_systolic
m27×27		27 (sa hannu) 27 (ba a sanya hannu ba)			Ba a yi amfani da shi ba

Bayanin Aiki

Cyclone 10 GX Native Fixed Point DSP IP core ya ƙunshi gine-gine 2; 18 × 18 ninkawa da 27 × 27 yawaita. Kowane lokaci na Cyclone 10 GX Native Fixed Point DSP IP core yana haifar da 1 kawai daga cikin gine-ginen 2 dangane da zaɓaɓɓun hanyoyin aiki. Kuna iya kunna na'urori na zaɓi zuwa aikace-aikacen ku.

Bayanai masu alaƙa
Maɓallai Madaidaicin DSP a cikin Intel Cyclone 10 GX Babi na Na'urori, Intel Cyclone 10 GX Core Fabric da Babban Manufar I/Os Handbook.

Hanyoyin Aiki

Cyclone 10 GX Native Fixed Point DSP IP core yana goyan bayan yanayin aiki guda 5:

• Cikakken Yanayin 18 × 18
• Jimillar 18 × 18 na Yanayin 2
• Yanayin 18 × 18 Plus 36
• Yanayin Systolic 18 × 18
• Yanayin 27 × 27

Cikakken Yanayin 18 × 18
Lokacin da aka saita azaman 18 × 18 cikakken yanayin, Cyclone 10 GX Native Fixed Point DSP IP core yana aiki azaman 18 masu zaman kansu guda biyu (sa hannu / ba a sanya hannu ba) × 19 (sa hannu) ko 18
(wanda aka sanya hannu/marasa hannu) × 18 (ba a sanya hannu ba) masu ninkawa tare da fitarwa 37-bit. Wannan yanayin yana amfani da ma'auni masu zuwa:

• resulta = ax * ay
• resultb = bx * ta

18 × 18 Cikakken Tsarin Gine-gine

Jimillar 18 × 18 na Yanayin 2
A cikin 18 × 18 Sum na 2 halaye, Cyclone 10 GX Native Fixed Point DSP IP core yana ba da damar haɓaka sama da ƙasa kuma yana haifar da sakamako daga ƙari ko raguwa tsakanin masu haɓaka 2. Siginar sarrafawa mai ƙarfi yana sarrafa ƙara don yin ayyukan ƙari ko ragi. Sakamakon fitarwa na nisa na Cyclone 10 GX Native Kafaffen Point DSP IP core na iya tallafawa har zuwa rago 64 lokacin da kuka kunna cascade / fitarwa. Wannan yanayin yana aiki da lissafin sakamakon = [±(ax * ay) + (bx * by)].

Jimlar 18 × 18 na Tsarin Tsarin Yanayi 2

Yanayin 18 × 18 Plus 36
Lokacin da aka saita azaman yanayin 18 × 18 Plus 36, Cyclone 10 GX Native Fixed Point DSP IP core yana ba da damar babban mai yawa kawai. Wannan yanayin yana aiki da lissafin sakamakon = (ax * ay) + concatenate (bx[17:0], ta[17:0]).

Yanayin Gine-gine na 18 × 18 Plus 36

Dole ne ku saita tsarin wakilci don masu ninkawa na ƙasa y operand zuwa rashin sa hannu yayin amfani da wannan yanayin. Lokacin da motar shigarwar ta kasa da 36-bit a cikin wannan yanayin, ana buƙatar ka samar da ƙarawar da aka sanya hannu don cika shigarwar 36-bit.

Amfani da Kasa da 36-bit Operand A Yanayin 18 × 18 Plus 36
Wannan example yana nuna yadda ake saita Cyclone 10 GX Native Fixed Point DSP IP core don amfani da yanayin aiki na 18 × 18 Plus 36 tare da sa hannun bayanan shigarwar 12-bit na 101010101010 (binary) maimakon 36-bit operand.

1. Saita tsarin wakilci don mai yawa x operand na ƙasa: don sanya hannu.
2. Saita tsarin wakilci don mai yawa na ƙasa y operand: zuwa wanda ba a sanya hannu ba.
3. Saita faɗin shigarwar bas ɗin 'bx' zuwa 18.
4. Saita faɗin shigarwar bas ɗin 'by' zuwa 18.
5. Samar da bayanan '111111111111111111' zuwa bas shigar bx.
6. Samar da bayanan '111111101010101010' zuwa ta hanyar shigar da bas.

Yanayin Systolic 18 × 18
A cikin yanayin aiki na systolic 18 × 18, Cyclone 10 GX Native Fixed Point DSP IP core yana ba da damar haɓaka sama da ƙasa, rajistar shigarwar systolic don babban mai ninka, da rajistar systolic sarkar don siginar shigarwa. Lokacin da kuka kunna cascade na fitarwa, wannan yanayin yana goyan bayan faɗin fitarwa na 44 bits. Lokacin da kuka kunna fasalin tarawa ba tare da kasidar fitarwa ba, zaku iya saita faɗin fitarwa zuwa 64 ragowa.

Tsarin 18 × 18 Systolic Mode Architecture

Yanayin 27 × 27
Lokacin da aka saita azaman yanayin 27 × 27, Cyclone 10 GX Native Fixed Point DSP IP core yana ba da damar 27 (sa hannu / ba a sanya hannu ba) × 27 (sa hannu / ba a sanya hannu ba) mai yawa. Bus ɗin fitarwa na iya tallafawa har zuwa rago 64 tare da kunna kaske mai tarawa/fitarwa. Wannan yanayin yana aiki da lissafin sakamakon = ax * ay.

Yanayin Gine-gine na 27 × 27

Modulolin Zaɓuɓɓuka

Na'urorin zaɓin da ake samu a cikin Cyclone 10 GX Native Fixed Point DSP IP Core sune:

• Shigar da cascade
• Pre-Adders
• Internal Coefficient
• Accumulator da fitarwa cascade
• Rijistar bututun mai

Shigar da Cascade
Ana goyan bayan fasalin cascade na shigarwa akan ay da kuma ta bas ɗin shigarwa. Lokacin da kuka saita Ƙaddamar da shigar da cascade don shigarwar 'ay' zuwa Ee, Cyclone 10 GX Native Fixed Point DSP IP core zai ɗauki bayanai daga siginar shigarwar scan maimakon ay shigar bas. Lokacin da kuka saita Ƙaddamar da shigar da cascade don shigarwar 'by' zuwa Ee, Ƙaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwallon Ƙwallon Ƙwallon Ƙwallon Ƙwallon Ƙwallon Ƙwallon Ƙasa na Cyclone 10 GX DSP IP core zai ɗauki bayanai daga motar shigarwar ay maimakon ta bas ɗin shigarwa.

Ana ba da shawarar ba da damar rajistar shigarwar don ay da/ko ta duk lokacin da aka kunna cascade na shigarwa don daidaiton aikace-aikacen.

Kuna iya ba da damar rijistar jinkiri don dacewa da buƙatun jinkiri tsakanin rajistar shigarwa da rajistar fitarwa. Akwai rajistar jinkiri guda 2 a cikin ainihin. Ana amfani da babban rajistar jinkiri don ay ko duba-in shigar da tashar jiragen ruwa yayin da ake amfani da rajistar jinkiri na ƙasa don tashoshin fitarwa na scanout. Ana goyan bayan waɗannan rijistar jinkiri a cikin cikakken yanayin 18 × 18, jimlar 18 × 18 na yanayin 2, da yanayin systolic 18 × 18.

Pre-Adder

Za a iya saita pre-adder a cikin saitunan masu zuwa:

• Biyu masu zaman kansu 18-bit (sa hannu/mara sa hannu) pre-adders.
• Daya 26-bit pre-adder.

Lokacin da kuka kunna pre-adder a cikin yanayin ninkawa na 18 × 18, ana amfani da ay da az azaman bas ɗin shigarwa zuwa saman pre-adder yayin da by da bz ana amfani da su azaman bas ɗin shigarwa zuwa ƙasa pre-adder. Lokacin da kuka kunna pre-adder a cikin yanayin ninkawa na 27 × 27, ay da az ana amfani da su azaman bas ɗin shigarwa zuwa pre-adder. Pre-Adder yana goyan bayan ayyukan ƙari da ragi. Lokacin da aka yi amfani da duka pre-adders a cikin toshe DSP ɗaya, dole ne su raba nau'in aiki iri ɗaya (ko dai ƙari ko ragi).

Internal Coefficient
Ƙididdigar cikin gida na iya tallafawa har zuwa ƙididdige ƙididdiga guda takwas don multiplicands a cikin yanayin 18-bit da 27-bit. Lokacin da kuka kunna fasalin haɗin kai na cikin gida, bas ɗin shigarwa guda biyu don sarrafa zaɓin mahaɗar maɗaukakiyar ƙira za a ƙirƙira. Ana amfani da bas ɗin shigarwar coefsela don zaɓar ƙayyadaddun ƙididdigar ƙididdiga don babban mai ninka kuma ana amfani da bas ɗin shigar da bas ɗin don zaɓar ƙayyadaddun ƙididdiga don mai ninka na ƙasa.

Ma'ajiyar ƙididdigewa ta ciki baya goyan bayan ƙimar ƙima mai ƙarfi mai ƙarfi kuma ana buƙatar ma'ajin ƙididdiga na waje don yin irin wannan aiki.

Accumulator da Output Cascade

Ana iya kunna tsarin tarawa don aiwatar da ayyuka masu zuwa:

• Ƙara ko ragi aiki
• Ayyukan zagaye na son rai ta amfani da ƙimar 2N akai-akai
• Taruwa tashoshi biyu

Don aiwatar da ƙari ko aikin ragi na mai tarawa, sarrafa siginar shigarwar negate. Don aikin zagaye na son zuciya, zaku iya ƙididdigewa da ɗora madaidaicin saiti na 2N kafin a kunna tsarin tarawa ta hanyar ƙididdige lamba zuwa ma'aunin N ƙimar saiti na akai-akai. Dole ne lamba N ta kasance ƙasa da 64. Kuna iya kunna ko kashe amfani da saiti akai-akai ta sarrafa siginar ɗaukar nauyi. Kuna iya amfani da wannan aikin azaman murƙushe kimar zagaye mai aiki a cikin hanyar amsawar tarawa. Farashin da aka ɗora da siginar amfani da siginar da aka tara ya keɓanta juna.

Kuna iya kunna rijistar tarawa biyu ta amfani da siga Kunna tara tara biyu don yin tarawa biyu. Tsarin tarawa na iya tallafawa sarƙar tubalan DSP da yawa don ƙarawa ko ayyukan ragi ta hanyar ba da damar shigar da sarƙoƙi da tashar fitarwa ta sarkar. A cikin yanayin systolic 18 × 18, kawai 44-bit na bas shigarwar sarkar da bas ɗin fitarwa za a yi amfani da shi. Koyaya, duk sarƙar 64-bit a cikin bas ɗin shigarwa dole ne a haɗa su zuwa bas ɗin fitarwa daga sarkar DSP da ta gabata.

Rajistan bututun mai

Cyclone 10 GX Native Fixed Point DSP IP core yana goyan bayan matakin rajista guda ɗaya na bututun mai. Rijistar bututun yana tallafawa har zuwa tushen agogo uku da sigina mai kama da juna don sake saita rajistar bututun. Akwai rajistan bututu guda biyar:

• rajistar bututun bututun bayanai
• sub Dynamic iko sigina bututu rajista
• Negate Dynamic Control Signal Register
• tara rikodin bututun sigina mai ƙarfi mai ƙarfi
• Loadconst Dynamic Control Bututun rajista

Kuna iya zaɓar don kunna rajistar bututun bututun bayanan shigar da bayanai da bututun siginar sarrafawa mai ƙarfi yana yin rijista da kansa. Koyaya, duk rajistar bututun da aka kunna dole ne suyi amfani da tushen agogo iri ɗaya.

Tsarin agogo

Shigarwa, bututun, da fitarwa suna yin rajista a cikin Cyclone 10 GX Native Fixed Point DSP IP core yana goyan bayan tushen agogo uku/sa da share guda biyu asynchronous. Duk rajistar shigarwa suna amfani da aclr[0] kuma duk bututun mai da rajistar fitarwa suna amfani da aclr[1]. Kowane nau'in rajista na iya zaɓar ɗaya daga cikin hanyoyin agogo uku da agogon kunna sigina. Lokacin da kuka saita Cyclone 10 GX Native Fixed Point DSP IP core zuwa yanayin aiki na 18 × 18 systolic, Intel Quartus Prime software zai saita rajistar shigarwar systolic da sarkar systolic rajistar agogon agogo zuwa tushen agogo iri ɗaya da rijistar fitarwa a ciki.

Lokacin da kuka kunna fasalin tarawa sau biyu, Intel Quartus Prime software zai saita tushen agogon rajista sau biyu zuwa tushen agogo iri ɗaya kamar rijistar fitarwa a ciki.

Matsalolin Tsare-tsaren agogo
Wannan shafin yana nuna ƙuntatawa dole ne ka nema don duk tsarin rufe rajistar.

Sharadi	Takura
Lokacin da aka kunna pre-adder	Tushen agogo don rajistar shigarwar ay da az dole ne su kasance iri ɗaya.

	Tushen agogo na by da bz rajistar shigarwa dole ne su kasance iri ɗaya.
Lokacin da aka kunna rajistar bututun mai	Tushen agogo na duk rajistar bututun dole ne ya zama iri ɗaya.
Lokacin da kowane shigarwar ya yi rajista don siginar sarrafawa mai ƙarfi	Madogarar agogo don rajistar shigarwa don ƙarami, tarawa, ɗaukar nauyi, da rashin ƙarfi dole ne su kasance iri ɗaya.

Cyclone 10 GX Kafaffen Mahimman Bayanai DSP IP Core Signals

Hoto mai zuwa yana nuna shigarwar da siginonin fitarwa na Cyclone 10 GX Native Fixed Point DSP IP core.

Cyclone 10 GX Kafaffen Mahimman Bayanai DSP IP Core Signals

Siginonin Shigar Bayanai

Sunan siginar	Nau'in	Nisa	Bayani
gatari[]	Shigarwa	27	Shigar da bas ɗin bayanai zuwa sama mai yawa.
ay[]	Shigarwa	27	Shigar da bas ɗin bayanai zuwa sama mai yawa. Lokacin da aka kunna pre-adder, ana ba da waɗannan sigina azaman sigina na shigarwa zuwa saman pre-adder.
az[]	Shigarwa	26	Waɗannan sigina sigina ne na shigarwa zuwa saman pre-adder. Waɗannan sigina suna samuwa ne kawai lokacin da aka kunna pre-adder. Ba a samun waɗannan sigina a ciki m18×18_plus36 yanayin aiki.
bx[]	Shigarwa	18	Shigar da bas ɗin bayanai zuwa ƙasa mai yawa. Ba a samun waɗannan sigina a ciki m27×27 yanayin aiki.
ta[]	Shigarwa	19	Shigar da bas ɗin bayanai zuwa ƙasa mai yawa. Lokacin da aka kunna pre-adder, waɗannan sigina suna aiki azaman siginar shigarwa zuwa ƙasa pre-adder. Ba a samun waɗannan sigina a ciki m27×27 yanayin aiki.
bz[]	Shigarwa	18	Waɗannan sigina sigina ne na shigarwa zuwa ƙasa pre-adder. Waɗannan sigina suna samuwa ne kawai lokacin da aka kunna pre-adder. Ba a samun waɗannan sigina a ciki m27×27 kuma m18×18_plus36 hanyoyin aiki.

Sigina na Fitar bayanai

Sunan siginar	Nau'in	Nisa	Ƙaddamarwa
sakamako[]	Fitowa	64	Bus ɗin fitar da bayanai daga sama mai yawa. Waɗannan sigina suna tallafawa har zuwa 37 ragowa don m18×18_cikakken yanayin aiki.
sakamako[]	Fitowa	37	Bus ɗin fitarwa daga ƙasa mai yawa. Ana samun waɗannan sigina a ciki kawai m18×18_cikakken yanayin aiki.

Agogo, Kunna, da Share Sigina

Sunan siginar	Nau'in	Nisa	Bayani
clk[]	Shigarwa	3	Sigina na agogon shigarwa don duk rajista. Waɗannan sigina na agogo suna samuwa ne kawai idan an saita kowane rajistar shigarwa, rajistar bututu, ko rajistar fitarwa zuwa Agogo0, Agogo1, ko Agogo2. • clk[0] = Agogo0 • clk[1] = Agogo1 • clk[2] = Agogo2
ina[]	Shigarwa	3	Kunna agogo don clk[2:0]. Wannan siginar yana aiki-Mai girma. • ena[0] don Agogo0 • ena[1] don Agogo1 • ena[2] don Agogo2
aclr[]	Shigarwa	2	Siginonin shigarwa masu daidaitawa ga duk rijistar. Wannan siginar yana aiki-Mai girma. Amfani aclr[0] don duk shigarwar rajista da amfani aclr[1] ga duk rajistar bututun mai da rajistar fitarwa. Ta hanyar tsoho, wannan siginar an soke shi.

Siginonin Sarrafa Mai ƙarfi

Sunan siginar	Nau'in	Nisa	Bayani
sub	Shigarwa	1	Siginar shigarwa don ƙarawa ko žasa abin da ake samu na babban mai yawa tare da fitowar mai yawa na ƙasa. • Saka wannan siginar don tantance aikin ƙari. Tabbatar da wannan siginar don tantance aikin ragi. Ta hanyar tsohuwa, wannan siginar an yayyafa shi. Kuna iya tabbatarwa ko saka wannan siginar yayin lokacin gudu.(3)
rashin gaskiya	Shigarwa	1	Siginar shigarwa don ƙara ko rage jimlar masu ninkawa sama da ƙasa tare da bayanai daga siginonin sarƙoƙi. • Saka wannan siginar don tantance aikin ƙari. Tabbatar da wannan siginar don tantance aikin ragi. Ta hanyar tsohuwa, wannan siginar an yayyafa shi. Kuna iya tabbatarwa ko saka wannan siginar yayin lokacin gudu.(3)
tara	Shigarwa	1	Siginar shigarwa don kunna ko kashe fasalin tarawa. • Saka wannan siginar don kashe fasalin tarawa. Tabbatar da wannan siginar don kunna fasalin tarawa. Ta hanyar tsohuwa, wannan siginar an yayyafa shi. Kuna iya tabbatarwa ko saka wannan siginar yayin lokacin gudu.(3)
loadconst	Shigarwa	1	Siginar shigarwa don kunna ko kashe fasalin kullun kaya. • Saka wannan siginar don musaki fasalin kullun da ake ɗauka. Tabbatar da wannan siginar don ba da damar siginar lodi akai-akai. Ta hanyar tsohuwa, wannan siginar an yayyafa shi. Kuna iya tabbatarwa ko saka wannan siginar yayin lokacin gudu.(3)

Sigina Haɗin Kai na Ciki

Sunan siginar	Nau'in	Nisa	Bayani
coefsela[]	Shigarwa	3	Alamun zaɓin shigarwa don ƙima mai ƙima 8 wanda mai amfani ya ayyana don babban mai ninka. Ana adana ƙididdiga masu ƙima a cikin ƙwaƙwalwar ajiyar ciki kuma an ƙayyade ta sigogi coef_a_0 ku coef_a_7. • coefsela[2:0] = 000 yana nufin coef_a_0 • coefsela[2:0] = 001 yana nufin coef_a_1 • coelsela[2:0] = 010 yana nufin coef_a_2 •… da sauransu. Waɗannan sigina suna samuwa ne kawai lokacin da aka kunna fasalin haɗin kai na ciki.
coefselb[]	Shigarwa	3	Alamun zaɓin shigarwa don ƙima mai ƙima 8 wanda mai amfani ya ayyana don mai ninka na ƙasa. Ana adana ƙididdiga masu ƙima a cikin ƙwaƙwalwar ajiyar ciki kuma an ƙayyade ta sigogi coef_b_0 ku coef_b_7. • coefselb[2:0] = 000 yana nufin coef_b_0 • coefselb[2:0] = 001 yana nufin coef_b_1 • coelselb[2:0] = 010 yana nufin coef_b_2 •… da sauransu. Waɗannan sigina suna samuwa ne kawai lokacin da aka kunna fasalin haɗin kai na ciki.

Shigar da Siginonin Cascade

Sunan siginar	Nau'in	Nisa	Bayani
scanin[]	Shigarwa	27	Bus ɗin bayanai don shigar da kascade module. Haɗa waɗannan sigina zuwa siginar dubawa daga ainihin DSP da ta gabata.
scanout[]	Fitowa	27	Bus ɗin bayanan fitarwa na tsarin shigar da cascade. Haɗa waɗannan sigina zuwa siginar na'urar daukar hoto na ainihin DSP na gaba.

Fitar da Siginonin Cascade

Sunan siginar	Nau'in	Nisa	Bayani
sarkar[]	Shigarwa	64	Bus ɗin bayanai don shigar da bayanan kascade. Haɗa waɗannan sigina zuwa siginar sarƙoƙi daga ainihin DSP na gaba.
sarkar[]	Fitowa	64	Bus ɗin bayanan fitarwa na samfurin kascade mai fitarwa. Haɗa waɗannan sigina zuwa siginar chainin na ainihin DSP na gaba.

Tarihin Bita na Takardu don Cyclone 10 GX Kafaffen Mahimman Bayanai DSP IP Core User Guide

Kwanan wata	Sigar	Canje-canje
Nuwamba 2017	2017.11.06	Sakin farko.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aikin FPGA da samfuran semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.

Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.

Takardu / Albarkatu

intel UG-20094 Cyclone 10 GX Kafaffen Ma'anar DSP IP Core [pdf] Jagorar mai amfani UG-20094 Cyclone 10 GX Native Fixed Point DSP IP Core, UG-20094, Cyclone 10 GX Native Fixed Point DSP IP Core, DSP IP Core, DSP IP Core, DSP IP Core.

Magana

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