I-AN 824 FPGA SDK yeBhodi le-OpenCL
Ukusekela Iphakheji Floorplan
Umhlahlandlela Womsebenzisi

 I-Intel® FPGA SDK ye I-OpenCL ™ Board Support Package ye-Floorplan Umhlahlandlela Wokuthuthukisa
I-Intel/® FPGA SDK ye-OpenCL™ Board Support Package (BSP) Floorplan Optimization Guide inikeza imihlahlandlela yokuhlela phansi ye-OpenCL) BSP. Iphinde inikeze umhlahlandlela wokuthi ungayithola kanjani imbewu yesisekelo ene-avareji ephezulu yokusebenza evamile futhi uhlole ukusebenza kahle kokusetshenziswa kwensiza ye-BSP.
Lo mbhalo ucabanga ukuthi uyayazi imiqondo ye-OpenCL(2) njengoba ichazwe enguqulweni ye-OpenCL Specification 1.0 yiQembu le-Khronos.

I-OpenCL BSP Compilation Flow
I-OpenCL BSP isekela izinhlobo ezilandelayo zokugeleza kokuhlanganiswa:

• I-Flat compile [–bsp-flow flat]: Lenza inhlanganisela eyisicaba yawo wonke umklamo (i-BSP kanye nezingxenyekazi zekhompyutha ezikhiqizwe yi-kernel).
• Isisekelo sokuhlanganisa [–bsp-flow base]: Yenza ukuhlanganiswa kwesisekelo ngokusebenzisa imikhawulo ye-LogicLock evela ku-base.qsf file. Iwashi le-kernel eliqondiwe lixegisiwe ukuze ihadiwe ye-BSP ibe nenkululeko eyengeziwe yokuhlangabezana nesikhathi. Isizindalwazi se-base.qar sidalelwe ukulondoloza ihadiwe ye-BSP, okuyisifunda esimile.
• Ngenisa iqoqo [ ]: Ibuyisela isikhathi isifunda esimile esivaliwe kusukela kusizindalwazi se-base.qar futhi ihlanganisa kuphela ihadiwe ekhiqizwe i-kernel. Iphinde inyuse iwashi le-kernel ukuze kutholwe imvamisa yokusebenza ephezulu kakhulu ye-kernel (fmax).

I-OpenCL BSP Floorplan Partition
I-OpenCL BSP floorplan ihlukaniswe ikakhulukazi izifunda ezimbili ezilandelayo:

• Isifunda esimile: Imele isifunda esinezingxenyekazi zekhompuyutha ezihlobene ne-BSP ezihlala zimile. Isikhathi sivaliwe kulesi sifunda ngesikhathi sokuhlanganiswa kwesisekelo. Ngokuvamile, umgomo uwukunciphisa izinsiza ze-chip ezisetshenziswa yilesi sifunda ukuvala isikhathi.
• Isifunda se-Kernel: Imele isifunda sokulungiswa kabusha kwengxenye (PR) ebekelwe imojuli ye-freeze_wrapper_inst|kernel_system_inst, equkethe i-kernel. Ngokuvamile, umgomo uwukugcina izinsiza ze-chip zibe sezingeni eliphezulu kulesi sifunda.

1. I-Intel FPGA SDK ye-OpenCL isuselwe ku-Khronos Specification eshicilelwe, futhi iphumelele Inqubo Yokuhlola Ukuvumelana kwe-Khronos. Isimo samanje sokuvumelana singatholakala kokuthi www.khronos.org/conformance.
2. I-OpenCL kanye nelogo ye-OpenCL yizimpawu zokuthengisa ze-Apple Inc. futhi zisetshenziswa ngemvume ye-Khronos Group™.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
*Amanye amagama namabhrendi angafunwa njengempahla yabanye.

Imihlahlandlela ye-OpenCL BSP Floorplanning

• Qala ngokuhlanganisa okuyisicaba ukuze uqonde lapho zonke izingxenye eziyinhloko ze-BSP zibekwa ngokwemvelo (ikakhulukazi i-IP ivimba ngoxhumo lwe-I/O olufana ne-PCIe noma i-DDR). Ngenkathi uklama i-BSP, kungase kudingeke ucabange ukusungula amaphayiphitagiphakathi kwama-IP ukuze kuvalwe isikhathi. Kufanele uqale usebenzise ukushanela kwembewu yeqoqo eliyisicaba ukuze ubone izindlela eziphindelelayo ezihlulekayo, bese uzama ukuzilungisa.
  Ithiphu: - Izinga elihle lokuvalwa kwesikhathi ekushanelweni kwembewu ehlanganisiwe lizoba namathuba aphezulu okuvala isikhathi sokuhlanganisa isisekelo.
  — Uma ubona ukwehluleka okungaguquki ku-mm_interconnect* (ingxenye yengezwe yi-Qsys), bese uvula Isistimu ene-Qsys Interconnect viewbese ubheka ubunkimbinkimbi bokuxhumana okuhlulekayo. Ungangeza ama-pipelining flipflops ku- viewer ukuthuthukisa isikhathi. Uma namanje ungakwazi ukubhekana nenkinga, kungase kudingeke ukuthi wephule indlela ebalulekile ye-mm_interconnect* ngokwengeza amabhuloho epayipi le-Avalon.
• Ngesikhathi sokuhlanganiswa kwesisekelo, qala nge-LogicLock endaweni ye-kernel equkethe okuthi freeze_wrapper_inst|kernel_system_inst. Ngaphandle kweminye imikhawulo, i-Intel Quartus Prime ingabeka ihadiwe ye-BSP ngokukhululeka endaweni esele ye-chip. Sebenzisa iqoqo eliyisicaba kanye nesihleli se-chip ukuze uhlonze usayizi nendawo yehadiwe ye-BSP, njenge-PCIe ne-DDR. Bese, gcina isifunda se-kernel ngokusebenzisa i-LogicLock ngenkathi ugwema izindawo ezihlanganisiwe eziyinhloko zehadiwe ye-BSP.
  Ithiphu: Uma umndeni we-chip osetshenzisiwe ufana nenkundla yesithenjwa futhi uma izingxenye ze-BSP zifana, kungase kusheshe ukuqala ngezifunda ze-LogicLock ze-freeze_wrapper_inst|kernel_system_inst ezithunyelwa nge-OpenCL reference BSP futhi sibhekane nokwehluleka.
• Ungangeza izingxenye ezengeziwe ezilandelayo ku-BSP yakho:
  — Amabhange enkumbulo: Uma wengeza amabhange enkumbulo engeziwe, kufanele ukhombe indawo yebhange le-I/O njengoba kungase kudingeke wengeze amabhuloho ukuze uhlangabezane nesikhathi.
  — Amashaneli e-I/O: Ungengeza amashaneli e-I/O njengevidiyo, i-Ethernet, noma isixhumi esibonakalayo se-serial. Uma ungeza iziteshi ze-I/O, kufanele ukhombe indawo yasebhange ye-I/O njengoba ungase udinge ukusebenzisa izifunda ezintsha ze-LogicLock ukuze kufakwe amapayipi uma isikhathi sokuvala sinzima.
  Ithiphu: Uma udinga ukwengeza amabhuloho amapayipi (ngokwesiboneloample, ngenxa yokubambezeleka okukhulu komzila okubangela ukuhluleka kwesikhathi), bese ucabangela ibanga lomzila ukusuka emthonjeni ukuya endaweni enengqondo ku-chip bese ukhulula isikhala esithile ebekelwe isifunda se-kernel.
• Landela le mihlahlandlela ejwayelekile lapho ubhukha izifunda ze-LogicLock ze-kernel:
  - Zama ukubeka wonke amakholomu e-DSP ku-kernel_system ngaphandle uma kudingwa i-BSP.
  - Zama ukugcina izinsiza ezengeziwe ze-kernel_system.
  - Zama ukugcina inani lamanotshi endaweni ye-kernel libe lincane.
  Isibalo esilandelayo sibonisa inothi eyengezwe ukuze kubekwe ibhuloho lamapayipi phakathi kwe-PCIe ne-DDR bank.

Umfanekiso 1. I-OpenCL BSP Floorplan ye-Intel Arria® 10 GX ekukhishweni kwe-17.0

Imihlahlandlela Yezikhathi Eziningi Zokusebenza
Ubuningi bemvamisa yokusebenza (i-fmax) etholwe ama-kernel ngokuvamile incike kusivinini se-FPGA njengoba iningi lama-IP kufanele selilungiselelwe kakade . Nokho, kungase kube nokulahlekelwa okuthile kwe-fmax kuye ngohlelo lwaphansi lwe-BSP. Okwesiboneloample, ngokuvamile inombolo yokusikwa endaweni ye-kernel ye-BSP ithinta i-kernel fmax.
Njengoba kubonisiwe emfanekisweni olandelayo, ukuthola imbewu eyisisekelo engcono kakhulu ekhiqiza isilinganiso esihle kakhulu se-fmax:

1. Yenza ukushanela kwembewu ekuhlanganisweni kwesisekelo esikhundleni sokukhetha imbewu yokuqala yesisekelo ehlangabezana nesikhathi.
2. Yenza ukuhlanganiswa kokungenisa (ngokusebenzisa izinhlamvu ezimbalwa ezivela ku-example designs) kuzo zonke izimbewu zesisekelo ezidlulayo.
3. Bala isilinganiso se-fmax sazo zonke izimbewu eziyisisekelo.
4. Khetha imbewu yesisekelo ekhiqiza isilinganiso esiphezulu se-fmax.
   Imbewu eyisisekelo ene-avareji engcono kakhulu ye-fmax iyikhandidethi elihle lokukhululwa nge-BSP. Uma unquma ukulandela indlela ehlukile kunezinyathelo ezinconyiwe, ungase ubone ukuhluka okungu-5-10% ku-fmax yenqubo yokuhlanganisa i-kernel yokungenisa.

Umfanekiso 2. Ukuhlonza Imbewu Eyisisekelo Engcono Kakhulu

• Ukuze uqonde ukuthi i-kernel ingasebenza ngokushesha kangakanani ngaphandle kwemikhawulo ye-floorplan:
  1. Yenza ukuhlanganiswa okuyisicaba kwe-kernel bese ubheka i-fmax.
  2. Enza ukuhlanganisa kokungenisa ku-kernel efanayo bese ubheka i-fmax.
  3. Qhathanisa imiphumela ye-fmax.
  Ngenxa yemikhawulo ye-floorplan, i-import compile fmax ihlala iphansi kune-flat compile fmax. Ukuze ugweme umsindo wembewu, hlanganisa i-kernel nembewu yesisekelo eyengeziwe bese ucabangela isilinganiso se-fmax ngenkathi uqhathanisa imiphumela ye-fmax.
• Ungalokothi uqhathanise i-kernel fmax kusukela ekuhlanganisweni kwesisekelo nefulethi noma ukuhlanganiswa kokungenisa. Okuqondiwe kwewashi le-Kernel kuyaxegiswa ngesikhathi sokuhlanganiswa kwesisekelo ngakho-ke awusoze wathola imiphumela emihle.
• Qaphela indlela ebalulekile yewashi le-kernel ekuhlanganiseni kwesisekelo noma kokungenisa. Uma indlela ebucayi inqamula isuka ku-kernel iye endaweni emile ku-floorplan, shintsha i-floorplan noma usebenzise imbewu yesisekelo embalwa ukuze ugweme le ndlela ebucayi.

Imihlahlandlela Yokuhlola Ukusebenza Kwensiza Ye-BSP

Amaphesenti aphezulu okusetshenziswa kwezinsizatage, kungcono ukusetshenziswa kwendawo endaweni emile ye-BSP yakho. Amaphesenti aphezulu okusetshenziswa kwezinsizatage futhi isho ukuthi izinsiza ezengeziwe ziyatholakala endaweni ye-kernel.
Landela izinyathelo ezingezansi ukuze ubale amaphesenti okusetshenziswa kwensizatage ye-BSP yakho:

1. Thola amanani azo zonke izinsiza ku-FPGA kusuka phezulu.fit.rpt noma i-base.fit.rpt etholakala ngaphansi kwesigaba Sezibalo Zesigaba sombiko we-Fitter.
2. Khipha inani le-“freeze_wrapper_inst|kernel_system_inst” (isifunda se-kernel).

Ithiphu:
Gxila kakhulu kumanani we-adaptive logic module (ALM) kunamanani ezinye izisetshenziswa. Qinisekisa ukuthi amaphesenti okusetshenziswa kwezinsizatagI-e ye-ALM iseduze ne-OpenCL reference BSP. Amaphesenti aphezulu kakhulutagI-e ye-ALM ingase iholele ekuminyaniseni, okungase kwenyuse isikhathi sokuhlanganisa futhi yethule ukuminyana komzila kuma-kernels ayinkimbinkimbi. Nokho, ungakwazi njalo ukwandisa noma wehlise indawo yesifunda emile, futhi ubheke isikhathi sokuhlanganiswa kanye ne-fmax.
Ithebula elilandelayo libonisa ukusetshenziswa kwensiza ye-OpenCL BSP yamadivayisi e-Arria ® 10 GX ekukhishweni kwe-17.0.

Ithebula 1.
Ukusetshenziswa Kwensiza ye-OpenCL BSP yamadivayisi we-IntelArria 10 GX ekukhishweni kwe-17.0

	Inani Elitholakalayo	Kugcinelwe i-Kernel	Itholakalela i-BSP	Isetshenziswa yi-BSP	0/0
LM	427200	393800	33400	23818.	71.%
Amarejista	1708800	1575200	133600	38913	29.%
M2KULUNGILE	2713	2534	179	134	75.%
I-DSP	1518	1518	0	0	N/A

Qaphela ukuthi i-floorplanning yenziwa ngendlela yokuthi isifunda esimile ngeke sibe namabhulokhi e-DSP.

Umlando Wokubuyekeza Idokhumenti

Ithebula 2.
Umlando Wokubuyekezwa Kombhalo we-Intel FPGA SDK ye-OpenCL Board Support Package Floorplan optimization Guide

Usuku	Inguqulo	Izinguquko
Agasti-17		Ukukhishwa kokuqala.

I-Online Version
Thumela Impendulo
Inombolo yepholisi: 683312
I-AN-824
Inguqulo: 2017.08.08
I-AN 824: Intel® FPGA SDK ye-OpenCL™ Board
Umhlahlandlela Wokusekela Wephakheji Ye-Floorplan

Amadokhumenti / Izinsiza

i-intel AN 824 FPGA SDK ye-OpenCL Board Support Package Floorplan [pdf] Umhlahlandlela Womsebenzisi I-AN 824 FPGA SDK ye-OpenCL Board Support Package Floorplan, AN 824, FPGA SDK ye-OpenCL Board Support Package Floorplan, I-OpenCL Board Support Package Floorplan, I-Board Support Package Floorplan, I-Support Package Floorplan, Floorplan Yephakheji,

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