AN 824 FPGA SDK don OpenCL Board
Taimako Kunshin Tsarin Floorplan
Jagorar Mai Amfani

 Intel® FPGA SDK don Buɗe CL ™ Hukumar Tallafin Fakitin Ingantaccen Tsarin Falo
Intel/® FPGA SDK don Kunshin Tallafi na Board na OpenCL™ (BSP) Jagoran Inganta Tsarin ƙasa yana ba da jagororin tsara ƙasa don OpenCL) BSP. Hakanan yana ba da jagora kan yadda zaku iya samun nau'in tushe tare da mafi kyawun matsakaicin matsakaicin matsakaicin aiki da kimanta ingancin amfanin albarkatun BSP.
Wannan takaddar tana ɗauka cewa kun saba da ra'ayoyin OpenCL(2) kamar yadda aka bayyana a cikin sigar Ƙaddamarwa ta OpenCL 1.0 ta Ƙungiyar Khronos.

BudeCL BSP Tarin Gudun Gudun
OpenCL BSP tana goyan bayan nau'ikan rarrabuwa masu zuwa:

• Flat compile [–bsp-flow flat]: Yana aiwatar da tsarin ƙira gabaɗaya (BSP tare da kayan aikin kwaya da aka samar).
• Tarin tushe [–bsp-flow base]: Yana aiwatar da harhada tushe ta amfani da ƙuntatawa na LogicLock daga base.qsf file. Maƙasudin agogon kwaya yana da annashuwa domin kayan aikin BSP su sami ƙarin 'yanci don saduwa da lokaci. An ƙirƙiri tushen bayanai na base.qar don adana kayan aikin BSP, wanda shine yanki na tsaye.
• Shigo da harhada [ ]: Yana mayar da lokacin da aka rufe a tsaye daga tushen bayanai.qar kuma yana tattara kayan aikin kwaya kawai. Hakanan yana ƙara maƙasudin agogon kwaya don samun mafi kyawun mitar kernel (fmax).

BudeCL BSP Rarraba Floorplan
OpenCL BSP shirin bene an raba shi zuwa yankuna biyu masu zuwa:

• Yanki a tsaye: Yana wakiltar yankin da ke da kayan aikin BSP masu alaƙa wanda ya tsaya a tsaye. An rufe lokacin don wannan yanki yayin haɗa tushe. Gabaɗaya, makasudin shine a rage albarkatun guntu da wannan yanki ke amfani da shi don rufe lokaci.
• Yankin Kernel: Yana wakiltar yanki na sake fasalin (PR) wanda aka tanada don freeze_wrapper_inst| kernel_system_inst module, wanda ya ƙunshi kernel. Gabaɗaya, makasudin shine adana albarkatun guntu zuwa iyakar iyakar wannan yanki.

1. Intel FPGA SDK na OpenCL ya dogara ne akan ƙayyadaddun ƙayyadaddun Khronos da aka buga, kuma ya wuce Tsarin Gwajin Ƙarfafawa na Khronos. Ana iya samun matsayin yarda na yanzu a www.khronos.org/conformance.
2. OpenCL da tambarin OpenCL alamun kasuwanci ne na Apple Inc. kuma ana amfani da su ta izinin Khronos Group™.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

Jagororin don BudeCL BSP Shirye-shiryen Falo

• Fara tare da haɗaɗɗiyar lebur don fahimtar inda duk manyan abubuwan da ke cikin BSP ke sanya su ta zahiri (musamman tubalan IP tare da haɗin I/O kamar PCIe ko DDR). Yayin zayyana BSP, ƙila za ku yi la'akari da kafa bututun stages tsakanin IPs don rufe lokaci. Ya kamata ku fara aiwatar da share iri mai lebur don gano hanyoyin da ba su ci gaba ba, sannan kuyi ƙoƙarin gyara su.
  Tukwici: - Kyakkyawan ƙimar lokacin rufewa akan share iri mai lebur zai sami babban damar rufe tushen tattara lokacin.
  - Idan kun lura da rashin gazawa a cikin mm_interconnect* (bangaren da Qsys ya ƙara), sannan buɗe tsarin tare da Qsys Interconnect viewer kuma lura da sarkar haɗin haɗin gwiwar da ke kasa. Kuna iya ƙara flipflops na bututu a cikin viewer don inganta lokaci. Idan har yanzu ba za ku iya magance matsalar ba, kuna iya lalata hanyar mm_interconnect* ta hanyar ƙara gadoji na bututun Avalon.
• Yayin hada tushe, fara da LogicLock akan yankin kwaya wanda ya ƙunshi freeze_wrapper_inst|kernel_system_inst. Ba tare da wasu hani ba, Intel Quartus Prime na iya sanya kayan aikin BSP kyauta a cikin sauran yanki na guntu. Yi amfani da haɗaɗɗen lebur da mai tsara guntu don gano girman da wurin kayan aikin BSP, kamar PCIe da DDR. Sannan, ajiye yankin kwaya ta amfani da LogicLock yayin guje wa manyan wuraren da aka taru na kayan aikin BSP.
  Tukwici: Idan dangin guntu da aka yi amfani da su iri ɗaya ne da dandamalin tunani kuma idan abubuwan BSP sun yi kama da juna, yana iya zama da sauri a fara tare da yankuna LogicLock don freeze_wrapper_inst|kernel_system_inst wanda aka aika tare da Buɗen bayanin BSP kuma yana aiki ta hanyar gazawar.
• Kuna iya ƙara ƙarin abubuwan da aka haɗa zuwa BSP ɗin ku:
  - Bankunan ƙwaƙwalwar ajiya: Idan kun ƙara ƙarin bankunan ƙwaƙwalwar ajiya, yakamata ku gano wurin bankin I/O tunda kuna iya buƙatar ƙara gadojin bututun don saduwa da lokaci.
  - Tashoshin I/O: Kuna iya ƙara tashoshi na I/O kamar bidiyo, Ethernet, ko serial interface. Idan kun ƙara tashoshin I/O, yakamata ku gano wurin bankin I/O tunda kuna iya buƙatar amfani da sabbin yankuna LogicLock don bututun mai idan lokacin rufewa yana da wahala.
  Tukwici: Idan kuna buƙatar ƙara gadojin bututu (misaliample, saboda babban jinkirin zirga-zirgar da ke haifar da gazawar lokaci), sannan la'akari da nisa ta hanya daga tushe zuwa dabarar manufa a cikin guntu kuma saki wasu sarari da aka tanada don yankin kernel.
• Bi waɗannan jagororin gabaɗayan lokacin da ke tanadin yankuna LogicLock don kwaya:
  - Ƙoƙarin sanya duk ginshiƙan DSP a cikin tsarin kernel_sai dai idan BSP ta buƙata.
  - Ƙoƙarin tanadin ƙarin albarkatu don tsarin kernel_system.
  - Ƙoƙarin kiyaye adadin ƙididdiga a cikin yankin kwaya zuwa ƙarami.
  Hoton da ke gaba yana kwatanta ƙimar da aka ƙara don sanya gadar bututu tsakanin PCIe da bankin DDR.

Hoto 1. Buɗe CL BSP Floorplan don Intel Arria® 10 GX a cikin Sakin 17.0

Jagora don Matsakaicin Mitar Aiki
Matsakaicin mitar aiki (fmax) da kernels ke samu ya dogara da saurin FPGA tunda yawancin IPs yakamata a inganta su. Koyaya, ana iya samun wasu asarar fmax dangane da tsarin bene na BSP. Domin misaliample, yawanci adadin yankewa a yankin kwaya na BSP yana shafar fmax kwaya.
Kamar yadda aka kwatanta a cikin adadi mai zuwa, don samun mafi kyawun iri mai tushe wanda ke samar da mafi kyawun matsakaicin fmax:

1. Yi share iri akan harhada tushe maimakon zaɓin iri na farko wanda ya dace da lokacin.
2. Yi lissafin shigo da kaya (ta amfani da ƴan kernels daga tsohonample designs) a kan duk tushen da ke wucewa.
3. Yi lissafin matsakaicin fmax don duk tushen tsaba.
4. Zaɓi tushen iri wanda ke samar da matsakaicin matsakaicin fmax.
   Tushen iri tare da mafi kyawun matsakaicin fmax shine ɗan takara mai kyau don saki tare da BSP. Idan ka yanke shawarar bin wata hanya daban da matakan da aka ba da shawarar, za ka iya lura da bambancin 5-10% a cikin fmax na tsarin tattara kernel.

Hoto 2. Gano Mafi Kyau Tushen iri

• Don fahimtar saurin kernel ɗin zai iya gudana ba tare da ƙuntatawa ba:
  1. Yi taɗi mai lebur na kwaya kuma lura fmax.
  2. Yi tarin shigo da kaya akan kwaya ɗaya kuma kula fmax.
  3. Kwatanta sakamakon fmax.
  Saboda ƙayyadaddun ƙayyadaddun tsarin ƙasa, shigo da haɗa fmax koyaushe yana ƙasa da filaye tara fmax. Don guje wa hayaniyar iri, tara kernel tare da ƙarin tushen tsaba kuma la'akari da matsakaicin fmax yayin kwatanta sakamakon fmax.
• Kar a taɓa kwatanta kwaya fmax daga haɗaɗɗiyar tushe tare da lebur ko haɗar shigo da kaya. Maƙasudin agogon kwaya suna annashuwa yayin haɗa tushe kuma don haka, ba za ku taɓa samun sakamako mai kyau ba.
• Lura da mahimmancin agogon kwaya a cikin harhada tushe ko shigo da kaya. Idan hanya mai mahimmanci tana hayewa daga kwaya zuwa yanki a tsaye a cikin shirin bene, canza tsarin bene ko gudanar da wasu 'yan tushe kaɗan don guje wa wannan hanya mai mahimmanci.

Sharuɗɗa don Ƙimar Ingancin Amfani da Albarkatun BSP

Mafi girman kashi na amfanin albarkatun ƙasatage, mafi kyawun amfani da yanki a cikin tsayayyen yanki na BSP ɗin ku. Babban kashi na amfani da albarkatutage kuma yana nuna cewa akwai ƙarin albarkatu don yankin kwaya.
Bi matakan da ke ƙasa don ƙididdige kashi na amfanin albarkatun ƙasatage na BSP ku:

1. Sami ƙima ga duk albarkatu a cikin FPGA daga saman.fit.rpt ko base.fit.rpt da ake samu a ƙarƙashin sashin Ƙididdiga na Rarraba na rahoton Fitter.
2. Cire ƙimar "freeze_wrapper_inst|kernel_system_inst" (yankin kernel).

Tukwici:
Mai da hankali kan ƙimar ma'auni na adaftar ma'ana (ALM) fiye da ƙimar sauran albarkatun. Tabbatar da cewa kashi na amfanin albarkatun ƙasatage don ALM ya fi kusa da OpenCL tunani BSP. Kashi mai girma sosaitage ga ALM na iya haifar da cunkoso, wanda zai iya ƙara lokacin tattarawa da gabatar da cunkoson ababen hawa a cikin hadaddun kernels. Koyaya, koyaushe kuna iya ƙarawa ko raguwa a tsaye yankin yanki, kuma ku lura da lokacin tattarawa da fmax.
Tebur mai zuwa yana nuna amfani da albarkatu na OpenCL BSP na na'urorin Arria ® 10 GX a cikin sakin 17.0.

Tebur 1.
BudeCL BSP Amfani da Albarkatun Na'urorin IntelArria 10 GX a cikin Sakin 17.0

	Gabaɗaya Akwai	An tanadi don Kernel	Akwai don BSP	Ana amfani da BSP	0/0
ALM	427200	393800	33400	23818.	71%
Masu yin rijista	1708800	1575200	133600	38913	29%
M2OK	2713	2534	179	134	75%
DSP	1518	1518	0	0	N/A

Lura cewa ana aiwatar da tsarin shimfidar ƙasa ta yadda yankin na tsaye ba zai sami tubalan DSP ba.

Tarihin Bita daftarin aiki

Tebur 2.
Tarihin Bita na Daftarin aiki na Intel FPGA SDK don Jagoran Haɓaka Fakitin Tallafin Filayen Buɗe

Kwanan wata	Sigar	Canje-canje
Agusta-17		Sakin farko.

Online Version
Aika da martani
Saukewa: 683312
AN-824
Shafin: 2017.08.08
AN 824: Intel® FPGA SDK don OpenCL™ Board
Taimako Kunshin Tallafi Jagoran Haɓaka Tsarin Gida

Takardu / Albarkatu

intel AN 824 FPGA SDK don Shirye-shiryen Fakitin Tallafi na Board OpenCL [pdf] Jagorar mai amfani AN 824 FPGA SDK don Buɗewar Fakitin Tallafin Board Plan, AN 824, FPGA SDK don Buɗewar Fakitin Tallafin Gidan Gida

Magana

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