AN 824 FPGA SDK yeOpenCL Board
Tsigira Package Floorplan
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 Intel® FPGA SDK ye OpenCL ™ Bhodhi Inotsigira Package Floorplan Optimization Guide
Iyo Intel/® FPGA SDK yeOpenCL™ Board Support Package (BSP) Floorplan Optimization Guide inopa nhungamiro yekuronga pasi yeOpenCL) BSP. Inopawo gwara rekuti iwe ungawana sei mhodzi yehwaro ine yakanakisa avhareji yepamusoro yekushanda frequency uye ongorora BSP zviwanikwa zvekushandisa.
Gwaro iri rinofungidzira kuti unoziva nezve OpenCL(2) pfungwa sekutsanangurwa kwazvinoitwa muOpenCL Specification vhezheni 1.0 neKhronos Group.

OpenCL BSP Compilation Flow
OpenCL BSP inotsigira anotevera marudzi ekuunganidza anoyerera:

• Flat compile [-bsp-flow flat]: Inoita mubatanidzwa wakafuratira wedhizaini yese (BSP pamwe chete nekernel yakagadzirwa Hardware).
• Base compile [-bsp-flow base]: Inoita chigadziko chekubatanidza nekushandisa LogicLock zvirambidzo kubva pabase.qsf file. Iyo kernel wachi yakanangwa yakadzoreredzwa kuitira kuti BSP hardware ive nerusununguko rwakawanda rwekusangana nenguva. Base.qar dhatabhesi yakagadzirwa kuchengetedza iyo BSP hardware, inova dunhu rakamira.
• Kupinza muunganidzwa [ ]: Inodzoreredza nguva yakavharwa static dunhu kubva ku base.qar dhatabhesi uye inounganidza chete kernel yakagadzirwa hardware. Iyo inowedzerawo kernel wachi chinangwa kuti uwane yakanakisa kernel yakanyanya kushanda frequency (fmax).

OpenCL BSP Floorplan Partition
OpenCL BSP floorplan inonyanya kukamurwa kuita matunhu maviri anotevera:

• Static dunhu: Inomiririra dunhu rine BSP ine hukama hardware inoramba yakamira. Nguva yakavharwa yedunhu iri panguva yekugadzira base. Kazhinji, chinangwa ndechekudzikisa zviwanikwa zvechip zvinoshandiswa nedunhu iri kuvhara nguva.
• Kernel dunhu: Inomiririra chikamu chekugadzirisa (PR) dunhu rakachengeterwa freeze_wrapper_inst|kernel_system_inst module, ine kernel. Kazhinji, chinangwa ndechekuchengetedza chip zviwanikwa kusvika pamwero mukuru wedunhu rino.

1. Iyo Intel FPGA SDK yeOpenCL yakavakirwa pane yakaburitswa Khronos Specification, uye yakapfuura iyo Khronos Conformance Yekuyedza Maitiro. Ikozvino kuenderana mamiriro anogona kuwanikwa pa www.khronos.org/conformance.
2. OpenCL nelogo yeOpenCL zviratidzo zveApple Inc. uye zvinoshandiswa nemvumo yeKhronos Group™.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
*Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Nhungamiro yeOpenCL BSP Floorplanning

• Tanga nekuumbwa kweflat kuti unzwisise kuti zvese zvakakosha zveBSP zvinoiswa papi (kunyanya iyo IP inovhara neI / O yekubatanidza sePCIe kana DDR). Paunenge uchigadzira iyo BSP, ungango funga kumisikidza pombi stagiri pakati peIPs kuvhara nguva. Iwe unofanirwa kutanga wamhanyisa kutsvaira kwembeu kuti uone nzira dzinoramba dzichitadza, wozoedza kudzigadzirisa.
  Zano: - Yakanaka nguva yekuvhara mwero pamusoro pekutsvaira kwembeu inotsvaira ichave nemikana yakakwira yekuvhara base yekuunganidza nguva.
  - Kana iwe ukaona kutadza kunoenderana mumm_interconnect* (chikamu chakawedzerwa neQsys), wobva wavhura iyo System neQsys Interconnect viewer uye tarisa kuoma kwekutadza kwekubatanidza. Iwe unogona kuwedzera pipelining flipflops mu viewer kuvandudza nguva. Kana iwe uchiri kutadza kugadzirisa nyaya, ungangofanira kuputsa iyo mm_interconnect* yakakosha nzira nekuwedzera Avalon pombi mabhiriji.
• Munguva yekubatanidza kwekutanga, tanga neLogicLock pane kernel dunhu rine freeze_wrapper_inst|kernel_system_inst. Pasina zvimwe zvirambidzo, Intel Quartus Prime inogona kuisa iyo BSP hardware zvakasununguka munzvimbo yasara static yechip. Shandisa iyo flat compile uye chip planner kuona saizi nenzvimbo yeBSP hardware, sePCIe neDDR. Zvadaro, chengetedza kernel dunhu nekushandisa LogicLock uchidzivirira nzvimbo dzakaungana dzeBSP hardware.
  Zano: Kana iyo chip mhuri yakashandiswa yakafanana neyereferensi papuratifomu uye kana zvikamu zveBSP zvakafanana, zvinogona kukurumidza kutanga neLogicLock matunhu efreeze_wrapper_inst|kernel_system_inst iyo inotumirwa neOpenCL reference BSP uye kushanda kuburikidza nekutadza.
• Iwe unogona kuwedzera zvinotevera zvimwe zvikamu kuBSP yako:
  - Memory mabhangi: Kana iwe ukawedzera mamwe ndangariro mabhangi, iwe unofanirwa kuona iyo I / O bhangi nzvimbo sezvo ungangoda kuwedzera mapaipi mabhiriji kusangana nenguva.
  - I/O zviteshi: Unogona kuwedzera I/O chiteshi sevhidhiyo, Ethernet, kana serial interface. Kana iwe ukawedzera I/O chiteshi, iwe unofanirwa kuona iyo I/O bhangi nzvimbo sezvo ungangoda kuisa matunhu matsva eLogicLock ekuputira pombi kana kuvhara nguva kwakaoma.
  Zano: Kana uchida kuwedzera mapaipi mabhiriji (eexample, nekuda kwekunonoka kwenzira kukonzeresa kukanganisa kwenguva), wobva wafunga nezve chinhambwe chenzira kubva kutsime kuenda kunzvimbo yekufunga muchip uye kusunungura imwe nzvimbo yakachengeterwa dunhu re kernel.
• Tevedza aya akajairwa nhungamiro kana uchichengetera LogicLock matunhu eiyo kernel:
  -Edza kuisa makoramu ese eDSP mu kernel_system kunze kwekunge zvichidikanwa neBSP.
  -Edza kuchengetedza zvimwe zviwanikwa zve kernel_system.
  - Edza kuchengetedza huwandu hwemanoti munharaunda yekernel kusvika padiki.
  Mufananidzo unotevera unoratidza notch yakawedzerwa kuisa pombi bhiriji pakati pePCIe neDDR bank.

Mufananidzo 1. OpenCL BSP Floorplan yeIntel Arria® 10 GX mu 17.0 Release

Nhungamiro dzeMaxim Operating Frequency
Hukuru hwekushandisa frequency (fmax) inowanikwa nemakernel zvakanyanya zvinoenderana nekumhanya kweFPGA sezvo mazhinji eIPs achifanirwa kunge atogadziridzwa. Nekudaro, panogona kunge paine fmax inorasikirwa zvichienderana neBSP floorplan. For example, kazhinji nhamba yekucheka-kubuda munharaunda yekernel yeBSP inobata kernel fmax.
Sezvinoratidzwa pamufananidzo unotevera, kuwana mhodzi yepamusoro inobereka avhareji yefmax yakanakisa:

1. Ita tsvairidzo yembeu pahwaro kuunganidzwa pachinzvimbo chekusarudza mhodzi yekutanga inoenderana nenguva.
2. Ita kubatanidza kunze (nekushandisa mashoma kernels kubva kune example designs) pambeu dzese dzinopfuura.
3. Kokorodza avhareji fmax yembeu dzese dzepasi.
4. Sarudza mhodzi yehwaro iyo inopa huwandu hwepamusoro hwepakati fmax.
   Mhodzi yehwaro ine avhareji yefmax yakanakisa mumiriri akanaka wekuburitswa neBSP. Kana iwe ukafunga kutevedzera nzira yakasiyana pane yakakurudzirwa matanho, unogona kuona 5-10% mutsauko mune fmax yeiyo kernel yekupinza yekuunganidza maitiro.

Mufananidzo 2. Kuziva Mbeu Yakanakisisa Yebhesi

• Kuti unzwisise kuti kernel inogona kumhanya sei pasina zvirambidzo zvefloorplan:
  1. Ita musanganiswa wakatsetseka we kernel uye tarisa fmax.
  2. Ita kuunganidza kwekunze pane imwe kernel uye tarisa fmax.
  3. Enzanisa fmax mhinduro.
  Nekuda kwezvirambidzo zvefloorplan, import compile fmax inogara yakaderera pane flat compile fmax. Kuti udzivise ruzha rwembeu, unganidza kernel nemhodzi dzakawanda uye funga avhareji fmax uchienzanisa fmax mhinduro.
• Usambofa wakafananidza kernel fmax kubva pakuumbwa kwechigadziko nefurati kana yekupinza muunganidzwa. Kernel wachi inotariswa yakadzoreredzwa panguva yekugadzira base uye nekudaro, haufe wakawana mhedzisiro yakanaka.
• Tarisa iyo kernel wachi yakakosha nzira mune base kana kupinza kuunganidzwa. Kana nzira yakakosha iri kuyambuka kubva kukernel ichienda kunzvimbo yakamira mufloorplan, shandura floorplan kana kumhanyisa dzimwe mhodzi dzehwaro kuti udzivise nzira yakaoma iyi.

Nhungamiro Yekuongorora BSP Resource Utilization Efficiency

Iyo yakakwirira yezviwanikwa zvekushandisa muzanatage, zvirinani kushandiswa kwenzvimbo munzvimbo yakamira yeBSP yako. Kuwanda kwekushandisa kwezviwanikwatage zvakare zvinoreva kuti zvimwe zviwanikwa zviripo kudunhu re kernel.
Tevedza matanho ari pasi apa kuti uverenge chikamu chekushandiswa kwezviwanikwatage yeBSP yako:

1. Wana makoshero ezvese zviwanikwa muFPGA kubva kumusoro.fit.rpt kana base.fit.rpt inowanikwa pasi pechikamu chePatition Statistics cheFitter report.
2. Bvisa kukosha kwe "freeze_wrapper_inst|kernel_system_inst" (kernel region).

Zano:
Tarisa zvakanyanya pane zvakakosha zveadaptive logic module (ALM) pane kukosha kwezvimwe zviwanikwa. Ita shuwa kuti zviwanikwa zvekushandisa percenttage yeALM iri padyo neOpenCL referensi BSP. Chiverengero chakakwirira kwazvotage yeALM inogona kutungamira mukusangana, izvo zvinogona kuwedzera nguva yekubatanidza uye kuunza kuungana kwenzira mumakernels akaoma. Nekudaro, iwe unogona kugara uchiwedzera kana kuderedza iyo static dunhu nzvimbo, uye tarisa iyo yekuunganidza nguva uye fmax.
Tafura inotevera inoratidza OpenCL BSP sosi yekushandisa yeArria ® 10 GX zvishandiso mukuburitswa kwe17.0.

Tafura 1.
OpenCL BSP Resource Utilization yeIntelArria 10 GX zvishandiso mune iyo 17.0 Kuburitswa.

	Total Available	Yakachengeterwa Kernel	Inowanikwa kuBSP	Inoshandiswa neBSP	0/0
ALM	427200	393800	33400	23818.	71%
Registers	1708800	1575200	133600	38913	29%
M2OK	2713	2534	179	134	75%
DSP	1518	1518	0	0	N/A

Tarisa uone kuti floorplanning inoitwa nenzira yekuti iyo static dunhu haizove neDSP zvidhinha.

Document Revision History

Tafura 2.
Gwaro Revision Nhoroondo yeIntel FPGA SDK yeOpenCL Board Tsigiro Package Floorplan Optimization Guide.

Date	Version	Kuchinja
Nyamavhuvhu-17		Kusunungurwa kwekutanga.

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AN-824
Shanduro: 2017.08.08
AN 824: Intel® FPGA SDK yeOpenCL™ Board
Tsigira Package Floorplan Optimization Guide

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References

• User Manual