AN 824 FPGA SDK no ka Papa OpenCL
Kākoʻo Pūʻulu papahele papahele
Ke alakaʻi hoʻohana

 Intel® FPGA SDK no ʻO OpenCL ™ Board Support Package Floorplan Optimization Guide
Hāʻawi ka Intel/® FPGA SDK no OpenCL™ Board Support Package (BSP) Floorplan Optimization Guide i nā alakaʻi hoʻolālā papahele no OpenCL) BSP. Hāʻawi pū ia i ke alakaʻi pehea e hiki ai iā ʻoe ke loaʻa i ka hua kumu me ka awelika ʻoi loa o ka hana ʻoi loa a loiloi i ka pono o ka hoʻohana ʻana i nā kumuwaiwai BSP.
Ke manaʻo nei kēia palapala ua kamaʻāina ʻoe i nā manaʻo OpenCL(2) e like me ka wehewehe ʻana ma ka OpenCL Specification version 1.0 e ka Khronos Group.

ʻO OpenCL BSP Hōʻuluʻulu Kahe
Kākoʻo ʻo OpenCL BSP i kēia mau ʻano o nā kahe hoʻohui:

• Hōʻuluʻulu palahalaha [–bsp-flow flat]: Hana i ka hōʻuluʻulu paʻa o ka hoʻolālā holoʻokoʻa (BSP me ka ʻenehana i hana ʻia).
• Hoʻopili kumu [–bsp-flow base]: Hana i kahi hōʻuluʻulu kumu ma o ka hoʻohana ʻana i nā palena LogicLock mai base.qsf file. Hoʻomaha ʻia ka pahu pahu pahu pahu i ʻoi aku ke kūʻokoʻa o ka hāmeʻa BSP e hālāwai me ka manawa. Hoʻokumu ʻia kahi waihona waihona base.qar e mālama i ka lako BSP, ʻo ia ka ʻāina paʻa.
• Hoʻopili hoʻohui [ ]: Hoʻihoʻi i ka ʻāina paʻa paʻa i ka manawa mai ka waihona base.qar a hōʻuluʻulu wale i ka ʻenehana i hana ʻia. Hoʻonui pū ia i ka pahu uʻi kernel no ka loaʻa ʻana o ka kernel kiʻekiʻe loa o ka hana pinepine (fmax).

ʻO ka wehe ʻana i ka papahele papahele BSP OpenCL
Hoʻokaʻawale ʻia ka papahele papahele OpenCL BSP i ʻelua mau ʻāpana:

• Māhele Kūʻokoʻa: Hōʻike i ka ʻāina i loaʻa nā lako pili BSP e paʻa mau. Hoʻopaʻa ʻia ka manawa no kēia māhele i ka wā o ka hōʻuluʻulu kumu. Ma keʻano laulā, ʻo ka pahuhopu ke hōʻemi i nā kumuwaiwai chip i hoʻohana ʻia e kēia ʻāina e pani i ka manawa.
• Māhele Kernel: Hōʻike i ka māhele hoʻonohonoho hou ʻana (PR) i mālama ʻia no freeze_wrapper_inst|kernel_system_inst module, aia i loko o ka kernel. Ma ka laulā, ʻo ka pahuhopu ka mālama ʻana i nā kumuwaiwai chip i ka palena kiʻekiʻe loa no kēia wahi.

1. Hoʻokumu ʻia ka Intel FPGA SDK no OpenCL ma kahi Khronos Specification i paʻi ʻia, a ua hala i ka Khronos Conformance Testing Process. Hiki ke loaʻa ke kūlana conformance o kēia manawa ma www.khronos.org/conformance.
2. ʻO OpenCL a me ka OpenCL logo nā hōʻailona kūʻai o Apple Inc. a hoʻohana ʻia e ka Khronos Group™.

Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā mālama ʻia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka ʻike. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā ​​​​lawelawe.
* Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.

Nā alakaʻi no ka OpenCL BSP Floorplanning

• E hoʻomaka me ka hōʻuluʻulu palahalaha e hoʻomaopopo ai i kahi e waiho maoli ʻia ai nā mea nui a pau o ka BSP (ʻoi aku ka nui o nā poloka IP me nā pilina I/O e like me PCIe a i ʻole DDR). I ka hoʻolālā ʻana i ka BSP, pono paha ʻoe e noʻonoʻo e hoʻokumu i nā paiputagaia ma waena o nā IP e pani i ka manawa. Pono ʻoe e holo mua i kahi kāhili hua hoʻohui palahalaha e ʻike ai i nā ala hele ʻole, a laila hoʻāʻo e hoʻoponopono.
  Manaʻo kōkua: — ʻO ka nui o ka pani ʻana o ka manawa maikaʻi ma luna o ka hoʻopili ʻana i nā hua hōʻuluʻulu palahalaha e ʻoi aku ka nui o ka manawa e pani ai i ka manawa hōʻuluʻulu kumu.
  — Inā ʻike ʻoe i nā hāʻule like ʻole ma mm_interconnect* (hui i hoʻohui ʻia e Qsys), a laila wehe i ka Pūnaewele me Qsys Interconnect. viewer a nānā i ka paʻakikī o ka launa ʻole. Hiki iā ʻoe ke hoʻohui i nā flipflops pipelining i ka viewe hoʻomaikaʻi i ka manawa. Inā ʻaʻole hiki iā ʻoe ke hoʻoponopono i ka pilikia, pono paha ʻoe e wāwahi i ke ala koʻikoʻi mm_interconnect * ma ka hoʻohui ʻana i nā alahaka pipeline Avalon.
• I ka wā o ka hōʻuluʻulu ʻana, e hoʻomaka me LogicLock ma ka ʻāina kernel i loaʻa freeze_wrapper_inst|kernel_system_inst. Me ka ʻole o nā kaohi ʻē aʻe, hiki iā Intel Quartus Prime ke waiho manuahi i ka lako BSP ma ke koena o ka ʻāpana static o ka chip. E hoʻohana i ka papa hoʻonohonoho paʻa a me ka chip planner e ʻike i ka nui a me kahi o ka lako BSP, e like me PCIe a me DDR. A laila, mālama i ka ʻāina kernel ma o ka hoʻohana ʻana iā LogicLock i ka wā e pale aku ai i nā wahi hui nui o ka lako BSP.
  Manaʻo kōkua: Inā like ka ʻohana chip i hoʻohana ʻia me ka paepae kuhikuhi a inā like nā ʻāpana BSP, ʻoi aku ka wikiwiki o ka hoʻomaka ʻana me nā ʻāpana LogicLock no freeze_wrapper_inst|kernel_system_inst i hoʻouna ʻia me ka OpenCL reference BSP a hana i nā hemahema.
• Hiki iā ʻoe ke hoʻohui i kēia mau mea hou i kāu BSP:
  — Nā panakō hoʻomanaʻo: Inā hoʻohui ʻoe i nā panakō hoʻomanaʻo hou aʻe, pono ʻoe e ʻike i ka wahi panakō I/O no ka mea pono ʻoe e hoʻohui i nā alahaka pipeline e hālāwai ai i ka manawa.
  — Nā kahawai I/O: Hiki iā ʻoe ke hoʻohui i nā kahawai I/O e like me ke wikiō, Ethernet, a i ʻole ke kikowaena serial. Inā hoʻohui ʻoe i nā kaha I/O, pono ʻoe e ʻike i ka wahi panakō I/O no ka mea pono ʻoe e noi i nā ʻāpana LogicLock hou no ka pipelining inā paʻakikī ka manawa pani.
  Manaʻo kōkua: Inā pono ʻoe e hoʻohui i nā alahaka pipeline (no ka exampe, ma muli o ka lohi nui o ka hoʻokele ʻana e hoʻopau ai i ka manawa), a laila e noʻonoʻo i ka mamao o ke alahele mai ke kumu a hiki i ka loina huakaʻi i loko o ka chip a hoʻokuʻu i kahi wahi i mālama ʻia no ka ʻāina kernel.
• E hahai i kēia mau alakaʻi maʻamau i ka wā e mālama ai i nā ʻāpana LogicLock no ka kernel:
  — E ho'āʻo e kau i nā kolamu DSP a pau i loko o ka kernel_system ke ʻole e koi ʻia e ka BSP.
  - E hoʻāʻo e mālama i nā kumuwaiwai hou aʻe no ka kernel_system.
  - E hoʻāʻo e mālama i ka helu o nā notches ma ka ʻāina kernel i ka liʻiliʻi.
  Hōʻike kēia kiʻi i kahi notch i hoʻohui ʻia e kau i kahi alahaka pipeline ma waena o PCIe a me DDR bank.

Kiʻi 1. OpenCL BSP papahele no Intel Arria® 10 GX ma ka 17.0 Hoʻokuʻu

Nā alakaʻi no ka ʻoi loa o ka hana ʻana
ʻO ke alapine hana kiʻekiʻe loa (fmax) i loaʻa e nā kernels e hilinaʻi nui ʻia i ka wikiwiki FPGA no ka mea ʻo ka hapa nui o nā IP e pono e hoʻomaikaʻi ʻia. Eia nō naʻe, aia paha kekahi mau fmax ma muli o ka papahele papahele BSP. No exampʻO ka maʻamau, ʻo ka helu o nā ʻokiʻoki ma ka ʻāpana kernel o BSP e pili ana i ka kernel fmax.
E like me ka mea i hōʻike ʻia ma ke kiʻi aʻe, e loaʻa i ka hua kumu maikaʻi loa e hāʻawi i ka awelika fmax maikaʻi loa:

1. E hana i kahi kāhili hua ma ka waihona kumu ma mua o ke koho ʻana i ka hua kumu mua i kūpono i ka manawa.
2. Hana i ka hoʻopili hoʻokomo ʻana (ma ka hoʻohana ʻana i nā kernels mai ka example designs) ma na anoano kumu a pau.
3. E helu i ka fmax awelika no na anoano kumu a pau.
4. E koho i ka hua kumu i hua mai i ka awelika fmax kiʻekiʻe loa.
   ʻO ka hua kumu me ka awelika fmax maikaʻi loa he moho maikaʻi no ka hoʻokuʻu ʻana me BSP. Inā hoʻoholo ʻoe e hahai i kahi ala ʻokoʻa ma mua o nā ʻanuʻu i manaʻo ʻia, hiki iā ʻoe ke nānā i ka 5-10% hoʻololi i ka fmax o ke kaʻina hana hoʻohui kernel import.

Kiʻi 2. ʻIke ʻana i ka hua kumu maikaʻi loa

• No ka hoʻomaopopo ʻana i ka wikiwiki o ka holo ʻana o ka kernel me ka ʻole o ka palena o ka papahele:
  1. Hana i ka houluulu palahalaha o ka kernel a nana i ka fmax.
  2. Hana i ka houluulu hookomo ana ma ka kernel hookahi a nana i ka fmax.
  3. Hoʻohālikelike i nā hopena fmax.
  Ma muli o ke kaohi ʻana o ka papahele papahele, ʻoi aku ka haʻahaʻa o ka hoʻokomo ʻana i ka fmax ma mua o ka fmax compile flat. No ka pale ʻana i ka walaʻau ʻanoʻano, e hōʻuluʻulu i ka kernel me nā hua kumu hou aʻe a noʻonoʻo i ka fmax awelika i ka hoʻohālikelike ʻana i nā hopena fmax.
• Mai hoʻohālikelike i ka kernel fmax mai kahi hōʻuluʻulu kumu me kahi hōʻuluʻulu palahalaha a i ʻole ka hoʻokomo ʻana mai. Hoʻomaha ʻia nā pahuhopu uaki Kernel i ka wā o ka hōʻuluʻulu kumu a no laila, ʻaʻole loa ʻoe e loaʻa nā hopena maikaʻi.
• E nānā i ke ala koʻikoʻi o ka uaki kernel ma ka waihona kumu a i ʻole ka hoʻokomo ʻana mai. Inā e hele ana ke ala koʻikoʻi mai ka kernel a hiki i ka ʻāina paʻa i ka papahele, e hoʻololi i ka papahele a i ʻole e holo i nā hua kumu hou e pale aku i kēia ala koʻikoʻi.

Nā alakaʻi no ka loiloi ʻana i ka maikaʻi o ka hoʻohana ʻana i nā kumuwaiwai BSP

ʻO ke kiʻekiʻe o ka pākēneka hoʻohana waiwaitage, ʻoi aku ka maikaʻi o ka hoʻohana ʻana i ka ʻāpana ma ka wahi paʻa o kāu BSP. He pākēneka hoʻohana waiwai kiʻekiʻetage hōʻike ana hoʻi i loaʻa nā kumuwaiwai hou aʻe no ka ʻāina kernel.
E hahai i nā ʻanuʻu ma lalo nei e helu i ka pākēneka hoʻohana waiwaitage o kāu BSP:

1. E kiʻi i nā waiwai no nā kumuwaiwai āpau i ka FPGA mai ka top.fit.rpt a i ʻole base.fit.rpt i loaʻa ma lalo o ka ʻāpana ʻIke Paʻi o ka hōʻike Fitter.
2. Wehe i ka waiwai no “freeze_wrapper_inst|kernel_system_inst” (ʻāpana kernel).

Manaʻo kōkua:
E noʻonoʻo nui i nā waiwai o ka modula loiloi adaptive (ALM) ma mua o nā waiwai o nā kumuwaiwai ʻē aʻe. E hōʻoia i ka pākēneka hoʻohana waiwaitage no ka ALM kokoke i ka BSP kuhikuhi OpenCL. He pākēneka kiʻekiʻe loatage no ka ALM hiki ke alakaʻi i ka hoʻopaʻa ʻana, hiki ke hoʻonui i ka manawa hōʻuluʻulu a hoʻokomo i nā ʻōnaʻi ala ala i nā kernel paʻakikī. Eia naʻe, hiki iā ʻoe ke hoʻonui a hoʻemi paha i ka ʻāpana static, a nānā i ka manawa hoʻohui a me ka fmax.
Hōʻike ka papa ma lalo i ka hoʻohana waiwai OpenCL BSP o Arria ® 10 GX i ka hoʻokuʻu 17.0.

Papa 1.
OpenCL BSP Resource Hoʻohana i nā polokalamu IntelArria 10 GX i ka 17.0 Release

	Huina Loaa	Mālama ʻia no Kernel	Loaʻa iā BSP	Hoʻohana ʻia e BSP	0/0
Alm	427200	393800	33400	23818.	71%
Kakau inoa	1708800	1575200	133600	38913	29%
M2OK	2713	2534	179	134	75%
DSP	1518	1518	0	0	N/A

E nānā i ka hoʻokō ʻia ʻana o ka hoʻolālā papahele i ʻole e loaʻa nā poloka DSP i ka ʻāina paʻa.

Moolelo Hooponopono Palapala

Papa 2.
Palapala Hoʻoponopono Moʻolelo o ka Intel FPGA SDK no OpenCL Board Support Package Floorplan Optimization Guide

Lā	Manao	Nā hoʻololi
ʻAukake-17		Hoʻokuʻu mua.

Online Version
Hoʻouna Manaʻo
ID: 683312
AN-824
Manaʻo: 2017.08.08
AN 824: Intel® FPGA SDK no ka Papa OpenCL™
Kākoʻo Papa Papa Hoʻolālā Papahana Papa kuhikuhi

Palapala / Punawai

intel AN 824 FPGA SDK no ka OpenCL Board Support Package Floorplan [pdf] Ke alakaʻi hoʻohana AN 824 FPGA SDK no ka Papa OpenCL Board Support Package Floorplan, AN 824, FPGA SDK no OpenCL Board Support Package Plan Plan, OpenCL Board Support Package Floorplan, Papa Support Package Floorplan, Support Package Floorplan, Package Floorplan, Floorplan

Nā kuhikuhi

• Palapala Hoʻohana