AN 824 FPGA SDK ya OpenCL Board
Phukusi Lothandizira Floorplan
Wogwiritsa Ntchito

 Intel® FPGA SDK ya OpenCL ™ Board Support Package Floorplan Optimization Guide
Intel/® FPGA SDK ya OpenCL™ Board Support Package (BSP) Floorplan Optimization Guide imapereka malangizo apansi a OpenCL) BSP. Imaperekanso chitsogozo chamomwe mungapezere mbewu zoyambira zokhala ndi ma frequency apamwamba kwambiri ogwiritsira ntchito ndikuwunika kugwiritsa ntchito bwino kwa BSP.
Chikalatachi chikuganiza kuti mumadziwa mfundo za OpenCL(2) monga zafotokozedwera mu OpenCL Specification version 1.0 ndi Khronos Group.

OpenCL BSP Compilation Flow
OpenCL BSP imathandizira mitundu iyi yophatikizira:

• Flat compile [-bsp-flow flat]: Imapanga kuphatikiza kosalala kwa kapangidwe kake (BSP pamodzi ndi zida zopangidwa ndi kernel).
• Base compile [-bsp-flow base]: Amapanga zoyambira pogwiritsa ntchito zoletsa za LogicLock zochokera ku base.qsf file. Cholinga cha wotchi ya kernel chimamasulidwa kuti zida za BSP zikhale ndi ufulu wambiri wokwaniritsa nthawi. Dongosolo la database la base.qar limapangidwa kuti lisunge zida za BSP, zomwe ndi gawo lokhazikika.
• Kulowetsa kunja [ ]: Imabwezeretsanso nthawi yotsekedwa yotsekedwa kuchokera ku database ya base.qar ndikungopanga zida zopangidwa ndi kernel zokha. Imawonjezeranso chandamale cha wotchi ya kernel kuti mupeze ma frequency apamwamba kwambiri a kernel (fmax).

OpenCL BSP Floorplan Partition
OpenCL BSP floorplan imagawidwa m'magawo awiri otsatirawa:

• Dera lokhazikika: likuyimira dera lomwe lili ndi zida zokhudzana ndi BSP zomwe zimakhazikika. Nthawi imatsekedwa m'derali panthawi yopanga maziko. Mwambiri, cholinga chake ndikuchepetsa zida za chip zomwe dera lino limagwiritsa ntchito kuti atseke nthawi.
• Chigawo cha Kernel: Chikuyimira gawo la kukonzanso pang'ono (PR) lomwe lasungidwa ku freeze_wrapper_inst|kernel_system_inst module, yomwe ili ndi kernel. Nthawi zambiri, cholinga ndikusunga zida za chip mpaka pamlingo waukulu m'derali.

1. Intel FPGA SDK ya OpenCL idakhazikitsidwa ndi Khronos Specification, ndipo yadutsa Khronos Conformance Testing Process. Mkhalidwe wamakono ukupezeka pa www.khronos.org/conformance.
2. OpenCL ndi logo ya OpenCL ndi zizindikiro za Apple Inc. ndipo zimagwiritsidwa ntchito ndi chilolezo cha Khronos Group™.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
*Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Malangizo a OpenCL BSP Floorplanning

• Yambani ndikuphatikiza mopanda phokoso kuti mumvetsetse komwe zigawo zonse zazikulu za BSP zimayikidwa mwachilengedwe (makamaka IP imatchinga ndi ma I/O monga PCIe kapena DDR). Mukamapanga BSP, mungafunike kuganizira zokhazikitsa mapaipitagali pakati pa ma IPs kuti atseke nthawi. Choyamba muyenera kusesa mbewu zophatikizika kuti muzindikire njira zomwe zasokonekera, ndikuyesa kukonza.
  Langizo: - Kutseka kwanthawi yabwino pakusesa kwa mbewu zophatikizika kumakhala ndi mwayi wotseka nthawi yophatikizira.
  - Ngati muwona zolephera zosasinthika mm_interconnect* (gawo lowonjezeredwa ndi Qsys), ndiye tsegulani System ndi Qsys Interconnect viewer ndikuwona zovuta za kulumikizana komwe kukulephera. Mukhoza kuwonjezera ma pipelining flipflops mu viewkuti muwonjezere nthawi. Ngati simungathe kuthana ndi vutoli, mungafunike kuwononga mm_interconnect* njira yovuta powonjezera milatho ya mapaipi a Avalon.
• Pakuphatikiza zoyambira, yambani ndi LogicLock pa kernel dera lomwe lili ndi freeze_wrapper_inst|kernel_system_inst. Popanda zoletsa zina, Intel Quartus Prime imatha kuyika zida za BSP momasuka m'chigawo chotsalira cha chip. Gwiritsani ntchito gulu lathyathyathya ndi chip planner kuti muzindikire kukula ndi komwe kuli zida za BSP, monga PCIe ndi DDR. Kenako, sungani dera la kernel pogwiritsa ntchito LogicLock ndikupewa madera akuluakulu a zida za BSP.
  Langizo: Ngati banja la chip lomwe likugwiritsidwa ntchito ndi lofanana ndi nsanja yolozera ndipo ngati zigawo za BSP zili zofanana, zitha kukhala zachangu kuyamba ndi zigawo za LogicLock za freeze_wrapper_inst|kernel_system_inst zomwe zimatumizidwa ndi OpenCL reference BSP ndikugwira ntchito molephera.
• Mutha kuwonjezera zina zowonjezera ku BSP yanu:
  - Mabanki okumbukira: Mukawonjezera mabanki ambiri okumbukira, muyenera kudziwa komwe banki ya I/O ilili chifukwa mungafunike kuwonjezera milatho yamapaipi kuti mukwaniritse nthawi.
  - Makanema a I/O: Mutha kuwonjezera mayendedwe a I/O monga kanema, Ethernet, kapena mawonekedwe a serial. Mukawonjezera ma tchanelo a I/O, muyenera kuzindikira komwe banki ya I/O ilili chifukwa mungafunike kuyika zigawo zatsopano za LogicLock popanga mapaipi ngati nthawi yotseka ndiyovuta.
  Langizo: Ngati mukufuna kuwonjezera milatho yamapaipi (mwachitsanzoample, chifukwa cha kuchedwa kwakukulu komwe kumayambitsa kulephera kwa nthawi), ndiye ganizirani mtunda wodutsa kuchokera kugwero kupita kumalingaliro ofikira mu chip ndikumasula malo ena osungidwira dera la kernel.
• Tsatirani malangizo awa posungira zigawo za LogicLock za kernel:
  - Yesani kuyika zigawo zonse za DSP mu kernel_system pokhapokha ngati BSP ikufuna.
  - Yesani kusungitsa zinthu zambiri za kernel_system.
  - Yesetsani kuchepetsa kuchuluka kwa notch m'dera la kernel.
  Chithunzi chotsatira chikuwonetsa notch yomwe idawonjezedwa kuti ayike mlatho wamapaipi pakati pa PCIe ndi DDR bank.

Chithunzi 1. OpenCL BSP Floorplan ya Intel Arria® 10 GX mu Kutulutsidwa kwa 17.0

Maupangiri anthawi yayitali yogwirira ntchito
Kuchuluka kwa ma frequency ogwiritsira ntchito (fmax) komwe kumapezeka ndi maso kumadalira kuthamanga kwa FPGA popeza ma IP ambiri amayenera kukonzedwa kale. Komabe, pakhoza kukhala kutayika kwa fmax kutengera dongosolo la BSP. Za example, nthawi zambiri kuchuluka kwa zodulidwa mu kernel dera la BSP kumakhudza kernel fmax.
Monga tawonetsera pachithunzi chotsatirachi, kuti mupeze mbewu yabwino kwambiri yomwe imabala fmax yabwino kwambiri:

1. Seserani mbeu pazophatikiza zoyambira m'malo mosankha mbeu yoyambira yomwe ikugwirizana ndi nthawi yake.
2. Pangani kuphatikiza zolowetsa (pogwiritsa ntchito masoko ochepa kuchokera ku example designs) pambewu zonse zodutsa.
3. Yerekezerani kuchuluka kwa fmax kwa mbewu zonse zoyambira.
4. Sankhani mbewu yoyambira yomwe imabala fmax yapamwamba kwambiri.
   Mbewu yoyambira yokhala ndi fmax yabwino kwambiri ndi munthu wabwino kuti amasulidwe ndi BSP. Mukasankha kutsatira njira yosiyana ndi njira zomwe mwalangizidwa, mutha kuwona kusiyanasiyana kwa 5-10% mu fmax ya njira yopangira kernel importation.

Chithunzi 2. Kuzindikiritsa Mbewu Yabwino Kwambiri

• Kuti mumvetsetse momwe kernel imatha kuthamanga popanda zoletsa zapansi:
  1. Pangani gulu lathyathyathya la kernel ndikuwona fmax.
  2. Pangani kuphatikiza zolowetsa pa kernel yomweyo ndikuwona fmax.
  3. Fananizani zotsatira za fmax.
  Chifukwa cha zoletsa za floorplan, import compile fmax nthawi zonse imakhala yotsika kuposa flat compile fmax. Kuti mupewe phokoso la mbeu, phatikizani kernel ndi njere zambiri zoyambira ndikuwona kuchuluka kwa fmax ndikuyerekeza zotsatira za fmax.
• Osafanizitsa kernel fmax kuchokera pakuphatikiza koyambira ndi gulu lathyathyathya kapena zolowetsa kunja. Zolinga za wotchi ya Kernel zimatsitsimutsidwa pakuphatikiza koyambira, chifukwa chake, simupeza zotsatira zabwino.
• Yang'anani njira yofunikira ya wotchi ya kernel mumayendedwe oyambira kapena olowetsa. Ngati njira yovuta ikudutsa kuchokera ku kernel kupita kudera lomwe lili pansi, sinthani pulani yapansi kapena tsitsani njere zochepa kuti mupewe njira yovutayi.

Maupangiri Owunika Kuchita Bwino kwa BSP Resource Utilization

Kuchulukirachulukira kwazomwe zimagwiritsidwa ntchitotage, kugwiritsa ntchito bwino dera lanu pamalo osasunthika a BSP yanu. Chiŵerengero chachikulu chogwiritsira ntchito zipangizotage akutanthauzanso kuti zinthu zambiri zilipo kudera la kernel.
Tsatirani njira zomwe zili pansipa kuti muwerenge kuchuluka kwa kagwiritsidwe ntchito ka zinthutagndi BSP yanu:

1. Pezani makonda azinthu zonse mu FPGA kuchokera pamwamba.fit.rpt kapena base.fit.rpt zomwe zikupezeka pansi pa gawo la Partition Statistics la lipoti la Fitter.
2. Chotsani mtengo wa “freeze_wrapper_inst|kernel_system_inst” (chigawo cha kernel).

Langizo:
Yang'anani kwambiri pamakhalidwe a adaptive logic module (ALM) kuposa pamakhalidwe azinthu zina. Onetsetsani kuti kuchuluka kwa zogwiritsidwa ntchitotage ya ALM ili pafupi ndi OpenCL reference BSP. Chiwerengero chokwera kwambiritage kwa ALM kungayambitse kusokonekera, komwe kungapangitse nthawi yophatikiza ndikuyambitsa kusokonekera kwa ma kernel ovuta. Komabe, mutha kuwonjezera kapena kuchepetsa dera lokhazikika, ndikuwona nthawi yophatikiza ndi fmax.
Gome lotsatirali likuwonetsa kugwiritsa ntchito zida za OpenCL BSP za zida za Arria ® 10 GX pakutulutsidwa kwa 17.0.

Table 1.
OpenCL BSP Resource Utilization of IntelArria 10 GX zida mu 17.0 Release

	Zonse Zilipo	Zasungidwa ku Kernel	Ikupezeka pa BSP	Zogwiritsidwa ntchito ndi BSP	0/0
ALM	427200	393800	33400	23818.	71%
Olembetsa	1708800	1575200	133600	38913	29%
M2 chabwino	2713	2534	179	134	75%
DSP	1518	1518	0	0	N / A

Onani kuti kupanga pansi kumachitidwa m'njira yoti dera lokhazikika lisakhale ndi midadada ya DSP.

Document Revision History

Table 2.
Mbiri Yokonzanso Zolemba za Intel FPGA SDK ya OpenCL Board Support Package Floorplan Optimization Guide

Tsiku	Baibulo	Zosintha
Ogasiti - 17		Kutulutsidwa koyamba.

Baibulo Lomasulira
Tumizani Ndemanga
ID: 683312
AN-824
Mtundu: 2017.08.08
AN 824: Intel® FPGA SDK ya OpenCL™ Board
Thandizo Package Floorplan Optimization Guide

Zolemba / Zothandizira

intel AN 824 FPGA SDK ya OpenCL Board Support Package Floorplan [pdf] Buku Logwiritsa Ntchito AN 824 FPGA SDK ya OpenCL Board Support Package Floorplan, AN 824, FPGA SDK ya OpenCL Board Support Package Floorplan, OpenCL Board Support Package Floorplan, Board Support Package Floorplan, Support Phukusi Floorplan, Phukusi Floorplan, Phukusi Floorplan,

Maumboni

• Buku Logwiritsa Ntchito