Microsemi DG0669 SmartFusion2 Code Shadowing lati SPI Flash to LPDDR Memory
ọja Alaye
SmartFusion2 SoC FPGA jẹ iṣẹ-giga, ojutu FPGA agbara kekere ti o ṣepọ ero isise ARM Cortex-M3, afọwọṣe ti eto ati awọn orisun oni-nọmba, ati awọn atọkun ibaraẹnisọrọ iyara-giga lori chirún kan. Sọfitiwia SoC v11.7 Libero jẹ suite apẹrẹ pipe fun apẹrẹ pẹlu Microsemi FPGAs.
Lilo ọja
Lati lo SmartFusion2 SoC FPGA pẹlu ojiji koodu lati SPI Flash si iranti LPDDR, tẹle awọn igbesẹ isalẹ:
Àsọyé
Idi
demo yii wa fun SmartFusion®2 eto-on-chip (SoC) awọn ohun elo ẹnu-ọna eto eto (FPGA). O pese awọn ilana lori bi o ṣe le lo apẹrẹ itọkasi ti o baamu.
Olugbo ti a pinnu
Itọsọna demo yii jẹ ipinnu fun:
- FPGA apẹẹrẹ
- Awọn apẹẹrẹ ti a fi sii
- Awọn apẹẹrẹ eto-ipele
Awọn itọkasi
Wo atẹle naa web oju-iwe fun pipe ati atokọ imudojuiwọn ti awọn iwe ohun elo SmartFusion2: http://www.microsemi.com/products/fpga-soc/soc-fpga/sf2docs
Awọn iwe aṣẹ wọnyi ni a tọka si ninu itọsọna demo yii.
- UG0331: SmartFusion2 Microcontroller Subsystem User Itọsọna
- SmartFusion2 System Akole olumulo Itọsọna
SmartFusion2 SoC FPGA – Ojiji koodu lati Flash SPI si Iranti LPDDR
Ọrọ Iṣaaju
Eleyi demo oniru fihan SmartFusion2 SoC FPGA ẹrọ agbara fun koodu ojiji lati ni tẹlentẹle agbeegbe ni wiwo (SPI) filasi iranti ẹrọ to kekere agbara ė data oṣuwọn (LPDDR) amuṣiṣẹpọ ìmúdàgba ID wiwọle iranti (SDRAM) ati ṣiṣe awọn koodu lati LPDDR SDRAM. Nọmba 1 ṣe afihan aworan atọka ipele oke-ipele fun ojiji koodu lati ẹrọ filasi SPI si iranti LPDDR.
Aworan 1 Top-Level Block aworan atọka ti Ririnkiri
Ojiji koodu jẹ ọna gbigbe ti o lo lati ṣiṣe aworan kan lati ita, yiyara, ati awọn iranti iyipada (DRAM). O jẹ ilana ti didakọ koodu lati iranti ti kii ṣe iyipada si iranti iyipada fun ipaniyan. Ojiji koodu wa ni ti beere, nigbati awọn ti kii-iyipada iranti ni nkan ṣe pẹlu a isise ko ni atilẹyin ID wiwọle si koodu fun ṣiṣẹ-ni ibi, tabi nibẹ ni insufficient ti kii-iyipada ID wiwọle iranti. Ninu awọn ohun elo to ṣe pataki, iyara ipaniyan le ni ilọsiwaju nipasẹ ojiji koodu, nibiti a ti daakọ koodu si Ramu ti o ga julọ fun ipaniyan yiyara. Oṣuwọn data ẹyọkan (SDR)/DDR SDRAM awọn iranti ni a lo ninu awọn ohun elo ti o ni aworan ṣiṣe ohun elo nla ati nilo iṣẹ ṣiṣe ti o ga julọ. Ni deede, awọn aworan ṣiṣe ti o tobi ti wa ni ipamọ ni iranti ti kii ṣe iyipada, gẹgẹbi filasi NAND tabi filasi SPI, ati daakọ si iranti iyipada, gẹgẹbi SDR/DDR SDRAM iranti, ni agbara soke fun ipaniyan. Awọn ẹrọ SmartFusion2 ṣepọ aṣọ FPGA ti o da filasi iran kẹrin, ero isise ARM® Cortex®-M3, ati awọn atọkun ibaraẹnisọrọ iṣẹ ṣiṣe giga lori chirún kan. Awọn oludari iranti iyara giga ninu awọn ẹrọ SmartFusion2 ni a lo lati ni wiwo pẹlu awọn iranti DDR2/DDR3/LPDDR ita. Iranti LPDDR le ṣiṣẹ ni iyara ti o pọju ti 166 MHz. Kotesi-M3 ero isise le taara ṣiṣe awọn ilana lati ita DDR iranti nipasẹ awọn microcontroller subsystem (MSS) DDR (MDDR). Adarí Kaṣe FPGA ati afara MSS DDR n ṣakoso sisan data fun iṣẹ to dara julọ.
Design awọn ibeere
Rii daju pe o ni awọn ibeere hardware ati sọfitiwia wọnyi:
Hardware ati Software Awọn ibeere
Table 1 Design ibeere
Design awọn ibeere | Apejuwe |
Hardware Awọn ibeere | |
SmartFusion2 Apo Igbelewọn Aabo:
• 12 V ohun ti nmu badọgba • FlashPro4 USB A si Mini – B okun USB |
Rev D tabi nigbamii |
Gbalejo PC tabi Laptop | Windows XP SP2 Eto Sisẹ – 32-/64-bit Windows 7 System Operating System – 32-/64-bit |
Software ibeere | |
Eto Libero® lori Chip (SoC) | v11.7 |
FlashPro siseto Software | v11.7 |
SoftConsole | v3.4 SP1* |
Ogun PC Drivers | USB to UART awakọ |
Ilana fun ifilọlẹ demo GUI | Microsoft .NET Framework 4 Onibara fun ifilọlẹ demo GUI |
Akiyesi: * Fun itọsọna demo yii, SoftConsole v3.4 SP1 ti lo. Fun lilo SoftConsole v4.0, wo awọn TU0546: SoftConsole v4.0 ati Libero SoC v11.7 Tutorial. |
- SmartFusion2 Idagbasoke Apo
- Libero SoC v11.7 software
- USB Blaster tabi okun USB Blaster II
Ririnkiri Design
Apẹrẹ demo nlo ọpọlọpọ-stage ọna ilana bata tabi ọna ẹrọ bata ohun elo lati gbe aworan ohun elo lati filasi SPI si iranti LPDDR. Tẹle awọn igbesẹ isalẹ: Apẹrẹ files wa fun igbasilẹ lati ọna atẹle ni Microsemi webojula: http://soc.microsemi.com/download/rsc/?f=m2s_dg0669_liberov11p7_df
Apẹrẹ files pẹlu:
Apẹrẹ demo files pẹlu:
- Sample elo images
- Siseto files
- Libero
- GUI ṣiṣẹ
- Awọn iwe afọwọkọ Linker
- DDR iṣeto ni files
- Ka iwe.txt file
SmartFusion2 SoC FPGA - Ojiji koodu lati Flash SPI si LPDDR Memory Figure 2 ṣe afihan eto ipele-oke ti apẹrẹ files. Fun alaye siwaju sii, tọka si Readme.txt file.
olusin 2 Design Files Top-Level Be
Ririnkiri Design Apejuwe
Apẹrẹ demo yii n ṣe ilana ilana ojiji koodu lati bata aworan ohun elo lati iranti DDR. Apẹrẹ yii tun pese wiwo agbalejo lori SmartFusion2 SoC FPGA multi-mode fun gbogbo asynchronous/ olugba amuṣiṣẹpọ / Atagba (MMUART) lati gbe ohun elo ibi-afẹde ti o ṣee ṣe aworan sinu filasi SPI ti o sopọ si wiwo MSS SPI0.
Ojiji koodu ti wa ni imuse ni awọn ọna meji wọnyi:
- Olona-stage bata ilana ọna lilo Cortex-M3 isise
- Hardware bata engine ọna lilo awọn FPGA fabric.
Olona-Stage Boot Ilana Ọna
- Ṣẹda aworan ohun elo fun iranti DDR nipa lilo sọfitiwia Libero SoC.
- Ṣe agberu SPI Flash sinu filasi SPI nipa lilo sọfitiwia Libero SoC.
- Ṣiṣe koodu Shadowing Demo GUI lati ṣe eto FPGA ati gbe aworan ohun elo lati filasi SPI si iranti LPDDR.
Awọn ohun elo image ti wa ni ṣiṣe lati ita DDR ìrántí ninu awọn wọnyi meji bata stages:
- Cortex-M3 ero isise bata bata bata bata asọ lati inu iranti ti kii ṣe iyipada (eNVM), eyiti o ṣe gbigbe aworan koodu lati ẹrọ filasi SPI si iranti DDR.
- Cortex-M3 ero isise bata aworan ohun elo lati iranti DDR.
Apẹrẹ yii n ṣe eto bootloader kan lati fifuye aworan ti o le ṣe ohun elo ibi-afẹde lati ẹrọ filasi SPI si iranti DDR fun ipaniyan. Eto bootloader ti nṣiṣẹ lati eNVM fo si ohun elo ibi-afẹde ti o fipamọ sinu iranti DDR lẹhin ti a daakọ aworan ohun elo ibi-afẹde si iranti DDR.
olusin 3 Code Shadowing Multi-Stage Boot Ilana Ririnkiri Àkọsílẹ aworan atọka
MDR naa jẹ tunto fun LPDDR lati ṣiṣẹ ni 166 MHz. "Afikun: Awọn atunto LPDDR" loju iwe 22 fihan awọn eto iṣeto LPDDR. A tunto DDR ṣaaju ṣiṣe koodu ohun elo akọkọ.
Bootloader
bootloader ṣe awọn iṣẹ wọnyi:
- Didaakọ aworan ohun elo ibi-afẹde lati iranti filasi SPI si iranti DDR.
- Remapping DDR iranti ti o bere adirẹsi lati 0xA0000000 to 0x00000000 nipa tito leto DDR_CR eto Forukọsilẹ.
- Bibẹrẹ itọka akopọ ero isise Cortex-M3 gẹgẹbi ohun elo ibi-afẹde. Ipo akọkọ ti tabili fekito ohun elo ibi-afẹde ni iye itọka akopọ. Tabili fekito ti ohun elo ibi-afẹde wa ti o bẹrẹ lati adirẹsi 0x00000000.
- Ikojọpọ counter eto (PC) lati tun oluṣakoso ohun elo ibi-afẹde fun ṣiṣe aworan ohun elo ibi-afẹde lati iranti DDR. Olutọju atunto ohun elo ibi-afẹde wa ni tabili vector ni adirẹsi 0x00000004.
olusin 4 Design Sisan fun Multi-Stage Boot Ilana Ọna
Hardware Boot Engine Ọna
- Ṣe ina alakomeji ti o le ṣiṣẹ file lilo sọfitiwia Libo SoC.
- Kojọpọ alakomeji file sinu filasi SPI nipa lilo sọfitiwia Libero SoC.
- Ṣiṣe awọn Apẹrẹ Boot Engine Hardware lati ṣe eto FPGA ati gbe aworan ohun elo lati filasi SPI si iranti LPDDR.
Ni ọna yii, Cortex-M3 taara bata aworan ohun elo ibi-afẹde lati awọn iranti DDR ita. Ẹnjini bata hardware daakọ aworan ohun elo lati ẹrọ filasi SPI si iranti DDR, ṣaaju ki o to dasile atunṣe ero isise Cortex-M3. Lẹhin itusilẹ atunto, ero isise Cortex-M3 bata taara lati iranti DDR. Ọna yii nilo akoko bata-soke diẹ sii ju ọpọlọpọ-stage bata ilana bi o ti yago fun ọpọ bata stages ati idaako ohun elo image to DDR iranti ni kere akoko. Apẹrẹ demo yii ṣe imuse ọgbọn engine bata ni aṣọ FPGA lati daakọ aworan ti o le ṣe ohun elo ibi-afẹde lati filasi SPI si iranti DDR fun ipaniyan. Apẹrẹ yii tun ṣe imuse agberu filasi SPI, eyiti o le ṣe nipasẹ ero isise Cortex-M3 lati gbe aworan imuṣiṣẹ ohun elo ibi-afẹde sinu ẹrọ filasi SPI nipa lilo wiwo agbalejo ti a pese lori SmartFusion2 SoC FPGA MMUART_1. DIP yipada1 lori Apo Igbelewọn Aabo SmartFusion2 le ṣee lo lati yan boya lati ṣe eto ẹrọ filasi SPI tabi lati ṣiṣẹ koodu naa lati iranti DDR. Ti ohun elo ibi-afẹde ti o ṣiṣẹ wa ni ẹrọ filasi SPI, ojiji koodu lati ẹrọ filasi SPI si iranti DDR ti bẹrẹ lori agbara ẹrọ. Ẹrọ bata naa ṣe ipilẹṣẹ MDDR, daakọ Aworan lati ẹrọ filasi SPI si iranti DDR, o si ṣe atunkọ aaye iranti DDR si 0x00000000 nipa titọju ero isise Cortex-M3 ni ipilẹ. Lẹhin ti ẹrọ bata ṣe idasilẹ atunṣe Cortex-M3, Cortex-M3 ṣe ohun elo ibi-afẹde lati iranti DDR. olusin 5 fihan awọn alaye Àkọsílẹ aworan atọka ti awọn demo oniru. FIC_0 ni a tunto ni ipo Ẹrú lati wọle si MSS SPI_0 lati FPGA fabric AHB oga. Ni wiwo MDDR AXI (DDR_FIC) ti ṣiṣẹ lati wọle si iranti DDR lati ọdọ FPGA fabric AXI titunto si.
olusin 5 Code Shadowing Hardware Boot Engine Ririnkiri Àkọsílẹ aworan atọka
Bata Engine
Eyi ni apakan pataki ti demo ojiji koodu ti o daakọ aworan ohun elo lati ẹrọ filasi SPI si iranti DDR. Ẹrọ bata n ṣe awọn iṣẹ wọnyi:
- Bibẹrẹ MDR fun iwọle si LPDDR ni 166 MHz nipa titọju ero isise Cortex-M3 ni ipilẹ.
- Didaakọ aworan ohun elo ibi-afẹde lati ẹrọ iranti filasi SPI si iranti DDR nipa lilo oluwa AXI ninu aṣọ FPGA nipasẹ wiwo MDDR AXI.
- Remapping DDR iranti ti o bere adirẹsi lati 0xA0000000 to 0x00000000 nipa kikọ si DDR_CR eto Forukọsilẹ.
- Itusilẹ atunto si ero isise Cortex-M3 lati bata lati iranti DDR.
olusin 6 Design Sisan fun Hardware Boot Engine Ọna
Ṣiṣẹda Àkọlé elo Image fun DDR Memory
Aworan ti o le ṣe lati iranti DDR ni a nilo lati ṣiṣẹ demo. Lo iṣelọpọ-ṣiṣe-ni-ibi-externalDDR.ld apejuwe asopọ file ti o wa ninu apẹrẹ files lati kọ aworan ohun elo. Eleyi linker apejuwe file n ṣalaye adirẹsi ibẹrẹ iranti DDR bi 0x00000000 lati igba ti bootloader tabi ẹrọ bata ṣe atunṣe iranti DDR lati 0xA0000000 si 0x00000000. Iwe afọwọkọ ọna asopọ yii ṣẹda aworan ohun elo pẹlu awọn ilana, data, ati awọn apakan BSS ni iranti eyiti adirẹsi ibẹrẹ rẹ jẹ 0x00000000. Diode didan ina ti o rọrun (LED) ti n paju, aago ati aworan ohun elo iran idalọwọduro orisun iyipada file ti pese fun demo yii.
SPI Flash agberu
Agberu filasi SPI ti wa ni imuse lati gbe iranti filasi SPI lori-ọkọ pẹlu aworan ohun elo ibi-afẹde ti o ṣiṣẹ lati ọdọ PC agbalejo nipasẹ wiwo MMUART_1. Awọn ero isise Cortex-M3 ṣe ifipamọ kan fun data ti nbọ lori wiwo MMUART_1 ati pe o bẹrẹ agbeegbe DMA (PDMA) lati kọ data ifipamọ sinu filasi SPI nipasẹ MSS_SPI0.
Nṣiṣẹ Ririnkiri
Lati ṣiṣẹ apẹrẹ demo, tẹle awọn igbesẹ isalẹ: demo fihan bi o ṣe le gbe aworan ohun elo sinu filasi SPI ki o ṣiṣẹ aworan ohun elo yẹn lati awọn iranti DDR ita. Eleyi demo pese ohun Mofiample elo aworan sample_image_LPDDR.bin. Aworan yii ṣe afihan awọn ifiranṣẹ itẹwọgba ati ifiranṣẹ idalọwọduro aago lori console tẹlentẹle ati ki o pa LED1 si LED8 lori Apo Igbelewọn Aabo SmartFusion2. Lati wo awọn ifiranṣẹ GPIO da gbigbi lori console tẹlentẹle, tẹ SW2 tabi SW3 yipada.
Ṣiṣeto Apẹrẹ Ririnkiri
Awọn igbesẹ wọnyi ṣe apejuwe bi o ṣe le ṣeto demo fun igbimọ Apo Igbelewọn Aabo SmartFusion2: So PC ogun pọ si Asopọ J18 nipa lilo USB A si okun mini-B. USB si UART awakọ afara ti wa ni wiwa laifọwọyi. Daju boya wiwa naa ba wa ninu oluṣakoso ẹrọ bi o ṣe han ni Nọmba 7.
- Ti a ko ba rii awakọ USB laifọwọyi, fi awakọ USB sii.
- Fun ibaraẹnisọrọ ebute ni tẹlentẹle nipasẹ okun USB mini FTDI, fi awakọ FTDI D2XX sori ẹrọ. Ṣe igbasilẹ awakọ ati itọsọna fifi sori ẹrọ lati:
http://www.microsemi.com/soc/documents/CDM_2.08.24_WHQL_Certified.zip.
olusin 7 Design Sisan fun Hardware Boot Engine Ọna
So awọn jumpers pọ lori igbimọ Apo Igbelewọn Aabo SmartFusion2, bi o ṣe han ninu Tabili 2.
Iṣọra: Ṣaaju ṣiṣe awọn asopọ jumper, PA iyipada ipese agbara, SW7.
Table 2 SmartFusion2 Aabo Igbelewọn Apo Jumper Eto
Jumper | Pin (Lati) | Pin (Si) | Comments |
J22 | 1 | 2 | Aiyipada |
J23 | 1 | 2 | Aiyipada |
J24 | 1 | 2 | Aiyipada |
J8 | 1 | 2 | Aiyipada |
J3 | 1 | 2 | Aiyipada |
Ninu Apo Igbelewọn Aabo SmartFusion2, so ipese agbara pọ si asopo J6. Nọmba 8 ṣe afihan iṣeto igbimọ fun ṣiṣe ojiji koodu lati filasi SPI si demo LPDDR lori Apo Igbelewọn Aabo SmartFusion2.
olusin 8 SmartFusion2 Aabo Igbelewọn Apo Oṣo
SPI Flash agberu ati koodu Shadowing Ririnkiri GUI
Eyi nilo lati ṣiṣẹ demo ojiji koodu. SPI Flash Loader ati koodu Shadowing Demo GUI jẹ wiwo olumulo ayaworan ti o rọrun ti o nṣiṣẹ lori PC agbalejo lati ṣe eto filasi SPI ati ṣiṣe demo ojiji koodu lori Apo Igbelewọn Aabo SmartFusion2. A lo UART gẹgẹbi ilana ibaraẹnisọrọ isale laarin PC agbalejo ati Apo Igbelewọn Aabo SmartFusion2. O tun pese apakan console ni tẹlentẹle lati tẹ sita awọn ifiranṣẹ yokokoro ti o gba lati inu ohun elo lori wiwo UART.
olusin 9 SPI Flash Loader ati Code Shadowing Ririnkiri GUI
GUI ṣe atilẹyin awọn ẹya wọnyi:
- Eto SPI Flash: Awọn eto aworan naa file sinu SPI filasi.
- Eto ati ojiji koodu lati SPI Flash si DDR: Awọn eto aworan naa file sinu SPI filasi, daakọ ti o si awọn DDR iranti, ati bata aworan lati DDR iranti.
- Eto ati ojiji koodu lati SPI Flash si SDR: Awọn eto aworan naa file sinu filasi SPI, daakọ si iranti SDR, ati bata aworan lati iranti SDR.
- Code Shadowing to DDR: Da awọn ti wa tẹlẹ image file lati SPI filasi to DDR iranti ati orunkun aworan lati DDR iranti.
- Ojiji koodu si SDR: Daakọ aworan ti o wa tẹlẹ file lati SPI filasi si iranti SDR ati bata aworan lati iranti SDR.
Tẹ Iranlọwọ fun alaye diẹ sii lori GUI.
So SmartFusion2 Apo Idagbasoke mọ kọnputa rẹ nipa lilo okun Blaster USB tabi okun Blaster II. Lẹhinna tẹle awọn igbesẹ isalẹ:
- Agbara lori Apo Idagbasoke SmartFusion2.
- Ṣii koodu Shadowing Demo GUI ninu sọfitiwia SoC Libero.
- Yan awọn eto ti o yẹ fun apẹrẹ rẹ ki o tẹ “Ipilẹṣẹ” lati ṣe agbekalẹ siseto naa file.
- Sopọ si SmartFusion2 Apo Idagbasoke nipa lilo okun Blaster USB tabi okun Blaster II USB.
- Ṣe eto FPGA ki o gbe aworan ohun elo lati filasi SPI si iranti LPDDR nipa tite “Eto” ni koodu Shadowing Demo GUI.
Ṣiṣe Apẹrẹ Ririnkiri fun Multi-Stage Boot Ilana Ọna
Lati ṣiṣe awọn demo oniru fun awọn olona-stage bata ilana ọna, tẹle awọn igbesẹ ni isalẹ:
- Agbara lori Apo Idagbasoke SmartFusion2.
- Sopọ si SmartFusion2 Apo Idagbasoke nipa lilo okun Blaster USB tabi okun Blaster II USB.
- Tun awọn ọkọ ati ki o duro fun o lati pari awọn bata ilana.
- Ohun elo naa yoo ṣiṣẹ laifọwọyi lati iranti LPDDR.
Awọn igbesẹ atẹle yii ṣe apejuwe bi o ṣe le ṣiṣe apẹrẹ demo fun ọpọlọpọ-stage bata ilana:
- Yi awọn ipese agbara yipada SW7 to ON.
- Ṣeto ẹrọ SmartFusion2 SoC FPGA pẹlu siseto naa file pese ni apẹrẹ files (SF2_CodeShadowing_LPDDR_DF \ Eto
Files\MultiStageBoot_method\CodeShadowing_LPDDR_top.stp ni lilo sọfitiwia apẹrẹ FlashPro. - Lọlẹ SPI Flash Loader ati koodu Shadowing Demo GUI ṣiṣe file wa ninu apẹrẹ files (SF2_CodeShadowing_LPDDR_DF \ GUI Executable \ SF2_FlashLoader.exe).
- Yan ibudo COM ti o yẹ (si eyiti awọn awakọ USB Serial ti tọka si) lati atokọ jabọ-silẹ Port Port.
- Tẹ Sopọ. Lẹhin ti iṣeto asopọ, So awọn ayipada pọ si Ge asopọ.
- Tẹ Kiri lati yan example afojusun executable image file pese pẹlu oniru files (SF2_CodeShadowing_LPDDR_DF/Sample Ohun elo Images/MultiStageBoot_ọna / sample_image_LPDDR.bin).
Akiyesi: Lati ṣe ina ohun elo bin bin file, tọka si “Afikun: Ti ipilẹṣẹ Executable Bin File” loju iwe 24. - Tọju adirẹsi ibẹrẹ ti iranti filasi SPI bi aiyipada ni 0x00000000.
- Yan Eto ati Shadowing koodu lati SPI Flash si aṣayan DDR.
- Tẹ Bẹrẹ bi o ṣe han ni Nọmba 10 lati gbe aworan ti o ṣiṣẹ sinu filasi SPI ati ojiji koodu lati iranti DDR.
olusin 10 Bibẹrẹ Ririnkiri
Ti ẹrọ SmartFusion2 ti ni eto pẹlu STAPL kan file ninu eyiti a ko tunto MDR fun iranti DDR lẹhinna o fihan ifiranṣẹ aṣiṣe, bi o ṣe han ni Nọmba 11.
Ṣe nọmba 11 Ẹrọ ti ko tọ tabi Ifiranṣẹ Aṣayan
Abala console ni tẹlentẹle lori GUI ṣe afihan awọn ifiranṣẹ yokokoro ati bẹrẹ siseto filasi SPI lori piparẹ filasi SPI ni aṣeyọri. Nọmba 12 fihan ipo ti kikọ filasi SPI.
olusin 12 Flash Loading
- Lori siseto filasi SPI ni aṣeyọri, bootloader nṣiṣẹ lori SmartFusion2 SoC FPGA daakọ aworan ohun elo lati filasi SPI si iranti DDR ati bata aworan ohun elo naa. Ti aworan ti a pese sample_image_LPDDR.bin ti yan, ni tẹlentẹle console fihan awọn kaabo awọn ifiranṣẹ, yipada da gbigbi ati aago awọn ifiranṣẹ bi o han ni Figure 13 ati Figure
- Apẹrẹ LED ti nṣiṣẹ ti han lori LED1 si LED8 lori Apo Iṣiro Aabo SmartFusion2.
- Tẹ awọn iyipada SW2 ati SW3 lati wo awọn ifiranṣẹ idalọwọduro lori console tẹlentẹle.
olusin 13 Ṣiṣe Aworan Ohun elo Àkọlé lati DDR3 Memory
Ṣe nọmba 14 Aago ati Awọn ifiranṣẹ Idilọwọ ni Tẹlentẹle Console
Nṣiṣẹ Hardware Boot Engine Ọna Apẹrẹ
Lati ṣiṣẹ apẹrẹ demo fun ọna ẹrọ bata ohun elo, tẹle awọn igbesẹ ni isalẹ:
- Agbara lori Apo Idagbasoke SmartFusion2.
- Sopọ si SmartFusion2 Apo Idagbasoke nipa lilo okun Blaster USB tabi okun Blaster II USB.
- Tun awọn ọkọ ati ki o duro fun o lati pari awọn bata ilana.
- Ohun elo naa yoo ṣiṣẹ laifọwọyi lati iranti LPDDR.
Awọn igbesẹ wọnyi ṣe apejuwe bi o ṣe le ṣiṣe apẹrẹ ọna ẹrọ bata ohun elo:
- Yi awọn ipese agbara yipada SW7 to ON.
- Ṣe eto ẹrọ SmarFusion2 SoC FPGA pẹlu siseto file pese ni apẹrẹ files (SF2_CodeShadowing_LPDDR_DF \ Eto Files \ HWBootEngine_method \ CodeShadowing_Fabric.stp lilo FlashPro oniru software.
- Lati ṣe eto Flash Flash SPI ṣe DIP yipada SW5-1 si ipo ON. Aṣayan yii ṣe lati bata Cortex-M3 lati eNVM. Tẹ SW6 lati tun SmartFusion2 ẹrọ.
- Lọlẹ SPI Flash Loader ati koodu Shadowing Demo GUI ṣiṣe file wa ninu apẹrẹ files (SF2_CodeShadowing_LPDDR_DF \ GUI Executable \ SF2_FlashLoader.exe).
- Yan ibudo COM ti o yẹ (si eyiti awọn awakọ USB Serial ti tọka si) lati atokọ jabọ-silẹ Port Port.
- Tẹ Sopọ. Lẹhin ti iṣeto asopọ, So awọn ayipada pọ si Ge asopọ.
- Tẹ Kiri lati yan example afojusun executable image file pese pẹlu oniru files (SF2_CodeShadowing_LPDDR_DF/Sample Ohun elo Images/HWBootEngine_method/sample_image_LPDDR.bin).
Akiyesi: Lati ṣe ina ohun elo bin bin file, tọka si “Afikun: Ti ipilẹṣẹ Executable Bin File” loju iwe 24. - Yan Hardware Boot Engine aṣayan ni Ọna Shadowing Code.
- Yan Eto SPI Flash aṣayan lati inu akojọ aṣayan.
- Tẹ Bẹrẹ, bi o ṣe han ni Nọmba 15 lati gbe aworan ti o le ṣiṣẹ sinu filasi SPI.
olusin 15 Bibẹrẹ Ririnkiri
Abala console ni tẹlentẹle lori GUI ṣe afihan awọn ifiranṣẹ yokokoro ati ipo kikọ filasi SPI, bi o ṣe han ni Nọmba 16.
olusin 16 Flash Loading
- Lẹhin siseto filasi SPI ni aṣeyọri, yi DIP yipada SW5-1 si ipo PA. Yiyan yi mu ki a bata Cortex-M3 ero isise lati DDR iranti.
- Tẹ SW6 lati tun SmartFusion2 ẹrọ. Enjini bata daakọ aworan ohun elo lati filasi SPI si iranti DDR ati awọn idasilẹ tun pada si Cortex-M3, eyiti o ṣe bata aworan ohun elo lati iranti DDR. Ti aworan ti a pese “sample_image_LPDDR.bin" ti wa ni ti kojọpọ to SPI filasi, ni tẹlentẹle console fihan awọn kaabo awọn ifiranṣẹ, yipada da gbigbi (tẹ SW2 tabi SW3) ati aago da gbigbi awọn ifiranṣẹ, bi o han ni Figure 17 ati ki o kan nṣiṣẹ LED Àpẹẹrẹ ti han lori LED1 to LED8 lori SmartFusion2 Apo Igbelewọn Aabo.
olusin 17 Ṣiṣe Aworan Ohun elo Àkọlé lati DDR3 Memory
Ipari
O ti lo SmartFusion2 SoC FPGA ni aṣeyọri pẹlu ojiji koodu lati SPI Flash si iranti LPDDR. demo yii ṣe afihan agbara ti ẹrọ SmartFusion2 lati ni wiwo pẹlu iranti DDR ati lati ṣiṣẹ aworan ti o ṣiṣẹ lati iranti DDR nipasẹ ojiji koodu lati ẹrọ iranti filasi SPI . O tun fihan awọn ọna meji ti imuse ojiji koodu lori ẹrọ SmartFusion2.
Àfikún: LPDDR Awọn atunto
olusin 18 General DDR iṣeto ni Eto
olusin 19 DDR Memory Initialization Eto
olusin 20 DDR Memory Time Eto
Àfikún: Ti o npese Executable Bin File
Awọn executable bin file O nilo lati ṣe eto filasi SPI fun ṣiṣe demo ojiji koodu. Lati se ina awọn executable bin file lati "sample_image_LPDDR” SoftConsole, ṣe awọn igbesẹ wọnyi:
- Kọ iṣẹ akanṣe SoftConsole pẹlu iṣelọpọ iwe afọwọkọ linker-execute-in-place-externalDDR.
- Ṣafikun ọna fifi sori ẹrọ SoftConsole, fun example,
C: \ Microsemi \ Libero_v11.7 \ SoftConsole \ Orisun-G ++ \ bin, si 'Ayika Alyipada', bi o han ni Figure 21.
olusin 21 Fifi SoftConsole fifi sori Ona
- Tẹ ipele lẹẹmeji file Bin-File-Generator.bat be ni: SoftConsole/CodeShadowing_LPDDR_MSS_CM3/Sample_image_LPDDR folda, bi o ṣe han ni Nọmba 22.
olusin 22 Fifi SoftConsole fifi sori Ona
- Bin-File-Apilẹṣẹ ṣẹda sample_image_LPDDR.bin file
Àtúnyẹwò History
Tabili ti o tẹle n ṣe afihan awọn ayipada pataki ti a ṣe ninu iwe yii fun atunyẹwo kọọkan.
Àtúnyẹwò | Awọn iyipada |
Atunyẹwo 2
(Oṣu Kẹrin ọdun 2016) |
Ṣe imudojuiwọn iwe-ipamọ fun idasilẹ sọfitiwia Libero SoC v11.7 (SAR 78258). |
Atunyẹwo 1
(Oṣu Keji ọdun 2015) |
Itusilẹ akọkọ. |
Ọja Support
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Awọn onimọ-ẹrọ ti o ni oye ga julọ oṣiṣẹ Ile-iṣẹ Atilẹyin Imọ-ẹrọ. Ile-iṣẹ Atilẹyin Imọ-ẹrọ le kan si nipasẹ imeeli tabi nipasẹ Microsemi SoC Products Group webojula.
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Awọn alabara Ẹgbẹ Awọn ọja Microsemi SoC le fi silẹ ati tọpa awọn ọran imọ-ẹrọ lori ayelujara nipa lilọ si Awọn ọran Mi.
Ita awọn US
Awọn alabara ti o nilo iranlọwọ ni ita awọn agbegbe akoko AMẸRIKA le kan si atilẹyin imọ-ẹrọ nipasẹ imeeli (soc_tekinoloji@microsemi.com) tabi kan si ọfiisi tita agbegbe kan. Ṣabẹwo Nipa Wa fun awọn atokọ ọfiisi tita ati awọn olubasọrọ ajọ.
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Microsemi DG0669 SmartFusion2 Code Shadowing lati SPI Flash to LPDDR Memory [pdf] Itọsọna olumulo DG0669 SmartFusion2 Koodu ojiji lati SPI Flash si Iranti LPDDR, DG0669, SmartFusion2 Koodu ojiji lati SPI Flash si Iranti LPDDR, Flash SPI si Iranti LPDDR |