Mataupu lalafi
1 Microsemi DG0669 SmartFusion2 Faʻailoga Faʻailoga mai le SPI Flash i le LPDDR Memory
2 Fa'amatalaga o oloa
3 Fa'aogaina o Mea
4 Upu Tomua
5 SmartFusion2 SoC FPGA - Faʻailoga Faʻailoga mai le SPI Flash i le LPDDR Memory
6 Fa'aopoopo: LPDDR Configurations
7 Fa'aopoopo: Fausiaina Talone Fa'atino File
8 Toe Iloilo Tala'aga
9 Lagolago oloa
10 Pepa / Punaoa
10.1 Fa'asinomaga
11 Fa'amatalaga Fa'atatau

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Microsemi DG0669 SmartFusion2 Faʻailoga Faʻailoga mai le SPI Flash i le LPDDR Memory

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-PRODUCT

Fa'amatalaga o oloa

O le SmartFusion2 SoC FPGA o se fofo FPGA maualuga, maualalo le malosi e tuʻufaʻatasia ai le ARM Cortex-M3 processor, polokalame analog ma numera numera, ma fesoʻotaʻiga fesoʻotaʻiga televave i luga o se pu e tasi. O le Libero SoC v11.7 software o se faʻataʻitaʻiga atoatoa mo le faʻatulagaina ma Microsemi FPGAs.

Fa'aogaina o Mea

Mo le faʻaogaina o le SmartFusion2 SoC FPGA faʻatasi ai ma le faʻailoga faʻailoga mai le SPI Flash i le LPDDR manatua, mulimuli i laasaga o loʻo i lalo:

Upu Tomua

Faamoemoega
O lenei demo e mo SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) masini. O lo'o tu'uina mai ai fa'atonuga i le fa'aogaina o le mamanu fa'atatau.

Tagata Fa'amoemoe

O lenei fa'ata'ita'iga ta'iala e fa'amoemoe mo:

  • FPGA mamanu
  • Fa'ailoga fa'apipi'i
  • Fa'atonu-tulaga faiga

Fa'asinomaga
Va'ai mea nei web itulau mo se lisi atoatoa ma faʻaonaponei o faʻamaumauga o masini SmartFusion2: http://www.microsemi.com/products/fpga-soc/soc-fpga/sf2docs
O pepa nei o lo'o tu'uina atu i lenei ta'iala fa'ata'ita'iga.

  • UG0331: SmartFusion2 Microcontroller Subsystem Guide Guide
  • SmartFusion2 System Builder Taiala mo Tagata Fa'aoga

SmartFusion2 SoC FPGA - Faʻailoga Faʻailoga mai le SPI Flash i le LPDDR Memory

Folasaga
O lenei faʻataʻitaʻiga mamanu faʻaalia SmartFusion2 SoC FPGA masini gafatia mo code ata lafoia mai le serial peripheral interface (SPI) flash memory device i le maualalo o le mana faʻalua faʻamaumauga (LPDDR) synchronous dynamic random access memory (SDRAM) ma le faʻatinoina o le code mai le LPDDR SDRAM. O le ata 1 o loʻo faʻaalia ai le ata pito i luga o le poloka poloka mo faʻailoga faʻailoga mai le SPI flash device i le LPDDR memory.

Ata 1 Fa'ata'ita'iga Poloka Tulaga Maualuga o le Fa'aaliga

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-1

Fa'ailoga fa'ailoga o se metotia fa'apolopolo lea e fa'aaogaina e fa'ata'ita'i ai se ata mai manatuaga i fafo, vave, ma fe'avea'i (DRAM). O le fa'agasologa o le kopiina o le code mai le manatua e le fa'afefeteina i le manatua fa'aletonu mo le fa'atinoina. E mana'omia le fa'aataina o le code, pe a le lagolagoina e le manatua e le fa'afefeteina e feso'ota'i ma se processor le avanoa fa'afuase'i i le code mo le fa'atinoina-i-nofoaga, po'o le le lava o le manatua avanoa fa'afuase'i. I faʻatinoga faʻapitoa, o le saoasaoa o le faʻatinoga e mafai ona faʻaleleia e ala i le faʻaogaina o le code, lea e kopiina ai le code i le maualuga maualuga o le RAM mo le faʻatinoina vave. Fa'amaumauga o fa'amaumauga ta'itasi (SDR)/DDR SDRAM e fa'aaogaina i tusi talosaga e iai se ata fa'atino tele ma e mana'omia ai le fa'atinoga maualuga. E masani lava, o ata lapopoa e mafai ona teuina i totonu o le mafaufau e le faʻafefe, e pei o le NAND flash poʻo le SPI flash, ma kopiina i le mafaufau faʻafefe, e pei o le SDR/DDR SDRAM memory, i le mana mo le faʻatinoina. O masini SmartFusion2 e tu'ufa'atasia le ie FPGA fa'avae fa'amalama lona fa, o le ARM® Cortex®-M3, ma feso'ota'iga feso'ota'iga maualuga i luga o se pu e tasi. O fa'atonuga manatua maualuga i totonu o masini SmartFusion2 o lo'o fa'aogaina e fa'afeso'ota'i ma manatuaga DDR2/DDR3/LPDDR fafo. Ole manatua ole LPDDR e mafai ona fa'agaoioia ile saoasaoa maualuga ole 166 MHz. O le Cortex-M3 processor e mafai ona faʻatautaia saʻo faatonuga mai fafo DDR memory e ala i le microcontroller subsystem (MSS) DDR (MDDR). O le FPGA Cache Controller ma MSS DDR alalaupapa e faʻatautaia le tafe o faʻamatalaga mo se faʻatinoga sili atu.

Fuafuaga Manaomia
Ia mautinoa o loʻo ia te oe meafaigaluega ma masini komepiuta e manaʻomia:

Meafaigaluega ma Polokalama Manaoga

Fuafuaga 1 Fuafuaga Manaomia

Fuafuaga Manaomia Fa'amatalaga
Meafaigaluega Manaomia
SmartFusion2 Saogalemu Su'esu'ega Kit:

• 12 V fetuutuunai

• FlashPro4

• USB A i le Mini – B uaea USB

 Rev D pe mulimuli ane
Host PC po'o le Laptop Windows XP SP2 Operating System – 32-/64-bit Windows 7 Operating System – 32-/64-bit
Polokalama Manaoga
Libero® System-on-Chip (SoC) v11.7
Polokalame Polokalama FlashPro v11.7
SoftConsole v3.4 SP1*
Talia ta'avale PC USB i avetaavale UART
Ta'iala mo le fa'alauiloa GUI demo Microsoft .NET Framework 4 Client mo le tatalaina o GUI demo
Fa'aaliga: *Mo lenei fa'ata'ita'iga ta'iala, SoftConsole v3.4 SP1 fa'aoga. Mo le fa'aogaina o SoftConsole v4.0, va'ai le TU0546: SoftConsole v4.0 ma Libero SoC v11.7 A'oa'oga.
  • SmartFusion2 Atina'e Kit
  • Libero SoC v11.7 polokalama
  • USB Blaster po'o le USB Blaster II uaea

Fa'ata'ita'iga Fuafuaga
O le faʻataʻitaʻiga faʻataʻitaʻiga e faʻaaogaina ai le tele-stagu faiga fa'aoso faiga po'o se masini fa'apipi'i masini auala e uta ai le ata talosaga mai le SPI flash i le LPDDR manatua. Mulimuli i laasaga o loʻo i lalo: Le mamanu files o loʻo avanoa mo le download mai le auala o loʻo i lalo i le Microsemi webnofoaga: http://soc.microsemi.com/download/rsc/?f=m2s_dg0669_liberov11p7_df

Fuafuaga filee aofia ai:
Le mamanu demo filee aofia ai:

  • Sample talosaga ata
  • Polokalama files
  • Libero
  • GUI fa'atino
  • Fa'asinomaga feso'ota'iga
  • Fa'atonuga DDR files
  • Faitau.txt file

SmartFusion2 SoC FPGA - Faʻailoga Faʻailoga mai le SPI Flash i le LPDDR Memory Figure 2 o loʻo faʻaalia ai le fausaga pito i luga o le mamanu. files. Mo nisi fa'amatalaga, tagai ile Readme.txt file.

Ata 2 Fuafuaga Files Fuafuaga Tulaga Maualuga

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-2

Fa'amatalaga Fa'ata'ita'iga

O lenei faʻataʻitaʻiga faʻataʻitaʻiga o loʻo faʻaogaina ai le faʻataʻitaʻiga o le faʻaogaina o le ata o le talosaga mai le DDR memory. O lenei mamanu o lo'o tu'uina atu ai fo'i feso'ota'iga talimalo i luga ole SmartFusion2 SoC FPGA multi-mode universal asynchronous/synchronous receiver/transmitter (MMUART) e utaina ai le ata fa'atino fa'atatau ile SPI flash e feso'ota'i ile MSS SPI0 interface.
O le faʻailoga code e faʻatinoina i auala nei e lua:

  • Tele-stage fa'aulu auala faiga fa'aoga le Cortex-M3 processor
  • Metotia fa'aa'e afi masini fa'aaoga le ie FPGA.

Tele-Stagu Metotia Fa'agasologa Fa'avae

  1. Fausia se ata tusi talosaga mo DDR manatua e faʻaaoga ai le polokalama Libero SoC.
  2. U'u le SPI Flash loader i le SPI flash e fa'aaoga ai le polokalame Libero SoC.
  3. Fa'asolo le Code Shadowing Demo GUI e fa'apolokalame ai le FPGA ma uta le ata talosaga mai le SPI flash i le LPDDR memory.

O le ata talosaga o loʻo faʻatautaia mai i fafo DDR manatua i le lua o loʻo mulimuli maitage:

  • O le Cortex-M3 processor e faʻapipiʻiina le faʻapipiʻiina o le seevae vaivai mai le manatua e le faʻafefeteina (eNVM), lea e faʻatino ai le faʻaliliuina o ata mai le SPI flash device i le DDR memory.
  • O le Cortex-M3 processor e faʻauluina le ata talosaga mai le DDR memory.

O lenei mamanu o loʻo faʻaaogaina se polokalame faʻapipiʻi e utaina ai le ata faʻatinoina o le talosaga mai le SPI flash device i le DDR memory mo le faʻatinoina. O le polokalame bootloader o loʻo tamoʻe mai le eNVM e oso i le faʻatonuga o loʻo teuina i le DDR memory pe a maeʻa ona kopiina le ata o le talosaga i le DDR memory.

Ata 3 Code Shadowing Multi-Stage Fa'aosoina Fa'asologa Fa'ata'ita'iga Poloka Ata

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-3

O le MDDR ua fa'atulagaina mo LPDDR e fa'agaoioi i le 166 MHz. “Faaopoopoga: LPDDR Configurations” i le itulau 22 o loʻo faʻaalia ai le faʻatulagaina o le LPDDR. O le DDR ua faʻapipiʻiina aʻo leʻi faʻatinoina le numera autu o talosaga.

Fa'ameamea

O le bootloader e faʻatino galuega nei:

  1. O le kopiina o le ata o le talosaga mai le SPI flash memory i le DDR memory.
  2. Toe fa'aleleia le tuatusi DDR manatua amata mai le 0xA0000000 i le 0x00000000 e ala i le fa'atulagaina o le DDR_CR system register.
  3. Amataina le Cortex-M3 processor stack pointer e tusa ai ma le faʻaoga faʻatatau. O le nofoaga muamua o le laulau fa'ata'ita'i fa'atatau o lo'o i ai le tau fa'ailoga fa'aputu. O lo'o avanoa le laulau ve'a ole fa'atatauga e amata ile tuatusi 0x00000000.
  4. O lo'o utaina le fata o polokalame (PC) e toe fa'afo'i ai le fa'atonu o le fa'atonuga mo le fa'atinoina o le ata fa'atatau o le talosaga mai le DDR memory. Toe fa'afo'i le fa'atonu o le talosaga fa'atatau o lo'o avanoa ile laulau ve'a ile tuatusi 0x00000004.

Ata 4 Fuafuaga Fa'asolo mo Multi-Stagu Metotia Fa'agasologa Fa'avae

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-4

Metotia Fa'aa'e Meafaigaluega Fa'aa'oa

  1. Fausia se binary executable file fa'aaoga le polokalame Libero SoC.
  2. uta le binary file i le SPI flash e faʻaaoga ai le polokalama Libero SoC.
  3. Fa'asolo le Mea Fa'apipi'i Mea Fa'aa'oa'oga e fa'apolokalame ai le FPGA ma uta le ata o le talosaga mai le SPI flash i le LPDDR memory.

I lenei metotia, o le Cortex-M3 e faʻapipiʻi saʻo ai le faʻataʻitaʻiga o le faʻataʻitaʻiga mai faʻamatalaga DDR i fafo. O le masini faʻapipiʻi meafaigaluega e kopiina le ata o le talosaga mai le SPI flash device i le DDR memory, aʻo leʻi tuʻuina atu le Cortex-M3 processor reset. A maeʻa ona tuʻuina atu le seti, o le Cortex-M3 processor e saʻo saʻo mai le DDR memory. O lenei metotia e manaʻomia ai le itiiti ifo o le taimi faʻapipiʻi nai lo le tele-stage fa'auluina fa'agasologa aua e 'alo'ese ai le tele o seevae stages ma kopi ata talosaga i le DDR manatua i se taimi itiiti. O lenei fa'ata'ita'iga fa'ata'ita'iga o lo'o fa'aogaina ai le fa'aogaina o le afi i le ie FPGA e kopi ai le ata fa'atinoina o le talosaga mai le SPI flash i le DDR memory mo le fa'atinoina. O lenei mamanu o loʻo faʻaaogaina ai le SPI flash loader, lea e mafai ona faʻatinoina e le Cortex-M3 processor e faʻapipiʻi ai le faʻaogaina o le ata faʻaogaina i totonu o le masini moli SPI e faʻaaoga ai le faʻaoga talimalo tuʻuina atu i luga o SmartFusion2 SoC FPGA MMUART_1. Ole DIP switch1 ile SmartFusion2 Security Evaluation Kit e mafai ona fa'aoga e filifili pe fa'apolokalame le SPI flash device pe fa'atino le code mai le DDR memory. Afai o lo'o maua le talosaga fa'atino i totonu o le SPI flash device, o le fa'ailoga fa'aali mai le SPI flash device i le DDR memory e amata i luga o le masini eletise. O le afi taʻavale e amataina le MDDR, kopi le ata mai le SPI flash device i le DDR memory, ma toe faʻapipiʻi le DDR memory space i le 0x00000000 e ala i le teuina o le Cortex-M3 processor i le toe setiina. A maeʻa ona faʻasaʻo e le afi afi le Cortex-M3 reset, o le Cortex-M3 e faʻatino le faʻaoga mai le DDR memory. Ata 5 o lo'o fa'aalia ai le fa'ata'ita'iga poloka fa'ata'ita'i o le fa'ata'ita'iga. O le FIC_0 o loʻo faʻapipiʻiina i le Slave mode e maua ai le MSS SPI_0 mai le FPGA fabric AHB master. O le MDDR AXI interface (DDR_FIC) e mafai ona maua le DDR memory mai le FPGA fabric AXI master.

Ata 5 Fa'ailoga Fa'aolooloina Meafaigaluega Boot Engine Fa'ata'ita'iga Block Diagram

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-5

Inisinia Fa'amau
O le vaega tele lea o le faʻataʻitaʻiga faʻataʻitaʻiga o loʻo kopiina le ata talosaga mai le SPI flash device i le DDR memory. O le afi afi e faia galuega nei:

  1. Amataina MDDR mo le mauaina o le LPDDR i le 166 MHz e ala i le tausia o le Cortex-M3 processor i le toe setiina.
  2. O le kopiina o le ata o le talosaga mai le SPI flash memory device i le DDR memory e faaaoga ai le AXI master i le FPGA fabric e ala i le MDDR AXI interface.
  3. Toe fa'ailogaina le DDR memory amata tuatusi mai le 0xA0000000 i le 0x00000000 e ala i le tusi i le DDR_CR system register.
  4. Faʻasaʻo le seti i le Cortex-M3 processor e faʻaulu mai le DDR memory.

Ata 6 Fuafuaga Fuafuaga mo Metotia Fa'aa'e Meafaigaluega

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-6

Fausiaina o Ata Fa'atatau mo le DDR Memory

O se ata e mafai ona faʻatinoina mai le DDR memory e manaʻomia e faʻatautaia ai le demo. Fa'aaogā le fa'amatalaga o feso'ota'iga production-execute-in-place-externalDDR.ld file e aofia ai i le mamanu files e fausia le ata talosaga. O lenei faʻamatalaga fesoʻotaʻiga file fa'amatalaina le tuatusi amata o le DDR e pei o le 0x00000000 talu ai ona o le bootloader po'o le afi afi e fa'atino ai le toe manatua o le DDR mai le 0xA0000000 i le 0x00000000. O lenei tusitusiga feso'ota'iga e fausia ai se ata talosaga ma fa'atonuga, fa'amaumauga, ma vaega BSS i le manatua o lona tuatusi amata o le 0x00000000. Ose moli-emitting diode faigofie (LED) emo, taimi ma fesuia'i fa'avae fa'atupu fa'alavelave fa'aoga ata file ua saunia mo lenei demo.

SPI Flash Loader

O le SPI flash loader o loʻo faʻatinoina e faʻapipiʻi ai le SPI flash memory i luga o le laupapa ma le faʻataʻitaʻiga faʻaoga faʻaoga mai le PC talimalo e ala i le MMUART_1 interface. O le Cortex-M3 processor e fai se pa'u mo fa'amatalaga o lo'o o'o mai i luga o le MMUART_1 ma fa'amataina le DMA lautele (PDMA) e tusi ai fa'amaumauga fa'asalaina i le SPI flash e ala i le MSS_SPI0.

Fa'atino le Demo
Ina ia faʻataʻitaʻiina le mamanu faʻataʻitaʻiga, mulimuli i laʻasaga o loʻo i lalo: O loʻo faʻaalia e le demo le auala e utaina ai le ata o le talosaga i le SPI flash ma faʻatino lena ata talosaga mai fafo DDR manatua. O lenei demo e maua ai se example ata talosaga sample_image_LPDDR.bin. O lenei ata o loʻo faʻaalia ai feʻau faʻafeiloaʻi ma le taimi faʻalavelave faʻalavelave i luga o le faʻamafanafanaga ma emo le LED1 i le LED8 i le SmartFusion2 Security Evaluation Kit. Ina ia va'ai i le GPIO fa'alavelave fe'au i luga o le fa'amafanafanaga fa'asologa, lolomi le SW2 po'o le SW3 ki.

Fa'atulaga le Fa'ata'ita'iga Design

O laasaga nei o loʻo faʻamatalaina pe faʻapefea ona seti le demo mo SmartFusion2 Security Evaluation Kit board: Faʻafesoʻotaʻi le PC talimalo ile J18 Connector e faʻaaoga ai le USB A i le mini-B cable. O le USB i UART alalaupapa avetaavale e otometi lava ona iloa. Fa'amaonia pe o faia le su'esu'ega ile pule ole masini e pei ona fa'aalia ile Ata 7.

  1. Afai e le otometi ona iloa avetaavale USB, faʻapipiʻi le avetaavale USB.
  2. Mo feso'ota'iga fa'asologa fa'asolosolo e ala i le FTDI mini USB cable, fa'apipi'i le aveta'avale FTDI D2XX. La'u mai aveta'avale ma fa'apipi'i ta'iala mai:
    http://www.microsemi.com/soc/documents/CDM_2.08.24_WHQL_Certified.zip.

Ata 7 Fuafuaga Fuafuaga mo Metotia Fa'aa'e Meafaigaluega

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-7

Fa'afeso'ota'i tagata osooso i luga o le laupapa SmartFusion2 Security Evaluation Kit, e pei ona fa'aalia i le Laulau 2.

Lapata'iga: A'o le'i faia so'oga osooso, tape le ki o le sapalai eletise, SW7.

Laulau 2 SmartFusion2 Su'esu'ega Su'esu'ega Kit Fa'atonuga

Tagata osooso Pin (Mai) Pin (I) Fa'amatalaga
J22 1 2 Fa'atonu
J23 1 2 Fa'atonu
J24 1 2 Fa'atonu
J8 1 2 Fa'atonu
J3 1 2 Fa'atonu

I le SmartFusion2 Security Evaluation Kit, faʻafesoʻotaʻi le eletise i le fesoʻotaʻiga J6. O le ata 8 o loʻo faʻaalia ai le faʻatulagaina o le laupapa mo le faʻaogaina o le faʻailoga faʻailoga mai le SPI flash i le LPDDR demo i luga o le SmartFusion2 Security Evaluation Kit.

Ata 8 SmartFusion2 Seti Su'esu'ega Pusa

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-8

SPI Flash Loader ma Code Shadowing Demo GUI
E mana'omia lenei mea e fa'agasolo ai le fa'ata'ita'iga fa'aata ata. SPI Flash Loader ma Code Shadowing Demo GUI o se faʻaoga faigofie faʻaoga faʻaoga e tamoʻe i luga o le PC talimalo e faʻapipiʻi le SPI flash ma faʻatautaia le faʻataʻitaʻiga faʻataʻitaʻiga i luga o le SmartFusion2 Security Evaluation Kit. O lo'o fa'aaogaina le UART e fai ma vase vase feso'ota'iga i le va o le PC talimalo ma le SmartFusion2 Security Evaluation Kit. O lo'o tu'uina atu ai fo'i le vaega fa'amafanafana fa'asologa e lolomi ai fe'au debug na maua mai le talosaga i luga o le UART interface.

Ata 9 SPI Flash Loader ma Code Shadowing Demo GUI

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-9

E lagolagoina e le GUI vaega nei:

  • Polokalama SPI Flash: Polokalama le ata file i totonu ole moli SPI.
  • Polokalama ma Code Shadowing mai le SPI Flash i le DDR: Polokalama le ata file i totonu o le SPI flash, kopi i le DDR memory, ma fa'ae'e le ata mai le DDR memory.
  • Polokalama ma Code Shadowing mai le SPI Flash i le SDR: Polokalama le ata file i totonu o le SPI flash, kopi i le SDR memory, ma fa'aa'e le ata mai le SDR memory.
  • Code Shadowing to DDR: Kopi le ata o lo'o iai file mai le SPI moli i le DDR manatua ma seevae le ata mai le DDR manatua.
  • Fa'ailoga Fa'ailoga i le SDR: Kopi le ata o lo'o iai file mai le SPI flash i le SDR manatua ma seevae le ata mai le SDR manatua.

Kiliki Fesoasoani mo nisi fa'amatalaga ile GUI.

Fa'afeso'ota'i le SmartFusion2 Development Kit i lau komepiuta e fa'aoga ai le USB Blaster po'o le USB Blaster II cable. Ona mulimuli lea i laasaga o loʻo i lalo:

  1. Malosiaga ile SmartFusion2 Development Kit.
  2. Tatala le Code Shadowing Demo GUI i le Libero SoC software.
  3. Filifili tulaga talafeagai mo lau mamanu ma kiliki "Fausia" e gaosia ai le polokalame file.
  4. Fa'afeso'ota'i le SmartFusion2 Development Kit e fa'aaoga ai le USB Blaster po'o le USB Blaster II cable.
  5. Polokalama le FPGA ma uta le ata talosaga mai le SPI flash i le LPDDR memory e ala i le kilikiina o le "Polokalame" i le Code Shadowing Demo GUI.

Fa'atino le Fa'ata'ita'iga Design mo Multi-Stagu Metotia Fa'agasologa Fa'avae
E faʻatautaia le mamanu faʻataʻitaʻiga mo le tele-stage boot process method, mulimuli i laasaga o loʻo i lalo:

  1. Malosiaga ile SmartFusion2 Development Kit.
  2. Fa'afeso'ota'i le SmartFusion2 Development Kit e fa'aaoga ai le USB Blaster po'o le USB Blaster II cable.
  3. Toe setiina le laupapa ma faʻatali seʻi maeʻa le faʻagasologa o le taʻavale.
  4. Ole talosaga ole a otometi lava ile LPDDR manatua.

O laasaga nei o loʻo faʻamatalaina pe faʻafefea ona faʻatino le mamanu faʻataʻitaʻiga mo le tele-stagauala faiga fa'avae:

  1. Suia le ki o le sapalai eletise SW7 i ON.
  2. Polokalama le masini SmartFusion2 SoC FPGA ma le polokalame file saunia i le mamanu files (SF2_CodeShadowing_LPDDR_DF\Polokalame
    Files\ MultiStageBoot_method\CodeShadowing_LPDDR_top.stp fa'aaoga le FlashPro design software.
  3. Tatala le SPI Flash Loader ma le Code Shadowing Demo GUI e mafai ona fa'atinoina file avanoa i le mamanu files (SF2_CodeShadowing_LPDDR_DF\GUI Executable\SF2_FlashLoader.exe).
  4. Filifili le taulaga COM talafeagai (lea e faasino i ai le USB Serial drivers) mai le COM Port drop-down list.
  5. Kiliki Feso'ota'i. A uma ona faʻamauina le fesoʻotaʻiga, Fesoʻotaʻi suiga i le Disconnect.
  6. Kiliki Su'esu'e e filifili ai le mea muamuaample ata fa'atinoina file saunia ma le mamanu files (SF2_CodeShadowing_LPDDR_DF/Sample Talosaga Ata/MultiStageBoot_method/sample_image_LPDDR.bin).
    Fa'aaliga: Ina ia fa'atupuina le talone ata talosaga file, va'ai i le “Fa'aopoopoga: Fausiaina o Talone Fa'atino File” i le itulau e 24.
  7. Taofi le tuatusi amata ole SPI flash memory e le mafai ile 0x00000000.
  8. Filifili le Polokalama ma Code Shadowing mai le SPI Flash i le DDR filifiliga.
  9. Kiliki Amata e pei ona faʻaalia i le Ata 10 e faʻapipiʻi ai le ata faʻatinoina i le SPI flash ma faʻailoga ata mai le DDR memory.

Ata 10 Amataina le Demo 

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-10

Afai o le SmartFusion2 masini e faʻapipiʻiina ma se STAPL file lea e le o faʻatulagaina le MDDR mo le DDR memory ona faʻaalia lea o se feʻau sese, e pei ona faʻaalia i le Ata 11.

Ata 11 Sese Meafaigaluega po'o le Filifiliga Feau

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-11

O le vaega fa'amafanafanaga fa'asologa i luga o le GUI o lo'o fa'aalia ai fe'au debug ma amata fa'apolokalame SPI flash i luga o le solo lelei o le SPI flash. Ata 12 o lo'o fa'aalia ai le tulaga o le SPI flash writing.

Ata 12 Fa'amomoli Uta

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-12

  1. I luga o le polokalame o le SPI flash ma le manuia, o le bootloader o loʻo taʻavale i luga o SmartFusion2 SoC FPGA e kopiina le ata talosaga mai le SPI flash i le DDR memory ma faʻaofuofu le ata talosaga. Afai o le ata ua tuuina atu sample_image_LPDDR.bin ua filifilia, o le faʻamafanafanaga serial o loʻo faʻaalia ai feʻau faʻafeiloaʻi, fesuiaʻi faʻalavelave ma faʻalavelave taimi savali e pei ona faʻaalia i le Ata 13 ma le Ata.
  2. O lo'o fa'aalia se fa'ata'ita'iga ta'avale LED ile LED1 i le LED8 ile SmartFusion2 Security Evaluation Kit.
  3. Oomi le SW2 ma le SW3 ki e va'ai ai fe'au fa'alavelave i luga ole fa'amafanafanaga.

Ata 13 Fa'ata'ita'iina le Ata Fa'atatauga Fa'atatau mai le DDR3 Memory

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-13

Ata 14 Taimi ma Fe'au Fa'alavelave ile Serial Console

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-14

Fa'agaoioi le Fuafuaga Metotia o Metotia Fa'aa'e Meafaigaluega
Ina ia faʻataʻitaʻiina le mamanu faʻataʻitaʻiga mo le masini faʻapipiʻi masini, mulimuli i laasaga o loʻo i lalo:

  1. Malosiaga ile SmartFusion2 Development Kit.
  2. Fa'afeso'ota'i le SmartFusion2 Development Kit e fa'aaoga ai le USB Blaster po'o le USB Blaster II cable.
  3. Toe setiina le laupapa ma faʻatali seʻi maeʻa le faʻagasologa o le taʻavale.
  4. Ole talosaga ole a otometi lava ile LPDDR manatua.

O laasaga nei o loʻo faʻamatalaina pe faʻafefea ona faʻagaoioia le faʻaogaina o le masini faʻapipiʻi meafaigaluega:

  1. Suia le ki o le sapalai eletise SW7 i ON.
  2. Polokalama le SmarFusion2 SoC FPGA masini ma le polokalame file saunia i le mamanu files (SF2_CodeShadowing_LPDDR_DF\Polokalame Files\HWBootEngine_method\CodeShadowing_Fabric.stp e fa'aaoga ai le FlashPro design software.
  3. E fa'apolokalame le SPI Flash fai le DIP sui SW5-1 i le ON tulaga. O lenei filifiliga e faʻaosoina ai Cortex-M3 mai le eNVM. Oomi le SW6 e toe setiina le masini SmartFusion2.
  4. Tatala le SPI Flash Loader ma le Code Shadowing Demo GUI e mafai ona fa'atinoina file avanoa i le mamanu files (SF2_CodeShadowing_LPDDR_DF\GUI Executable\SF2_FlashLoader.exe).
  5. Filifili le taulaga COM talafeagai (lea e faasino i ai le USB Serial drivers) mai le COM Port drop-down list.
  6. Kiliki Feso'ota'i. A uma ona faʻamauina le fesoʻotaʻiga, Fesoʻotaʻi suiga i le Disconnect.
  7. Kiliki Su'esu'e e filifili ai le mea muamuaample ata fa'atinoina file saunia ma le mamanu files (SF2_CodeShadowing_LPDDR_DF/Sample Fa'aoga Ata/HWBootEngine_method/sample_image_LPDDR.bin).
    Fa'aaliga: Ina ia fa'atupuina le talone ata talosaga file, va'ai i le “Fa'aopoopoga: Fausiaina o Talone Fa'atino File” i le itulau e 24.
  8. Filifili Hardware Boot Engine filifiliga i Code Shadowing Method.
  9. Filifili le Polokalame SPI Flash filifiliga mai Filifiliga lisi.
  10. Kiliki Amata, e pei ona faʻaalia i le Ata 15 e faʻapipiʻi ai le ata faʻatinoina ile SPI flash.

Ata 15 Amataina le Demo

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-15

Ole vaega ole fa'amafanafanaga ile GUI o lo'o fa'aalia ai fe'au debug ma le tulaga ole SPI flash writing, e pei ona fa'aalia ile Ata 16.
Ata 16 Fa'amomoli Uta

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-16

  1. A mae'a fa'apolokalame lelei le moli SPI, sui le sui DIP SW5-1 ile tulaga OFF. O lenei filifiliga e faʻaosoina ai le Cortex-M3 processor mai le DDR memory.
  2. Oomi le SW6 e toe setiina le masini SmartFusion2. E kopiina e le afi afi le ata talosaga mai le SPI flash i le DDR memory ma faʻasaʻo le toe setiina i Cortex-M3, lea e faʻaulu ai le ata talosaga mai le DDR memory. Afai o le ata ua tuuina atu “sample_image_LPDDR.bin” ua utaina i le moli SPI, o le faʻamafanafanaga serial o loʻo faʻaalia ai le feʻau faʻafeiloaʻi, faʻafesoʻotaʻi faʻalavelave (oomi SW2 poʻo SW3) ma savali faʻalavelave taimi, e pei ona faʻaalia i le Ata 17 ma o loʻo faʻaalia se mamanu LED i le LED1 i le LED8 i le SmartFusion2 Pusa Iloiloga Puipuiga.

Ata 17 Fa'agaoioi le Ata Fa'atatauga Fa'atatau mai le DDR3 Memory

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-17

Fa'ai'uga
Ua e faʻaaogaina ma le manuia le SmartFusion2 SoC FPGA faʻatasi ai ma le faʻaogaina o le code mai le SPI Flash i le LPDDR memory.O lenei faʻataʻitaʻiga o loʻo faʻaalia ai le gafatia o le SmartFusion2 masini e faʻafesoʻotaʻi ma le DDR memory ma faʻatautaia le ata faʻatinoina mai le DDR memory e ala i le paolo code mai le SPI flash memory device. . O loʻo faʻaalia ai foʻi ni auala se lua o le faʻaogaina o le faʻaogaina o tulafono ile SmartFusion2 masini.

Fa'aopoopo: LPDDR Configurations

Ata 18 Fa'atonu Fa'atonu DDR Lautele

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-18

Ata 19 DDR Memory Initialization Seti

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-19

Ata 20 DDR Fa'atonu Taimi Fa'amanatu

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-20

Fa'aopoopo: Fausiaina Talone Fa'atino File

O le talone fa'atino file e mana'omia le fa'apolokalameina o le SPI flash mo le fa'agaioia o le fa'ata'ita'iga fa'aata. Le fa'atupuina o le talone fa'atino file mai le “sample_image_LPDDR” SoftConsole, fai laasaga nei:

  1. Fausia le Poloketi SoftConsole fa'atasi ai ma le feso'ota'iga script production-fa'atino-i-nofoaga-externalDDR.
  2. Faʻaopoopo le auala faʻapipiʻi SoftConsole, mo faʻataʻitaʻigaample,
    C:\Microsemi\Libero_v11.7\SoftConsole\Sourcery-G++\bin, i le 'Environment Variables', e pei ona fa'aalia i le Ata 21.

Ata 21 Fa'aopoopoina le Ala Fa'apipi'i SoftConsole

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-21

  1. Kiliki faalua le vaega file Bin-File-Generator.bat o lo'o maua ile: SoftConsole/CodeShadowing_LPDDR_MSS_CM3/Sample_image_LPDDR faila, e pei ona faʻaalia i le Ata 22.

Ata 22 Fa'aopoopoina le Ala Fa'apipi'i SoftConsole

Microsemi-DG0669-SmartFusion2-Code-Shadowing-mai-SPI-Flash-i-LPDDR-Memory-FIG-22

  • O le Bin-File-Generator faia sample_image_LPDDR.bin file

Toe Iloilo Tala'aga

O le siata o lo'o i lalo o lo'o fa'aalia ai suiga taua na faia i lenei pepa mo toe iloiloga ta'itasi.

Toe Iloiloga Suiga
Toe Iloiloga 2

(Aperila 2016)

 Fa'afou le pepa mo Libero SoC v11.7 fa'amatu'u polokalama (SAR 78258).
Toe Iloiloga 1

(Tesema 2015)

 Fa'asalalauga muamua.

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Pepa / Punaoa

Microsemi DG0669 SmartFusion2 Faʻailoga Faʻailoga mai le SPI Flash i le LPDDR Memory [pdf] Taiala mo Tagata Fa'aoga
DG0669 SmartFusion2 Code Fa'aata mai le SPI Flash i le LPDDR Memory, DG0669, SmartFusion2 Code Fa'aali mai le SPI Flash i le LPDDR Memory, SPI Flash i le LPDDR Memory

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