AN 824 FPGA SDK bakeng sa Boto ea OpenCL
Support Package Floorplan
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 Intel® FPGA SDK bakeng sa OpenCL ™ Board Support Package Floorplan Tataiso ea Ntlafatso ea Boto
Intel/® FPGA SDK bakeng sa OpenCL™ Board Support Package (BSP) Floorplan Optimization Guide e fana ka litataiso tsa moralo oa fatše bakeng sa OpenCL) BSP. E boetse e fana ka tataiso ea hore na u ka fumana peo ea motheo joang ka lebelo le holimo la ho sebetsa le ho lekola katleho ea ts'ebeliso ea lisebelisoa tsa BSP.
Tokomane ena e nka hore u tloaelane le mehopolo ea OpenCL(2) joalo ka ha e hlalositsoe ho OpenCL Specification mofuta 1.0 ke Khronos Group.

Phallo ea Kopano ea OpenCL BSP
OpenCL BSP e ts'ehetsa mefuta e latelang ea phallo ea pokello:

• Flat compile [-bsp-flow flat]: E etsa pokello e bataletseng ea moralo oohle (BSP hammoho le lisebelisoa tse hlahisoang ke kernel).
• Base compile [-bsp-flow base]: E etsa pokello ea motheo ka ho sebelisa lithibelo tsa LogicLock ho tsoa ho base.qsf file. Sepheo sa oache ea kernel se phutholohile e le hore lisebelisoa tsa BSP li be le bolokolohi bo eketsehileng ba ho finyella nako. Sebaka sa polokelo ea base.qar se etselitsoe ho boloka lisebelisoa tsa BSP, e leng sebaka se tsitsitseng.
• Kopanya thepa [ ]: E khutlisetsa nako e koetsoeng sebakeng se tsitsitseng ho tloha ho base.qar database mme e bokella feela lisebelisoa tse entsoeng ke kernel. E boetse e eketsa sepheo sa oache ea kernel ho fumana lebelo le holimo la ho sebetsa la kernel (fmax).

OpenCL BSP Floorplan Partition
OpenCL BSP floorplan e arotsoe haholo ka libaka tse peli tse latelang:

• Sebaka se tsitsitseng: E ​​emela sebaka se nang le lisebelisoa tse amanang le BSP tse lulang li tsitsitse. Nako e koetsoe sebakeng sena nakong ea pokello ea motheo. Ka kakaretso, sepheo ke ho fokotsa lisebelisoa tsa chip tse sebelisoang ke sebaka sena ho koala nako.
• Sebaka sa Kernel: E emela sebaka sa "reconfiguration" sa karolo (PR) se boloketsoeng mojule oa freeze_wrapper_inst|kernel_system_inst, o nang le kernel. Ka kakaretso, sepheo ke ho boloka lisebelisoa tsa chip ho isa tekanyong e phahameng bakeng sa sebaka sena.

1. Intel FPGA SDK bakeng sa OpenCL e ipapisitse le Tlhaloso ea Khronos e phatlalalitsoeng, 'me e fetile Ts'ebetso ea Teko ea Khronos Conformance. Boemo ba hona joale ba ho lumellana bo ka fumanoa ho www.khronos.org/conformance.
2. OpenCL le logo ya OpenCL ke matshwao a kgwebo a Apple Inc. mme a sebediswa ka tumello ya Khronos Group™.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba beha litaelo tsa lihlahisoa kapa lits'ebeletso.
*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

Litaelo tsa OpenCL BSP Floorplanning

• Qala ka pokello e bataletseng ho utloisisa hore na likarolo tsohle tsa mantlha tsa BSP li beoa kae ka tlhaho (haholo-holo li-block tsa IP tse nang le likhokahano tsa I/O joalo ka PCIe kapa DDR). Ha o ntse o rala BSP, o kanna oa tlameha ho nahana ka ho theha lipeipi tsa stage lipakeng tsa li-IP ho koala nako. O lokela ho qala ka ho fiela ka mokhoa o bataletseng oa peo ho bona litsela tse hlolehang khafetsa, ebe u leka ho li lokisa.
  Keletso: - Sekhahla se setle sa ho koala nako ha ho fiela peo e kopaneng e tla ba le menyetla e mengata ea ho koala nako ea pokello ea lipeo.
  - Haeba u bona liphoso tse sa fetoheng ho mm_interconnect* (karolo e kenyellelitsoeng ke Qsys), bula Sistimi ka Qsys Interconnect viewer le ho hlokomela ho rarahana ha khokahano e hlolehang. U ka eketsa li-flipflops tsa pipelining ho viewho ntlafatsa nako. Haeba u ntse u sa khone ho rarolla bothata, u kanna ua tlameha ho qhaqha mm_interconnect* tsela ea bohlokoa ka ho eketsa marokho a lipeipi tsa Avalon.
• Nakong ea pokello ea motheo, qala ka LogicLock sebakeng sa kernel se nang le freeze_wrapper_inst|kernel_system_inst. Ha ho na lithibelo tse ling, Intel Quartus Prime e ka beha lisebelisoa tsa BSP ka bolokolohi sebakeng se setseng sa chip. Sebelisa komporo e bataletseng le chip planner ho tseba boholo le sebaka sa thepa ea BSP, joalo ka PCIe le DDR. Ebe u boloka sebaka sa kernel ka ho sebelisa LogicLock ha u ntse u qoba libaka tse kopaneng tsa thepa ea BSP.
  Keletso: Haeba lelapa la chip le sebelisitsoeng le tšoana le sethala sa litšupiso 'me haeba likarolo tsa BSP li tšoana, ho ka ba kapele ho qala ka libaka tsa LogicLock bakeng sa freeze_wrapper_inst|kernel_system_inst e rometsoeng ka referense ea OpenCL BSP le ho rarolla liphoso.
• U ka eketsa likarolo tse latelang ho BSP ea hau:
  - Libanka tsa memori: Haeba o eketsa libanka tsa memori tse ling, o lokela ho tseba sebaka sa banka sa I/O kaha o kanna oa hloka ho eketsa marokho a lipeipi ho fihlela nako.
  - Liteishene tsa I/O: O ka eketsa liteishene tsa I/O joalo ka video, Ethernet, kapa segokanyimmediamentsi sa seriale. Haeba o eketsa liteishene tsa I/O, o lokela ho tseba sebaka sa banka sa I/O kaha o kanna oa hloka ho sebelisa libaka tse ncha tsa LogicLock bakeng sa ho kenya lipeipi haeba ho le thata ho koala nako.
  Keletso: Haeba o hloka ho kenya marokho a liphaephe (mohlalaample, ka lebaka la tieho e kholo ea litsela e bakang ho hloleha ha nako), joale nahana ka sebaka sa ho tsamaea ho tloha mohloling ho ea moo u eang teng ka har'a chip 'me u lokolle sebaka se itseng se boloketsoeng sebaka sa kernel.
• Latela litataiso tsena tse akaretsang ha u boloka libaka tsa LogicLock bakeng sa kernel:
  - Leka ho beha litšiea tsohle tsa DSP ho kernel_system ntle le haeba BSP e batlile.
  - Leka ho boloka lisebelisoa tse ling bakeng sa kernel_system.
  - Leka ho boloka palo ea li-notch sebakeng sa kernel bonyane.
  Setšoantšo se latelang se bontša notch e kentsoeng ho beha borokho ba lipeipi lipakeng tsa PCIe le DDR bank.

Setšoantšo sa 1. OpenCL BSP Floorplan bakeng sa Intel Arria® 10 GX ho Phatlalatso ea 17.0

Litaelo bakeng sa Maqhubu a Mangata a Ts'ebetso
Maqhubu a phahameng a ts'ebetso (fmax) a fihletsoeng ke li-kernels haholo a ipapisitse le lebelo la FPGA kaha boholo ba li-IP li tlameha ho se li ntlafalitsoe. Leha ho le joalo, ho ka ba le tahlehelo e itseng ea fmax ho latela BSP floorplan. Bakeng sa mohlalaample, hangata palo ea likheo sebakeng sa kernel ea BSP e ama kernel fmax.
Joalo ka ha ho bonts'itsoe setšoantšong se latelang, ho fumana peo e ntle ka ho fetisisa e fanang ka kakaretso e ntle ka ho fetisisa ea fmax:

1. Hlakola peō mokhahlelong oa motheo ho e-na le ho khetha peo ea pele e lumellanang le nako.
2. Etsa pokello ea lintho tse tsoang kantle ho naha (ka ho sebelisa lithollo tse 'maloa ho tsoa ho example designs) holim'a lipeo tsohle tse fetang.
3. Bala kakaretso ea fmax bakeng sa lipeo tsohle tsa motheo.
4. Khetha peo ea motheo e hlahisang palo e phahameng ka ho fetisisa ea fmax.
   Peo ea motheo e nang le karolelano e ntle ka ho fetisisa ea fmax ke mokhethoa ea molemo oa ho lokolloa ka BSP. Haeba u nka qeto ea ho latela mokhoa o fapaneng le mehato e khothaletsoang, u ka bona phapang ea 5-10% ho fmax ea ts'ebetso ea ho kopanya kernel.

Setšoantšo sa 2. Ho Khetholla Peo e Molemohali ea Motheo

• Ho utloisisa hore na kernel e ka matha kapele hakae ntle le lithibelo tsa floorplan:
  1. Etsa pokello e bataletseng ea kernel 'me u shebe fmax.
  2. Etsa pokello ea thepa e tsoang ho kernel e le 'ngoe 'me u shebe fmax.
  3. Bapisa liphetho tsa fmax.
  Ka lebaka la lithibelo tsa floorplan, import compile fmax e lula e le tlase ho feta flat compile fmax. Ho qoba lerata la peo, bokella kernel le peo ea mantlha 'me u nahane ka karolelano ea fmax ha u bapisa liphetho tsa fmax.
• Le ka mohla u se ke ua bapisa kernel fmax ho tsoa pokellong ea mantlha le pokello ea thepa e tsoang kantle. Lipheo tsa oache ea Kernel lia phutholoha nakong ea ho bokelloa ha motheo, ka hona, ha ho mohla u tla fumana litholoana tse ntle.
• Ela hloko tsela ea bohlokoa ea oache ea kernel ha u ntse u bokella kapa u kopanya thepa. Haeba tsela ea bohlokoa e tlohang kernel ho ea sebakeng se tsitsitseng ho floorplan, fetola floorplan kapa tsamaisa peo e 'maloa ho qoba tsela ena ea bohlokoa.

Litaelo tsa ho Lekola Bokhoni ba Tšebeliso ea Mehloli ea BSP

Ho ba le liperesente tse phahameng tsa tšebeliso ea lisebelisoatage, ho ntlafatsa ts'ebeliso ea sebaka sebakeng se tsitsitseng sa BSP ea hau. Liphesente tse phahameng tsa tšebeliso ea lisebelisoatage boetse e bolela hore lisebelisoa tse ngata li teng bakeng sa sebaka sa kernel.
Latela mehato e ka tlase ho bala liperesente tsa tšebeliso ea lisebelisoatagea BSP ea hau:

1. Fumana boleng ba lisebelisoa tsohle tse ho FPGA ho tsoa holimo.fit.rpt kapa base.fit.rpt e fumanehang tlasa karolo ea Partition Statistics tlalehong ea Fitter.
2. Tlosa boleng ba "freeze_wrapper_inst|kernel_system_inst" (kernel region).

Keletso:
Tsepamisa maikutlo haholo holim'a boleng ba adaptive logic module (ALM) ho feta boleng ba lisebelisoa tse ling. Etsa bonnete ba hore karolo ea tšebeliso ea lisebelisoatage bakeng sa ALM e haufi le OpenCL referense BSP. Palo e phahameng haholotage bakeng sa ALM e ka lebisa ho tšubuhlellano, e ka eketsang nako ea ho bokella le ho hlahisa tšubuhlellano ea litsela ka har'a lithollo tse rarahaneng. Leha ho le joalo, u ka lula u eketsa kapa ua fokotsa sebaka sa sebaka se tsitsitseng, 'me u hlokomele nako ea ho bokella le fmax.
Tafole e latelang e bonts'a tšebeliso ea lisebelisoa tsa OpenCL BSP ea lisebelisoa tsa Arria ® 10 GX tokollong ea 17.0.

Lethathamo la 1.
Tšebeliso ea OpenCL BSP ea lisebelisoa tsa IntelArria 10 GX tokollong ea 17.0

	Kakaretso e Fumanehang	E boloketsoe Kernel	E fumaneha bakeng sa BSP	E sebelisoa ke BSP	0/0
ALM	427200	393800	33400	23818.	71.%
Ngoliso	1708800	1575200	133600	38913	29.%
M2OK	2713	2534	179	134	75.%
DSP	1518	1518	0	0	N/A

Hlokomela hore floorplanning e etsoa ka tsela eo sebaka se tsitsitseng se ke keng sa ba le li-block tsa DSP.

Nalane ea Phetoho ea Litokomane

Lethathamo la 2.
Nalane ea Tokomane ea Tokomane ea Intel FPGA SDK bakeng sa Tataiso ea Ntlafatso ea Boto ea OpenCL Board Package Floorplan Optimization.

Letsatsi	Phetolelo	Liphetoho
Phato-17		Tokollo ea pele.

Online Version
Romella Maikutlo
ID: 683312
AN-824
Phetolelo: 2017.08.08
AN 824: Intel® FPGA SDK bakeng sa OpenCL™ Board
Tataiso ea Ts'ehetso ea Phakete ea Floorplan

Litokomane / Lisebelisoa

intel AN 824 FPGA SDK bakeng sa OpenCL Board Support Package Floorplan [pdf] Bukana ea Mosebelisi AN 824 FPGA SDK bakeng sa OpenCL Board Support Package Floorplan, AN 824, FPGA SDK bakeng sa OpenCL Board Support Package Floorplan, OpenCL Board Support Package Floorplan, Board Support Package Floorplan, Support Package Floorplan, Package Floorplan,

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