eSRAM Intel FPGA IP
Cov ntaub ntawv khoom
Cov khoom yog Intel FPGA IP, uas yog sib xws nrog Intel Quartus Prime Design Suite software. Tus IP muaj ntau qhov sib txawv uas phim cov software versions txog v19.1. Pib los ntawm software version 19.2, lub tswv yim tshiab versioning yog qhia rau Intel FPGA IP.
IP versions yog raws li nram no:
| Version | Hnub tim | Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
|---|---|---|---|---|
| v20.1.0 ua | 2022.09.26 | 22.3 | Enabled Intel AgilexTM eSRAM IP system tivthaiv kev sib txuas kev txhawb nqa hauv Platform Designer tool. |
Daim ntawv pov thawj ISO 9001: 2015 |
| v20.0.0 ua | 2021.10.04 | 21.3 | Hloov tshiab ch{0-7}_ecc_dec_eccmode thiab ch{0-7}_ecc_enc_ecmcode parameters rau ECC_DISABLED rau cov chaw nres nkoj tsis siv. |
Yuav tsum tau hloov kho IP kom tau txais cov qauv tsim dhau los ua ke nrog Intel Quartus Prime Pro Edition software version 21.3. |
| v19.2.1 ua | 2021.06.29 | 21.2 | Kho qhov tuav ua txhaum cai los ntawm kev ntxiv (* altera_attribute = -name HYPER_REGISTER_DELAY_CHAIN 100*) rau eSRAM Intel Agilex FPGA IP. |
Kev hloov pauv yog xaiv tau. Yuav tsum hloov kho IP yog tias koj tus IP tsis tuaj yeem ua tau raws li qhov kev ua tau zoo tshaj plaws vim yog tuav ua txhaum cai. |
| v19.2.0 ua | 2020.12.14 | 19.4 | Tshem tawm lub dynamic ECC encoder thiab decoder - bypass feature. |
N/A |
| v19.1.1 ua | 2019.07.01 | 19.2 | Thawj tso tawm rau Intel Agilex li. | N/A |
Yog tias daim ntawv tso tawm tsis muaj rau qhov tshwj xeeb IP version, nws txhais tau tias tsis muaj kev hloov pauv hauv qhov version ntawd.
Nco tseg: Intel FPGA IP version (XYZ) tus lej tuaj yeem hloov pauv nrog txhua Intel Quartus Prime software version.
Cov lus qhia siv khoom
Txhawm rau siv Intel FPGA IP, ua raws li cov kauj ruam no:
- Xyuas kom koj muaj qhov sib xws Intel Quartus Prime Design Suite software nruab rau hauv koj lub cev.
- Rub tawm qhov sib raug Intel FPGA IP version uas phim koj cov software version.
- Extract tus IP downloaded files mus rau qhov chaw tsim nyog ntawm koj lub computer.
- Qhib Intel Quartus Prime software thiab tsim ib qhov project tshiab lossis qhib qhov project uas twb muaj lawm.
- Hauv qhov project nqis lossis IP catalog, nrhiav thiab ntxiv Intel FPGA IP rau koj qhov project.
- Configure IP parameter raws li koj xav tau.
- Txuas tus IP rau lwm cov khoom lossis cov qauv hauv koj tus qauv siv lub platform Designer cuab yeej.
- Xyuas kom tseeb tias qhov kev hloov kho IP tsim nyog tau ua yog tias tau teev tseg hauv cov ntaub ntawv khoom.
- Sau thiab txheeb xyuas koj tus qauv siv Intel Quartus Prime software.
- Ua raws li cov kauj ruam ntxiv raws li koj qhov kev xav tau tsim thiab lub hom phiaj ntawm qhov project.
eSRAM Intel® Agilex™ FPGA IP
Tso Lus Ceeb Toom
Yog tias daim ntawv tso tawm tsis muaj rau qhov tshwj xeeb IP version, IP tsis muaj kev hloov pauv hauv qhov version ntawd. Rau cov ntaub ntawv ntawm IP hloov tshiab tshaj tawm txog v18.1, xa mus rau Intel® Quartus® Prime Design Suite Update Release Notes.
Intel FPGA IP versions phim Intel Quartus Prime Design Suite software versions txog v19.1. Pib hauv Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP muaj cov txheej txheem tshiab.
Intel FPGA IP version (XYZ) tus lej tuaj yeem hloov pauv nrog txhua Intel Quartus Prime software version.
- X qhia txog kev hloov kho loj ntawm IP. Yog tias koj hloov kho Intel Quartus Prime software, koj yuav tsum rov tsim dua tus IP.
- Y qhia tias tus IP suav nrog cov yam ntxwv tshiab. Rov tsim koj tus IP kom suav nrog cov yam ntxwv tshiab no.
- Z qhia tias IP suav nrog kev hloov pauv me me. Rov tsim koj tus IP kom suav nrog cov kev hloov pauv no.
Cov ntaub ntawv ntsig txog
- Intel Quartus Prime Design Suite Hloov Kho Cov Lus Qhia
- Intel Agilex™ Embedded Memory User Guide
- Errata rau eSRAM Intel Agilex™ FPGA IP hauv Kev Paub Txog
eSRAM Intel Agilex™ FPGA IP v20.1.0
Table 1. v20.1.0 2022.09.26
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 22.3 | Enabled Intel Agilex™ eSRAM IP system tivthaiv kev sib txuas txhawb nqa hauv Platform Designer cuab yeej. | Kev hloov kho IP yog xaiv tau hauv Intel Quartus Prime Pro Edition software version 22.3.
|
eSRAM Intel Agilex FPGA IP v20.0.0
Table 2. v20.0.0 2021.10.04
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 21.3 | Hloov kho ch{0-7}_ecc_dec_eccmode thiab ch{0-7}_ecc_enc_eccmode tsis mus rau ECC_DISABLED rau cov chaw nres nkoj tsis siv. | Kev hloov kho IP yuav tsum tau kom tau txais cov qauv tsim dhau los nrog Intel Quartus Prime Pro Edition software version 21.3. |
Table 3. v19.2.1 2021.06.29
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 21.2 | Kho qhov tuav ua txhaum cai los ntawm kev ntxiv (* altera_attribute = “-name HYPER_REGISTER_DELAY_CHAIN 100″*) rau eSRAM Intel Agilex FPGA IP. | Kev hloov pauv yog xaiv tau. Koj yuav tsum ua qhov hloov kho IP yog tias koj tus IP tsis tuaj yeem ua tau raws li qhov kev ua tau zoo tshaj plaws vim yog kev ua txhaum cai. |
eSRAM Intel Agilex FPGA IP v19.2.0
Table 4. v19.2.0 2020.12.14
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 19.4 | Tshem tawm lub dynamic ECC encoder thiab decoder bypass feature. | — |
eSRAM Intel Agilex FPGA IP v19.1.1
Table 5. v19.1.1 2019.07.01
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 19.2 | Thawj tso tawm rau Intel Agilex li. | — |
eSRAM Intel FPGA IP Release Notes (Intel Stratix® 10 Devices)
Yog tias daim ntawv tso tawm tsis muaj rau qhov tshwj xeeb IP version, IP tsis muaj kev hloov pauv hauv qhov version ntawd. Rau cov ntaub ntawv ntawm IP hloov tshiab tso tawm mus txog v18.1, xa mus rau Intel Quartus Prime Design Suite Update Release Notes.
Intel FPGA IP versions phim Intel Quartus Prime Design Suite software versions txog v19.1. Pib hauv Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP muaj cov txheej txheem tshiab.
Intel FPGA IP version (XYZ) tus lej tuaj yeem hloov pauv nrog txhua Intel Quartus Prime software version. Kev hloov hauv:
- X qhia txog kev hloov kho loj ntawm IP. Yog tias koj hloov kho Intel Quartus Prime software, koj yuav tsum rov tsim dua tus IP.
- Y qhia tias tus IP suav nrog cov yam ntxwv tshiab. Rov tsim koj tus IP kom suav nrog cov yam ntxwv tshiab no.
- Z qhia tias IP suav nrog kev hloov pauv me me. Rov tsim koj tus IP kom suav nrog cov kev hloov pauv no.
Cov ntaub ntawv ntsig txog
- Intel Quartus Prime Design Suite Hloov Kho Cov Lus Qhia
- Intel Stratix® 10 Embedded Memory User Guide
- Errata rau eSRAM Intel FPGA IP hauv Kev Paub Txog
eSRAM Intel FPGA IP v19.2.0
Table 6. v19.2.0 2022.09.26
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 22.3 | Enabled Intel Stratix® 10 eSRAM IP system tivthaiv kev sib txuas txhawb nqa hauv Platform Designer cuab yeej. | Kev hloov kho IP yog xaiv tau hauv Intel Quartus Prime Pro Edition software version 22.3.
|
eSRAM Intel FPGA IP v19.1.5
Table 7. v19.1.5 2020.10.12
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 20.3 | Hloov kho cov lus piav qhia rau Qhib Hom Fais Fab Tsawg hauv eSRAM Intel FPGA IP parameter editor. | — |
eSRAM Intel FPGA IP v19.1.4
Table 8. v19.1.4 2020.08.03
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 20.2 | Renamed I/O PLL filenpe kom zam cov lus ceeb toom los ntawm IOPLL file.
Yog tias ob lub eSRAMs muaj tib qhov PLL tsis sib xws (PLL siv moos zaus thiab PLL xav tau moos zaus), cov lus ceeb toom tuaj yeem tsis quav ntsej. Yog tias ob lub eSRAMs muaj qhov sib txawv PLL tsis sib xws, tom qab muab tso ua ke lawv yuav raug teeb tsa rau tib PLL zaus coj los ntawm ib qho ntawm eSRAM Intel FPGA IP tsis. Xa mus rau Quartus Fitter qhia ➤ Plan Stage ➤ Cov ntsiab lus ntawm kev siv PLL los soj ntsuam cov kev siv eSRAM IOPLL zaus. IP hloov tshiab yog xav tau thaum PLL parameter rau ob qho tib si eSRAM txawv. |
— |
eSRAM Intel FPGA IP v19.1.3
Table 9. v19.1.3 2019.10.11
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 19.3 | Hloov kho cov lus piav qhia rau PLL Siv Lub Sij Hawm Ntau hauv eSRAM Intel FPGA IP parameter editor. | — |
eSRAM Intel FPGA IP v18.1
Table 10. v18.1 2018.10.03
| Intel Quartus Prime Version | Kev piav qhia | Kev cuam tshuam |
| 18.1 | Tshem tawm HIPI rau npe rau iopl_lock2core_reg. | Koj tuaj yeem hloov kho koj tus IP core. |
eSRAM Intel FPGA IP v18.0
Table 11. v 18.0 May 2018
| Kev piav qhia | Kev cuam tshuam |
| Renamed Native eSRAM IP core rau eSRAM Intel FPGA IP raws li Intel rebranding. | — |
Ntxiv lub teeb liab interface tshiab:
eSRAM IOPLL xauv xwm txheej. |
— |
Cov ntaub ntawv ntsig txog
- Taw qhia rau Intel FPGA IP Cores
- Intel Stratix 10 Embedded Memory User Guide
- Errata rau lwm tus IP cores hauv Kev Paub Txog Kev Paub
Native eSRAM IP Core v17.1
Table 12. v 17.1 Kaum Ib Hlis 2017
| Kev piav qhia | Kev cuam tshuam |
| Kev tso tawm thawj zaug. Cov tub ntxhais IP no tsuas yog muaj nyob hauv Intel Stratix 10 cov khoom siv. | — |
Cov ntaub ntawv ntsig txog
- Taw qhia rau Intel FPGA IP Cores
- Intel Stratix 10 Embedded Memory User Guide
- Errata rau lwm tus IP cores hauv Kev Paub Txog Kev Paub
Intel Stratix 10 Embedded Memory User Guide Archives
Rau qhov tseeb thiab yav dhau los versions ntawm cov neeg siv phau ntawv qhia no, saib Intel® Stratix® 10 Embedded Memory User Guide. Yog tias tus IP lossis software version tsis tau teev tseg, cov lus qhia siv rau tus IP yav dhau los lossis software version siv.
eSRAM Intel® FPGA IP Tso Lus Sau
Cov ntaub ntawv / Cov ntaub ntawv
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Intel eSRAM Intel FPGA IP [ua pdf] Cov neeg siv phau ntawv qhia eSRAM Intel FPGA IP, Intel FPGA IP, FPGA IP, IP |
