ʻIkepili huna
1 eSRAM Intel FPGA IP
2 ʻIke Huahana
3 Nā ʻōlelo hoʻohana huahana
4 eSRAM Intel® Agilex™ FPGA IP
5 eSRAM Intel FPGA IP Release Notes (Intel Stratix® 10 Devices)
6 Palapala / Punawai
6.1 Nā kuhikuhi
7 Nā leka pili

eSRAM Intel FPGA IP Mea Hoʻohana Kiʻi Hōʻikeʻike: ʻAʻole file koho Hoʻohou Post Hoʻohui MediaVisualText Poʻomanaʻo 3 H3 Hoʻopau i ke kamaʻilio E hoʻouka i nā hana hoʻoili filesMedia Library Kānā i ka mediaKāna ma ke ʻano Nā mea pāʻoihana a pau kānana ma ka lā a pau Huli Papa inoa Media E hōʻike ana i 81 o 5375076 mau mea media E hoʻouka hou aku NĀ HOPE eSRAM-logo-image-1.jpg Iulai 22, 2023 13 KB 357 by 74 pixels Hoʻoponopono kiʻi Holoi mau loa. Alt Text E aʻo pehea e wehewehe ai i ke kumu o ke kiʻi(wehe ʻia ma ka ʻaoʻao hou). E waiho haʻahaʻa inā he mea hoʻonani maʻemaʻe ke kiʻi. Title eSRAM-logo-image Caption Description File URL: https://manuals.plus/wp-content/uploads/2023/07/eSRAM-logo-image-1.jpg Kope URL i ka papa ʻokiʻoki E HOʻOPIʻI HOʻOPIʻI SETTINGS Alignment Center Link i ʻAʻohe Nui Nui piha – 357 × 74 Nā hana media i koho ʻia 1 mea i koho ʻia Holoi i loko o ka pou No file koho ʻia

eSRAM Intel FPGA IP

eSRAM Intel FPGA IP Mea Hoʻohana Kiʻi Hōʻikeʻike: ʻAʻole file koho ʻia Hoʻohou Post Hoʻohui MediaVisualText Poʻomanaʻo 4 DIV »H4 Hoʻopau i ke kamaʻilio Hoʻouka i nā hana hoʻoili filesMedia Library Kānā i ka mediaKāna ma ke ʻano Nā mea media a pau kānana ma ka lā a pau Huli Papa inoa Media Hōʻike ʻia 82 o 5375077 mau mea media E hoʻouka hou aku NĀ MEA HUI eSRAM-Intel-FPGA-IP-produt-image.jpg Iulai 22, 2023 35 KB 442 by 328 pixels Hoʻoponopono Kiʻi Holoi mau loa Alt Text E aʻo pehea e wehewehe ai i ke kumu o ke kiʻi(wehe ʻia ma kahi ʻaoʻao hou). E waiho haʻahaʻa inā he mea hoʻonani maʻemaʻe ke kiʻi. Title eSRAM-Intel-FPGA-IP-produt-image Caption Description File URL: https://manuals.plus/wp-content/uploads/2023/07/eSRAM-Intel-FPGA-IP-produt-image.jpg Kope URL i ka papa ʻokiʻoki E HOʻOPIʻI HOʻOPIʻI SETTINGS Alignment Center Link i ʻAʻohe Nui Nui piha – 442 × 328 Nā hana media i koho ʻia 1 mea i koho ʻia Holoi i loko o ka pou No file koho ʻia

ʻIke Huahana

ʻO ka huahana ka Intel FPGA IP, i kūpono me ka polokalamu Intel Quartus Prime Design Suite. Loaʻa i ka IP nā mana like ʻole e pili ana i nā mana polokalamu a hiki i ka v19.1. E hoʻomaka ana mai ka polokalamu polokalamu 19.2, ua hoʻokomo ʻia kahi hoʻolālā hou no ka Intel FPGA IP.

ʻO nā mana IP penei:

Manao Lā ʻO Intel Quartus Prime Version wehewehe Ka hopena
v20.1.0 2022.09.26 22.3 Hoʻohana ʻia ka pilina ʻōnaehana Intel AgilexTM eSRAM IP
kākoʻo ma ka mea hana hoʻolālā Platform.		 ISO 9001:2015 Kakau
v20.0.0 2021.10.04 21.3 Hoʻohou i ka ch{0-7}_ecc_dec_eccmode a me ch{0-7}_ecc_enc_eccmode
nā ʻāpana i ECC_DISABLED no nā awa i hoʻohana ʻole ʻia.		 Pono ka hoʻonui ʻana i ka IP no ka loaʻa ʻana o ka hōʻuluʻulu pass design
me ka polokalamu polokalamu Intel Quartus Prime Pro Edition 21.3.
v19.2.1 2021.06.29 21.2 Hoʻopaʻa i ka uhaki paʻa ma ka hoʻohui ʻana (* altera_attribute = -name
HYPER_REGISTER_DELAY_CHAIN ​​100*) i ka eSRAM Intel Agilex FPGA
IP.		 He koho ka hoʻololi. Pono ʻia kahi hoʻonui IP inā ʻo kāu IP
ʻaʻole hiki ke hoʻokō i nā kikoʻī hana kiʻekiʻe ma muli o kahi paʻa
uhaki.
v19.2.0 2020.12.14 19.4 Wehe ia i ka ECC encoder a me ka decoder — bypass
hiʻona.		 N/A
v19.1.1 2019.07.01 19.2 Hoʻokuʻu mua no nā polokalamu Intel Agilex. N/A

Inā ʻaʻole i loaʻa kahi leka hoʻokuʻu no kahi mana IP kikoʻī, ʻo ia ka mea ʻaʻohe loli i kēlā mana.

Nānā: Hiki ke loli ka helu Intel FPGA IP (XYZ) me kēlā me kēia polokalamu polokalamu Intel Quartus Prime.

Nā ʻōlelo hoʻohana huahana

No ka hoʻohana ʻana i ka Intel FPGA IP, e hahai i kēia mau ʻanuʻu:

  1. E hōʻoia i loaʻa iā ʻoe ka polokalamu Intel Quartus Prime Design Suite i hoʻokomo ʻia ma kāu ʻōnaehana.
  2. Hoʻoiho i ka mana Intel FPGA IP e pili ana i kāu polokalamu polokalamu.
  3. Wehe i ka IP i hoʻoiho ʻia files i kahi kūpono ma kāu kamepiula.
  4. E wehe i ka polokalamu Intel Quartus Prime a hana i kahi papahana hou a wehe paha i kahi papahana e kū nei.
  5. Ma nā hoʻonohonoho papahana a i ʻole ka helu IP, e ʻimi a hoʻohui i ka Intel FPGA IP i kāu papahana.
  6. E hoʻonohonoho i nā palena IP e like me kāu mau koi.
  7. Hoʻohui i ka IP i nā ʻāpana ʻē aʻe a i ʻole modules i kāu hoʻolālā me ka hoʻohana ʻana i ka mea hana Platform Designer.
  8. E hōʻoia i ka hana ʻana i nā hoʻomaikaʻi IP pono inā i kuhikuhi ʻia i ka ʻike huahana.
  9. E hōʻuluʻulu a hōʻoia i kāu hoʻolālā me ka polokalamu Intel Quartus Prime.
  10. E hoʻomau i nā hana hou aku e like me kāu mau koi hoʻolālā a me nā pahuhopu papahana.

eSRAM Intel® Agilex™ FPGA IP

Hoʻokuʻu ʻŌlelo
Inā ʻaʻole i loaʻa kahi leka hoʻokuʻu no kahi mana IP kikoʻī, ʻaʻohe loli o ka IP i kēlā mana. No ka ʻike e pili ana i ka hoʻopuka IP a hiki i ka v18.1, e nānā i ka Intel® Quartus® Prime Design Suite Update Release Notes.
Kūlike nā mana Intel FPGA IP me nā polokalamu polokalamu Intel Quartus Prime Design Suite a hiki i ka v19.1. E hoʻomaka ana ma Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP he polokalamu hoʻololi hou.
Hiki ke loli ka helu Intel FPGA IP (XYZ) me kēlā me kēia polokalamu polokalamu Intel Quartus Prime.

He hoʻololi i:
  • Hōʻike ʻo X i kahi hoʻoponopono nui o ka IP. Inā hōʻano hou ʻoe i ka polokalamu Intel Quartus Prime, pono ʻoe e hana hou i ka IP.
  • Hōʻike ʻo Y i ka IP me nā hiʻohiʻona hou. E hana hou i kāu IP e hoʻokomo i kēia mau hiʻohiʻona hou.
  • Hōʻike ʻo Z i ka IP me nā loli liʻiliʻi. E hana hou i kāu IP e hoʻokomo i kēia mau hoʻololi.

ʻIke pili

  • Nā memo hoʻokuʻu hou ʻana o Intel Quartus Prime Design Suite
  • Ke alakaʻi hoʻohana ʻana o Intel Agilex™ i hoʻokomo ʻia
  • ʻO Errata no ka eSRAM Intel Agilex™ FPGA IP ma ke kahua ʻike

 eSRAM Intel Agilex™ FPGA IP v20.1.0

Papa 1. v20.1.0 2022.09.26

ʻO Intel Quartus Prime Version wehewehe Ka hopena
22.3 Hoʻohana ʻia i ke kākoʻo pili ʻōnaehana ʻōnaehana Intel Agilex™ eSRAM IP ma ka mea hana Platform Designer. ʻO ka hoʻonui ʻana i ka IP he koho ma ka polokalamu polokalamu Intel Quartus Prime Pro Edition 22.3.
  • Pono ka hana hou ʻana o IP inā makemake nā mea kūʻai aku e hoʻohana i ka eSRAM IP i ka mea hana Platform Designer.
  • ʻAʻohe hoʻololi i nā hiʻohiʻona eSRAM.

eSRAM Intel Agilex FPGA IP v20.0.0

Papa 2. v20.0.0 2021.10.04

ʻO Intel Quartus Prime Version wehewehe Ka hopena
21.3 Hoʻohou i nā ʻāpana ch{0-7}_ecc_dec_eccmode a me ch{0-7}_ecc_enc_eccmode i ECC_DISABLED no nā awa i hoʻohana ʻole ʻia. Pono ka hoʻonui IP no ka loaʻa ʻana o ka hōʻuluʻulu hoʻolālā hoʻolālā me ka mana polokalamu polokalamu Intel Quartus Prime Pro Edition 21.3.
 eSRAM Intel Agilex FPGA IP v19.2.1
Papa 3. v19.2.1 2021.06.29
ʻO Intel Quartus Prime Version wehewehe Ka hopena
21.2 Hoʻopaʻa i ka uhaki paʻa ma ka hoʻohui ʻana (* altera_attribute = "-name HYPER_REGISTER_DELAY_CHAIN ​​100″*) i ka eSRAM Intel Agilex FPGA IP. He koho ka hoʻololi. Pono ʻoe e hana i kahi hoʻonui IP inā ʻaʻole hiki i kāu IP ke hoʻokō i nā kikoʻī hana kiʻekiʻe loa ma muli o ka uhaki paʻa.

 eSRAM Intel Agilex FPGA IP v19.2.0

Papa 4. v19.2.0 2020.12.14

ʻO Intel Quartus Prime Version wehewehe Ka hopena
19.4 Wehe ʻia ka hiʻohiʻona ECC encoder a me ka decoder bypass. —

eSRAM Intel Agilex FPGA IP v19.1.1

Papa 5. v19.1.1 2019.07.01

ʻO Intel Quartus Prime Version wehewehe Ka hopena
19.2 Hoʻokuʻu mua no nā polokalamu Intel Agilex. —

eSRAM Intel FPGA IP Release Notes (Intel Stratix® 10 Devices)

Inā ʻaʻole i loaʻa kahi leka hoʻokuʻu no kahi mana IP kikoʻī, ʻaʻohe loli o ka IP i kēlā mana. No ka ʻike e pili ana i ka hoʻopuka hou ʻana o IP a hiki i ka v18.1, e nānā i ka Intel Quartus Prime Design Suite Update Release Notes.

Kūlike nā mana Intel FPGA IP me nā polokalamu polokalamu Intel Quartus Prime Design Suite a hiki i ka v19.1. E hoʻomaka ana ma Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP he polokalamu hoʻololi hou.

Hiki ke loli ka helu Intel FPGA IP (XYZ) me kēlā me kēia polokalamu polokalamu Intel Quartus Prime. He hoʻololi i:

  • Hōʻike ʻo X i kahi hoʻoponopono nui o ka IP. Inā hōʻano hou ʻoe i ka polokalamu Intel Quartus Prime, pono ʻoe e hana hou i ka IP.
  •  Hōʻike ʻo Y i ka IP me nā hiʻohiʻona hou. E hana hou i kāu IP e hoʻokomo i kēia mau hiʻohiʻona hou.
  •  Hōʻike ʻo Z i ka IP me nā loli liʻiliʻi. E hana hou i kāu IP e hoʻokomo i kēia mau hoʻololi.

ʻIke pili

  • Nā memo hoʻokuʻu hou ʻana o Intel Quartus Prime Design Suite
  • Intel Stratix® 10 Embedded Memory User Guide
  • ʻO Errata no ka eSRAM Intel FPGA IP ma ke kahua ʻike

 eSRAM Intel FPGA IP v19.2.0

Papa 6. v19.2.0 2022.09.26

ʻO Intel Quartus Prime Version wehewehe Ka hopena
22.3 Hoʻohana ʻia i ke kākoʻo hoʻohui ʻōnaehana ʻōnaehana Intel Stratix® 10 eSRAM IP ma ka mea hana Platform Designer. ʻO ka hoʻonui ʻana i ka IP he koho ma ka polokalamu polokalamu Intel Quartus Prime Pro Edition 22.3.
  • Pono ka hana hou ʻana o IP inā makemake nā mea kūʻai aku e hoʻohana i ka eSRAM IP i ka mea hana Platform Designer.
  • ʻAʻohe hoʻololi i nā hiʻohiʻona eSRAM.

 eSRAM Intel FPGA IP v19.1.5

Papa 7. v19.1.5 2020.10.12

ʻO Intel Quartus Prime Version wehewehe Ka hopena
20.3 Hoʻohou i ka wehewehe no E ho'ā i ke ʻano mana haʻahaʻa i ka eSRAM Intel FPGA IP hoʻoponopono hoʻoponopono. —

eSRAM Intel FPGA IP v19.1.4

Papa 8. v19.1.4 2020.08.03

ʻO Intel Quartus Prime Version wehewehe Ka hopena
20.2 Kapa hou i ka I/O PLL fileinoa e haʻalele i ka leka hoʻomaopopo mai ka IOPLL file.

Inā loaʻa i nā eSRAM ʻelua nā palena PLL like (PLL reference clock frequency a me PLL i makemake ʻia), hiki ke nānā ʻole ʻia ka leka hoʻomaopopo.

Inā loaʻa i nā eSRAM ʻelua nā ʻāpana PLL ʻokoʻa, ma hope o ka hōʻuluʻulu ʻana e hoʻonohonoho ʻia lākou i nā alapine PLL like i lawe ʻia mai kekahi o nā ʻāpana eSRAM Intel FPGA IP. Nānā i ka Hōʻike ʻo Quartus Fitter ➤ Plan Stage ➤ Hōʻuluʻulu Manaʻo PLL e nānā i nā alapine eSRAM IOPLL i hoʻokō ʻia.

Pono ka hoʻonui IP inā ʻokoʻa ka ʻokoʻa PLL no nā eSRAM ʻelua.

 —

eSRAM Intel FPGA IP v19.1.3

Papa 9. v19.1.3 2019.10.11

ʻO Intel Quartus Prime Version wehewehe Ka hopena
19.3 Hoʻohou i ka wehewehe no PLL Kuhikuhi Uki Ka pinepine i ka eSRAM Intel FPGA IP hoʻoponopono hoʻoponopono. —

 eSRAM Intel FPGA IP v18.1

Papa 10. v18.1 2018.10.03

ʻO Intel Quartus Prime Version wehewehe Ka hopena
18.1 Wehe ʻia ka papa inoa HIPI no iopll_lock2core_reg. Hiki iā ʻoe ke hoʻonui i kāu IP core.

eSRAM Intel FPGA IP v18.0

Papa 11. v18.0 Mei 2018

wehewehe Ka hopena
Ua kapa hou ʻia ʻo Native eSRAM IP core i eSRAM Intel FPGA IP e like me ka Intel rebranding. —
Hoʻohui ʻia i kahi hōʻailona interface hou:
  • iopll_lock2core

kūlana laka eSRAM IOPLL.

 —

ʻIke pili

  • Hoʻolauna i nā Intel FPGA IP Cores
  • Intel Stratix 10 Embedded Memory User Guide
  • Errata no nā cores IP ʻē aʻe ma ka waihona ʻike

 ESRAM IP Core v17.1

Papa 12. v17.1 Nowemapa 2017

wehewehe Ka hopena
Hoʻokuʻu mua. Loaʻa kēia IP core ma nā polokalamu Intel Stratix 10 wale nō. —

ʻIke pili

  • Hoʻolauna i nā Intel FPGA IP Cores
  • Intel Stratix 10 Embedded Memory User Guide
  • Errata no nā cores IP ʻē aʻe ma ka waihona ʻike

Intel Stratix 10 Embedded Memory User Guide Archives
No nā mana hou loa o kēia alakaʻi hoʻohana, e nānā i ka Intel® Stratix® 10 Embedded Memory User Guide. Inā ʻaʻole i helu ʻia kahi IP a i ʻole ka mana lako polokalamu, pili ke alakaʻi mea hoʻohana no ka IP mua a i ʻole ka mana polokalamu.

Nā memo hoʻokuʻu IP eSRAM Intel® FPGA

Palapala / Punawai

intel eSRAM Intel FPGA IP [pdf] Ke alakaʻi hoʻohana
eSRAM Intel FPGA IP, Intel FPGA IP, FPGA IP, IP

Nā kuhikuhi

Nā leka pili

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