Abubuwan da ke ciki boye
1 eSRAM Intel FPGA IP
2 Bayanin samfur
3 Umarnin Amfani da samfur
4 eSRAM Intel® Agilex™ FPGA IP
5 eSRAM Intel FPGA IP Bayanan Bayani na Sakin (Intel Stratix® 10 Na'urori)
6 Takardu / Albarkatu
6.1 Magana
7 Labarai masu alaka

eSRAM Intel FPGA IP Jagorar Mai amfani Featured Hoton: A'a file Ɗaukaka Post Ƙara MediaVisualTsarin Rubutun 3 H3 Rufe maganganu Ƙara Ayyukan Ayyukan Mai jarida filesMedia Laburaren Tace Mai jaridaTace ta nau'in Duk abubuwan mai jarida Tace ta kwanan wata Duk kwanan wata Bincika jerin labaran Yana Nuna 81 na 5375076 abubuwan watsa labarai Load ƙarin BAYANIN HUKUNCI eSRAM-logo-image-1.jpg Yuli 22, 2023 13 KB 357 ta 74 pixels Shirya hoto na dindindin. Alt Rubutun Koyi yadda ake kwatanta manufar hoton (yana buɗewa a cikin sabon shafin). Bar komai idan hoton na ado ne kawai.Title eSRAM-logo-image Description File URLhttps://manuals.plus/wp-content/uploads/2023/07/eSRAM-logo-image-1.jpg Kwafi URL zuwa allo haɗe-haɗe NUNA SAI KYAUTA Cibiyar daidaitawa zuwa Babu Girman Cikakkun Girma - 357 × 74 Zaɓaɓɓen ayyukan watsa labarai 1 abu da aka zaɓa Share Saka cikin post No. file zaba

eSRAM Intel FPGA IP

eSRAM Intel FPGA IP Jagorar Mai amfani Featured Hoton: A'a file Ɗaukaka Post Ƙara MediaVisualTsarin Rubutun 4 DIV »H4 Rufe maganganu Ƙara Ayyukan Ayyukan Mai jarida filesMedia Library Tace mai jaridaTace ta nau'in Duk abubuwan mai jarida Tace ta kwanan wata Duk kwanan wata Bincika lissafin mai jarida yana Nuna 82 na 5375077 abubuwan watsa labarai Load ƙarin BAYANIN NUFIN eSRAM-Intel-FPGA-IP-produt-image.jpg Yuli 22, 2023 35 KB 442 ta pixels 328 Shirya Share Hoto na dindindin Alt Rubutu Koyi yadda ake kwatanta manufar hoton(yana buɗewa a cikin sabon shafin). Bar komai idan hoton na ado ne kawai.Title eSRAM-Intel-FPGA-IP-produt-image Caption Description File URLhttps://manuals.plus/wp-content/uploads/2023/07/eSRAM-Intel-FPGA-IP-produt-image.jpg Kwafi URL zuwa allo haɗe-haɗe NUNA SAI KYAUTA Cibiyar daidaitawa zuwa Babu Girman Cikakkun Girma - 442 × 328 Zaɓaɓɓen ayyukan watsa labarai 1 abu da aka zaɓa Share Saka cikin post No. file zaba

Bayanin samfur

Samfurin shine Intel FPGA IP, wanda ya dace da Intel Quartus Prime Design Suite software. IP ɗin yana da nau'ikan iri daban-daban waɗanda suka dace da nau'ikan software har zuwa v19.1. An fara daga sigar software ta 19.2, an gabatar da sabon tsarin siga don Intel FPGA IP.

Siffofin IP sune kamar haka:

Sigar Kwanan wata Intel Quartus Prime Version Bayani Tasiri
v20.1.0 2022.09.26 22.3 An kunna haɗin haɗin haɗin tsarin Intel AgilexTM eSRAM IP
goyon baya a cikin Platform Designer kayan aiki.		 ISO 9001: 2015 Rajista
v20.0.0 2021.10.04 21.3 An sabunta ch{0-7}_ecc_dec_eccmode da ch{0-7}_ecc_enc_eccmode
sigogi zuwa ECC_DISABLED don tashoshin jiragen ruwa marasa amfani.		 Ana buƙatar haɓaka IP don samun haɗar fasfo ɗin ƙira
Tare da Intel Quartus Prime Pro Edition software version 21.3.
v19.2.1 2021.06.29 21.2 Kafaffen ƙetare ta hanyar ƙara (* altera_attribute = -name
HYPER_REGISTER_DELAY_CHAIN ​​100*) zuwa eSRAM Intel Agilex FPGA
IP.		 Canjin na zaɓi ne. Ana buƙatar haɓaka IP idan IP ɗin ku
ba zai iya cika madaidaicin ƙayyadaddun aiki ba saboda riƙewa
cin zarafi.
v19.2.0 2020.12.14 19.4 Cire ƙwaƙƙwaran ECC encoder da dikodi - kewaye
fasali.		 N/A
v19.1.1 2019.07.01 19.2 Sakin farko don na'urorin Intel Agilex. N/A

Idan bayanin kula ba ya samuwa don takamaiman sigar IP, yana nufin babu canje-canje a wannan sigar.

Lura: Lambar Intel FPGA IP (XYZ) na iya canzawa tare da kowace sigar software ta Intel Quartus Prime.

Umarnin Amfani da samfur

Don amfani da Intel FPGA IP, bi waɗannan matakan:

  1. Tabbatar cewa an shigar da software na Intel Quartus Prime Design Suite masu dacewa akan tsarin ku.
  2. Zazzage sigar IP na Intel FPGA daidai da ta dace da sigar software ɗin ku.
  3. Cire IP ɗin da aka sauke files zuwa wurin da ya dace akan kwamfutarka.
  4. Bude Intel Quartus Prime software kuma ƙirƙirar sabon aiki ko buɗe aikin da ke akwai.
  5. A cikin saitunan aikin ko kundin adireshin IP, gano wuri kuma ƙara Intel FPGA IP zuwa aikin ku.
  6. Sanya sigogin IP bisa ga buƙatun ku.
  7. Haɗa IP zuwa wasu abubuwan haɗin gwiwa ko kayayyaki a cikin ƙirar ku ta amfani da kayan aikin Platform Designer.
  8. Tabbatar cewa an yi duk wani mahimmancin haɓakawa na IP idan an ƙayyade a cikin bayanin samfurin.
  9. Haɗa kuma tabbatar da ƙirar ku ta amfani da Intel Quartus Prime software.
  10. Ci gaba tare da ƙarin matakai bisa ga buƙatun ƙira da manufofin aikin ku.

eSRAM Intel® Agilex™ FPGA IP

Bayanan Saki
Idan bayanin kula ba ya samuwa don takamaiman sigar IP, IP ɗin ba shi da canje-canje a wannan sigar. Don bayani game da sabuntawar IP har zuwa v18.1, koma zuwa Bayanan Bayanan Saki na Intel® Quartus® Prime Design Suite.
Siffofin IP na Intel FPGA sun dace da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. An fara a cikin sigar software ta Intel Quartus Prime Design Suite 19.2, Intel FPGA IP yana da sabon tsarin siga.
Lambar Intel FPGA IP (XYZ) na iya canzawa tare da kowace sigar software ta Intel Quartus Prime.

Canji a:
  • X yana nuna babban bita na IP. Idan kun sabunta Intel Quartus Prime software, dole ne ku sake haɓaka IP ɗin.
  • Y yana nuna IP ɗin ya ƙunshi sabbin abubuwa. Sake haɓaka IP ɗin ku don haɗa waɗannan sabbin fasalolin.
  • Z yana nuna IP ɗin ya ƙunshi ƙananan canje-canje. Sake haɓaka IP ɗin ku don haɗa waɗannan canje-canje.

Bayanai masu alaƙa

  • Intel Quartus Prime Design Suite Sabunta Bayanan Bayanan Sakin
  • Intel Agilex™ Jagorar Mai Amfani da Ƙwaƙwalwar Ƙwaƙwalwa
  • Errata don eSRAM Intel Agilex™ FPGA IP a cikin Tushen Ilimi

 eSRAM Intel Agilex FPGA IP v20.1.0

Table 1. v20.1.0 2022.09.26

Intel Quartus Prime Version Bayani Tasiri
22.3 An kunna Intel Agilex™ eSRAM tsarin haɗin haɗin tsarin IP a cikin kayan aikin Platform Designer. Haɓakawa ta IP zaɓi ne a cikin Intel Quartus Prime Pro Edition software 22.3.
  • Ana buƙatar sabuntawar IP kawai idan abokan ciniki suna son amfani da eSRAM IP a cikin kayan aikin Platform Designer.
  • Babu wasu canje-canje ga abubuwan eSRAM masu wanzuwa.

eSRAM Intel Agilex FPGA IP v20.0.0

Table 2. v20.0.0 2021.10.04

Intel Quartus Prime Version Bayani Tasiri
21.3 An sabunta ch{0-7}_ecc_dec_eccmode da ch{0-7}_ecc_enc_eccmode sigogi zuwa ECC_DISABLED don tashoshin jiragen ruwa marasa amfani. Ana buƙatar haɓakawar IP don samun haɗar ƙirar ƙirar ƙira tare da Intel Quartus Prime Pro Edition software 21.3.
 eSRAM Intel Agilex FPGA IP v19.2.1
Table 3. v19.2.1 2021.06.29
Intel Quartus Prime Version Bayani Tasiri
21.2 Kafaffen cin zarafi ta hanyar ƙara (* altera_attribute = "-name HYPER_REGISTER_DELAY_CHAIN ​​100″*) zuwa eSRAM Intel Agilex FPGA IP. Canjin na zaɓi ne. Ana buƙatar ka yi haɓakawar IP idan IP ɗinka ba zai iya cika iyakar ƙayyadaddun aiki ba saboda cin zarafi.

 eSRAM Intel Agilex FPGA IP v19.2.0

Table 4. v19.2.0 2020.12.14

Intel Quartus Prime Version Bayani Tasiri
19.4 Cire ƙwaƙƙwaran ECC encoder da fasalin kewayawa. —

eSRAM Intel Agilex FPGA IP v19.1.1

Table 5. v19.1.1 2019.07.01

Intel Quartus Prime Version Bayani Tasiri
19.2 Sakin farko don na'urorin Intel Agilex. —

eSRAM Intel FPGA IP Bayanan Bayani na Sakin (Intel Stratix® 10 Na'urori)

Idan bayanin kula ba ya samuwa don takamaiman sigar IP, IP ɗin ba shi da canje-canje a wannan sigar. Don bayani game da sabuntawar IP har zuwa v18.1, koma zuwa Bayanan Bayanin Sakin Sabuntawa na Intel Quartus Prime Design Suite.

Siffofin IP na Intel FPGA sun dace da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. An fara a cikin sigar software ta Intel Quartus Prime Design Suite 19.2, Intel FPGA IP yana da sabon tsarin siga.

Lambar Intel FPGA IP (XYZ) na iya canzawa tare da kowace sigar software ta Intel Quartus Prime. Canji a:

  • X yana nuna babban bita na IP. Idan kun sabunta Intel Quartus Prime software, dole ne ku sake haɓaka IP ɗin.
  •  Y yana nuna IP ɗin ya ƙunshi sabbin abubuwa. Sake haɓaka IP ɗin ku don haɗa waɗannan sabbin fasalolin.
  •  Z yana nuna IP ɗin ya ƙunshi ƙananan canje-canje. Sake haɓaka IP ɗin ku don haɗa waɗannan canje-canje.

Bayanai masu alaƙa

  • Intel Quartus Prime Design Suite Sabunta Bayanan Bayanan Sakin
  • Intel Stratix® 10 Jagorar Mai Amfani da Ƙwaƙwalwar Ƙwaƙwalwa
  • Errata don eSRAM Intel FPGA IP a cikin Tushen Ilimi

 eSRAM Intel FPGA IP v19.2.0

Table 6. v19.2.0 2022.09.26

Intel Quartus Prime Version Bayani Tasiri
22.3 An kunna Intel Stratix® 10 eSRAM IP tsarin haɗin haɗin haɗin haɗin a cikin kayan aikin Platform Designer. Haɓakawa ta IP zaɓi ne a cikin Intel Quartus Prime Pro Edition software 22.3.
  • Ana buƙatar sabuntawar IP kawai idan abokan ciniki suna son amfani da eSRAM IP a cikin kayan aikin Platform Designer.
  • Babu wasu canje-canje ga abubuwan eSRAM masu wanzuwa.

 eSRAM Intel FPGA IP v19.1.5

Table 7. v19.1.5 2020.10.12

Intel Quartus Prime Version Bayani Tasiri
20.3 An sabunta bayanin don Kunna Yanayin Ƙarfin Ƙarfi a cikin eSRAM Intel FPGA IP editan siga. —

eSRAM Intel FPGA IP v19.1.4

Table 8. v19.1.4 2020.08.03

Intel Quartus Prime Version Bayani Tasiri
20.2 An sake suna I/O PLL filesuna don barin saƙon gargaɗi daga IOPLL file.

Idan eSRAM guda biyu suna da sigogin PLL iri ɗaya (mitar agogon PLL da mitar agogon PLL da ake so), ana iya yin watsi da saƙon gargaɗin.

Idan eSRAM guda biyu suna da sigogin PLL daban-daban, bayan haɗa su za a saita su zuwa mitocin PLL iri ɗaya waɗanda aka ɗauka daga ɗayan eSRAM Intel FPGA IP sigogi. Koma zuwa ga Rahoton Quartus Fitter ➤ Shirin Stage ➤ Takaitaccen Amfanin PLL don lura da aiwatar da mitocin eSRAM IOPLL.

Ana buƙatar sabunta IP lokacin da ma'aunin PLL na eSRAM biyu ya bambanta.

 —

eSRAM Intel FPGA IP v19.1.3

Table 9. v19.1.3 2019.10.11

Intel Quartus Prime Version Bayani Tasiri
19.3 An sabunta bayanin don Mitar agogo na PLL a cikin eSRAM Intel FPGA IP editan siga. —

 eSRAM Intel FPGA IP v18.1

Table 10. v18.1 2018.10.03

Intel Quartus Prime Version Bayani Tasiri
18.1 An cire rajistar HIPI na iopll_lock2core_reg. Kuna iya haɓaka ainihin IP ɗin ku.

eSRAM Intel FPGA IP v18.0

Table 11. v18.0 Mayu 2018

Bayani Tasiri
An Sake suna 'Native eSRAM IP core' zuwa eSRAM Intel FPGA IP kamar yadda ake sake fasalin Intel. —
An ƙara sabon siginar dubawa:
  • iopll_lock2core

eSRAM IOPLL matsayin kulle.

 —

Bayanai masu alaƙa

  • Gabatarwa zuwa Intel FPGA IP Cores
  • Intel Stratix 10 Jagorar Mai Amfani da Ƙwaƙwalwar Ƙwaƙwalwa
  • Errata don sauran nau'ikan IP a cikin Tushen Ilimi

 Asalin eSRAM IP Core v17.1

Table 12. v17.1 Nuwamba 2017

Bayani Tasiri
Sakin farko. Wannan ainihin IP ɗin yana samuwa ne kawai a cikin na'urorin Intel Stratix 10. —

Bayanai masu alaƙa

  • Gabatarwa zuwa Intel FPGA IP Cores
  • Intel Stratix 10 Jagorar Mai Amfani da Ƙwaƙwalwar Ƙwaƙwalwa
  • Errata don sauran nau'ikan IP a cikin Tushen Ilimi

Rukunin Rukunin Jagorar Mai Amfani na Intel Stratix 10
Don sababbin sifofin wannan jagorar mai amfani da na baya da kuma na baya, koma zuwa Intel® Stratix® 10 Jagorar Mai Amfani da Ƙwaƙwalwar Ƙwaƙwalwa. Idan ba a jera sigar IP ko software ba, jagorar mai amfani na IP ɗin da ta gabata ko sigar software ta shafi.

eSRAM Intel® FPGA IP Bayanan kula na Sakin

Takardu / Albarkatu

intel eSRAM Intel FPGA IP [pdf] Jagorar mai amfani
eSRAM Intel FPGA IP, Intel FPGA IP, FPGA IP, IP

Magana

Labarai masu alaka

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