AX7203 Papan Pangembangan FPGA
Informasi produk
ARTIX-7 FPGA Development Board AX7203 User Manual
| Versi | Rev 1.2 |
|---|---|
| Tanggal | 2023-02-23 |
| Rilis Miturut | Rachel Zhou |
| Katrangan | Rilis pisanan |
Part 1: FPGA Development Board Pambuka
Papan pangembangan AX7203 FPGA minangka papan inti + operator
platform Papan sing ngidini kanggo pembangunan secondary trep
nggunakake papan inti. Iki nggunakake papan antar-kacepetan dhuwur
konektor antarane Papan inti lan Papan operator.
Papan operator AX7203 nyedhiyakake macem-macem antarmuka periferal,
kalebu:
- 1 antarmuka PCIex4
- 2 Gigabit Ethernet antarmuka
- 1 antarmuka Output HDMI
- 1 antarmuka Input HDMI
- 1 Antarmuka Uart
- 1 slot kertu SD
- Antarmuka konektor XADC (ora diinstal kanthi gawan)
- 2-cara 40-pin header expansion
- Sawetara tombol
- LED
- sirkuit EEPROM
Part 2: AC7200 inti Papan Pambuka
Papan inti AC7200 adhedhasar seri ARTIX-7 XILINX 200T
AC7200-2FGG484I. Iku papan inti kinerja dhuwur cocok kanggo
komunikasi data kacepetan dhuwur, pangolahan gambar video, lan
disualekno data-kacepetan dhuwur.
Fitur utama papan inti AC7200 kalebu:
- Rong lembar chip MICRON MT41J256M16HA-125 DDR3 kanthi
kapasitas 4Gbit saben, nyediakake 32-dicokot data bus jembaré lan nganti
25Gb maca / nulis bandwidth data antarane FPGA lan DDR3. - 180 port IO standar tingkat 3.3V
- 15 port IO standar tingkat 1.5V
- 4 pasangan GTP-kacepetan dhuwur RX/TX sinyal diferensial
- Dawane witjaksono lan proses diferensial nuntun antarane
chip FPGA lan antarmuka - Ukuran kompak 45*55 (mm)
Pandhuan Panggunaan Produk
Kanggo nggunakake ARTIX-7 FPGA Development Board AX7203, tindakake iki
langkah:
- Sambungake papan inti lan papan operator nggunakake kacepetan dhuwur
konektor interboard. - Yen perlu, nginstal antarmuka XADC nggunakake kasedhiya
konektor. - Sambungake peripheral sing dikarepake menyang antarmuka sing kasedhiya
Papan operator, kayata piranti PCIex4, Gigabit Ethernet
piranti, piranti HDMI, piranti Uart, kertu SD, utawa njaba
header expansion. - Daya ing papan pangembangan nggunakake daya sing cocog
pasokan.
ARTIX-7 Papan Pangembangan FPGA
AX7203
Manual pangguna
ARTIX-7 FPGA Development Board AX7203 User Manual
Versi Rekam
Versi Rev 1.2
Tanggal 2023-02-23
Rilis Miturut Rachel Zhou
Deskripsi First Release
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ARTIX-7 FPGA Development Board AX7203 User Manual
Daftar Isi
Rekaman Versi ………………………………………………………………………………………2 Bagian 1: Pambuka Papan Pengembangan FPGA ……………………… …………… 6 Bagean 2: Papan Inti AC7200 Pambuka ……………………………………………..9
Bagean 2.1: Chip FPGA ………………………………………………………………… 10 Bagean 2.2: Kristal Diferensial Aktif ………………………………… ……………..12 Bagean 2.3: Jam Diferensial Aktif 200Mhz …………………………………12 Bagean 2.4: Kristal Diferensial Aktif 148.5Mhz ………………………………….. 13 Bagean 2.5: DRAM DDR3 ………………………………………………………15 Bagean 2.6: Flash QSPI ………………………………… …………………………………19 Bagean 2.7: Lampu LED ing Papan Inti ……………………………………………. 21 Bagean 2.8: Tombol Reset ……………………………………………………… 22 Bagean 2.9: JTAG Antarmuka ……………………………………………………… 23 Bagean 2.10: Antarmuka Daya ing Papan Inti …………………………………. 24 Bagean 2.11: Konektor Papan menyang Papan …………………………………………….. 25 Bagean 2.12: Pasokan Daya ……………………………………………………… …………32 Bagean 2.13: Diagram Struktur ………………………………………………………..33 Bagean 3: Papan pembawa ………………………………… ……………………………………………. 34 Bagean 3.1: Carrier board Pambuka …………………………………………… 34 Bagean 3.2: Antarmuka Ethernet Gigabit …………………………………………… 35 Bagean 3.3: Antarmuka PCIe x4 ……………………………………………………….. 38 Bagean 3.4: Antarmuka output HDMI …………………………………………… ………….40 Bagean 3.5: Antarmuka Input HDMI ……………………………………………42 Bagean 3.6: Slot Kertu SD ………………………………… ………………………………… 44 Bagean 3.7: USB menyang Port Serial ……………………………………………………….45 Bagean 3.8: EEPROM 24LC04 … …………………………………………….47 Bagean 3.9: Header Ekspansi ……………………………………………………… 48 Bagean 3.10: JTAG Antarmuka ………………………………………………………. 51
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ARTIX-7 FPGA Development Board AX7203 User Manual
Bagean 3.11: Antarmuka XADC (ora diinstal kanthi gawan) …………………….. 52 Bagean 3.12: tombol ……………………………………………………… …………53 Bagean 3.13: Lampu LED ………………………………………………………………… 54 Bagean 3.14: Sumber Daya ……………………… …………………………………55
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ARTIX-7 FPGA Development Board AX7203 User Manual
Platform pangembangan FPGA ARTIX-7 iki (Modul: AX7203) nggunakake mode papan inti + papan operator, sing trep kanggo pangguna nggunakake papan inti kanggo pangembangan sekunder.
Ing desain saka Papan operator, kita wis lengkap kasugihan saka antarmuka kanggo pangguna, kayata 1 PCIex4 antarmuka, 2 Gigabit Ethernet antarmuka, 1 antarmuka Output HDMI, 1 antarmuka Input HDMI, Uart Interface, slot kertu SD etc. Iku meets syarat pangguna. kanggo PCIe ijol-ijolan data kacepetan dhuwur, pangolahan transmisi video lan kontrol industri. Iku "Versatile" ARTIX-7 FPGA platform pangembangan. Nyedhiyakake kamungkinan kanggo transmisi video kanthi kacepetan dhuwur, pra-validasi lan pasca-aplikasi jaringan lan komunikasi serat lan pangolahan data. Produk iki cocok banget kanggo siswa, insinyur lan grup liyane sing melu pangembangan ARTIX-7FPGA.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 1: FPGA Development Board Pambuka
Struktur kabeh papan pangembangan AX7203 FPGA diwarisake saka model papan inti + papan operator sing konsisten. Konektor antar-papan kanthi kacepetan dhuwur digunakake ing antarane papan inti lan papan operator.
Papan inti utamané dumadi saka FPGA + 2 DDR3 + QSPI FLASH, kang undertakes fungsi dhuwur-kacepetan Processing data lan panyimpenan saka FPGA, dhuwur-kacepetan data maca lan nulis antarane FPGA lan loro DDR3s, ambane dicokot data punika 32 bit, lan bandwidth kabeh sistem nganti 25Gb. /s(800M*32bit); Rong kapasitas DDR3 nganti 8Gbit, sing nyukupi kabutuhan buffer dhuwur sajrone pangolahan data. FPGA sing dipilih yaiku chip XC7A200T saka seri ARTIX-7 XILINX, ing paket BGA 484. Frekuensi komunikasi antarane XC7A200T lan DDR3 tekan 400Mhz lan tingkat data yaiku 800Mhz, sing nyukupi kabutuhan pangolahan data multi-saluran kanthi kacepetan dhuwur. Kajaba iku, XC7A200T FPGA nduweni papat transceiver kacepetan dhuwur GTP kanthi kecepatan nganti 6.6Gb/s saben saluran, dadi becik kanggo komunikasi serat optik lan komunikasi data PCIe.
Papan operator AX7203 ngembangake antarmuka periferal sing sugih, kalebu 1 antarmuka PCIex4, 2 antarmuka Gigabit Ethernet, 1 antarmuka Output HDMI, 1 antarmuka Input HDMI, 1 Antarmuka Uart, 1 slot kertu SD, antarmuka konektor XADC, ekspansi 2-pin 40 arah. header, sawetara tombol, LED lan sirkuit EEPROM.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gambar 1-1-1: Diagram Skema AX7203 Liwat diagram iki, sampeyan bisa ndeleng antarmuka lan fungsi sing ana ing Papan Pengembangan FPGA AX7203: Papan inti FPGA Artix-7
Papan inti kasusun saka XC7A200T + 8Gb DDR3 + 128Mb QSPI FLASH. Ana rong kristal diferensial Sitime LVDS kanthi tliti dhuwur, siji ing 200MHz lan liyane ing 125MHz, nyedhiyakake input jam sing stabil kanggo sistem FPGA lan modul GTP. Antarmuka PCIe x1 4 saluran Ndhukung standar PCI Express 2.0, nyedhiyakake antarmuka transmisi data kecepatan tinggi PCIe x4, tingkat komunikasi saluran tunggal nganti 5GBaud Antarmuka RJ-2 Gigabit Ethernet 45 saluran Antarmuka RJ-9031 Gigabit Ethernet chip nggunakake chip KSZXNUMXRNX Ethernet PHY Micrel. kanggo nyedhiyakake layanan komunikasi jaringan kanggo pangguna.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Chip KSZ9031RNX ndhukung tingkat transmisi jaringan 10/100/1000 Mbps; duplex lengkap lan adaptif. Antarmuka Output HDMI 1 saluran Chip enkoding SIL9134 HDMI Silion Image dipilih kanggo ndhukung nganti output 1080P@60Hz lan ndhukung output 3D. Antarmuka Input HDMI 1 saluran Chip dekoder SIL9013 HDMI Silion Image dipilih, sing ndhukung input nganti 1080P@60Hz lan ndhukung output data ing macem-macem format. 1-saluran Uart kanggo antarmuka USB 1 Uart kanggo antarmuka USB kanggo komunikasi karo komputer kanggo pangguna debugging. Chip port serial yaiku chip USB-UAR saka Silicon Labs CP2102GM, lan antarmuka USB yaiku antarmuka USB MINI. Wadah kertu SD mikro 1-port Wadah kertu SD mikro, ndhukung mode SD lan mode SPI EEPROM Onboard antarmuka IIC EEPROM 24LC04 2-way 40-pin expansion port 2-way 40-pin 2.54mm pitch expansion port bisa disambungake menyang macem-macem ALINX modul (kamera binokular, layar LCD TFT, modul AD kacepetan dhuwur, lsp). Port expansion ngandhut 1 saluran 5V sumber daya, 2 saluran 3.3V sumber daya, 3 cara lemah, 34 IOs port. JTAG Antarmuka A standar jarak 10-pin 0.1 inci JTAG port kanggo program FPGA download lan debugging. tombol 2 tombol; 1 tombol reset (ing papan inti) Lampu LED 5 LED pangguna (1 ing papan inti lan 4 ing papan operator)
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2: AC7200 inti Papan Pambuka
AC7200 (model papan inti, padha ing ngisor iki) Papan inti FPGA, adhedhasar seri ARTIX-7 XILINX 200T AC7200-2FGG484I. Iku papan inti kinerja dhuwur karo kacepetan dhuwur, bandwidth dhuwur lan kapasitas dhuwur. Cocog kanggo komunikasi data kanthi kacepetan dhuwur, pangolahan gambar video, akuisisi data kanthi kacepetan dhuwur, lsp.
Papan inti AC7200 iki nggunakake rong lembar chip MICRON MT41J256M16HA-125 DDR3, saben DDR nduweni kapasitas 4Gbit; loro Kripik DDR digabungake menyang 32-dicokot data bus jembaré, lan maca / nulis bandwidth data antarane FPGA lan DDR3 nganti 25Gb; konfigurasi kuwi bisa nyukupi kabutuhan Processing data bandwidth dhuwur.
Papan inti AC7200 ngembangake 180 port IO standar level 3.3V, 15 port IO standar level 1.5V, lan 4 pasangan sinyal diferensial RX/TX kacepetan dhuwur GTP. Kanggo pangguna sing butuh akeh IO, papan inti iki bakal dadi pilihan sing apik. Menapa malih, nuntun antarane chip FPGA lan antarmuka padha dawa lan Processing diferensial, lan ukuran Papan inti mung 45 * 55 (mm), kang cocok banget kanggo pembangunan secondary.
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ARTIX-7 FPGA Development Board AX7203 User Manual AC7200 Core Board (Ngarep View)
Papan Inti AC7200 (Rear View)
Bagean 2.1: Chip FPGA
Kaya sing kasebut ing ndhuwur, model FPGA sing digunakake yaiku AC7200-2FGG484I, sing kalebu seri Artix-7 Xilinx. Kelas kacepetan yaiku 2, lan kelas suhu minangka kelas industri. Model iki minangka paket FGG484 kanthi 484 pin. Xilinx ARTIX-7 FPGA aturan jeneng chip minangka ngisor
Definisi Model Chip Spesifik saka Seri ARTIX-7
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ARTIX-7 FPGA Development Board AX7203 User Manual
Chip FPGA ing Papan Paramèter utama chip FPGA AC7200 minangka nderek
Jeneng Sel Logika
Irisan CLB flip-flop Blok RAMkb DSP Irisan
PCIe Gen2 XADC
GTP Transceiver Speed Grade
Kelas Suhu
Parameter spesifik 215360 33650 269200 13140 740 1
1 XADC, 12bit, 1Mbps AD 4 GTP6.6Gb/s maks -2 Industri
Sistem sumber daya FPGA Artix-7 Penyetor daya FPGA yaiku V, CCINT V, CCBRAM V, CCAUX VCCO, VMGTAVCC lan V. MGTAVTT VCCINT minangka pin sumber daya inti FPGA, sing kudu disambungake menyang 1.0V; VCCBRAM punika pin sumber daya saka FPGA blok RAM, nyambung menyang 1.0V; VCCAUX minangka pin sumber daya tambahan FPGA, nyambungake 1.8V; VCCO punika voltage saka
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ARTIX-7 FPGA Development Board AX7203 User Manual
saben BANK FPGA, kalebu BANK0, BANK13~16, BANK34~35. Ing papan inti AC7200 FPGA, BANK34 lan BANK35 kudu disambungake menyang DDR3, voltage sambungan BANK punika 1.5V, lan voltage saka BANK liyane 3.3V. VCCO saka BANK15 lan BANK16 powered by LDO, lan bisa diganti dening ngganti chip LDO. VMGTAVCC minangka sumber voltage saka transceiver GTP internal FPGA, disambungake menyang 1.0V; VMGTAVTT punika voltage saka transceiver GTP, disambungake menyang 1.2V.
Sistem FPGA Artix-7 mbutuhake urutan power-up didhukung dening VCCINT, banjur VCCBRAM, banjur VCCAUX, lan pungkasane VCCO. Yen VCCINT lan VCCBRAM duwe vol padhatage, padha bisa powered munggah ing wektu sing padha. Urutan daya outages diwalik. Urutan power-up saka transceiver GTP yaiku VCCINT, banjur VMGTAVCC, banjur VMGTAVTT. Yen VCCINT lan VMGTAVCC duwe volume sing padhatage, padha bisa powered munggah ing wektu sing padha. Urutan power-off mung kebalikan saka urutan power-on.
Bagean 2.2: Crystal Diferensial Aktif
Papan inti AC7200 dilengkapi karo loro kristal diferensial aktif Sitime, siji yaiku 200MHz, model yaiku SiT9102-200.00MHz, jam utama sistem kanggo FPGA lan digunakake kanggo ngasilake jam kontrol DDR3; liyane 125MHz, model SiT9102 -125MHz, referensi input jam kanggo transceiver GTP.
Bagean 2.3: Jam Diferensial Aktif 200Mhz
G1 ing Figure 3-1 punika 200M kristal diferensial aktif sing nyedhiyani Papan pembangunan sumber jam sistem. Output kristal disambungake menyang pin jam global BANK34 MRCC (R4 lan T4) saka FPGA. Jam diferensial 200Mhz iki bisa digunakake kanggo nyopir logika pangguna ing FPGA. Pangguna bisa ngatur PLLs lan DCMs nang FPGA kanggo generate jam saka frekuensi beda.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Skema Kristal Diferensial Aktif 200Mhz
Kristal Diferensial Aktif 200Mhz ing Papan Inti
200Mhz Diferensial Jam Pin Assignment
Jeneng Sinyal SYS_CLK_P SYS_CLK_N
PIN FPGA R4 T4
Part 2.4: 148.5Mhz Active Diferensial Crystal
G2 minangka kristal diferensial aktif 148.5Mhz, yaiku jam input referensi sing diwenehake menyang modul GTP ing FPGA. Output kristal disambungake menyang pin jam GTP BANK216 MGTREFCLK0P (F6) lan MGTREFCLK0N (E6) saka FPGA.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Skema Kristal Diferensial Aktif 148.5Mhz
Kristal Diferensial Aktif 1148.5Mhz ing Papan Inti
125Mhz Diferensial Jam Pin Assignment
Jeneng Net
PIN FPGA
MGT_CLK0_P
F6
MGT_CLK0_N
E6
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.5: DDR3 DRAM
Papan inti FPGA AC7200 dilengkapi karo rong chip DDR4 Micron 512Gbit (3MB), model MT41J256M16HA-125 (kompatibel karo MT41K256M16HA-125). DDR3 SDRAM nduweni kacepetan operasi maksimum 800MHz (data rate 1600Mbps). Sistem memori DDR3 langsung disambungake menyang antarmuka memori saka BANK 34 lan BANK35 saka FPGA. Konfigurasi tartamtu saka DDR3 SDRAM kapacak ing Tabel 4-1.
Nomer Bit U5,U6
Model Chip MT41J256M16HA-125
Kapasitas 256M x 16bit
Pabrik Micron
Konfigurasi DDR3 SDRAM
Desain hardware DDR3 mbutuhake pertimbangan ketat integritas sinyal. Kita wis kebak dianggep resistor cocog / resistance terminal, tilak kontrol impedansi, lan tilak kontrol dawa ing desain sirkuit lan desain PCB kanggo mesthekake dhuwur-kacepetan lan operasi stabil saka DDR3.
Skema DDR3 DRAM
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ARTIX-7 FPGA Development Board AX7203 User Manual
DDR3 ing Papan inti
Tugas pin DRAM DDR3:
Jeneng Net
Jeneng PIN FPGA
DDR3_DQS0_P
IO_L3P_T0_DQS_AD5P_35
DDR3_DQS0_N DDR3_DQS1_P DDR3_DQS1_N DDR3_DQS2_P DDR3_DQS2_N DDR3_DQS3_P DDR3_DQS3_N
DDR3_DQ[0] DDR3_DQ [1] DDR3_DQ [2] DDR3_DQ [3] DDR3_DQ [4] DDR3_DQ [5]
IO_L3N_T0_DQS_AD5N_35 IO_L9P_T1_DQS_AD7P_35 IO_L9N_T1_DQS_AD7N_35
IO_L15P_T2_DQS_35 IO_L15N_T2_DQS_35 IO_L21P_T3_DQS_35 IO_L21N_T3_DQS_35 IO_L2P_T0_AD12P_35 IO_L5P_T0_AD13P_35 IO_L1N_T0_AD4N_35
IO_L6P_T0_35 IO_L2N_T0_AD12N_35 IO_L5N_T0_AD13N_35
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FPGA P/N E1 D1 K2 J2 M1 L1 P5 P4 C2 G1 A1 F3 B2 F1
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ARTIX-7 FPGA Development Board AX7203 User Manual
DDR3_DQ [6]
IO_L1P_T0_AD4P_35
B1
DDR3_DQ [7]
IO_L4P_T0_35
E2
DDR3_DQ [8]
IO_L11P_T1_SRCC_35
H3
DDR3_DQ [9]
IO_L11N_T1_SRCC_35
G3
DDR3_DQ [10]
IO_L8P_T1_AD14P_35
H2
DDR3_DQ [11]
IO_L10N_T1_AD15N_35
H5
DDR3_DQ [12]
IO_L7N_T1_AD6N_35
J1
DDR3_DQ [13]
IO_L10P_T1_AD15P_35
J5
DDR3_DQ [14]
IO_L7P_T1_AD6P_35
K1
DDR3_DQ [15]
IO_L12P_T1_MRCC_35
H4
DDR3_DQ [16]
IO_L18N_T2_35
L4
DDR3_DQ [17]
IO_L16P_T2_35
M3
DDR3_DQ [18]
IO_L14P_T2_SRCC_35
L3
DDR3_DQ [19]
IO_L17N_T2_35
J6
DDR3_DQ [20]
IO_L14N_T2_SRCC_35
K3
DDR3_DQ [21]
IO_L17P_T2_35
K6
DDR3_DQ [22]
IO_L13N_T2_MRCC_35
J4
DDR3_DQ [23]
IO_L18P_T2_35
L5
DDR3_DQ [24]
IO_L20N_T3_35
P1
DDR3_DQ [25]
IO_L19P_T3_35
N4
DDR3_DQ [26]
IO_L20P_T3_35
R1
DDR3_DQ [27]
IO_L22N_T3_35
N2
DDR3_DQ [28]
IO_L23P_T3_35
M6
DDR3_DQ [29]
IO_L24N_T3_35
N5
DDR3_DQ [30]
IO_L24P_T3_35
P6
DDR3_DQ [31]
IO_L22P_T3_35
P2
DDR3_DM0
IO_L4N_T0_35
D2
DDR3_DM1
IO_L8N_T1_AD14N_35
G2
DDR3_DM2
IO_L16N_T2_35
M2
DDR3_DM3
IO_L23N_T3_35
M5
DDR3_A[0]
IO_L11N_T1_SRCC_34
AA4
DDR3_A[1]
IO_L8N_T1_34
AB2
DDR3_A[2]
IO_L10P_T1_34
AA5
DDR3_A[3]
IO_L10N_T1_34
AB5
DDR3_A[4]
IO_L7N_T1_34
AB1
DDR3_A[5]
IO_L6P_T0_34
U3
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ARTIX-7 FPGA Development Board AX7203 User Manual
DDR3_A[6] DDR3_A[7] DDR3_A[8] DDR3_A[9] DDR3_A[10] DDR3_A[11] DDR3_A[12] DDR3_A[13] DDR3_A[14] DDR3_BA[0] DDR3_BA[1] DDR3_BA[2] DDR3_S0 DDR3_ DDR3_CAS DDR3_WE DDR3_ODT DDR3_RESET DDR3_CLK_P DDR3_CLK_N DDR3_CKE
IO_L5P_T0_34 IO_L1P_T0_34 IO_L2N_T0_34 IO_L2P_T0_34 IO_L5N_T0_34 IO_L4P_T0_34 IO_L4N_T0_34 IO_L1N_T0_34 IO_L6N_T0_VREF_34 IO_L9N_T1_DQS_34 IO_L9P_T1_DQS_34 IO_L11P_T1_SRCC_34 IO_L8P_T1_34 IO_L12P_T1_MRCC_34 IO_L12N_T1_MRCC_34 IO_L7P_T1_34 IO_L14N_T2_SRCC_34 IO_L15P_T2_DQS_34 IO_L3P_T0_DQS_34 IO_L3N_T0_DQS_34 IO_L14P_T2_SRCC_34
W1 T1 V2 U2 Y1 W2 Y2 U1 V3 AA3 Y3 Y4 AB3 V4 W4 AA1 U5 W6 R3 R2 T5
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ARTIX-7 FPGA Development Board AX7203 User Manual
Bagean 2.6: QSPI Flash
Papan inti FPGA AC7200 dilengkapi siji 128MBit QSPI FLASH, lan model W25Q256FVEI, sing nggunakake 3.3V CMOS voltage standar. Amarga sifat non-molah malih saka QSPI FLASH, bisa digunakake minangka piranti boot kanggo sistem kanggo nyimpen gambar boot saka sistem. Gambar kasebut utamane kalebu bit FPGA files, kode aplikasi ARM, kode aplikasi inti lan data pangguna liyane files. Model khusus lan paramèter sing gegandhengan karo QSPI FLASH ditampilake.
Posisi U8
Model N25Q128
Kapasitas 128M Bit
Pabrik Numonyx
Spesifikasi QSPI FLASH
QSPI FLASH disambungake menyang pin khusus BANK0 lan BANK14 saka chip FPGA. Pin jam disambungake menyang CCLK0 saka BANK0, lan data liyane lan sinyal chip pilih disambungake menyang D00 ~ D03 lan pin FCS saka BANK14. Nuduhake sambungan hardware QSPI Flash.
QSPI Flash Schematic QSPI Flash pin assignments:
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ARTIX-7 FPGA Development Board AX7203 User Manual
Jeneng Net QSPI_CLK QSPI_CS QSPI_DQ0 QSPI_DQ1 QSPI_DQ2 QSPI_DQ3
Jeneng PIN FPGA CCLK_0
IO_L6P_T0_FCS_B_14 IO_L1P_T0_D00_MOSI_14 IO_L1N_T0_D01_DIN_14
IO_L2P_T0_D02_14 IO_L2N_T0_D03_14
FPGA P/N L12 T19 P22 R22 P21 R21
QSPI ing Papan Inti
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.7: Lampu LED ing Papan Inti
Ana 3 lampu LED abang ing papan inti AC7200 FPGA, salah sijine yaiku lampu indikator daya (PWR), siji yaiku lampu LED konfigurasi (DONE), lan siji yaiku lampu LED pangguna. Nalika Papan inti powered, indikator daya bakal madhangi; nalika FPGA diatur, konfigurasi LED bakal madhangi. Lampu LED pangguna disambungake menyang IO BANK34, pangguna bisa ngontrol lan mateni lampu kanthi program kasebut. Nalika IO voltage disambungake menyang pangguna LED dhuwur, pangguna LED mati. Nalika sambungan IO voltage kurang, pangguna LED bakal surem. Diagram skematis sambungan hardware lampu LED ditampilake:
Lampu LED ing Papan inti Skema
Lampu LED ing Papan Inti Pangguna LED Pin Assignment
Jeneng sinyal LED1
Jeneng Pin FPGA IO_L15N_T2_DQS_34
Nomer Pin FPGA W5
Deskripsi User LED
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ARTIX-7 FPGA Development Board AX7203 User Manual
Bagean 2.8: Tombol Reset
Ana tombol reset ing papan inti AC7200 FPGA. Tombol reset disambungake menyang IO normal BANK34 chip FPGA. Pangguna bisa nggunakake tombol reset iki kanggo miwiti program FPGA. Nalika tombol dipencet ing desain, sinyal voltage input kanggo IO kurang, lan sinyal reset bener; nalika tombol ora dipencet, input sinyal kanggo IO dhuwur. Diagram skematis sambungan tombol reset ditampilake:
Skema Tombol Reset
tombol Reset ing Papan inti Reset tombol pin assignment
Jeneng Sinyal RESET_N
Jeneng Pin ZYNQ IO_L17N_T2_34
Nomer Pin ZYNQ T6
Deskripsi FPGA system reset
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ARTIX-7 FPGA Development Board AX7203 User Manual
Bagian 2.9: JTAG Antarmuka
Ing JTAG soket test J1 dilindhungi undhang-undhang ing papan inti AC7200 kanggo JTAG download lan debugging nalika Papan inti digunakake piyambak. Gambar minangka bagéan skematik saka JTAG port, kang melu TMS, TDI, TDO, TCK. , GND, +3.3V enem sinyal iki.
JTAG Skema Antarmuka JTAG antarmuka J1 ing AC7200 FPGA inti Papan nggunakake 6-pin 2.54mm pitch single-row test bolongan. Yen sampeyan kudu nggunakake JTAG sambungan kanggo debug ing Papan inti, sampeyan kudu solder 6-pin single-baris pin header. nuduhake JTAG antarmuka J1 ing Papan inti AC7200 FPGA.
JTAG Antarmuka ing Papan Inti
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ARTIX-7 FPGA Development Board AX7203 User Manual
Bagean 2.10: Antarmuka Daya ing Papan Inti
Supaya Papan inti AC7200 FPGA bisa digunakake piyambak, Papan inti dilindhungi undhang-undhang karo antarmuka daya 2PIN (J3). Nalika pangguna sumber daya kanggo Papan inti liwat antarmuka daya 2PIN (J3), iku ora bisa powered liwat Papan operator. Yen ora, konflik saiki bisa kedadeyan.
Antarmuka Daya ing Papan Inti
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 2.11: Papan kanggo Papan Konektor
Papan inti wis total papat Papan-kacepetan dhuwur kanggo konektor Papan. Papan inti nggunakake papat konektor antar-papan 80-pin kanggo nyambung menyang papan operator. Port IO saka FPGA disambungake menyang papat konektor kanthi nuntun diferensial. Jarak pin konektor yaiku 0.5mm, lebokake menyang papan menyang konektor papan ing papan operator kanggo komunikasi data kanthi kacepetan dhuwur.
Papan inti wis total papat Papan-kacepetan dhuwur kanggo konektor Papan. Papan inti nggunakake papat konektor antar-papan 80-pin kanggo nyambung menyang papan operator. Port IO saka FPGA disambungake menyang papat konektor kanthi nuntun diferensial. Jarak pin konektor yaiku 0.5mm, lebokake menyang papan menyang konektor papan ing papan operator kanggo komunikasi data kanthi kacepetan dhuwur.
Papan kanggo Papan konektor CON1 Papan 80-pin kanggo Papan konektor CON1, kang digunakake kanggo nyambungake
karo sumber daya VCCIN (+5V) lan lemah ing Papan operator, ngluwihi IOs normal saka FPGA. Sampeyan kudu nyatet kene sing 15 pin CON1 disambungake menyang port IO saka BANK34, amarga sambungan BANK34 disambungake menyang DDR3. Mulane, voltage standar kabeh IOs BANK34 iki 1.5V. Pin Assignment saka Papan kanggo Papan Konektor CON1
CON1 PIN PIN1 PIN3 PIN5 PIN7 PIN9
Jeneng Sinyal
VCCIN VCCIN VCCIN VCCIN GND
Pin FPGA Voltage Tataran
–
+5V
–
+5V
–
+5V
–
+5V
–
lemah
CON1 PIN PIN2 PIN4 PIN6 PIN8 PIN10
Jeneng Sinyal
VCCIN VCCIN VCCIN VCCIN
GND
Pin FPGA Voltage Tataran
–
+5V
–
+5V
–
+5V
–
+5V
–
lemah
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71
NC NC NC NC GND B13_L5_P B13_L5_N B13_L7_P B13_L7_P GND B13_L3_P B13_L3_N B34_L23_P B34_L23_N GND B34_L18_N GND B34_L18_N B34_L19_C34 VN XADC_VP NC NC GND B19_L16_N B1_L16_P B1_L16_N B4_L16_P GND B4_L16_N
Y13 AA14 AB11 AB12 AA13 AB13 Y8 Y7 AA6 Y6 V7 W7 M9 L10 F14 F13 E14 E13 D15
Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 1.5V 1.5V Ground 1.5V 1.5V 1.5V 1.5V Ground ADC ADC Ground 3.3V 3.3V 3.3V 3.3V Ground
PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72
NC NC B13_L4_P B13_L4_N GND B13_L1_P B13_L1_N B13_L2_P B13_L2_N GND B13_L6_P B13_L6_N B34_L20_P B34_L20_N GND B34_L21_N GND B34_L21_L34 _L22_N GND NC B34_L22 B34_L25_P B34_L24_N GND NC NC NC NC GND NC
AA15 AB15 Y16 AA16 AB16 AB17 W14 Y14 AB7 AB6 V8 V9 AA8 AB8 –
3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 1.5V 1.5V Ground 1.5V 1.5V 1.5V 1.5V Ground
U7
1.5V
W9
1.5V
Y9
1.5V
–
lemah
–
–
–
–
–
–
–
–
–
lemah
–
–
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ARTIX-7 FPGA Development Board AX7203 User Manual
Papan kanggo Papan Konektor CON2 80-pin wadon sambungan header CON2 digunakake kanggo ngluwihi normal
IO saka BANK13 lan BANK14 saka FPGA. Voltage standar saka loro BANK punika 3.3V. Pin Assignment saka Papan kanggo Papan Konektor CON2
CON1 Pin
Jeneng Sinyal
PIN1 B13_L16_P
PIN3 B13_L16_N
PIN5 B13_L15_P
PIN7 B13_L15_N
PIN 9
GND
PIN11 B13_L13_P
PIN13 B13_L13_N
PIN15 B13_L12_P
PIN17 B13_L12_N
PIN 19
GND
PIN21 B13_L11_P
PIN23 B13_L11_N
PIN25 B13_L10_P
PIN27 B13_L10_N
PIN 29
GND
PIN31 B13_L9_N
PIN33 B13_L9_P
PIN35 B13_L8_N
PIN37 B13_L8_P
PIN 39
GND
PIN41 B14_L11_N
PIN43 B14_L11_P
PIN45 B14_L14_N
PIN47 B14_L14_P
Pin FPGA W15 W16 T14 T15 V13 V14 W11 W12 Y11 Y12 V10 W10 AA11 AA10 AB10 AA9 V20 U20 V19 V18
Voltage Level 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V
CON1 Pin PIN2 PIN4 PIN6 PIN8 PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48
Jeneng Sinyal
B14_L16_P B14_L16_N B13_L14_P B13_L14_N
GND B14_L10_P B14_L10_N B14_L8_N B14_L8_P
GND B14_L15_N B14_L15_P B14_L17_P B14_L17_N
GND B14_L6_N B13_IO0 B14_L7_N B14_L7_P
GND B14_L4_P B14_L4_N B14_L9_P B14_L9_N
Pin FPGA Voltage
tingkat
V17
3.3V
W17
3.3V
U15
3.3V
V15
3.3V
–
lemah
AB21
3.3V
AB22
3.3V
AA21
3.3V
AA20
3.3V
–
lemah
AB20
3.3V
AA19
3.3V
AA18
3.3V
AB18
3.3V
–
lemah
T20
3.3V
Y17
3.3V
W22
3.3V
W21
3.3V
–
lemah
T21
3.3V
U21
3.3V
Y21
3.3V
Y22
3.3V
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79
GND B14_L5_N B14_L5_P B14_L18_N B14_L18_P
GND B13_L17_P B13_L17_N B14_L21_N B14_L21_P
GND B14_L22_P B14_L22_N B14_L24_N B14_L24_P
B14_IO0
R19 P19 U18 U17
T16 U16 P17 N17
P15 R16 R17 P16 P20
Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V 3.3V
PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72 PIN74 PIN76 PIN78 PIN80
GND B14_L12_N B14_L12_P B14_L13_N B14_L13_P
GND B14_L3_N B14_L3_P B14_L20_N B14_L20_P
GND B14_L19_N B14_L19_P B14_L23_P B14_L23_N B14_IO25
W20 W19 Y19 Y18
V22 U22 T18 R18
R14 P14 N13 N14 N15
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V 3.3V
Papan kanggo Papan Konektor CON3 80-pin konektor CON3 digunakake kanggo ngluwihi IO normal saka
BANK15 lan BANK16 saka FPGA. Kajaba iku, papat JTAG sinyal uga disambungake menyang Papan operator liwat konektor CON3. Voltage standar BANK15 lan BANK16 bisa diatur dening chip LDO. LDO sing diinstal standar yaiku 3.3V. Yen sampeyan pengin output tingkat standar liyane, sampeyan bisa ngganti karo LDO cocok. Pin Assignment Papan kanggo Papan Konektor CON3
CON1 PIN PIN1 PIN3 PIN5 PIN7
Jeneng Sinyal
B15_IO0 B16_IO0 B15_L4_P B15_L4_N
Pin FPGA J16 F15 G17 G18
Voltage Tataran
CON1 Pin
3.3V PIN2
3.3V PIN4
3.3V PIN6
3.3V
PIN 8
Jeneng Sinyal
B15_IO25 B16_IO25 B16_L21_N B16_L21_P
Pin FPGA Voltage Tataran
M17
3.3V
F21
3.3V
A21
3.3V
B21
3.3V
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71
GND B15_L2_P B15_L2_N B15_L12_P B15_L12_N
GND B15_L11_P B15_L11_N B15_L1_N B15_L1_P
GND B15_L5_P B15_L5_N B15_L3_N B15_L3_P
GND B15_L19_P B15_L19_N B15_L20_P B15_L20_N
GND B15_L14_P B15_L14_N B15_L21_P B15_L21_N
GND B15_L23_P B15_L23_N B15_L22_P B15_L22_N
GND B15_L24_P
G15 G16 J19 H19
J20 J21 G13 H13
J15 H15 H14 J14
K13 K14 M13 L13
L19 L20 K17 J17 L16 K16 L14 L15 M15
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V
PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72
GND B16_L23_P B16_L23_N B16_L22_P B16_L22_N
GND B16_L24_P B16_L24_N B15_L8_N B15_L8_P
GND B15_L7_N B15_L7_P B15_L9_P B15_L9_N
GND B15_L15_N B15_L15_P B15_L6_N B15_L6_P
GND B15_L13_N B15_L13_P B15_L10_P B15_L10_N
GND B15_L18_P B15_L18_N B15_L17_N B15_L17_P
GND B15_L16_P
E21 D21 E22 D22
G21 G22 G20 H20
H22 J22 K21 K22
M22 N22 H18 H17
K19 K18 M21 L21
N20 M20 N19 N18
M18
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN73 B15_L24_N
M16
3.3V
PIN74 B15_L16_N
L18
3.3V
PIN 75
NC
–
PIN 76
NC
–
PIN77 FPGA_TCK
V12
3.3V
PIN 78
FPGA_TDI
R13
3.3V
PIN79 FPGA_TDO
U13
3.3V
PIN80 FPGA_TMS
T13
3.3V
Konektor Papan menyang Papan CON4 Konektor 80-Pin CON4 digunakake kanggo ngluwihi IO lan GTP normal
data kacepetan dhuwur lan sinyal jam saka FPGA BANK16. Voltage standar port IO saka BANK16 bisa diatur dening chip LDO. LDO sing diinstal standar yaiku 3.3V. Yen pangguna pengin output tingkat standar liyane, bisa diganti dening LDO cocok. Data-kacepetan dhuwur lan sinyal jam saka GTP strictly diferensial routed ing Papan inti. Garis data padha dawa lan disimpen ing interval tartamtu kanggo nyegah gangguan sinyal. Pin Assignment Papan kanggo Papan Konektor CON4
CON1 Pin PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29
Jeneng Sinyal
NC NC
Pin FPGA Voltage tingkat -
–
CON1 Pin NC NC
NC
–
NC
NC
–
NC
GND NC
–
PIN lemah 10
–
PIN 12
NC
–
PIN 14
GND
–
PIN lemah 16
MGT_TX3_P
D7 Diferensial PIN18
MGT_TX3_N
C7 Diferensial PIN20
GND
–
PIN lemah 22
MGT_RX3_P D9 Diferensial PIN24
MGT_RX3_N
C9 Diferensial PIN26
GND
– Lemah
PIN 28
MGT_TX1_P
D5 Diferensial PIN30
Jeneng Sinyal FPGA Pin Voltage
tingkat
–
NC
–
NC
–
NC
–
NC
GND
–
lemah
MGT_TX2_P
B6 Diferensial
MGT_TX2_N
A6 Diferensial
GND
–
lemah
MGT_RX2_P
B10 Diferensial
MGT_RX2_N
A10 Diferensial
GND
–
lemah
MGT_TX0_P
B4 Diferensial
MGT_TX0_N
A4 Diferensial
GND
–
lemah
MGT_RX0_P
B8 Diferensial
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ARTIX-7 FPGA Development Board AX7203 User Manual
PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79
MGT_TX1_N GND
MGT_RX1_P MGT_RX1_N
GND B16_L5_P B16_L5_N B16_L7_P B16_L7_N
GND B16_L9_P B16_L9_N B16_L11_P B16_L11_N
GND B16_L13_P B16_L13_N B16_L15_P B16_L15_N
GND B16_L17_P B16_L17_N B16_L19_P B16_L19_N
NC
C5 D11 C11 E16 D16 B15 B16 A15 A16 B17 B18 C18 C19 F18 E18 A18 A19 D20 C20 –
Tanah Diferensial
Diferensial Diferensial
Lemah 3.3V 3.3V 3.3V 3.3V
Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V Lemah 3.3V 3.3V 3.3V 3.3V
PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72 PIN74 PIN76 PIN78 PIN80
MGT_RX0_N GND
MGT_CLK1_P MGT_CLK1_N
GND B16_L2_P B16_L2_N B16_L3_P B16_L3_N
GND B16_L10_P B16_L10_N B16_L12_P B16_L12_N
GND B16_L14_P B16_L14_N B16_L16_P B16_L16_N
GND B16_L18_P B16_L18_N B16_L20_P B16_L20_N
NC
A8 Diferensial
–
lemah
F10 Diferensial
E10 Diferensial
–
lemah
F16
3.3V
E17
3.3V
C14
3.3V
C15
3.3V
–
lemah
A13
3.3V
A14
3.3V
D17
3.3V
C17
3.3V
–
lemah
E19
3.3V
D19
3.3V
B20
3.3V
A20
3.3V
–
lemah
F19
3.3V
F20
3.3V
C22
3.3V
B22
3.3V
–
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ARTIX-7 FPGA Development Board AX7203 User Manual
Bagean 2.12: Sumber Daya
Papan inti AC7200 FPGA didhukung dening DC5V liwat papan operator, lan didhukung dening antarmuka J3 nalika digunakake piyambak. Ati-ati supaya ora nyuplai daya kanthi antarmuka J3 lan papan operator bebarengan kanggo nyegah karusakan. Diagram desain sumber daya ing papan ditampilake ing.
Power Supply ing skema papan inti
Papan pangembangan didhukung dening + 5V lan diowahi dadi + 3.3V, + 1.5V, + 1.8V, + 1.0V sumber daya papat arah liwat papat chip sumber daya DC / DC TLV62130RGT. Arus output bisa nganti 3A saben saluran. VCCIO digawe dening siji LDOSPX3819M5-3-3. VCCIO utamané nyuplai daya kanggo BANK15 lan BANK16 saka FPGA. Pangguna bisa ngganti IO saka BANK15,16 kanggo vol bedatage standar dening ngganti chip LDO sing. 1.5V Ngasilake VTT lan VREF voltages dibutuhake dening DDR3 liwat TI kang TPS51200. Sumber daya 1.8V MGTAVTT MGTAVCC kanggo transceiver GTP digawe dening chip TPS74801 TI. Fungsi saben distribusi daya ditampilake ing tabel ing ngisor iki:
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ARTIX-7 FPGA Development Board AX7203 User Manual
Power Supply + 1.0V + 1.8V + 3.3V + 1.5V
VREF,VTT(+0.75V) MVCCIP(+3.3V) MGTAVTT(+1.2V)
MGTVCCAUX(+1.8V)
Fungsi Inti FPGA Voltage FPGA tambahan voltage, TPS74801 sumber daya VCCIO saka Bank0, Bank13 lan Bank14 saka FPGA, QSIP FLASH, Clock Crystal DDR3, Bank34 lan Bank35 saka FPGA
DDR3 FPGA Bank15, Bank16 GTP Transceiver Bank216 saka FPGA GTP Transceiver Bank216 saka FPGA
Amarga sumber daya Artix-7 FPGA nduweni syarat urutan daya, ing desain sirkuit, kita wis ngrancang miturut syarat daya chip, lan daya-on yaiku 1.0V->1.8V->(1.5 V, 3.3V, VCCIO) lan 1.0V-> MGTAVCC -> MGTAVTT, desain sirkuit kanggo njamin operasi normal chip.
Bagean 2.13: Diagram Struktur
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ARTIX-7 FPGA Development Board AX7203 User Manual
Bagean 3: Papan pembawa
Bagean 3.1: Papan pembawa Pambuka
Liwat introduksi fungsi sadurungé, sampeyan bisa ngerti fungsi saka bagean Papan operator
1-saluran PCIe x4 antarmuka transmisi data kacepetan dhuwur 2-saluran 10/100M/1000M Ethernet RJ-45 antarmuka 1-saluran antarmuka input video HDMI 1-saluran antarmuka output video HDMI 1-saluran USB Antarmuka Komunikasi Uart 1 Slot Kartu SD Antarmuka XADA EEPROM 2-saluran 40-pin port ekspansi JTAG antarmuka debugging 2 tombol independen 4 pangguna lampu LED
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.2: Antarmuka Ethernet Gigabit
Papan pangembangan AX7203 FPGA nyedhiyakake pangguna kanthi 2 saluran
Layanan komunikasi jaringan Gigabit liwat Micrel KSZ9031RNX
Chip Ethernet PHY. Chip KSZ9031RNX ndhukung 10/100/1000 Mbps
tingkat transmisi jaringan lan komunikasi karo FPGA liwat GMII
antarmuka. KSZ9031RNX ndhukung adaptasi MDI / MDX, macem-macem kacepetan
adaptasi, Master / budak adaptasi, lan support kanggo MDIO bis kanggo PHY
manajemen ndhaftar.
KSZ9031RNX bakal ndeteksi status tingkat sawetara IOs tartamtu kanggo
nemtokake mode kerjane sawise diuripake. Tabel 3-1-1 nggambaraken
informasi persiyapan standar sawise chip GPHY diuripake.
Instruksi Pin Konfigurasi
Nilai konfigurasi
PHYAD[2:0] CLK125_EN
SELRGV AN [1: 0] RX Tundha TX Tundha
Mode MDIO/MDC Alamat PHY 3.3V, 2.5V, 1.5/1.8V voltage pilihan Auto-rembugan konfigurasi
RX jam 2ns tundha TX jam 2ns tundha RGMII utawa GMII pilihan
Alamat PHY 011 3.3V
(10/100/1000M) adaptif Tundha tundha GMII
Tabel 3-2-1: Nilai konfigurasi standar chip PHY
Nalika jaringan disambungake menyang Gigabit Ethernet, transmisi data FPGA lan chip PHY KSZ9031RNX disampekno liwat bis GMII, jam transmisi 125Mhz. Jam nampa E_RXC diwenehake dening chip PHY, jam transmisi E_GTXC diwenehake dening FPGA, lan data kasebut s.ampdipimpin ing pojok munggah jam.
Nalika jaringan disambungake menyang 100M Ethernet, transmisi data FPGA lan chip PHY KSZ9031RNX disampekno liwat bis GMII, jam transmisi 25Mhz. Jam nampa E_RXC diwenehake dening chip PHY, jam transmisi E_GTXC diwenehake dening FPGA, lan data kasebut
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ARTIX-7 Papan Pangembangan FPGA AX7203 User Manual sampdipimpin ing pojok munggah jam.
Gambar 3-2-1: Skema Antarmuka Gigabit Ethernet
Figure 3-3-2: antarmuka Gigabit Ethernet ing Papan Carrier
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gigabit Ethernet Chip PHY1 pin assignments minangka nderek
Jeneng Sinyal E1_GTXC E1_TXD0 E1_TXD1 E1_TXD2 E1_TXD3 E1_TXEN E1_RXC E1_RXD0 E1_RXD1 E1_RXD2 E1_RXD3 E1_RXDV E1_MDC E1_MDIO E1_RESET
Nomer Pin FPGA E18 C20 D20 A19 A18 F18 B17 A16 B18 C18 C19 A15 B16 B15 D16
Deskripsi PHY1 RGMII ngirim jam
PHY1 Ngirim Data bit0 PHY1 Ngirim Data bit1 PHY1 Ngirim Data bit2 PHY1 Ngirim Data bit3 PHY1 Kirim Aktifake Sinyal PHY1 RGMII Nampa Jam PHY1 Nampa Data Bit0 PHY1 Nampa Data Bit1 PHY1 Nampa Data Bit2 PHY1 Nampa Data Bit3 PHY1 Manajemen nampa sinyal Clock data PHY1 data
PHY1 Reset Sinyal
Gigabit Ethernet Chip PHY2 pin assignments minangka nderek
Jeneng Sinyal E2_GTXC E2_TXD0 E2_TXD1 E2_TXD2 E2_TXD3 E2_TXEN E2_RXC E2_RXD0 E2_RXD1 E2_RXD2 E2_RXD3 E2_RXDV E2_MDC E2_MDIO E2_RESET
Nomer Pin FPGA A14 E17 C14 C15 A13 D17 E19 A20 B20 D19 C17 F19 F20 C22 B22
Deskripsi PHY2 RGMII ngirim jam
PHY2 Ngirim Data bit0 PHY2 Ngirim Data bit1 PHY2 Ngirim Data bit2 PHY2 Ngirim Data bit3 PHY2 Kirim Aktifake Sinyal PHY2 RGMII Nampa Jam PHY2 Nampa Data Bit0 PHY2 Nampa Data Bit1 PHY2 Nampa Data Bit2 PHY2 Nampa Data Bit3 PHY2 Manajemen nampa sinyal Clock data PHY2 data
PHY2 Reset Sinyal
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.3: Antarmuka PCIe x4
Papan pangembangan AX7203 FPGA nyedhiyakake antarmuka transfer data kecepatan tinggi industri PCIe x4. Antarmuka kertu PCIE cocog karo spesifikasi listrik kertu PCIe standar lan bisa digunakake langsung ing slot x4 PCIe PC normal.
Sinyal ngirim lan nampa antarmuka PCIe langsung disambungake menyang transceiver GTP saka FPGA. Patang saluran sinyal TX lan RX disambungake menyang FPGA ing sinyal diferensial, lan tingkat komunikasi saluran siji bisa nganti bandwidth bit 5G. Jam referensi PCIe diwenehake menyang papan pangembangan AX7203 FPGA dening slot PCIe PC kanthi frekuensi jam referensi 100Mhz.
Diagram desain antarmuka PCIe saka papan pangembangan AX7203 FPGA ditampilake ing Figure 3-3-1, ing ngendi sinyal ngirimake TX lan sinyal CLK jam referensi disambungake ing mode gabungan AC.
Gambar 3-3-1: skema PCIex4
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gambar 3-3-2: PCIex4 ing Papan Carrier
Tugas Pin Antarmuka PCIex4:
Jeneng Sinyal
Pin FPGA
PCIE_RX0_P
D11
PCIE_RX0_N
C11
PCIE_RX1_P
B8
PCIE_RX1_N
A8
PCIE_RX2_P
B10
PCIE_RX2_N
A10
PCIE_RX3_P
D9
PCIE_RX3_N
C9
PCIE_TX0_P
D5
PCIE_TX0_N
C5
PCIE_TX1_P
B4
PCIE_TX1_N
A4
PCIE_TX2_P
B6
PCIE_TX2_N
A6
PCIE_TX3_P
D7
PCIE_TX3_N
C7
PCIE_CLK_P
F10
PCIE_CLK_N
E10
Katrangan Saluran PCIE 0 Data Nampa Saluran PCIE Positif 0 Data Nampa Saluran PCIE Negatif 1 Data Nampa Saluran PCIE Positif 1 Data Nampa Saluran PCIE Negatif 2 Data Nampa Saluran PCIE Positif 2 Data Nampa Saluran PCIE Negatif 3 Data Nampa Saluran PCIE Positif 3 Data Nampa Negatif Saluran 0 Ngirim Data Positif Saluran PCIE 0 Ngirim Data Negatif Saluran PCIE 1 Ngirim Data Positif Saluran PCIE 1 Ngirim Data Negatif Saluran PCIE 2 Ngirim Data Positif PCIE Channel 2 Ngirim Data Negatif Saluran PCIE 3 Ngirim Data Saluran PCIE Positif 3 Ngirim Data Negatif
PCIE Referensi Jam Positif PCIE Referensi Jam Negatif
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ARTIX-7 FPGA Development Board AX7203 User Manual
Bagean 3.4: Antarmuka output HDMI
Antarmuka output HDMI, pilih chip enkoding SIL9134 HDMI (DVI) Silion Image, ndhukung nganti output 1080P@60Hz, ndhukung output 3D.
Antarmuka konfigurasi IIC SIL9134 uga disambungake menyang IO saka FPGA. SIL9134 diinisialisasi lan dikontrol dening pemrograman FPGA. Sambungan hardware antarmuka output HDMI ditampilake ing Gambar 3-4-1.
Gambar 3-4-1: Skema Output HDMI
Gambar 3-4-1: Output HDMI ing Papan Carrier
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ARTIX-7 FPGA Development Board AX7203 User Manual
Tugas Pin Input HDMI:
Jeneng Sinyal 9134_nRESET
9134_CLK 9134_HS 9134_VS 9134_DE 9134_D[0] 9134_D[1] 9134_D[2] 9134_D[3] 9134_D[4] 9134_D[5] 9134_D[6] 9134_D[7] 9134_D 8_D[9134] 9_D[9134] 10_D[ 9134] 11_D[9134] 12_D[9134] 13_D[9134] 14_D[9134] 15_D[9134] 16_D[9134] 17_D[9134] 18_D[9134] [19] 9134_D[20] [9134] 21_D[9134] 22_D[9134] 23_D[XNUMX] [XNUMX] [XNUMX_XNUMX] XNUMX] XNUMX_D[XNUMX]
Pin FPGA J19 M13 T15 T14 V13 V14 H14 J14 K13 K14 L13 L19 L20 K17 J17 L16 K16 L14 L15 M15 M16 L18 M18 N18 N19 M20 N20 L21 M21
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.5: antarmuka Input HDMI
Antarmuka output HDMI, pilih chip dekoder HDMI SIL9013 Silion Image, ndhukung input nganti 1080P@60Hz lan ndhukung output data ing macem-macem format.
Antarmuka konfigurasi IIC saka SIL9013 disambungake menyang IO saka FPGA. SIL9013 diinisialisasi lan dikontrol liwat pemrograman FPGA. Sambungan hardware antarmuka input HDMI ditampilake ing Gambar 3-5-1.
Gambar 3-5-1: Skema Input HDMI
Gambar 3-5-2: Input HDMI ing Papan Carrier
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ARTIX-7 FPGA Development Board AX7203 User Manual
Tugas Pin Input HDMI:
Jeneng Sinyal 9013_nRESET
9013_CLK 9013_HS 9013_VS 9013_DE 9013_D[0] 9013_D[1] 9013_D[2] 9013_D[3] 9013_D[4] 9013_D[5] 9013_D[6] 9013_D[7] 9013_D 8_D[9013] 9_D[9013] 10_D[ 9013] 11_D[9013] 12_D[9013] 13_D[9013] 14_D[9013] 15_D[9013] 16_D[9013] 17_D[9013] 18_D[9013] [19] 9013_D[20] [9013] 21_D[9013] 22_D[9013] 23_D[XNUMX] [XNUMX] [XNUMX_XNUMX] XNUMX] XNUMX_D[XNUMX]
Nomer Pin FPG H19 K21 K19 K18 H17 H18 N22 M22 K22 J22 H22 H20 G20 G22 G21 D22 E22 D21 E21 B21 A21 F21 M17 J16 F15 G17 G18 G15 G16
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ARTIX-7 FPGA Development Board AX7203 User Manual
Part 3.6: Slot kertu SD
Kertu SD (Secure Digital Memory Card) minangka kertu memori adhedhasar proses memori lampu kilat semikonduktor. Iki rampung ing taun 1999 dening konsep Jepang sing dipimpin Panasonic, lan peserta Toshiba lan SanDisk saka Amerika Serikat nindakake riset lan pangembangan sing akeh. Ing taun 2000, perusahaan-perusahaan kasebut ngluncurake Asosiasi SD (Asosiasi Digital Aman), sing nduwe barisan sing kuat lan narik akeh vendor. Iki kalebu IBM, Microsoft, Motorola, NEC, Samsung, lan liya-liyane. Didhukung dening manufaktur terkemuka iki, kertu SD wis dadi kertu memori sing paling akeh digunakake ing piranti digital konsumen.
Kertu SD minangka piranti panyimpenan sing umum banget. Kertu SD lengkap ndhukung mode SPI lan mode SD. Kertu SD sing digunakake yaiku kertu MicroSD. Diagram skematis ditampilake ing Gambar 3-6-1.
Gambar 3-6-1: Skema Card SD
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ARTIX-7 FPGA Development Board AX7203 User Manual
Figure 3-6-2: Slot kertu SD ing Papan Carrier
Tugas pin slot kertu SD:
Jeneng Sinyal SD_CLK SD_CMD SD_CD_N SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3
Mode SD
PIN FPGA AB12 AB11 F14 AA13 AB13 Y13 AA14
Part 3.7: USB kanggo Port Serial
Papan pangembangan AX7203 FPGA kalebu chip USB-UAR saka Silicon Labs CP2102GM. Antarmuka USB nggunakake antarmuka USB MINI. Bisa disambungake menyang port USB saka PC ndhuwur kanggo komunikasi data serial karo kabel USB. Diagram skematis desain sirkuit USB Uart ditampilake ing Gambar 3-7-1:
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ARTIX-7 Papan Pengembangan FPGA AX7203 Panduan Pengguna Gambar 3-7-1: Skema port USB ke serial
Figure 3-7-2: USB kanggo port serial ing Papan Carrier
Loro pratondho LED (LED3 lan LED4) disetel kanggo sinyal port serial, lan silkscreen ing PCB punika TX lan RX, nuduhake yen port serial wis transmisi data utawa reception, minangka ditampilake ing ngisor iki Figure 3-3-3
Gambar 3-7-3: Komunikasi Port Serial Skema Indikator LED
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ARTIX-7 FPGA Development Board AX7203 User Manual
USB to serial port pin assignment:
Jeneng Sinyal UART1_RXD UART1_TXD
PIN FPGA P20 N15
Bagean 3.8: EEPROM 24LC04
Papan operator AX7013 ngemot EEPROM, model 24LC04, lan nduweni kapasitas 4Kbit (2*256*8bit). Iku kasusun saka loro pamblokiran 256-bait lan komunikasi liwat bis IIC. EEPROM onboard yaiku sinau babagan komunikasi karo bis IIC. Sinyal I2C saka EEPROM disambungake menyang port BANK14 IO ing sisih FPGA. Gambar 3-8-1 ing ngisor iki nuduhake desain EEPROM
Gambar 3-8-1: Skema EEPROM
Gambar 3-8-2: EEPROM ing Papan Carrier
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ARTIX-7 FPGA Development Board AX7203 User Manual
EEPROM Pin Assignment
Jeneng Net EEPROM_I2C_SCL EEPROM_I2C_SDA
PIN FPGA F13 E14
Bagean 3.9: Header Expansion
Papan operator dilindhungi undhang-undhang karo rong 0.1inch standar 40-pin expansion bandar J11 lan J13, kang digunakake kanggo nyambungake modul ALINX utawa sirkuit external dirancang dening pangguna. Port expansion wis 40 sinyal, kang 1-saluran 5V sumber daya, 2-saluran 3.3 V sumber daya, 3-saluran lemah lan 34 IOs. Aja langsung nyambungake IO menyang piranti 5V supaya ora kobong FPGA. Yen sampeyan pengin nyambungake peralatan 5V, sampeyan kudu nyambungake chip konversi tingkat.
Resistor 33 ohm disambungake kanthi seri antarane port ekspansi lan sambungan FPGA kanggo nglindhungi FPGA saka vol eksternal.tage utawa saiki. Sirkuit port expansion (J11) ditampilake ing Figure 3-9-1.
Gambar 3-9-1: Skema header ekspansi J11
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ARTIX-7 FPGA Development Board AX7203 User Manual
Tokoh 3-9-2 rinci port expansion J4 ing Papan operator. Pin1 lan Pin2 saka port expansion wis ditandhani ing Papan.
Gambar 3-9-2: Header ekspansi J11 ing papan Carrier
J11 Expansion Header Pin Assignment
Nomer Pin
Pin FPGA
Nomer Pin
Pin FPGA
1
GND
2
+5V
3
P16
4
R17
5
R16
6
P15
7
N17
8
P17
9
U16
10
T16
11
U17
12
U18
13
P19
14
R19
15
V18
16
V19
17
U20
18
V20
19
AA9
20
AB10
21
AA10
22
AA11
23
W10
24
V10
25
Y12
26
Y11
27
W12
28
W11
29
AA15
30
AB15
31
Y16
32
AA16
33
AB16
34
AB17
35
W14
36
Y14
37
GND
38
GND
39
+3.3V
40
+3.3V
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gambar 3-9-3: Skema header ekspansi J13
Tokoh 3-9-4 rinci port expansion J13 ing Papan operator. Pin1 lan Pin2 saka port expansion wis ditandhani ing Papan.
Gambar 3-9-4: Header ekspansi J13 ing papan operator
J13 Expansion Header Pin Assignment
Nomer Pin
Pin FPGA
1
GND
3
W16
5
V17
7
U15
Nomer Pin 2 4 6 8
Pin FPGA + 5V W15 W17 V15
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ARTIX-7 FPGA Development Board AX7203 User Manual
9
AB21
10
AB22
11
AA21
12
AA20
13
AB20
14
AA19
15
AA18
16
AB18
17
T20
18
Y17
19
W22
20
W21
21
T21
22
U21
23
Y21
24
Y22
25
W20
26
W19
27
Y19
28
Y18
29
V22
30
U22
31
T18
32
R18
33
R14
34
P14
35
N13
36
N14
37
GND
38
GND
39
+3.3V
40
+3.3V
Bagian 3.10: JTAG Antarmuka
AJTAG antarmuka dilindhungi undhang-undhang ing Papan operator AX7203 FPGA kanggo download program FPGA utawa perangkat kukuh kanggo FLASH. Kanggo nyegah karusakan ing chip FPGA sing disebabake panas plugging, dioda proteksi ditambahake menyang JTAG sinyal kanggo mesthekake yen voltage saka sinyal ing sawetara ditampa dening FPGA supaya karusakan saka chip FPGA.
Gambar 3-10-1: JTAG Skema Antarmuka
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gambar 3-10-2: JTAG Antarmuka ing papan operator
Ati-ati supaya ora hot swap nalika JTAG kabel wis kepasang lan copot.
Bagean 3.11: Antarmuka XADC (ora diinstal kanthi gawan)
Papan operator AX7203 wis antarmuka konektor XADC lengkap, lan konektor nggunakake 2 × 8 0.1inch Jarak pin pindho baris. Antarmuka XADC ngluwihi telung pasang antarmuka input diferensial ADC menyang konverter analog-to-digital 12-Bit 1Msps saka FPGA. Siji pasangan antarmuka diferensial disambungake menyang saluran input analog diferensial khusus VP / VN saka FPGA, lan rong pasangan liyane disambungake kanthi beda menyang saluran input analog tambahan (saluran analog 0 lan saluran analog 9). Gambar 3-11-1 nuduhake filter anti-aliasing sing dirancang kanggo telung input XADC diferensial.
Gambar 3-11-1: Skema Filter Anti-Aliasing
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gambar 3-11-2: Skema Konektor XADC
Gambar 3-11-3: Konektor XADC ing Papan Carrier
XADC Pin Assignment
Antarmuka XADC
Input Pin FPGA amplitude
Katrangan
12 56 910
VP_0 : L10 VN_0 : M9 AD9P : J15 AD9N : H15 AD0P : H13 AD0N : G13
Puncak nganti puncak saluran input XADC spesifik FPGA 1V
Puncak nganti puncak 1V Puncak nganti puncak 1V
Saluran input XADC sing dibantu FPGA 9 (bisa digunakake minangka IO normal)
Saluran input XADC sing dibantu FPGA 0 (bisa digunakake minangka IO normal)
Bagean 3.12: tombol
Papan operator AX7203 FPGA ngemot rong tombol pangguna KEY1~KEY2. Kabeh tombol disambungake menyang IO normal FPGA. Tombol aktif kurang. Nalika tombol dipencet, IO input voltage saka FPGA kurang. Nalika tombol ora ditekan, IO input voltage saka FPGA dhuwur. Sirkuit saka bagean tombol ditampilake ing Figure 3-12-1.
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gambar 3-12-1: Skema kunci
Gambar 3-13-2: Loro tombol ing Papan Carrier
tombol Pin Assignment
Jeneng Net KEY1 KEY2
PIN FPGA J21 E13
Bagean 3.13: Cahya LED
Ana pitung LED abang ing papan operator AX7203 FPGA, salah sijine yaiku indikator daya (PWR), loro yaiku data USB Uart nampa lan ngirim indikator, lan papat yaiku lampu LED pangguna (LED1~LED4). Nalika Papan diuripake, indikator daya bakal murup; Pangguna LED1~LED4 disambungake menyang IO normal saka FPGA. Nalika IO voltage disambungake menyang pangguna LED diatur tingkat kurang, pangguna LED murup. Nalika disambungake IO voltage dikonfigurasi minangka tingkat dhuwur, pangguna LED bakal dipateni. Ing
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ARTIX-7 FPGA Development Board AX7203 User Manual
diagram skematis saka sambungan hardware LED pangguna ditampilake ing Figure 3-13-1.
Gambar 3-13-1: Skema LED pangguna
Gambar 3-13-2: LED pangguna ing papan Carrier
Pin assignment saka lampu LED pangguna
Jeneng Sinyal LED1 LED2 LED3 LED4
PIN FPGA B13 C13 D14 D15
Bagean 3.14: Sumber Daya
Daya input voltage saka papan pangembangan AX7203 FPGA yaiku DC12V. Papan pangembangan uga ndhukung daya saka antarmuka PCIe lan ndhukung sumber daya langsung saka sumber daya sasis ATX (12V).
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ARTIX-7 FPGA Development Board AX7203 User Manual
Gambar 3-14-1: Metode catu daya kanggo Papan FPGA AX7203 Papan operator FPGA ngowahi vol +12Vtage menyang + 5V, +3.3V, +1.8V lan +1.2V papat-cara sumber daya liwat 4-saluran DC / DC power supply chip MP1482. Kajaba iku, sumber daya +5V ing papan operator FPGA nyedhiyakake daya menyang papan inti FPGA AC7100B liwat konektor antar-papan. Desain sumber daya ing expansion ditampilake ing Figure 3-14-2.
Gambar 3-14-2: Skema sumber daya ing Papan Carrier
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ARTIX-7 Papan Pengembangan FPGA AX7203 Manual Pangguna Gambar 3-14-3: Sirkuit Pasokan Daya ing papan Carrier
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Dokumen / Sumber Daya
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Papan Pangembangan ALINX AX7203 FPGA [pdf] Manual pangguna AX7203 Papan Pengembangan FPGA, AX7203, Papan Pengembangan FPGA, Papan Pengembangan, Papan |
