AX7203 FPGA Development Board
Bayanin samfur
ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
| Sigar | Rev. 1.2 |
|---|---|
| Kwanan wata | 2023-02-23 |
| Saki Ta | Rachel Zhou |
| Bayani | Sakin Farko |
Sashe na 1: Gabatarwar Hukumar Ci gaban FPGA
Kwamitin ci gaban AX7203 FPGA shine babban allo + mai ɗaukar kaya
dandali na hukumar da ke ba da damar haɓaka haɓaka na biyu masu dacewa
amfani da core board. Yana amfani da allo mai sauri mai sauri
mai haɗawa tsakanin babban allo da allon ɗauka.
Kwamitin jigilar kayayyaki na AX7203 yana ba da musaya na yanki daban-daban,
ciki har da:
- 1 PCIex4
- 2 Gigabit Ethernet musaya
- 1 HDMI Fitar dubawa
- 1 HDMI Input interface
- 1 Uart Interface
- 1 katin SD Ramin
- XADC connector interface (ba a shigar da shi ta tsohuwa ba)
- 2-hanyar 40-pin fadada kai
- Wasu maɓallai
- LED
- Farashin EEPROM
Kashi na 2: AC7200 Core Board Gabatarwa
Babban allon AC7200 ya dogara ne akan jerin XILINX's ARTIX-7 200T
Saukewa: AC7200-2FGG484I. Yana da babban aiki core allon dace da
sadarwar bayanai mai sauri, sarrafa hoton bidiyo, da
high-gudun bayanai saye.
Mahimman abubuwan da ke cikin allon AC7200 sun haɗa da:
- Guda biyu na MICRON's MT41J256M16HA-125 DDR3 kwakwalwan kwamfuta tare da
iya aiki na 4Gbit kowanne, yana ba da faɗin bas ɗin bayanai 32-bit har zuwa
25Gb karanta/rubutu bandwidth tsakanin FPGA da DDR3. - 180 daidaitattun tashoshin IO na matakin 3.3V
- 15 daidaitattun tashoshin IO na matakin 1.5V
- 4 nau'i-nau'i na sigina daban-daban na GTP mai sauri RX/TX
- Daidaita tsayi da bambance-bambancen sarrafawa tsakanin
FPGA guntu da ke dubawa - Karamin girman 45*55 (mm)
Umarnin Amfani da samfur
Don amfani da ARTIX-7 FPGA Development Board AX7203, bi waɗannan
matakai:
- Haɗa ainihin allo da allon ɗauka ta amfani da babban sauri
inter-board connector. - Idan an buƙata, shigar da ƙirar XADC ta amfani da abin da aka bayar
mai haɗawa. - Haɗa duk wani yanki da ake so zuwa abubuwan da ke akwai a kunne
hukumar dakon kaya, kamar na'urorin PCIex4, Gigabit Ethernet
na'urori, na'urorin HDMI, na'urorin Uart, katunan SD, ko na waje
fadada kai. - Ƙarfin wutar lantarki ta hanyar amfani da wutar lantarki mai dacewa
wadata.
ARTIX-7 FPGA Development Board
Farashin AX7203
Manual mai amfani
ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Rikodin Sigar
Shafin Rev 1.2
Kwanan wata 2023-02-23
Sakin Rachel Zhou
Bayanin Sakin Farko
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Teburin Abubuwan Ciki
Rikodin version .......................................................................................... ………………… 2 Kashi na 1: AC6 Core Board Gabatarwa …………………………………………………………………………
Sashe na 2.1: Chip FPGA .............. 10mhz mai banbanci na banbanci ......... Sashi ……………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………. 2.2 Part 12: Sake saita maɓallin .......................................................... JTAG Interface ...................................................................................................... 23 Sashe na 2.10: Jirgin zuwa Masu Haɗin allo……………………………………….. 24 Sashe na 2.11: Samar da Wutar Lantarki …………25 Sashe na 2.12: Tsari Tsari …………………………………………………………………………..32 Sashe na 2.13: allo mai ɗaukar kaya……………………………………… …………………………………………. 33 Sashi na 3: allon jigilar kaya Gabatarwa ………………………………………………. 34 Sashe na 3.1: Gigabit Ethernet Interface…………………………………………… 34: PCIe x3.2 Interface……………………………………………………………….. ………….35 Sashe na 3.3: HDMI Interface Interface ………………………………………… 4 Sashe na 38: USB zuwa Serial Port……………………………………………………….3.4 Sashe na 40: EEPROM 3.5LC42… ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………. 3.6: JTAG Interface …………………………………………………………………………. 51
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 3.11: XADC interface (ba a shigar da shi ta tsohuwa ba) ………………………………….. 52 Sashe 3.12: maɓallai .......... 53 Kashi na 3.13: LED Haske ....................................................................................... ………………………………………………………………………………………… 54
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Wannan dandali na ci gaba na ARTIX-7 FPGA (Module: AX7203) yana ɗaukar babban allo + yanayin allon jigilar kaya, wanda ya dace da masu amfani don amfani da babban allo don haɓaka sakandare.
A cikin zane na jirgi mai ɗaukar kaya, mun ƙaddamar da wadatar musaya don masu amfani, irin su 1 PCIex4 interface, 2 Gigabit Ethernet musaya, 1 HDMI Output interface, 1 HDMI Input interface, Uart Interface, SD katin Ramin da dai sauransu Ya dace da bukatun mai amfani. don PCIe babban musayar bayanai, sarrafa watsa bidiyo da sarrafa masana'antu. Dandali ne na ci gaba na ARTIX-7 FPGA mai “Mai-girma”. Yana ba da damar yin watsa shirye-shiryen bidiyo mai sauri, pre-validation da post-application na hanyar sadarwa da fiber sadarwa da sarrafa bayanai. Wannan samfurin ya dace sosai ga ɗalibai, injiniyoyi da sauran ƙungiyoyi masu tsunduma cikin ci gaban ARTIX-7FPGA.
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 1: Gabatarwar Hukumar Ci gaban FPGA
Dukkanin tsarin hukumar ci gaban AX7203 FPGA an gaji su ne daga daidaitaccen babban kwamitin mu + samfurin hukumar jigilar kaya. Ana amfani da mai haɗa allo mai sauri tsakanin allon mahimmanci da allon ɗaukar hoto.
Babban allon yana kunshe da FPGA + 2 DDR3 + QSPI FLASH, wanda ke aiwatar da ayyukan sarrafa bayanai masu sauri da adana FPGA, karatun bayanai da rubutu mai sauri tsakanin FPGA da DDR3s guda biyu, girman bit bayanan shine 32 ragowa, kuma bandwidth na dukkan tsarin ya kai 25Gb. /s(800M*32bit); Ƙarfin DDR3 guda biyu sun kai 8Gbit, wanda ya dace da buƙatar manyan buffer yayin sarrafa bayanai. FPGA da aka zaɓa shine guntun XC7A200T na jerin ARTIX-7 na XILINX, a cikin kunshin BGA 484. Mitar sadarwa tsakanin XC7A200T da DDR3 ta kai 400Mhz kuma adadin bayanai shine 800Mhz, wanda ke cika buƙatun sarrafa bayanan tashoshi masu saurin gaske. Bugu da ƙari, XC7A200T FPGA yana da siffofi guda huɗu na GTP masu sauri masu sauri tare da gudu har zuwa 6.6Gb / s ta kowane tashar, yana sa ya dace don sadarwar fiber-optic da kuma bayanan bayanan PCIe.
Kwamitin jigilar kaya na AX7203 yana faɗaɗa ƙaƙƙarfan ƙaƙƙarfan ƙaƙƙarfan ƙayyadaddun ƙayyadaddun kayan aiki, gami da 1 PCIex4 interface, 2 Gigabit Ethernet musaya, 1 HDMI Fitarwar dubawa, 1 HDMI Input interface, 1 Uart Interface, 1 katin katin SD, XADC mai haɗin haɗin yanar gizo, 2-hanyar 40-pin fadada fadadawa. header, wasu maɓalli, LED da EEPROM kewaye.
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto 1-1-1: Tsarin Tsari na AX7203 Ta wannan zane, zaku iya ganin musaya da ayyukan da Hukumar Ci gaban AX7203 FPGA ta ƙunshi: Artix-7 FPGA core board
Babban allon ya ƙunshi XC7A200T + 8Gb DDR3 + 128Mb QSPI FLASH. Akwai lu'ulu'u daban-daban na Sitime LVDS masu tsayi guda biyu, ɗaya a 200MHz ɗayan kuma a 125MHz, suna ba da ingantaccen shigar da agogo don tsarin FPGA da samfuran GTP. 1-tashar PCIe x4 interface Yana goyan bayan daidaitattun PCI Express 2.0, yana ba da saurin watsa bayanai na PCIe x4, ƙimar sadarwar tashoshi ɗaya har zuwa 5GBaud 2-tashar Gigabit Ethernet Interface RJ-45 interface Gigabit Ethernet interface guntu yana amfani da guntu na Micrel's KSZ9031RNX Ethernet PHY guntu. don samar da sabis na sadarwar cibiyar sadarwa ga masu amfani.
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Guntuwar KSZ9031RNX tana goyan bayan ƙimar watsa hanyar sadarwar 10/100/1000 Mbps; cikakken duplex da daidaitawa. 1-tashar HDMI Output interface Silion Image's SIL9134 HDMI guntu rufaffiyar guntu an zaɓa don tallafawa fitarwa har zuwa 1080P@60Hz da goyan bayan fitowar 3D. 1-tashar HDMI Input interface Silion Image's SIL9013 HDMI guntu decoder an zaɓi guntu, wanda ke goyan bayan shigarwar 1080P@60Hz kuma yana goyan bayan fitowar bayanai ta nau'i daban-daban. 1-tashar Uart zuwa kebul na dubawa 1 Uart zuwa kebul na kebul don sadarwa tare da kwamfuta don lalata mai amfani. Guntuwar tashar tashar jiragen ruwa ta serial guntu ce ta USB-UAR guntu na Silicon Labs CP2102GM, kuma kebul ke dubawa shine MINI kebul na USB. Micro SD katin mariƙin 1-tashar Micro SD katin, goyan bayan yanayin SD da yanayin SPI EEPROM A kan IIC dubawa EEPROM 24LC04 2-hanyar 40-pin fadada tashar jiragen ruwa 2-hanyar 40-pin 2.54mm farar fadada tashar jiragen ruwa za a iya haɗa zuwa daban-daban ALINX modules (binocular kamara, TFT LCD allon, high-gudun AD module, da dai sauransu). Tashar tashar fadada tana ƙunshe da tashar wutar lantarki ta 1 tashoshi 5V, tashar wutar lantarki ta 2 tashar 3.3V, ƙasa ta 3, tashar tashar IOs 34. JTAG Interface A 10-pin 0.1inch tazara daidaitaccen JTAG tashoshin jiragen ruwa don zazzagewar shirin FPGA da gyara kuskure. maɓalli 2 maɓalli; Maɓallin sake saiti 1 (a kan babban allo) LED Light 5 masu amfani da LEDs (1 akan babban allo da 4 akan allon ɗauka)
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Kashi na 2: AC7200 Core Board Gabatarwa
AC7200 (samfurin jirgi na ainihi, iri ɗaya a ƙasa) FPGA core board, ya dogara ne akan jerin XILINX's ARTIX-7 200T AC7200-2FGG484I. Yana da babban aiki core jirgin tare da babban gudun, high bandwidth da kuma high iya aiki. Ya dace da sadarwar bayanai mai sauri, sarrafa hoton bidiyo, sayan bayanai mai sauri, da sauransu.
Wannan babban allo na AC7200 yana amfani da guntu guda biyu na MICRON's MT41J256M16HA-125 DDR3 guntu, kowane DDR yana da ƙarfin 4Gbit; an haɗa kwakwalwan DDR guda biyu zuwa cikin faɗin bas ɗin bayanai 32-bit, kuma bandwidth karanta/rubutu tsakanin FPGA da DDR3 ya kai 25Gb; irin wannan tsari na iya saduwa da buƙatun sarrafa bayanan bandwidth mai girma.
Babban allon AC7200 yana faɗaɗa daidaitattun tashoshin IO na 180 na matakin 3.3V, daidaitattun tashoshin IO na 15 na matakin 1.5V, da nau'ikan nau'ikan 4 na GTP babban saurin RX/TX sigina na banbanta. Ga masu amfani waɗanda ke buƙatar IO mai yawa, wannan babban allon zai zama zaɓi mai kyau. Haka kuma, kewayawa tsakanin guntu FPGA da ke dubawa daidai yake da tsayi da aiki na bambance-bambancen, kuma girman allo shine kawai 45 * 55 (mm), wanda ya dace sosai don haɓaka na biyu.
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ARTIX-7 FPGA Development Board AX7203 Manual Mai amfani AC7200 Core Board (Gaba) View)
AC7200 Core Board (Rear View)
Kashi na 2.1: FPGA Chip
Kamar yadda aka ambata a sama, samfurin FPGA da muke amfani da shi shine AC7200-2FGG484I, wanda ke cikin jerin Xilinx's Artix-7. Makin gudun shine 2, kuma ƙimar zafin jiki shine darajar masana'antu. Wannan samfurin fakiti ne na FGG484 tare da fil 484. Xilinx ARTIX-7 FPGA dokokin sawa guntu kamar yadda ke ƙasa
Takamaiman Samfurin Chip Definition na ARTIX-7 Series
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
FPGA guntu akan jirgi Babban sigogi na guntu FPGA AC7200 sune kamar haka
Sunan Kwayoyin Logic
Yanki CLB flip-flops Toshe RAMkb DSP Yanki
PCIe Gen2 XADC
Gudun Gudun GTP
Matsayin Zazzabi
Takamaiman sigogi 215360 33650 269200 13140 740 1
1 XADC, 12bit, 1Mbps AD 4 GTP6.6Gb/s max -2 Masana'antu
Tsarin samar da wutar lantarki na FPGA Artix-7 FPGA samar da wutar lantarki sune V, CCINT V, CCBRAM V, CCAUX VCCO, VMGTAVCC da V. MGTAVTT VCCINT shine fil ɗin samar da wutar lantarki na FPGA, wanda ke buƙatar haɗawa zuwa 1.0V; VCCBRAM shine fil ɗin samar da wutar lantarki na FPGA toshe RAM, haɗa zuwa 1.0V; VCCAUX shine fil ɗin samar da wutar lantarki na FPGA, haɗa 1.8V; VCCO shine voltage na
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
kowane BANK na FPGA, gami da BANK0, BANK13~16, BANK34~35. A kan AC7200 FPGA core board, BANK34 da BANK35 suna buƙatar haɗa su zuwa DDR3, vol.tage haɗin BANK shine 1.5V, kuma voltage na sauran BANK shine 3.3V. VCCO na BANK15 da BANK16 suna da ƙarfi daga LDO, kuma ana iya canza su ta maye gurbin guntu na LDO. VMGTAVCC shine samar da voltage na FPGA na ciki GTP transceiver, wanda aka haɗa zuwa 1.0V; VMGTAVTT shine ƙaddamarwa voltage na GTP transceiver, wanda aka haɗa zuwa 1.2V.
Tsarin Artix-7 FPGA yana buƙatar jerin ƙarfin wutar lantarki ya kasance mai ƙarfi ta VCCINT, sannan VCCBRAM, sannan VCCAUX, kuma a ƙarshe VCCO. Idan VCCINT da VCCBRAM suna da voltage, ana iya ƙarfafa su a lokaci guda. Tsarin iko kutages yana juyawa. Tsarin wutar lantarki na GTP transceiver shine VCCINT, sannan VMGTAVCC, sannan VMGTAVTT. Idan VCCINT da VMGTAVCC suna da voltage, ana iya ƙarfafa su a lokaci guda. Jerin kashe wutar lantarki shine kawai akasin tsarin kunnawa.
Sashe na 2.2: Crystal Bambanci Mai Aiki
The AC7200 core jirgin sanye take da biyu Sitime aiki daban-daban lu'ulu'u, daya ne 200MHz, model ne SiT9102-200.00MHz, da tsarin babban agogon FPGA da kuma amfani da su samar da DDR3 iko agogo; ɗayan kuma shine 125MHz, ƙirar ita ce SiT9102 -125MHz, shigar da agogon tunani don masu karɓar GTP.
Kashi na 2.3: 200Mhz Agogon Daban-daban mai aiki
G1 a cikin Hoto 3-1 shine 200M mai aiki daban-daban crystal wanda ke ba da tushen agogon tsarin allon ci gaba. An haɗa fitarwar crystal zuwa BANK34 agogon duniya MRCC (R4 da T4) na FPGA. Ana iya amfani da wannan agogon bambancin agogon 200Mhz don fitar da dabaru masu amfani a cikin FPGA. Masu amfani za su iya saita PLLs da DCMs a cikin FPGA don samar da agogo na mitoci daban-daban.
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
200Mhz Aiki Daban Daban Crystal Schematic
200Mhz Active Banbancin Crystal akan allon Core
200Mhz Banbancin Agogo Pin Assignment
Sunan siginar SYS_CLK_P SYS_CLK_N
FPGA PIN R4 T4
Kashi na 2.4: 148.5Mhz Aiki Bambancin Crystal
G2 shine kristal mai aiki na 148.5Mhz, wanda shine agogon shigar da bayanai da aka bayar ga tsarin GTP a cikin FPGA. An haɗa fitarwar crystal zuwa madaidaitan agogon GTP BANK216 MGTREFCLK0P (F6) da MGTREFCLK0N (E6) na FPGA.
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
148.5Mhz Aiki Daban Daban Crystal Schematic
1148.5Mhz Active Banbancin Crystal akan allon Core
125Mhz Banbancin Agogo Pin Assignment
Sunan Net
FPGA PIN
MGT_CLK0_P
F6
MGT_CLK0_N
E6
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Kashi na 2.5: DDR3 DRAM
FPGA core board AC7200 sanye take da guda biyu Micron 4Gbit (512MB) DDR3 kwakwalwan kwamfuta, model MT41J256M16HA-125 (mai jituwa da MT41K256M16HA-125). DDR3 SDRAM yana da matsakaicin saurin aiki na 800MHz ( ƙimar bayanai 1600Mbps). An haɗa tsarin ƙwaƙwalwar DDR3 kai tsaye zuwa ƙirar ƙwaƙwalwar ajiya na BANK 34 da BANK35 na FPGA. Ana nuna takamaiman ƙayyadaddun ƙayyadaddun tsarin DDR3 SDRAM a cikin Tebu 4-1.
Bit Number U5,U6
Samfurin Chip MT41J256M16HA-125
Iyakar 256M x 16bit
Kamfanin Micron
DDR3 SDRAM Kanfigareshan
Tsarin kayan masarufi na DDR3 yana buƙatar tsananin la'akari da amincin sigina. Mun yi cikakken la'akari da matching resistor/terminal juriya, gano impedance iko, da kuma gano tsawon iko a kewaye zane da PCB zane don tabbatar da high-gudun da barga aiki na DDR3.
Bayanan Bayani na DDR3DRAM
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
DDR3 akan Core Board
DDR3 DRAM fil aiki:
Sunan Net
Sunan PIN na FPGA
DDR3_DQS0_P
IO_L3P_T0_DQS_AD5P_35
DDR3_DQS0_N DDR3_DQS1_P DDR3_DQS1_N DDR3_DQS2_P DDR3_DQS2_N DDR3_DQS3_P DDR3_DQS3_N
DDR3_DQ[0] DDR3_DQ [1] DDR3_DQ [2] DDR3_DQ [3] DDR3_DQ [4] DDR3_DQ [5]
IO_L3N_T0_DQS_AD5N_35 IO_L9P_T1_DQS_AD7P_35 IO_L9N_T1_DQS_AD7N_35
IO_L15P_T2_DQS_35 IO_L15N_T2_DQS_35 IO_L21P_T3_DQS_35 IO_L21N_T3_DQS_35 IO_L2P_T0_AD12P_35 IO_L5P_T0_AD13P_35 IO_L1N_T0_AD4N_35
IO_L6P_T0_35 IO_L2N_T0_AD12N_35 IO_L5N_T0_AD13N_35
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FPGA P/N E1 D1 K2 J2 M1 L1 P5 P4 C2 G1 A1 F3 B2 F1
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
DDR3_DQ [6]
IO_L1P_T0_AD4P_35
B1
DDR3_DQ [7]
IO_L4P_T0_35
E2
DDR3_DQ [8]
IO_L11P_T1_SRCC_35
H3
DDR3_DQ [9]
IO_L11N_T1_SRCC_35
G3
DDR3_DQ [10]
IO_L8P_T1_AD14P_35
H2
DDR3_DQ [11]
IO_L10N_T1_AD15N_35
H5
DDR3_DQ [12]
IO_L7N_T1_AD6N_35
J1
DDR3_DQ [13]
IO_L10P_T1_AD15P_35
J5
DDR3_DQ [14]
IO_L7P_T1_AD6P_35
K1
DDR3_DQ [15]
IO_L12P_T1_MRCC_35
H4
DDR3_DQ [16]
IO_L18N_T2_35
L4
DDR3_DQ [17]
IO_L16P_T2_35
M3
DDR3_DQ [18]
IO_L14P_T2_SRCC_35
L3
DDR3_DQ [19]
IO_L17N_T2_35
J6
DDR3_DQ [20]
IO_L14N_T2_SRCC_35
K3
DDR3_DQ [21]
IO_L17P_T2_35
K6
DDR3_DQ [22]
IO_L13N_T2_MRCC_35
J4
DDR3_DQ [23]
IO_L18P_T2_35
L5
DDR3_DQ [24]
IO_L20N_T3_35
P1
DDR3_DQ [25]
IO_L19P_T3_35
N4
DDR3_DQ [26]
IO_L20P_T3_35
R1
DDR3_DQ [27]
IO_L22N_T3_35
N2
DDR3_DQ [28]
IO_L23P_T3_35
M6
DDR3_DQ [29]
IO_L24N_T3_35
N5
DDR3_DQ [30]
IO_L24P_T3_35
P6
DDR3_DQ [31]
IO_L22P_T3_35
P2
DDR3_DM0
IO_L4N_T0_35
D2
DDR3_DM1
IO_L8N_T1_AD14N_35
G2
DDR3_DM2
IO_L16N_T2_35
M2
DDR3_DM3
IO_L23N_T3_35
M5
DDR3_A[0]
IO_L11N_T1_SRCC_34
AA4
DDR3_A[1]
IO_L8N_T1_34
AB2
DDR3_A[2]
IO_L10P_T1_34
AA5
DDR3_A[3]
IO_L10N_T1_34
AB5
DDR3_A[4]
IO_L7N_T1_34
AB1
DDR3_A[5]
IO_L6P_T0_34
U3
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
DDR3_A[6] DDR3_A[7] DDR3_A[8] DDR3_A[9] DDR3_A[10] DDR3_A[11] DDR3_A[12] DDR3_A[13] DDR3_A[14] DDR3_BA[0] DDR3_BA[1] DDR3_BA[2] DDR3_CAS DDR0_WE DDR3_ODT DDR3_RESET DDR3_CLK_P DDR3_CLK_N DDR3_CKE
IO_L5P_T0_34 IO_L1P_T0_34 IO_L2N_T0_34 IO_L2P_T0_34 IO_L5N_T0_34 IO_L4P_T0_34 IO_L4N_T0_34 IO_L1N_T0_34 IO_L6N_T0_VREF_34 IO_L9N_T1_DQS_34 IO_L9P_T1_DQS_34 IO_L11P_T1_SRCC_34 IO_L8P_T1_34 IO_L12P_T1_MRCC_34 IO_L12N_T1_MRCC_34 IO_L7P_T1_34 IO_L14N_T2_SRCC_34 IO_L15P_T2_DQS_34 IO_L3P_T0_DQS_34 IO_L3N_T0_DQS_34 IO_L14P_T2_SRCC_34
W1 T1 V2 U2 Y1 W2 Y2 U1 V3 AA3 Y3 Y4 AB3 V4 W4 AA1 U5 W6 R3 R2 T5
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 2.6: QSPI Flash
FPGA core board AC7200 sanye take da 128MBit QSPI FLASH, kuma samfurin shine W25Q256FVEI, wanda ke amfani da 3.3V CMOS vol.tage misali. Saboda yanayin rashin daidaituwa na QSPI FLASH, ana iya amfani dashi azaman na'urar taya don tsarin don adana hoton taya na tsarin. Waɗannan hotuna sun haɗa da bit FPGA files, lambar aikace-aikacen ARM, lambar aikace-aikacen ainihin da sauran bayanan mai amfani files. Ana nuna takamaiman samfura da sigogi masu alaƙa na QSPI FLASH.
Matsayi U8
Samfuran N25Q128
Iyakar 128M Bit
Kamfanin Numonyx
Ƙididdigar QSPI FLASH
QSPI FLASH an haɗa shi zuwa keɓaɓɓen fil na BANK0 da BANK14 na guntu FPGA. Ana haɗa fil ɗin agogo zuwa CCLK0 na BANK0, kuma sauran bayanai da guntu zaɓaɓɓen sigina ana haɗa su zuwa D00~D03 da FCS fil na BANK14 bi da bi. Yana nuna haɗin kayan aikin QSPI Flash.
QSPI Flash Schematic QSPI Flash fil aiyuka:
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Net Name QSPI_CLK QSPI_CS QSPI_DQ0 QSPI_DQ1 QSPI_DQ2 QSPI_DQ3
Sunan PIN na FPGA CCLK_0
IO_L6P_T0_FCS_B_14 IO_L1P_T0_D00_MOSI_14 IO_L1N_T0_D01_DIN_14
IO_L2P_T0_D02_14 IO_L2N_T0_D03_14
FPGA P/N L12 T19 P22 R22 P21 R21
QSPI a kan Core Board
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 2.7: Hasken LED akan allon Core
Akwai fitilu jajayen LED guda 3 akan allon AC7200 FPGA, daya daga cikinsu shine hasken wutar lantarki (PWR), daya shine hasken LED na daidaitawa (DONE), daya kuma shine hasken LED mai amfani. Lokacin da babban allon yana kunna, alamar wutar lantarki zata haskaka; lokacin da aka saita FPGA, saitin LED zai haskaka. An haɗa hasken LED mai amfani da IO na BANK34, mai amfani zai iya sarrafa hasken da kashewa ta shirin. Lokacin da IO voltage haɗa zuwa mai amfani LED yana da girma, LED mai amfani yana kashe. Lokacin haɗin IO voltage yana da ƙasa, za a kunna LED mai amfani. Ana nuna zane-zane na haɗin kayan aikin hasken LED:
LED fitilu a kan core jirgin Schematic
Fitilar LED akan Madaidaicin Mai amfani da LEDs Pin Assignment
Sunan siginar LED1
Sunan fil FPGA IO_L15N_T2_DQS_34
FPGA Pin Number W5
Bayanin LED mai amfani
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 2.8: Sake saitin Maɓallin
Akwai maɓallin sake saiti akan allo na AC7200 FPGA. Ana haɗa maɓallin sake saiti zuwa IO na yau da kullun na BANK34 na guntu FPGA. Mai amfani zai iya amfani da wannan maɓallin sake saitin don fara shirin FPGA. Lokacin da aka danna maɓallin a cikin ƙira, siginar voltage shigarwa zuwa IO yana da ƙasa, kuma siginar sake saiti yana aiki; lokacin da ba a danna maɓallin ba, shigar da siginar zuwa IO yana da girma. Ana nuna zane-zane na haɗin maɓallin sake saiti:
Sake saitin Maɓallin Tsari
Maɓallin sake saiti akan aikin fil ɗin Sake saitin maɓallin Core Board
Sunan siginar RESET_N
Sunan Fil na ZYNQ IO_L17N_T2_34
Lambar Fil na ZYNQ T6
Bayanin sake saitin tsarin FPGA
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Kashi na 2.9: JTAG Interface
A JTAG an tanada soket ɗin gwajin J1 akan babban allon AC7200 don JTAG zazzagewa da gyara kurakurai lokacin da ake amfani da babban allo shi kaɗai. Hoto shine sashin tsari na JTAG tashar jiragen ruwa, wanda ya ƙunshi TMS, TDI, TDO, TCK. , GND, +3.3V waɗannan sigina shida.
JTAG Tsarin Intanet na JTAG dubawa J1 akan allon AC7200 FPGA yana amfani da rami mai lamba 6-pin 2.54mm. Idan kuna son amfani da JTAG haɗi don gyara kuskure a kan ainihin allo, kuna buƙatar siyar da babban filin-jere guda 6-pin. nuna JTAG dubawa J1 akan allon core AC7200 FPGA.
JTAG Interface akan Core Board
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 2.10: Ƙaddamar da Wutar Lantarki a kan Babban allo
Domin yin AC7200 FPGA core panel aiki shi kaɗai, an tanadar da babban allon tare da 2PIN ikon dubawa (J3). Lokacin da mai amfani ya ba da wutar lantarki zuwa ainihin allon ta hanyar haɗin wutar lantarki na 2PIN (J3), ba za a iya kunna shi ta hanyar allon ɗauka ba. In ba haka ba, rikici na yanzu zai iya faruwa.
Interface Power a kan Core Board
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 2.11: Jirgin zuwa Masu Haɗin Jirgin
Babban allon yana da jimlar allo mai sauri huɗu zuwa masu haɗin jirgi. Babban allon yana amfani da masu haɗin allo guda huɗu 80-pin don haɗawa da allon ɗauka. An haɗa tashar IO na FPGA zuwa masu haɗin kai huɗu ta hanyar kewayawa daban. Matsakaicin fil na masu haɗawa shine 0.5mm, saka a cikin allo zuwa masu haɗin jirgi akan allon ɗaukar hoto don sadarwar bayanai mai sauri.
Babban allon yana da jimlar allo mai sauri huɗu zuwa masu haɗin jirgi. Babban allon yana amfani da masu haɗin allo guda huɗu 80-pin don haɗawa da allon ɗauka. An haɗa tashar IO na FPGA zuwa masu haɗin kai huɗu ta hanyar kewayawa daban. Matsakaicin fil na masu haɗawa shine 0.5mm, saka a cikin allo zuwa masu haɗin jirgi akan allon ɗaukar hoto don sadarwar bayanai mai sauri.
Board to Board Connectors CON1 The 80-pin board to board connectors CON1, wanda ake amfani da su haɗi.
tare da samar da wutar lantarki na VCCIN (+5V) da ƙasa akan allon jigilar kaya, ƙara IOs na yau da kullun na FPGA. Ya kamata a lura a nan cewa 15 fil na CON1 an haɗa su zuwa tashar IO na BANK34, saboda haɗin BANK34 yana da alaƙa da DDR3. Saboda haka, voltage misali na duk IOs na wannan BANK34 shine 1.5V. Pin Assignment na Board zuwa Board Connectors CON1
CON1 Pin PIN1 PIN3 PIN5 PIN7 PIN9
Sunan siginar
VCCIN VCCIN VCCIN VCCIN GND
FPGA Pin Voltage Darasi
–
+5V
–
+5V
–
+5V
–
+5V
–
Kasa
CON1 Pin PIN2 PIN4 PIN6 PIN8 PIN10
Sunan siginar
VCCIN VCCIN VCCIN VCCIN
GND
FPGA Pin Voltage Darasi
–
+5V
–
+5V
–
+5V
–
+5V
–
Kasa
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
PIN11 PIN13PIN15 PIN17PIN19PIN21PIN23PIN25PIN27PIN29PIN31PIN33PIN35PIN37PIN39PIN41PIN43PIN
NC NC NC GND B13_L5_P B13_L5_N B13_L7_P B13_L7_P GND B13_L3_P B13_L3_N B34_L23_P B34_L23_N GND B34_L18_N B34_L18_PND B34_L19_N B34_L19_PND VN XADC_VP NC NC GND B16_L1_N B16_L1_P B16_L4_N B16_L4_P GND B16_L6_N
Y13 AA14 AB11 AB12 AA13 AB13 Y8 Y7 AA6 Y6 Y7 V7 W9 M10 L14 F13 F14 E13 E15 DXNUMX
Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 1.5V 1.5V Ground 1.5V 1.5V 1.5V 1.5V Ground ADC ADC Ground 3.3V 3.3V 3.3V 3.3V Ground
PIN12 PIN14PIN16 PIN18PIN20PIN22PIN24PIN26PIN28PIN30PIN32PIN34PIN36PIN38PIN40PIN42PIN44PIN
NC NC B13_L4_P B13_L4_N GND B13_L1_P B13_L1_N B13_L2_P B13_L2_N GND B13_L6_P B13_L6_N B34_L20_P B34_L20_N GND B34_L21_P B34_L21_ _L34_N GND NC B22_L34 B22_L34_P B25_L34_N GND NC NC NC GND NC
AA15 AB15 Y16 AA16 AB16 AB17 W14 Y14 AB7 AB6 V8 V9 AA8 AB8 -
3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V
U7
1.5V
W9
1.5V
Y9
1.5V
–
Kasa
–
–
–
–
–
–
–
–
–
Kasa
–
–
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Board to Board Connectors CON2 Ana amfani da taken haɗin mata 80-pin CON2 don tsawaita al'ada
IO na BANK13 da BANK14 na FPGA. Voltage Standards na duka bankunan 3.3V. Pin Assignment na Board zuwa Board Connectors CON2
CON1 Pin
Sunan siginar
PIN1 B13_L16_P
PIN3 B13_L16_N
PIN5 B13_L15_P
PIN7 B13_L15_N
Lambar PIN9
GND
PIN11 B13_L13_P
PIN13 B13_L13_N
PIN15 B13_L12_P
PIN17 B13_L12_N
Lambar PIN19
GND
PIN21 B13_L11_P
PIN23 B13_L11_N
PIN25 B13_L10_P
PIN27 B13_L10_N
Lambar PIN29
GND
PIN31 B13_L9_N
PIN33 B13_L9_P
PIN35 B13_L8_N
PIN37 B13_L8_P
Lambar PIN39
GND
PIN41 B14_L11_N
PIN43 B14_L11_P
PIN45 B14_L14_N
PIN47 B14_L14_P
FPGA Pin W15 W16 T14 T15 V13 V14 W11 W12 Y11 Y12 V10 W10 AA11 AA10 AB10 AA9 V20 U20 V19 V18
Voltage Level 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Ground 3.3V.
CON1 Pin PIN2 PIN4 PIN6 PIN8 PIN10 PIN12PIN14 PIN16 PIN18 PIN20 PIN22PIN24
Sunan siginar
B14_L16_P B14_L16_N B13_L14_P B13_L14_N
GND B14_L10_P B14_L10_N B14_L8_N B14_L8_P
GND B14_L15_N B14_L15_P B14_L17_P B14_L17_N
GND B14_L6_N B13_IO0 B14_L7_N B14_L7_P
GND B14_L4_P B14_L4_N B14_L9_P B14_L9_N
FPGA Pin Voltage
Mataki
V17
3.3V
W17
3.3V
U15
3.3V
V15
3.3V
–
Kasa
AB21
3.3V
AB22
3.3V
AA21
3.3V
AA20
3.3V
–
Kasa
AB20
3.3V
AA19
3.3V
AA18
3.3V
AB18
3.3V
–
Kasa
Saukewa: T20
3.3V
Y17
3.3V
W22
3.3V
W21
3.3V
–
Kasa
Saukewa: T21
3.3V
U21
3.3V
Y21
3.3V
Y22
3.3V
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65
GND B14_L5_N B14_L5_P B14_L18_N B14_L18_P
GND B13_L17_P B13_L17_N B14_L21_N B14_L21_P
GND B14_L22_P B14_L22_N B14_L24_N B14_L24_P
B14_IO0
R19 P19 U18 U17
T16 U16 P17 N17
Saukewa: P15R16R17
Ƙasa 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66
GND B14_L12_N B14_L12_P B14_L13_N B14_L13_P
GND B14_L3_N B14_L3_P B14_L20_N B14_L20_P
GND B14_L19_N B14_L19_P B14_L23_P B14_L23_N B14_IO25
W20 W19 Y19 Y18
V22 U22 T18 R18
R14 P14 N13 N14 N15
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V 3.3V
Board to Board Connectors CON3 Ana amfani da haɗin 80-pin CON3 don tsawaita IO na al'ada.
BANK15 da BANK16 na FPGA. Bugu da kari, hudu JTAG Hakanan ana haɗa sigina zuwa allon ɗauka ta hanyar haɗin CON3. Voltage matsayin BANK15 da BANK16 ana iya daidaita su ta guntu na LDO. Tsohuwar shigar LDO shine 3.3V. Idan kuna son fitar da wasu madaidaitan matakan, zaku iya maye gurbinsa da LDO mai dacewa. Pin Assignment na Board zuwa Board Connectors CON3
CON1 Pin PIN1 PIN3 PIN5 PIN7
Sunan siginar
B15_IO0 B16_IO0 B15_L4_P B15_L4_N
FPGA Pin J16 F15 G17 G18
Voltage Darasi
CON1 Pin
3.3V PIN2
3.3V PIN4
3.3V PIN6
3.3V
Lambar PIN8
Sunan siginar
B15_IO25 B16_IO25 B16_L21_N B16_L21_P
FPGA Pin Voltage Darasi
M17
3.3V
F21
3.3V
A21
3.3V
B21
3.3V
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
PIN9 PIN11 PIN13PIN15 PIN17PIN19PIN21PIN23PIN25PIN27PIN29PIN31PIN33PIN 35PIN37PIN39PIN41PIN
GND B15_L2_P B15_L2_N B15_L12_P B15_L12_N
GND B15_L11_P B15_L11_N B15_L1_N B15_L1_P
GND B15_L5_P B15_L5_N B15_L3_N B15_L3_P
GND B15_L19_P B15_L19_N B15_L20_P B15_L20_N
GND B15_L14_P B15_L14_N B15_L21_P B15_L21_N
GND B15_L23_P B15_L23_N B15_L22_P B15_L22_N
GND B15_L24_P
G15 G16 J19 H19
Saukewa: J20J21 G13H13
J15 H15 H14 J14
K13 K14 M13 L13
L19 L20 K17 J17 L16 K16 L14 L15 M15
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V 3.3V
PIN10 PIN12 PIN14PIN16 PIN18PIN20PIN22PIN24PIN26PIN28PIN30PIN32PIN34PIN 36PIN38PIN40PIN42PIN
GND B16_L23_P B16_L23_N B16_L22_P B16_L22_N
GND B16_L24_P B16_L24_N B15_L8_N B15_L8_P
GND B15_L7_N B15_L7_P B15_L9_P B15_L9_N
GND B15_L15_N B15_L15_P B15_L6_N B15_L6_P
GND B15_L13_N B15_L13_P B15_L10_P B15_L10_N
GND B15_L18_P B15_L18_N B15_L17_N B15_L17_P
GND B15_L16_P
Saukewa: E21D21
Saukewa: G21 G22 G20H20
Hoton H22 J22 K21 K22
M22 N22 H18 H17
K19 K18 M21 L21
N20 M20 N19 N18
M18
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V
Kasa 3.3V
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
PIN73 B15_L24_N
M16
3.3V
PIN74 B15_L16_N
L18
3.3V
Lambar PIN75
NC
–
Lambar PIN76
NC
–
PIN77 FPGA_TCK
V12
3.3V
Lambar PIN78
FPGA_TDI
R13
3.3V
PIN79 FPGA_TDO
U13
3.3V
PIN80 FPGA_TMS
Saukewa: T13
3.3V
Board to Board Connectors CON4 Ana amfani da haɗin 80-Pin CON4 don tsawaita IO da GTP na yau da kullun.
bayanai masu sauri da siginonin agogo na FPGA BANK16. Voltage daidaitaccen tashar tashar IO na BANK16 ana iya daidaita shi ta guntu na LDO. Tsohuwar shigar LDO shine 3.3V. Idan mai amfani yana son fitar da wasu daidaitattun matakan, ana iya maye gurbinsa da LDO mai dacewa. Bayanai masu sauri da siginar agogo na GTP suna da bambanci sosai a kan allo. Layukan bayanan daidai suke da tsayi kuma ana kiyaye su a wani tazara don hana tsangwama sigina. Pin Aikin Hukumar zuwa Masu Haɗin Jirgin CON4
CON1 Pin PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29
Sunan siginar
Farashin NC
FPGA Pin Voltage Darasi -
–
Abubuwan da aka bayar na CON1 Pin NC
NC
–
NC
NC
–
NC
GND NC
–
PIN na ƙasa10
–
Lambar PIN12
NC
–
Lambar PIN14
GND
–
PIN na ƙasa16
MGT_TX3_P
D7 Bambancin PIN18
MGT_TX3_N
C7 Bambancin PIN20
GND
–
PIN na ƙasa22
MGT_RX3_P D9 Bambancin PIN24
MGT_RX3_N
C9 Bambancin PIN26
GND
– Kasa
Lambar PIN28
MGT_TX1_P
D5 Bambancin PIN30
Sunan siginar FPGA Pin Voltage
Mataki
–
NC
–
NC
–
NC
–
NC
GND
–
Kasa
MGT_TX2_P
Banbancin B6
MGT_TX2_N
A6 Bambanci
GND
–
Kasa
MGT_RX2_P
Banbancin B10
MGT_RX2_N
A10 Bambanci
GND
–
Kasa
MGT_TX0_P
Banbancin B4
MGT_TX0_N
A4 Bambanci
GND
–
Kasa
MGT_RX0_P
Banbancin B8
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
PIN31 PIN33 PIN35 PIN37 PIN39PIN41PIN 43PIN 45 PIN47
MGT_TX1_N GND
MGT_RX1_P MGT_RX1_N
GND B16_L5_P B16_L5_N B16_L7_P B16_L7_N
GND B16_L9_P B16_L9_N B16_L11_P B16_L11_N
GND B16_L13_P B16_L13_N B16_L15_P B16_L15_N
GND B16_L17_P B16_L17_N B16_L19_P B16_L19_N
NC
C5 D11 C11 E16 D16 B15 B16 A15 A16 B17 B18 C18 C19 F18 E18 A18 A19 D20 C20 -
Banbancin Ƙasa
Bambancin Bambanci
Ƙasa 3.3V 3.3V 3.3V 3.3V
Ƙasa 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
PIN32 PIN34 PIN36 PIN38 PIN40PIN42PIN 44PIN 46 PIN48
MGT_RX0_N GND
MGT_CLK1_P MGT_CLK1_N
GND B16_L2_P B16_L2_N B16_L3_P B16_L3_N
GND B16_L10_P B16_L10_N B16_L12_P B16_L12_N
GND B16_L14_P B16_L14_N B16_L16_P B16_L16_N
GND B16_L18_P B16_L18_N B16_L20_P B16_L20_N
NC
A8 Bambanci
–
Kasa
F10 bambanci
E10 bambanci
–
Kasa
F16
3.3V
E17
3.3V
C14
3.3V
C15
3.3V
–
Kasa
A13
3.3V
A14
3.3V
D17
3.3V
C17
3.3V
–
Kasa
E19
3.3V
D19
3.3V
B20
3.3V
A20
3.3V
–
Kasa
F19
3.3V
F20
3.3V
C22
3.3V
B22
3.3V
–
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 2.12: Samar da Wutar Lantarki
AC7200 FPGA core panel ana amfani da ita ta DC5V ta hanyar jirgi mai ɗaukar kaya, kuma ana yin ta ta hanyar haɗin J3 lokacin da aka yi amfani da ita ita kaɗai. Da fatan za a yi hankali kada a ba da wutar lantarki ta hanyar haɗin J3 da allon jigilar kaya a lokaci guda don guje wa lalacewa. Ana nuna zanen ƙirar wutar lantarki a kan allo a ciki.
Samar da wutar lantarki akan tsarin tsarin allo
Hukumar ci gaba tana aiki da +5V kuma an canza ta zuwa +3.3V, +1.5V, +1.8V, +1.0V samar da wutar lantarki ta hanyoyi huɗu ta guntuwar wutar lantarki ta DC/DC guda huɗu TLV62130RGT. Abubuwan da ake fitarwa na yanzu na iya zama har zuwa 3A kowane tashoshi. LDOSPX3819M5-3-3 ne ya samar da VCCIO guda ɗaya. VCCIO galibi tana samar da wuta ga BANK15 da BANK16 na FPGA. Masu amfani za su iya canza IO na BANK15,16 zuwa voltage ka'idodin ta maye gurbin guntu na LDO. 1.5V Yana Samar da VTT da VREF voltages da ake buƙata ta DDR3 ta hanyar TI's TPS51200. Samar da wutar lantarki 1.8V MGTAVTT MGTAVCC don mai karɓar GTP an samar dashi ta guntu TPS74801 TI. Ana nuna ayyukan kowane rarraba wutar lantarki a cikin tebur mai zuwa:
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Samar da wutar lantarki +1.0V +1.8V +3.3V +1.5V
VREF,VTT(+0.75V) MVCCIP(+3.3V) MGTAVTT(+1.2V)
MGTVCCAUX(+1.8V)
Ayyukan FPGA Core Voltage FPGA auxiliary voltage, TPS74801 samar da wutar lantarki VCCIO na Bank0, Bank13 da Bank14 na FPGA, QSIP FLASH, Clock Crystal DDR3, Bank34 da Bank35 na FPGA
DDR3 FPGA Bank15, Bank16 GTP Transceiver Bank216 na FPGA GTP Transceiver Bank216 na FPGA
Saboda ƙarfin wutar lantarki na Artix-7 FPGA yana da tsarin da ake buƙata, a cikin ƙirar kewaye, mun tsara shi bisa ga buƙatun wutar lantarki na guntu, kuma wutar lantarki shine 1.0V-> 1.8V->(1.5). V, 3.3V, VCCIO) da 1.0V-> MGTAVCC -> MGTAVTT, ƙirar kewaye don tabbatar da aikin al'ada na guntu.
Sashe na 2.13: Tsarin Tsarin
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Kashi na 3: allo mai ɗaukar hoto
Sashe na 3.1: Jirgin jigilar kaya Gabatarwa
Ta hanyar gabatarwar aikin da ya gabata, zaku iya fahimtar aikin sashin allon jigilar kaya
1-tashar PCIe x4 babban saurin watsa bayanai mai saurin watsawa 2-tashar 10/100M/1000M Ethernet RJ-45 dubawa 1-tashar HDMI shigar da bidiyo 1-tashar HDMI bidiyo Fitar dubawa 1-tashar USB Uart Sadarwa dubawa 1 SD Card Ramin XADA Interface EEPROM 2-tashar 40-pin fadada tashar jiragen ruwa JTAG Maɓalli masu zaman kansu 2 masu amfani da fitilun LED
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 3.2: Gigabit Ethernet Interface
Hukumar ci gaban AX7203 FPGA tana ba masu amfani da tashoshi 2
Sabis ɗin sadarwar cibiyar sadarwar Gigabit ta hanyar Micrel KSZ9031RNX
Ethernet PHY guntu. KSZ9031RNX guntu yana goyan bayan 10/100/1000 Mbps
Yawan watsa cibiyar sadarwa da sadarwa tare da FPGA ta hanyar GMII
dubawa. KSZ9031RNX yana goyan bayan daidaitawar MDI/MDX, gudu daban-daban
gyare-gyare, daidaitawar Jagora/Bawa, da goyan bayan motar MDIO don PHY
gudanar da rajista.
KSZ9031RNX zai gano matsayin matakin wasu takamaiman IOs zuwa
ƙayyade yanayin aikin su bayan kunnawa. Tebu 3-1-1 ya bayyana
bayanan saitin tsoho bayan an kunna guntu GPHY.
Umarnin Kanfigareshan Pin
Ƙimar daidaitawa
PHYAD[2:0] CLK125_EN
SELRGV AN[1:0] Jinkirta TX RX
Yanayin MDIO/MDC Adireshin PHY 3.3V, 2.5V, 1.5/1.8V voltage zaɓi Tsarin sasantawa ta atomatik
Agogon RX 2ns jinkiri agogon TX agogon 2ns jinkirta RGMII ko zaɓin GMII
Adireshin PHY 011 3.3V
(10/100/1000M) jinkirin jinkiri na daidaitawa GMII
Tebur 3-2-1: PHY guntu tsoho mai ƙima
Lokacin da aka haɗa hanyar sadarwa zuwa Gigabit Ethernet, ana isar da watsa bayanai na FPGA da PHY guntu KSZ9031RNX ta bas ɗin GMII, agogon watsawa shine 125Mhz. Ana samar da agogon karɓar E_RXC ta guntu na PHY, agogon watsa E_GTXC na FPGA ne, kuma bayanan s ne.ampjagoranci a kan tashi gefen agogo.
Lokacin da aka haɗa cibiyar sadarwar zuwa 100M Ethernet, ana isar da watsa bayanai na FPGA da PHY guntu KSZ9031RNX ta hanyar bas ɗin GMII, agogon watsawa shine 25Mhz. Ana samar da agogon karɓar E_RXC ta guntu na PHY, agogon watsa E_GTXC na FPGA ne, kuma bayanan shine
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani sampjagoranci a kan tashi gefen agogo.
Hoto 3-2-1: Gigabit Ethernet Interface Schematic
Hoto 3-3-2: Gigabit Ethernet interface akan allon mai ɗauka
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Gigabit Ethernet Chip PHY1 fil ayyuka kamar haka
Sunan siginar E1_GTXC E1_TXD0 E1_TXD1 E1_TXD2 E1_TXD3 E1_TXEN E1_RXC E1_RXD0 E1_RXD1 E1_RXD2 E1_RXD3 E1_RXDV E1_MDC E1_MDIO E1_RESTES
Lambar Fil na FPGA E18 C20 D20 A19 A18 F18 B17 A16 B18 C18 C19 A15 B16 B15 D16
Bayanin agogon watsawa PHY1 RGMII
PHY1 watsa bayanai bit0 PHY1 watsa bayanai bit1 PHY1 watsa bayanai bit2 PHY1 watsa bayanai bit3 PHY1 Canja wurin Siginar PHY1 RGMII Karɓar Agogo PHY1 Karɓi Data Bit0 PHY1 Karɓi Data Bit1 PHY1 Karɓi Data Bit2 PHY1 Karɓi Data Bit3 PHY1 Karɓi Ingataccen Bayanin Gudanarwa PHY1 Bayanai
PHY1 Sake saitin siginar
Gigabit Ethernet Chip PHY2 fil ayyuka kamar haka
Sunan siginar E2_GTXC E2_TXD0 E2_TXD1 E2_TXD2 E2_TXD3 E2_TXEN E2_RXC E2_RXD0 E2_RXD1 E2_RXD2 E2_RXD3 E2_RXDV E2_MDC E2_MDIO E2_RESTES
Lambar Fil na FPGA A14 E17 C14 C15 A13 D17 E19 A20 B20 D19 C17 F19 F20 C22 B22
Bayanin agogon watsawa PHY2 RGMII
PHY2 watsa bayanai bit0 PHY2 watsa bayanai bit1 PHY2 watsa bayanai bit2 PHY2 watsa bayanai bit3 PHY2 Canja wurin Siginar PHY2 RGMII Karɓar Agogo PHY2 Karɓi Data Bit0 PHY2 Karɓi Data Bit1 PHY2 Karɓi Data Bit2 PHY2 Karɓi Data Bit3 PHY2 Karɓi Ingataccen Bayanin Gudanarwa PHY2 Bayanai
PHY2 Sake saitin siginar
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 3.3: PCIe x4 Interface
Hukumar ci gaban AX7203 FPGA tana ba da babban saurin canja wurin bayanai na masana'antu na PCIe x4. Ƙididdigar katin PCIE ya dace da daidaitattun ƙayyadaddun lantarki na katin PCIe kuma ana iya amfani dashi kai tsaye akan x4 PCIe ramin PC na yau da kullun.
Ana watsawa da karɓar sigina na ƙirar PCIe kai tsaye zuwa mai karɓar GTP na FPGA. An haɗa tashoshi huɗu na siginar TX da RX zuwa FPGA a cikin sigina daban-daban, kuma adadin sadarwar tashoshi ɗaya na iya zama har zuwa 5G bit bandwidth. Ana ba da agogon tunani na PCIe ga hukumar haɓaka AX7203 FPGA ta hanyar PCIe na PC tare da mitar agogo na 100Mhz.
Zane-zane na ƙirar ƙirar PCIe na hukumar ci gaban AX7203 FPGA an nuna shi a cikin Hoto 3-3-1, inda aka haɗa siginar watsa TX da siginar agogon CLK a cikin yanayin haɗin AC.
Hoto 3-3-1: Tsarin tsarin PCIex4
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto 3-3-2: PCIex4 akan allon ɗauka
PCIex4 Interface Pin Assignment:
Sunan siginar
FPGA Pin
PCIE_RX0_P
D11
PCIE_RX0_N
C11
PCIE_RX1_P
B8
PCIE_RX1_N
A8
PCIE_RX2_P
B10
PCIE_RX2_N
A10
PCIE_RX3_P
D9
PCIE_RX3_N
C9
PCIE_TX0_P
D5
PCIE_TX0_N
C5
PCIE_TX1_P
B4
PCIE_TX1_N
A4
PCIE_TX2_P
B6
PCIE_TX2_N
A6
PCIE_TX3_P
D7
PCIE_TX3_N
C7
PCIE_CLK_P
F10
PCIE_CLK_N
E10
Bayanin Tashar PCIE 0 Bayanan Yana Karɓar Tashar PCIE Mai Kyau 0 Bayanan Karɓar Tashar PCIE mara kyau. Tashar Tashar 1 Mai Taimakawa Tashar Tashar PCIE Mai Kyau 1 Tashar Tashar Tashar PCIE mara kyau 2 Tashar Bayanan Tashar Tashar PCIE Mai Kyau.
PCIE Reference Clock Madaidaicin agogo na PCIE mara kyau
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 3.4: HDMI fitarwa dubawa
HDMI fitarwa dubawa, zaɓi Silion Image's SIL9134 HDMI (DVI) guntu rufaffiyar guntu, goyan bayan fitowar 1080P@60Hz, goyan bayan fitowar 3D.
Hakanan ana haɗa haɗin haɗin IIC na SIL9134 zuwa IO na FPGA. An fara SIL9134 kuma ana sarrafa shi ta shirye-shiryen FPGA. Ana nuna haɗin haɗin hardware na ƙirar fitarwa na HDMI a cikin Hoto 3-4-1.
Hoto 3-4-1: HDMI Tsarin fitarwa
Hoto 3-4-1: Fitar da HDMI akan allon mai ɗauka
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
HDMI Shigar Pin Assignment:
Sunan siginar 9134_nRESET
9134_CLK 9134_HS 9134_VS 9134_DE 9134_D[0] 9134_D[1] 9134_D [2] 9134_D 3_D[9134] 4_D[9134] 5_D[ 9134] 6_D[9134] 7_D[9134] 8_D[9134] 9_D[9134] 10_D[9134] 11_D[9134] 12_D [9134] 13_D[9134] 14_D[9134] 15] 9134_D[16]
FPGA Pin J19 M13 T15 T14 V13 V14 H14 J14 K13 K14 L13 L19 L20 K17 J17 L16 K16 L14 L15 M15 M16 L18 M18 N18 N19 M20 N20 L21 M21
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 3.5: HDMI Input interface
HDMI fitarwa dubawa, zaɓi Silion Image's SIL9013 HDMI guntu dikodi, goyan bayan har zuwa 1080P@60Hz shigarwar da goyan bayan bayanai fitarwa a daban-daban tsari.
An haɗa haɗin haɗin IIC na SIL9013 zuwa IO na FPGA. An fara SIL9013 kuma an sarrafa shi ta hanyar shirye-shiryen FPGA. Ana nuna haɗin haɗin hardware na haɗin shigarwar HDMI a cikin Hoto 3-5-1.
Hoto 3-5-1: HDMI Tsarin Shigarwa
Hoto 3-5-2: Shigarwar HDMI akan allo mai ɗaukar hoto
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
HDMI Shigar Pin Assignment:
Sunan siginar 9013_nRESET
9013_CLK 9013_HS 9013_VS 9013_DE 9013_D[0] 9013_D[1] 9013_D [2] 9013_D 3_D[9013] 4_D[9013] 5_D[ 9013] 6_D[9013] 7_D[9013] 8_D[9013] 9_D[9013] 10_D[9013] 11_D[9013] 12_D [9013] 13_D[9013] 14_D[9013] 15] 9013_D[16]
Lambar Fil ɗin FPG H19 K21 K19 K18 H17 H18 N22 M22 K22 J22 H22 H20 G20 G22 G21 D22 E22 D21 E21 B21 A21 F21 M17 J16 F15 G17 G18 G15 G16
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Sashe na 3.6: Ramin Katin SD
Katin SD (Secure Digital Memory Card) katin žwažwalwar ajiya ne bisa tsarin ƙwaƙwalwar filasha na semiconductor. An kammala shi a cikin 1999 ta hanyar tunanin Panasonic na Japan, kuma mahalarta Toshiba da SanDisk na Amurka sun gudanar da bincike da ci gaba mai mahimmanci. A cikin 2000, waɗannan kamfanoni sun ƙaddamar da Ƙungiyar SD (Secure Digital Association), wanda ke da ƙaƙƙarfan layi kuma ya jawo hankalin masu yawa masu sayarwa. Waɗannan sun haɗa da IBM, Microsoft, Motorola, NEC, Samsung, da sauransu. Waɗannan manyan masana'antun ke tafiyar da su, katunan SD sun zama katin ƙwaƙwalwar ajiya da aka fi amfani da shi a cikin na'urorin dijital na mabukaci.
Katin SD na'urar ajiya ce ta gama gari. Katin SD mai tsawo yana goyan bayan yanayin SPI da yanayin SD. Katin SD da ake amfani da shi shine katin MicroSD. Ana nuna zane-zane a cikin hoto 3-6-1.
Hoto 3-6-1: Tsarin Katin SD
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto 3-6-2: Ramin Katin SD akan allo mai ɗauka
Aikin fil ɗin Ramin katin SD:
Sunan siginar SD_CLK SD_CMD SD_CD_N SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3
Yanayin SD
FPGA PIN AB12 AB11 F14 AA13 AB13 Y13 AA14
Sashe na 3.7: USB zuwa Serial Port
Kwamitin haɓaka AX7203 FPGA ya haɗa da guntu USB-UAR na Silicon Labs CP2102GM. Kebul na USB yana amfani da kebul na USB na MINI. Ana iya haɗa shi zuwa tashar USB na PC na sama don sadarwar bayanan serial tare da kebul na USB. An nuna zane-zane na ƙirar kebul na Uart na kebul a cikin hoto 3-7-1:
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ARTIX-7 FPGA Development Board AX7203 Manual Mai amfani Hoto 3-7-1: USB zuwa tsarin tashar tashar jiragen ruwa
Hoto 3-7-2: USB zuwa tashar tashar jiragen ruwa a kan allo mai ɗaukar hoto
An saita alamun LED guda biyu (LED3 da LED4) don siginar tashar tashar jiragen ruwa, kuma siliki akan PCB shine TX da RX, yana nuna cewa tashar tashar jiragen ruwa tana da watsa bayanai ko liyafar, kamar yadda aka nuna a cikin hoto mai zuwa 3-3-3.
Hoto 3-7-3: Serial Port Communication LED Manuniya Tsari
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Kebul zuwa serial port fil assignment:
Sunan siginar UART1_RXD UART1_TXD
FPGA PIN P20 N15
Kashi na 3.8: EEPROM 24LC04
Hukumar AX7013 ta ƙunshi EEPROM, samfurin 24LC04, kuma yana da ƙarfin 4Kbit (2*256*8bit). Ya ƙunshi tubalan 256-byte guda biyu kuma suna sadarwa ta bas ɗin IIC. Jirgin EEPROM shine koyon yadda ake sadarwa tare da bas ɗin IIC. An haɗa siginar I2C na EEPROM zuwa tashar BANK14 IO a gefen FPGA. Hoto na 3-8-1 da ke ƙasa yana nuna ƙirar EEPROM
Hoto 3-8-1: Tsarin EEPROM
Hoto 3-8-2: EEPROM akan allon ɗauka
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
EEPROM Pin Assignment
Net Sunan EEPROM_I2C_SCL EEPROM_I2C_SDA
FPGA PIN F13 E14
Sashe na 3.9: Babban Fadada
An tanadar allon jigilar kaya tare da tazarar 0.1inch guda biyu daidaitattun tashoshin faɗaɗa 40-pin J11 da J13, waɗanda ake amfani da su don haɗa kayan aikin ALINX ko kewayen waje da mai amfani ya tsara. Tashar tashar fadada tana da sigina 40, wanda 1-tashar 5V mai samar da wutar lantarki, 2-tashar wutar lantarki 3.3 V, 3-channle ƙasa da 34 IOs. Kada ka haɗa kai tsaye IO kai tsaye zuwa na'urar 5V don guje wa ƙone FPGA. Idan kana son haɗa kayan aikin 5V, kana buƙatar haɗa guntu juzu'in matakin.
An haɗa 33 ohm resistor a cikin jeri tsakanin tashar faɗaɗawa da haɗin FPGA don kare FPGA daga vol na waje.tage ko halin yanzu. Ana nuna kewaye na tashar fadada tashar (J11) a cikin Hoto 3-9-1.
Hoto 3-9-1: Fadada taken J11 makirci
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto na 3-9-2 yayi cikakken bayanin tashar fadada J4 akan allon jigilar kaya. An riga an yi alama Pin1 da Pin2 na tashar fadadawa akan allo.
Hoto 3-9-2: Fadada kai J11 akan allon ɗauka
J11 Faɗawa Babban Fil Assignment
Lambar Pin
FPGA Pin
Lambar Pin
FPGA Pin
1
GND
2
+5V
3
P16
4
R17
5
R16
6
P15
7
N17
8
P17
9
U16
10
Saukewa: T16
11
U17
12
U18
13
P19
14
R19
15
V18
16
V19
17
U20
18
V20
19
AA9
20
AB10
21
AA10
22
AA11
23
W10
24
V10
25
Y12
26
Y11
27
W12
28
W11
29
AA15
30
AB15
31
Y16
32
AA16
33
AB16
34
AB17
35
W14
36
Y14
37
GND
38
GND
39
+3.3V
40
+3.3V
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto 3-9-3: Fadada taken J13 makirci
Hoto na 3-9-4 yayi cikakken bayanin tashar fadada J13 akan allon jigilar kaya. An riga an yi alama Pin1 da Pin2 na tashar fadadawa akan allo.
Hoto 3-9-4: Fadada kai J13 akan allon jigilar kaya
J13 Faɗawa Babban Fil Assignment
Lambar Pin
FPGA Pin
1
GND
3
W16
5
V17
7
U15
Pin Number 2 4 6 8
FPGA Fin + 5V W15 W17 V15
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
9
AB21
10
AB22
11
AA21
12
AA20
13
AB20
14
AA19
15
AA18
16
AB18
17
Saukewa: T20
18
Y17
19
W22
20
W21
21
Saukewa: T21
22
U21
23
Y21
24
Y22
25
W20
26
W19
27
Y19
28
Y18
29
V22
30
U22
31
Saukewa: T18
32
R18
33
R14
34
P14
35
N13
36
N14
37
GND
38
GND
39
+3.3V
40
+3.3V
Kashi na 3.10: JTAG Interface
AJTAG an tanadar da mu'amala akan allon jigilar kaya na AX7203 FPGA don zazzage shirye-shiryen FPGA ko firmware zuwa FLASH. Don hana lalacewa ga guntu FPGA da ke haifar da toshe mai zafi, ana ƙara diode na kariya zuwa JTAG sigina don tabbatar da cewa voltage na siginar yana cikin kewayon da FPGA ke karɓa don gujewa lalacewar guntuwar FPGA.
Hoto 3-10-1: JTAG Tsare-tsare na Interface
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto 3-10-2: JTAG Interface akan allon jigilar kaya
Yi hankali kada a yi musanyar zafi lokacin da JTAG an toshe kebul kuma an cire shi.
Sashe na 3.11: XADC interface (ba a shigar da shi ta tsohuwa ba)
Kwamitin jigilar kaya na AX7203 yana da tsawaita mai haɗin haɗin XADC, kuma mai haɗawa yana amfani da fil ɗin 2 × 8 0.1 inch mai lamba biyu. Ƙaddamarwar XADC ta ƙaddamar da nau'i-nau'i uku na bambancin shigar da shigar ADC zuwa 12-Bit 1Msps analog-to-dijital Converter na FPGA. Ɗayan nau'i-nau'i na bambance-bambancen musaya an haɗa su zuwa tashar shigar da analog na musamman VP/VN na FPGA, kuma sauran nau'i-nau'i biyu an haɗa su daban-daban zuwa tashoshi na shigarwa na analog (tashar analog 0 da tashar analog 9). Hoto na 3-11-1 yana nuna matatar anti-aliasing da aka tsara don abubuwan shigar XADC daban-daban guda uku.
Hoto 3-11-1: Anti-Aliasing filter Schematic
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto 3-11-2: XADC Connector Schematic
Hoto 3-11-3: Mai Haɗin XADC akan allon ɗauka
XADC Pin Assignment
XADC Interface
FPGA Pin Input amplitude
Bayani
12 56 910
VP_0 : L10 VN_0 : M9 AD9P : J15 AD9N : H15 AD0P : H13 AD0N : G13
Kololuwa zuwa kololuwar tashar shigarwar XADC ta musamman ta 1V FPGA
Kololuwa zuwa kololuwar 1V Kololuwa zuwa kololuwar 1V
Tashar shigarwar XADC ta FPGA 9 (ana iya amfani da ita azaman IO na yau da kullun)
Tashar shigarwar XADC ta FPGA 0 (ana iya amfani da ita azaman IO na yau da kullun)
Sashe na 3.12: maɓalli
Kwamitin jigilar kaya na AX7203 FPGA ya ƙunshi maɓallan mai amfani guda biyu KEY1~KEY2. Ana haɗa duk maɓallan zuwa IO na FPGA na yau da kullun. Maɓallin yana aiki ƙasa kaɗan. Lokacin da aka danna maɓallin, shigar da IO voltage na FPGA yana da ƙasa. Lokacin da ba'a danna maɓalli ba, shigar da IO voltage na FPGA yana da girma. Ana nuna kewayar ɓangaren maɓalli a cikin hoto 3-12-1.
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto 3-12-1: Maɓalli Maɓalli
Hoto 3-13-2: Maɓallai biyu akan allon ɗauka
Maɓallan Pin Assignment
Net Sunan KEY1 KEY2
FPGA PIN J21 E13
Sashe na 3.13: Hasken LED
Akwai jajayen ledoji guda bakwai akan jirgi mai ɗaukar hoto na AX7203 FPGA, ɗayansu shine alamar wutar lantarki (PWR), biyu sune masu karɓar bayanan Uart na USB, kuma huɗun fitilun LED masu amfani ne (LED1 ~ LED4). Lokacin da aka kunna allon, alamar wutar lantarki zata haskaka; An haɗa LED1 ~ LED4 mai amfani zuwa IO na FPGA na yau da kullun. Lokacin da IO voltage haɗa zuwa mai amfani LED an saita low matakin, mai amfani LED fitilu sama. Lokacin da aka haɗa IO voltage an saita a matsayin babban matakin, mai amfani LED za a kashe. The
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Ana nuna zane-zane na haɗin kayan aikin LEDs mai amfani a cikin Hoto 3-13-1.
Hoto 3-13-1: Tsarin LEDs Mai amfani
Hoto 3-13-2: Fitilolin mai amfani akan allon ɗauka
Fitilar fitilun LED masu amfani
Sunan siginar LED1 LED2 LED3 LED4
FPGA PIN B13 C13 D14 D15
Sashe na 3.14: Samar da Wutar Lantarki
Shigar da wutar lantarki voltage na hukumar ci gaban AX7203 FPGA shine DC12V. Hakanan hukumar haɓaka tana goyan bayan wuta daga ƙirar PCIe kuma tana tallafawa samar da wutar lantarki kai tsaye daga wutar lantarki ta ATX chassis (12V).
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ARTIX-7 FPGA Development Board AX7203 Manual mai amfani
Hoto 3-14-1: Hanyar samar da wutar lantarki don hukumar AX7203 FPGA Hukumar mai ɗaukar kaya ta FPGA tana canza +12V vol.tage cikin + 5V, + 3.3V, +1.8V da +1.2V masu samar da wutar lantarki ta hanyar 4-tashar DC/DC guntu samar da wutar lantarki MP1482. Bugu da kari, wutar lantarki ta +5V akan hukumar jigilar kaya ta FPGA tana ba da wutar lantarki ga babban allon AC7100B FPGA ta hanyar haɗin allo. Ana nuna ƙirar wutar lantarki akan haɓakawa a cikin Hoto 3-14-2.
Hoto 3-14-2: Tsarin samar da wutar lantarki akan allon mai ɗauka
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ARTIX-7 FPGA Development Board AX7203 Hoto na Mai Amfani 3-14-3: Da'irar Samar da Wuta akan allon Mai ɗauka
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ALINX AX7203 FPGA Development Board [pdf] Manual mai amfani AX7203 FPGA Development Board, AX7203, FPGA Development Board, Board Development Board, Board |
