Arty Z7 Jagorar Jagora
Arty Z7 shiri ne na ci gaba mai amfani wanda aka tsara a kusa da Zynq-7000 ™ Duk Tsarin Tsarin Tsarin Tsarin Chip (AP SoC) daga Xilinx. Tsarin gine-ginen Zynq-7000 ya hada karfi-da-daki, mai sarrafa 650 MHz () mai sarrafa ARM Cortex-A9 tare da dabarun Xilinx 7-jerin Field Programmable Gate Array (FPGA). Wannan haɗin yana ba da damar kewaye da mai sarrafa mai ƙarfi tare da keɓaɓɓen saitin kayan aikin software da masu sarrafawa, wanda aka tsara don aikace-aikacen manufa.
Abubuwan kayan aiki na Vivado, Petalinux, da SDSoC kowannensu yana ba da hanya mai kusanta tsakanin bayyana tsarin al'adunku na yau da kullun da kuma kawo aikinsa har zuwa Linux OS () ko shirin ƙaramin ƙarfe da ke gudana akan mai sarrafawa. Ga waɗanda ke neman ƙwarewar ƙirar ƙirar dijital na gargajiya, yana yiwuwa kuma a yi watsi da masu sarrafa ARM kuma a shirya FPGA ta Zynq kamar yadda za ku yi da kowane Xilinx FPGA. Digilent yana ba da abubuwa da albarkatu da yawa don Arty Z7 wanda zai ba ku damar aiki da kayan aikin da kuka zaɓa da sauri.
Arty Z7 Jagorar Jagora [Bayani.Digilentinc]
Zazzage Wannan Littafin Nuni
- Wannan littafin koyarwar bai riga ya iya saukewa ba.
Siffofin
Mai sarrafa ZYNQ
- 650MHz mai kwakwalwa biyu Cortex-A9 mai sarrafawa
- Mai sarrafa ƙwaƙwalwar DDR3 tare da tashoshin DMA 8 da tashar jiragen ruwa 4 mai girma AXI3
- Masu sarrafa keɓaɓɓun-bandwidth: 1G Ethernet, USB 2.0, SDIO
- -Ananan mai haɗin bandwidth na gefe: SPI, UART, CAN, I2C
- Mai shirye-shirye daga JTAG, Quad-SPI flash, da katin microSD
- Shirye-shiryen maganganu daidai da Artix-7 FPGA
Ƙwaƙwalwar ajiya
- 512MB DDR3 tare da bas 16-bit @ 1050Mbps
- 16MB Quad-SPI Flash tare da masana'antar da aka tsara 48-bit a duniya ta musamman EUI-48/64 ident mai ganowa mai jituwa
- katin microSD
Ƙarfi
- Ana amfani da shi daga USB ko kowane tushen ƙarfin waje na 7V-15V
USB da Ethernet
- Gigabit Ethernet PHY
- USB-JTAG Shirye-shiryen kewayawa
- USB-UART gada
- USB OTG PHY (yana tallafawa mai masaukin kawai)
Audio da Bidiyo
- HDMI nutse tashar jiragen ruwa (labari)
- HDMI tashar tashar ruwa (fitarwa)
- PWM wanda aka fitar dashi na sauti daya tare da jack na 3.5mm
Masu sauyawa, Maballin maɓallan wuta, da kuma ledodi
- 4 maɓallan turawa
- 2 nunin faifai
- 4 LEDs
- 2 RGB LEDs
Haɗa Fadada
- Tashoshin Pmod guda biyu
- 16 Jimlar FPGA I / O
- Arduino / chipKIT Garkuwan Garkuwa
- Har zuwa 49 Total FPGA I / O (duba tebur a ƙasa)
- 6 Abubuwan da aka yi amfani da su na Analog mai ƙare-guda wanda ya ƙare zuwa XADC
- 4 Bambancin 0-1.0V abubuwan Analog zuwa XADC
Zaɓuɓɓukan Sayayya
Ana iya siyan Arty Z7 tare da ko wacce Zynq-7010 ko Zynq-7020 da aka loda. Wadannan nau'ikan samfurin Arty Z7 guda biyu ana kiran su Arty Z7-10 da Arty Z7-20, bi da bi. Lokacin da takaddar Digilent ke bayanin aikin da yake gama gari ga duka waɗannan bambance-bambancen, ana kiran su gaba ɗaya azaman "Arty Z7". Lokacin bayyana wani abu wanda yake sananne ne ga takamaiman bambance-bambancen, za a kira mai bambancin da sunansa.
Bambanci kawai tsakanin Arty Z7-10 da Arty Z7-20 sune iyawar ɓangaren Zynq da adadin I / O da ke kan mahaɗin garkuwar. Masu sarrafa Zynq duka suna da iko iri ɗaya, amma -20 yana da kusan sau 3 wanda ya fi girma FPGA fiye da -10. Bambance-bambance tsakanin bambance-bambancen guda biyu an taƙaita su a ƙasa:
| Samfurin Bambanci | Farashin Z7-10 | Farashin Z7-20 |
| Zynq Kashi | Saukewa: XC7Z010-1CLG400C | Saukewa: XC7Z020-1CLG400C |
| 1 MSPS Kunnawa ADC () | Ee | Ee |
| Kallon kallo (LUTs) | 17,600 | 53,200 |
| Juyawa-Flops | 35,200 | 106,400 |
| Toshe RAM () | 270 KB | 630 KB |
| Fale-falen Gudanar da agogo | 2 | 4 |
| Garkuwan da ke akwai I/O | 26 | 49 |
A Arty Z7-10, layin ciki na garkuwar dijital (IO26-IO41) da IOA (wanda ake kira IO42) ba a haɗa su da FPGA ba, kuma ana iya amfani da A0-A5 azaman abubuwan analog. Wannan ba zai shafi aikin mafi yawan garkuwar Arduino ba, saboda yawancin basu amfani da wannan layi na sigina na dijital.
Ana iya siyan kwamitin tsayawa shi kaɗai ko tare da baucan don buɗe kayan aikin kayan aikin Xilinx SDSoC. Fansar SDSoC tana buɗe lasisin shekara 1 kuma ana iya amfani dashi kawai tare da Arty Z7. Bayan lasisi ya ƙare, duk wani nau'I na SDSoC da aka saki a cikin wannan lokacin na shekara 1 na iya ci gaba da amfani da shi har abada. Don ƙarin bayani game da siyayya, duba Shafin Arty Z7 (http://store.digilentinc.com/artyz7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/).
A lokacin sayan, zai yiwu kuma a ƙara katin microSD, 12V 3A mai ba da wuta, da kuma kebul na USB kamar yadda ake buƙata.
Lura cewa saboda ƙaramin FPGA a cikin Zynq-7010, bai dace sosai da amfani dashi a SDSoC don aikace-aikacen hangen nesa ba. Muna ba da shawarar mutane su sayi Arty Z7-20 idan suna sha'awar waɗannan nau'ikan aikace-aikacen.
Bambanci daga PYNQ-Z1
Arty Z7-20 yayi daidai da SoC daidai da PYNQ-Z1. Mai hikima, Arty Z7-20 ya rasa shigarwar makirufo, amma yana ƙara maɓallin Sake saita Maɓallin-Kunnawa. Software da aka rubuta don PYNQ-Z1 yakamata ya canza ba tare da shigar da makirufo ba, wanda aka bar fil ɗin FPGA ba'a haɗa shi ba.
Tallafin Software
Arty Z7 ya dace da Xilinx's babban aikin Vivado Design Suite. Wannan kayan aikin kayan kayan yana amfani da fasahar FPGA da kuma shigar da kayan aikin ARM cikin sauki-da-amfani, kwararar zane mai sauki. Ana iya amfani da shi don tsara tsarin kowane irin rikitarwa, daga cikakken tsarin aiki wanda ke gudanar da aikace-aikacen sabar da yawa a cikin jaka, zuwa ƙasa mai sauƙi na ƙarfe wanda yake sarrafa wasu LED.
Hakanan yana yiwuwa a kula da Zynq AP SoC a matsayin FPGA na tsaye ga waɗanda ba su da sha'awar amfani da na'ura mai sarrafawa a ƙirar su. Tun daga fitowar Vivado 2015.4, Mai Analyzer Logic da Siffofin Haɗin Haɓakawa na Vivado suna da kyauta don amfani ga kowa. WebPACK hari, wanda ya haɗa da Arty Z7. Mai Binciken Logic yana taimakawa tare da dabaru na gyara kuskure, kuma kayan aikin HLS yana ba ku damar haɗa lambar C kai tsaye zuwa HDL.
Tsarin dandamali na Zynq sun dace sosai don saka makasudin Linux, kuma Arty Z7 ba banda bane. Don taimaka muku farawa, Digilent yana ba da aikin Petalinux wanda zai tashe ku tare da tsarin Linux da sauri. Don ƙarin bayani, duba Arty Z7 Cibiyar Sadarwa (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start).
Hakanan ana iya amfani da Arty Z7 a cikin yanayin SDSoC na Xilinx, wanda ke ba ku damar tsara shirye-shiryen FPGA cikin sauri da bututun bidiyo tare da sauƙi a cikin yanayin C / C ++ gaba ɗaya. Don ƙarin bayani akan SDSoC, duba Shafin Xilinx SDSoC
(https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html). Digilent za ta saki dandamali mai iya Bidiyo tare da tallafi na Linux a cikin lokaci don sakin SDSoC 2017.1. Lura cewa saboda ƙaramin FPGA a cikin Arty Z7-10, ƙirar demokradiyya ta asali kawai ake haɗawa tare da wannan dandalin. Digilent yana ba da shawarar Arty Z7-20 don waɗanda ke da sha'awar sarrafa bidiyo.
Waɗanda suka saba da tsofaffin kayan aikin kayan aikin Xilinx ISE / EDK daga gabanin a saki Vivado suna iya zaɓar amfani da Arty Z7 a cikin wannan kayan aikin. Digilent bashi da kayan aiki da yawa don tallafawa wannan, amma koyaushe kuna iya neman taimako akan Dandalin Digilent (https://forum.digilentinc.com).
Kayayyakin Wutar Lantarki
Ana iya kunna Arty Z7 daga Digilent USB-JTAG-UART tashar jiragen ruwa (J14) ko daga wani nau'in tushen wutar lantarki kamar baturi ko wutar lantarki ta waje. Jumper JP5 (kusa da wutar lantarki) yana ƙayyade wane tushen wutar lantarki ake amfani da shi.
Tashar tashar USB 2.0 na iya isar da iyakar 0.5A na halin yanzu bisa ga ƙayyadaddun bayanai. Wannan ya kamata ya samar da isasshen ƙarfi don ƙananan ƙirar ƙira. Ƙarin aikace-aikacen da ake buƙata, gami da duk wani mai sarrafa allunan gefe ko wasu na'urorin USB, na iya buƙatar ƙarin ƙarfi fiye da yadda tashar USB ke bayarwa. A wannan yanayin, amfani da wutar lantarki zai ƙaru har sai an iyakance shi ta wurin mai masaukin USB. Wannan iyaka ya bambanta da yawa tsakanin masu kera kwamfutoci masu masaukin baki kuma ya dogara da abubuwa da yawa. Lokacin a cikin iyaka na yanzu, sau ɗaya voltage dogo sun nutse ƙasa da ƙimar ƙimar su, ana sake saita Zynq ta siginar Sake saitin Wuta kuma amfani da wutar yana komawa zuwa ƙimar sa mara amfani. Hakanan, wasu aikace-aikacen na iya buƙatar aiki ba tare da an haɗa su da tashar USB ta PC ba. A cikin waɗannan lokuta, ana iya amfani da wutar lantarki ta waje ko baturi.
Ana iya amfani da wutar lantarki ta waje (misali wart bango) ta hanyar toshe shi cikin jack ɗin wuta (J18) da saita jumper JP5 zuwa "REG". Dole ne wadatawar ta yi amfani da coax, filogi mai diamita na tsakiya 2.1mm, kuma ya isar da 7VDC zuwa 15VDC. Ana iya siyan kayayyaki masu dacewa daga Digilent website ko ta hanyar dillalai kamar DigiKey. Mai ba da wutar lantarki voltages sama da 15VDC na iya haifar da lalacewa ta dindindin. An haɗa wutar lantarki mai dacewa ta waje tare da kayan haɗi na Arty Z7.
Kama da yin amfani da wutar lantarki ta waje, ana iya amfani da baturi don ƙarfafa Arty Z7 ta hanyar haɗa shi zuwa mahaɗin garkuwar da saita tsalle JP5 zuwa "REG". Dole ne a haɗa tabbatacciyar tashar batirin da fil ɗin da aka yiwa lakabi da "VIN" akan J7, kuma dole ne a haɗa m ɗin ɗin da lambar GND () mai lamba J7.
Kayan Texas Kayan aiki TPS65400 PMU ya kirkiro buƙatun 3.3V, 1.8V, 1.5V, da 1.0V da ake buƙata daga babban shigarwar wutar lantarki. Tebur 1.1 yana ba da ƙarin bayani (hankula na yau da kullun suna dogara ne ƙwarai akan daidaitawar Zynq kuma ƙimomin da aka bayar sune na sifofin matsakaici / saurin sauri).
Arty Z7 ba shi da wutar lantarki, don haka lokacin da aka haɗa tushen wuta kuma aka zaɓa tare da JP5 koyaushe za a kunna shi. Don sake saita Zynq ba tare da cire haɗin da sake haɗa wutar lantarki ba, ana iya amfani da maɓallin SRST ja. Alamar wutar lantarki LED () (LD13) tana kunne lokacin da duk hanyoyin dogo na samarwa suka kai ga ƙimatage.
| wadata | Da'irori | Current (max/typical) |
| 3.3V | FPGA I / O, tashar USB, Clocks, Ethernet, SD slot, Flash, HDMI | 1.6A / 0.1A zuwa 1.5A |
| 1.0V | FPGA, Ethernet Core | 2.6A / 0.2A zuwa 2.1A |
| 1.5V | DDR3 | 1.8A / 0.1A zuwa 1.2A |
| 1.8V | Mataimakin FPGA, Ethernet I / O, Mai Kula da USB | 1.8A / 0.1A zuwa 0.6A |
Tebur 1.1. Arty Z7 wutar lantarki.
Zynq APSoC Gine-gine
Zynq APSoC ya kasu kashi biyu daban-daban na tsarin aiki: Tsarin Gudanarwa (PS) da Dabarun Shirye-shiryen (PL). Hoto 2.1 yana nuna ƙarewaview na gine-ginen Zynq APSoC, tare da PS mai launin kore mai haske da PL a cikin rawaya. Lura cewa PCIe Gen2 mai sarrafa da Multi-gigabit transceivers ba su samuwa akan na'urorin Zynq-7020 ko Zynq-7010. 
(https://reference.digilentinc.com/_detail/zybo/zyng1.png?id=reference%3Aprogrammable-logic%3Aarty-z7%3Areference-manual)
Hoto 2.1 gine-ginen Zynq APSoC
PL yana kusan kama da jerin Xilinx 7 Artix FPGA, sai dai yana ƙunshe da tashoshin jiragen ruwa da bas da yawa waɗanda ke haɗa shi zuwa PS. Hakanan PL ɗin ba ya ƙunshi kayan masarufi iri ɗaya kamar FPGA na 7-jeri na yau da kullun, kuma dole ne a saita shi ko dai ta hanyar mai sarrafawa ko ta hanyar J.TAG tashar jiragen ruwa.
PS ɗin ta ƙunshi abubuwa da yawa, gami da Unungiyar Aikace-aikacen Aikace-aikacen (APU, wanda ya haɗa da masu sarrafa 2 Cortex-A9), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory mai kula, da kuma masu kula da gefe daban-daban tare da kayan aikinsu da kayan aikin da aka ninka zuwa 54 sadaukarwa fil (wanda ake kira Multiplexed I / O, ko MIO pin). Masu kula da gefe waɗanda basu da kayan aikin su da kayan haɗin da aka haɗa da madogarar MIO na iya maimakon hanyar I / O ta hanyar PL, ta hanyar hanyar Extended-MIO (EMIO). Masu haɗin gefe suna haɗuwa da masu sarrafawa azaman bayi ta hanyar haɗin AMBA kuma suna ƙunshe da bayanan rijista mai saurin karantawa wanda za'a iya magance su a cikin sararin ƙwaƙwalwar sarrafawa. Hakanan an haɗa ma'anar shirye-shiryen zuwa haɗin haɗi azaman bawa, kuma ƙira na iya aiwatar da ɗimbin abubuwa a cikin masana'antar FPGA cewa kowannensu ma yana da rijistar sarrafa adireshi. Bugu da ƙari, ƙananan abubuwan da aka aiwatar a cikin PL na iya haifar da tsangwama ga masu sarrafawa (haɗin da ba a nuna a cikin hoto na 3 ba) da yin damar DMA zuwa ƙwaƙwalwar DDR3.
Akwai fannoni da yawa na tsarin gine-ginen Zynq APSoC waɗanda suka fi ƙarfin wannan kundin. Don cikakken cikakken bayanin, koma zuwa ga Zynq Bayanin Fasaha Saukewa: ug585-Zynq-7000TRM [PDF]
Tebur 2.1 yana kwatanta abubuwan waje da aka haɗa zuwa fil ɗin MIO na Arty Z7. Zynq Presets File samu akan Arty Z7 Cibiyar Sadarwa (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start) za a iya shigo da su cikin EDK da Vivado Designs don tsara PS ɗin yadda yakamata don aiki tare da waɗannan kayan haɗin.
| MIO 500 3.3 V | Na'urorin haɗi |
| Pin | SAMU 0 | Farashin SPI | Kebul na USB 0 | Garkuwa | Farashin 0 |
| 0 (N / C) | |||||
| 1 | CS () | ||||
| 2 | DQ0 | ||||
| 3 | DQ1 | ||||
| 4 | DQ2 | ||||
| 5 | DQ3 | ||||
| 6 | SCLK () | ||||
| 7 (N / C) | |||||
| 8 | SLCK FB | ||||
| 9 | Sake saitin Ethernet | ||||
| 10 | Ethernet katsewa | ||||
| 11 | USB Sama da Yanzu | ||||
| 12 | Garkuwar Garkuwa | ||||
| 13 (N / C) | |||||
| 14 | Shigar da UART | ||||
| 15 | Sakamakon UART |
| MIO 501 1.8V | Na'urorin haɗi | ||
| Pin | SAMU 0 | Kebul na USB 0 | SDI 0 |
| 16 | Lambar rubutu | ||
| 17 | MUX0 | ||
| 18 | MUX1 | ||
| 19 | MUX2 | ||
| 20 | MUX3 | ||
| 21 | Lissafi | ||
| 22 | RXCK | ||
| 23 | Saukewa: RXD0 | ||
| 24 | Saukewa: RXD1 | ||
| 25 | Saukewa: RXD2 | ||
| 26 | Saukewa: RXD3 | ||
| 27 | RXCTL | ||
| 28 | DATA4 | ||
| 29 | DIR | ||
| 30 | STP | ||
| 31 | NXT | ||
| 32 | DATA0 | ||
| 33 | DATA1 | ||
| 34 | DATA2 | ||
| 35 | DATA3 | ||
| 36 | CLK | ||
| 37 | DATA5 | ||
| 38 | DATA6 | ||
| 39 | DATA7 | ||
| 40 | CCLK | ||
| 41 | CMD | ||
| 42 | D0 | ||
| 43 | D1 | ||
| 44 | D2 | ||
| 45 | D3 | ||
| 46 | SAUKA | ||
| 47 | CD | ||
| 48 (N / C) | |||
| 49 (N / C) | |||
| 50 (N / C) | |||
| 51 (N / C) | |||
| 52 | MDC | ||
| 53 | MDIO |
Zynq Kanfigareshan
Ba kamar na'urorin Xilinx FPGA ba, na'urorin APSoC kamar Zynq-7020 an ƙirƙira su a kusa da na'ura mai sarrafawa, wanda ke aiki azaman jagora ga masana'anta na dabaru da duk sauran abubuwan da ke kan guntu a cikin tsarin sarrafawa. Wannan yana haifar da tsarin taya Zynq ya zama kama da na microcontroller fiye da FPGA. Wannan tsari ya haɗa da lodawa da aiwatar da Hoton Zynq Boot, wanda ya haɗa da Farko Stage Bootloader (FSBL), wani bitstream don daidaita tsarin dabaru (na zaɓi), da aikace-aikacen mai amfani. Tsarin taya ya karye zuwa s ukutage:
Stage 0
Bayan an kunna Arty Z7 ko an sake saita Zynq (a cikin software ko ta latsa SRST), ɗayan masu sarrafawa (CPU0) zai fara aiwatar da wani yanki na lambar karantawa kawai da ake kira BootROM. Idan kuma kawai idan an kunna Zynq ne kawai, BootROM zai fara saka yanayin yanayin fil din cikin rijistar yanayin (fil din an lika shi zuwa JP4 akan Arty Z7). Idan ana aiwatar da BootROM saboda abin da ya faru na sake saiti, to, ba a kunna fil fil ɗin yanayin ba, kuma ana amfani da yanayin da ya gabata na yanayin rajistar. Wannan yana nufin cewa Arty Z7 yana buƙatar sake zagayowar wuta don yin rijistar kowane canji a cikin yanayin tsalle-tsalle (JP4). Gaba, BootROM yana kwafin FSBL daga nau'ikan ƙwaƙwalwar ajiyar ƙwaƙwalwa wanda aka ƙayyade ta hanyar rijistar yanayin zuwa 256 KB na RAM na ciki () a cikin APU (wanda ake kira On-Chip Memory, ko OCM). FSBL dole ne a nade shi a cikin Zynq Boot Image domin BootROM ya kwafe shi yadda yakamata. Abu na karshe da BootROM yayi shine kashe kashe ga FSBL a cikin OCM.
Stage 1
A lokacin wannan stage, FSBL ta fara gama daidaita abubuwan PS, kamar mai sarrafa ƙwaƙwalwar ajiyar DDR. Sannan, idan bitstream yana cikin Hoton Zynq Boot, ana karanta shi kuma ana amfani dashi don saita PL. A ƙarshe, ana loda aikace-aikacen mai amfani zuwa ƙwaƙwalwar ajiya daga Hoton Boot na Zynq, kuma ana ƙaddamar da aiwatar da shi.
Stage 2
Karshe stage shine aiwatar da aikace-aikacen mai amfani wanda FSBL ya loda. Wannan na iya zama kowane irin shiri, daga ƙirar "Hello Duniya" mai sauƙi zuwa na biyu Stage Boot Loder da ake amfani da shi don taya tsarin aiki kamar Linux. Don ƙarin cikakkun bayanai game da tsarin taya, koma zuwa Babi na 6 na Zynq Bayani na fasaha (Taimako [PDF]).
An ƙirƙiri Hoton Zynq Boot yana raira waƙa Vivado da Kit ɗin Ci gaban Software na Xilinx (Xilinx SDK). Don bayani game da ƙirƙirar wannan hoton da fatan za a duba samfuran samfuran Xilinx don waɗannan kayan aikin.
Arty Z7 yana goyan bayan nau'ikan taya uku: microSD, Quad SPI Flash, da JTAG. An zaɓi yanayin taya ta amfani da Jump Mode (JP4), wanda ke shafar yanayin madaidaitan fil ɗin Zynq bayan kunnawa. Hoto 3.1 yana kwatanta yadda ake haɗa fil ɗin daidaitawar Zynq akan Arty Z7.
(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-config.png?d=reference%3Aprogrammable-ogic%3Aartyz7%3Areference-manual)
Hoto na 3.1. Arty Z7 ƙirar sanyi.
An bayyana hanyoyi guda uku na taya a cikin sassan masu zuwa.
Yanayin Taya microSD
Arty Z7 na goyan bayan haɓaka daga katin microSD da aka saka a cikin J9 mai haɗawa. Hanyar da ke tafe za ta ba ka damar kora Zynq daga microSD tare da daidaitaccen Hoton Zynq Boot da aka kirkira tare da kayan aikin Xilinx:
- Shirya katin microSD tare da FAT32 file tsarin.
- Kwafi Hoton Zynq Boot wanda aka kirkira tare da Xilinx SDK zuwa katin microSD.
- Sake suna Hoton Zynq Boot akan katin microSD zuwa BOOT.bin.
- Fitar da katin microSD daga kwamfutarka kuma saka shi cikin haɗin J9 akan Arty Z7.
- Haɗa tushen wuta zuwa Arty Z7 kuma zaɓi shi ta amfani da JP5.
- Sanya tsalle ɗaya a kan JP4, rage gajeren maɓallan saman guda biyu (wanda aka yiwa alama "SD").
- Kunna allon. A yanzu hukumar za ta taya hoton a kan katin microSD.
Yanayin Boot na Quad SPI
Arty Z7 yana da Flash 16MB Quad-SPI Flash wanda Zynq zai iya farawa daga. Takardun da aka samo daga Xilinx ya bayyana yadda ake amfani da Xilinx SDK don shirya Hoton Zynq Boot a cikin na'urar Flash da ke haɗe da Zynq. Da zarar an ɗora Quad SPI Flash tare da Zynq Boot Image, za a iya bin waɗannan matakan don taya daga ita:
- Haɗa tushen wuta zuwa Arty Z7 kuma zaɓi shi ta amfani da JP5.
- Sanya tsalle ɗaya a kan JP4, rage gajeren maɓallan tsakiya biyu (mai taken "QSPI").
- Kunna allon. Yanzu hukumar za ta taya hoton da aka adana a cikin filashin Quad SPI.
JTAG Yanayin Boot
Lokacin da aka sanya a cikin JTAG Yanayin boot, mai sarrafa na'ura zai jira har sai an ɗora software ta kwamfutar mai watsa shiri ta amfani da kayan aikin Xilinx. Bayan an loda software, yana yiwuwa ko dai a bar software ta fara aiwatarwa, ko kuma a bi ta layi ta hanyar amfani da Xilinx SDK.
Hakanan yana yiwuwa a saita PL kai tsaye akan JTAG, mai zaman kansa daga mai sarrafawa. Ana iya yin wannan ta amfani da Vivado Hardware Server.
An saita Arty Z7 don taya a cikin Cascaded JTAG yanayin, wanda ke ba da damar samun dama ga PS ta hanyar JTAG tashar jiragen ruwa kamar PL. Hakanan yana yiwuwa a kunna Arty Z7 a cikin Independent JTAG yanayin ta loda jumper a cikin JP2 kuma rage shi. Wannan zai sa ba za a iya samun damar PS daga kan JTAG circuitry, kuma kawai PL za a iya gani a cikin scan sarkar. Don samun dama ga PS akan JTAG yayin da yake zaman kansa JTAG yanayin, masu amfani dole ne su bi siginonin PJTAG na gefe sama da EMIO, kuma yi amfani da na'urar waje don sadarwa da ita.
Yan hudu SPI Flash
Arty Z7 yana fasalin Quad SPI serial NOR flash. Ana amfani da Fadada S25FL128S akan wannan jirgin. Ana amfani da Multi-I / O SPI Flash memory don samar da lambar da ba ta canzawa da kuma adana bayanai. Ana iya amfani dashi don farawa tsarin tsarin PS tare da daidaita tsarin tsarin PL. Abubuwan halayyar na'urar masu dacewa sune:
- 16 MB ()
- x1, x2, da x4 tallafi
- Motar ta gudu zuwa 104 MHz (), tana tallafawa ƙididdigar daidaitawar Zynq @ 100 MHz (). A cikin yanayin Quad SPI, wannan yana fassara zuwa 400Mbs
- Ana aiki daga 3.3V
SPI Flash yana haɗuwa da Zynq-7000 APSoC kuma yana goyan bayan Quad SPI interface. Wannan yana buƙatar haɗi zuwa takamaiman fil a cikin MIO Bank 0/500, musamman MIO [1: 6,8] kamar yadda aka tsara a cikin Zynq datasheet. Ana amfani da yanayin ba da martani na Quad-SPI, saboda haka qspi_sclk_fb_out / MIO [8] ana barin shi don canzawa da yardar kaina kuma an haɗa shi kawai zuwa maƙerin ja-in ja 20K zuwa 3.3V. Wannan yana bawa damar Quad SPI mitar ta fi FQSPICLK2 girma (Duba littafin Zynq Technical Reference manual
( ug585-Zynq-7000-TRM [PDF]) don ƙarin bayani akan wannan).
Ƙwaƙwalwar DDR
Arty Z7 ya haɗa da abubuwan ƙwaƙwalwar IS43TR16256A-125KBL DDR3 waɗanda ke ƙirƙirar matsayi guda, mai faɗin 16-faɗi mai faɗi, da jimlar 512MiB na iya aiki. An haɗa DDR3 zuwa mai sarrafa ƙwaƙwalwar ajiya mai ƙarfi a cikin Processor Subsystem (PS), kamar yadda aka tsara a cikin takardun Zynq.
PS ɗin ta haɗu da tashar tashar tashar ƙwaƙwalwar ajiyar AXI, mai sarrafa DDR, haɗin PHY, da bankin I / O. Ana goyan bayan ƙwaƙwalwar ajiyar DDR3 har zuwa 533 MHz () / 1066 Mbps ana tallafawa ¹.
An kori Arty Z7 tare da 40 ohms (+/-- 10%) alama ta alama don siginoni masu ƙarewa guda ɗaya, da agogo daban da hanzari waɗanda aka saita zuwa 80 ohms (+/- 10%). Wani fasali da ake kira DCI (Tsarin Digiri Na Digitally) ana amfani dashi don dacewa da ƙarfin tuki da ƙarewar ƙwanƙwasa na fil na PS zuwa maƙasudin alama. A gefen ƙwaƙwalwar, kowane guntu yana ƙayyade ƙarshen mutuwarsa da ƙarfin motsawa ta amfani da tsayayyar 240-ohm akan lambar ZQ.
Saboda dalilan shimfidawa, an canza wasu rukunin baiti guda biyu (DQ [0-7], DQ [8-15]). A daidai wannan sakamakon, an sauya ragin bayanan cikin ƙungiyoyin baiti. Waɗannan canje-canje suna bayyane ga mai amfani. Yayin duk tsarin ƙira, an bi ka'idodin Xilinx PCB.
Dukkanin kwakwalwar ƙwaƙwalwar ajiya da bankin PS DDR suna da ƙarfi daga wadatar 1.5V. Matsakaicin matsakaici na 0.75V an ƙirƙira shi tare da mai rarrabuwa mai sauƙi kuma akwai shi ga Zynq azaman isharar waje.
Don aikin da ya dace, yana da mahimmanci cewa an daidaita mai sarrafa ƙwaƙwalwar ajiyar PS yadda ya kamata. Saituna suna kewayo daga ainihin ɗanɗanon ƙwaƙwalwar ajiya zuwa jinkirin alamar allo. Don jin daɗin ku, saitattun Zynq file domin an bayar da Arty Z7 akan cibiyar albarkatun
(https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start) kuma ta atomatik yana daidaita Zynq Processing System IP core tare da madaidaitan sigogi.
Don mafi kyawun aikin DDR3, ana ba da horo na DRAM don daidaitaccen rubutu, karanta ƙofar, da karanta zaɓuɓɓukan ido na bayanai a cikin Kayan Gudanarwar PS a cikin kayan aikin Xilinx. Ana gudanar da horo koyaushe ta hanyar mai kula don yin lissafin jinkirin jirgi, bambance-bambancen aiwatarwa da kuma yawo da zafi. Valuesimar farawa mafi kyau don tsarin horo sune jinkirin jirgi (jinkirin yaɗuwa) don takamaiman siginar ƙwaƙwalwa.
An bayyana jinkirin kwamiti don kowane rukunin byte. Waɗannan sigogi suna takamaiman kwamiti kuma an lissafta su daga rahoton rahoton PCB. Ana ƙididdige ƙididdigar DQS zuwa CLK da jinkirin jinkiri na Musamman ga ƙirar ƙwaƙwalwar ajiyar Arty Z7 PCB.
Don ƙarin bayani game da aikin mai sarrafa ƙwaƙwalwa, koma zuwa Xilinx Zynq Bayani na fasaha ( ug585-Zynq-7000-TRM [PDF]).
¹ Matsakaicin matsakaicin tsayin agogo shine 525 MHz () akan Arty Z7 saboda iyakance PLL.
Kebul UART Bridge (Serial Port)
Arty Z7 ya haɗa da gada ta FTDI FT2232HQ USB-UART (haɗe da mai haɗa J14) wanda zai baka damar amfani da aikace-aikacen PC don
sadarwa tare da kwamiti ta amfani da ƙa'idodin tashar tashar jiragen ruwa ta COM (ko ƙirar TTY a cikin Linux). Ana shigar da direbobi ta atomatik a cikin Windows da sababbin nau'ikan Linux. Ana musaya bayanan tashar serial tare da Zynq ta amfani da tashar tashar waya mai waya biyu (TXD / RXD). Bayan an shigar da direbobi, ana iya amfani da umarni na / O daga PC ɗin da aka tura zuwa tashar jiragen ruwa ta COM don samar da zirga-zirgar bayanan bayanai a kan fil na Zynq. An haɗa tashar jiragen ruwa zuwa maɓallan PS (MIO) kuma ana iya amfani dashi a haɗe tare da mai kula da UART.
Saitattun Zynq file (akwai a cikin Arty Z7 Cibiyar Sadarwa (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start))
yana kula da tsara taswirar MIO daidai zuwa mai kula da UART 0 kuma yana amfani da sigogin yarjejeniya ta tsoho: ƙimar 115200, ƙarancin dakatarwa 1, babu daidaituwa, tsayin hali 8-bit.
Matsayin matsayi guda biyu LEDs suna ba da ra'ayi na gani akan zirga-zirgar da ke gudana ta tashar jiragen ruwa: LED mai watsawa () (LD11) da LED mai karɓar () (LD10). Sunayen sigina waɗanda ke nuna jagora sun fito ne daga maƙasudin--view na DTE (Data Terminal Equipment), a wannan yanayin PC.
Hakanan ana amfani da FT2232HQ azaman mai sarrafawa don Digilent USB-JTAG na'ura mai ba da hanya tsakanin hanyoyin sadarwa, amma USB-UART da USB-JTAG ayyuka suna yin gaba ɗaya ba tare da juna ba. Masu shirye-shirye masu sha'awar yin amfani da aikin UART na FT2232 a cikin ƙirar su ba sa buƙatar damuwa game da J.TAG circuitry yana tsoma baki tare da canja wurin bayanai na UART, da mataimakinsa. Haɗin waɗannan fasalulluka guda biyu zuwa na'ura ɗaya yana ba da damar Arty Z7 don tsarawa, sadarwa da su ta hanyar UART, da kuma kunna wutar lantarki daga kwamfutar da aka makala tare da Micro USB USB guda ɗaya.
Alamar DTR daga mai sarrafa UART akan FT2232HQ an haɗa ta zuwa MIO12 na na'urar Zynq ta hanyar JP1. Idan Arduino IDE za a tura shi don aiki tare da Arty Z7, ana iya gajarta wannan tsalle kuma za a iya amfani da MIO12 don sanya Arty Z7 a cikin "shirye don karɓar sabon zane". Wannan zaiyi kama da dabi'un kayan marubutan IDU na IDE.
microSD Slot
Arty Z7 yana ba da maɓallin MicroSD (J9) don ajiyar ƙwaƙwalwar ajiyar waje mara kyau da kuma kunna Zynq. Ramin yana da wayoyi zuwa Bankin 1/501 MIO [40-47], gami da Gano Katin. A gefen PS, ana tsara SDIO 0 na gefe zuwa waɗannan fil ɗin kuma yana sarrafa sadarwa tare da katin SD. Ana iya ganin pinout a cikin Table 7.1. Mai kula da gefe yana tallafawa 1-bit da 4-bit SD canja yanayin amma baya tallafawa yanayin SPI. Bisa ga Zynq Bayani na fasaha ( Taimako [PDF]), Yanayin mai karɓar SDIO shine kawai hanyar da ake tallafawa.
| Sunan siginar | Bayani | Pin Zynq | Pin Ramin SD |
| SD_D0 | Bayanai [0] | MIO42 | 7 |
| SD_D1 | Bayanai [1] | MIO43 | 8 |
| SD_D2 | Bayanai [2] | MIO44 | 1 |
| SD_D3 | Bayanai [3] | MIO45 | 2 |
| SD_CCLK | Agogo | MIO40 | 5 |
| SD_CMD | Umurni | MIO41 | 3 |
| SD_CD | Gano Katin | MIO47 | 9 |
Tebur 7.1. gyaran microSD
Ramin SD yana aiki daga 3.3V amma an haɗa shi ta hanyar MIO Bank 1/501 (1.8V). Saboda haka, TI TXS02612 matakin canjawa yana yin wannan fassarar. TXS02612 shine ainihin mai faɗaɗa tashar tashar SDIO mai tashar jiragen ruwa 2, amma kawai ana amfani da aikin canza matakinsa. Ana iya ganin zanen haɗin gwiwa akan Hoto 7.1. Ana aiwatar da taswirar madaidaitan fil tare da daidaita mahaɗin ta hanyar saitattun kayan aikin Arty 7 Zynq file, samuwa a kan Arty Z7 Cibiyar Sadarwa (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start).
(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-microsd.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)
Hoto 7.1. sigina na microSD
Dukansu ƙananan-sauri da katunan sauri suna tallafawa, matsakaicin mitar agogo shine 50 MHz (). Katin Class 4 ko mafi kyau shine
shawarar.
Koma zuwa sashe na 3.1 don bayani kan yadda ake kora daga katin SD. Don ƙarin bayani, tuntuɓi Zynq Bayani na fasaha ( ug585-Zynq-7000-TRM [PDF]).
USB Mai watsa shiri
Arty Z7 yana aiwatar da ɗayan samfuran PS USB OTG guda biyu akan na'urar Zynq. Ana amfani da Microchip USB3320 USB 2.0 Transceiver Chip tare da haɗin keɓaɓɓiyar ALPI 8-bit azaman PHY. PHY yana haɓaka cikakkun saurin tallafi na HS-USB Physical Front-End na tallafi har zuwa 480Mbs. PHY an haɗa shi da MIO Bank 1/501, wanda ke aiki da 1.8V. Ana amfani da kewayen usb0 a kan PS, an haɗa ta MIO [28-39]. Keɓaɓɓen kebul na USB OTG an tsara shi don aiki a matsayin mai masaukin ciki. USB OTG da yanayin na'urar USB ba su da tallafi.
Arty Z7 fasaha ce ta "mai masaukin baki" saboda ba ta samar da µF 150 na ƙarfin ƙarfin aiki akan VBUS da ake buƙata don cancanta a matsayin babban mai masaukin baki ba. Zai yiwu a gyara Arty Z7 don ta bi ƙa'idodin babban haɗin kebul na masu buƙata ta hanyar ɗora C41 tare da ƙarfin 150 µF. Wadanda suka kware wajen siyar da ƙananan kayan aiki akan PCBs ne kawai zasu gwada wannan aikin. Yawancin na'urorin kebul na USB zasuyi aiki daidai ba tare da ɗora C41 ba. Ko Arty Z7 an saita shi azaman mai masaukin baki ko babban mai masaukin baki, zai iya samar da 500 mA akan layin 5V VBUS. Lura cewa lodawar C41 na iya sa Arty Z7 ya sake saita lokacin da yake kunna Linux yayin sakawa daga tashar USB, ba tare da la’akari da cewa idan akwai wata na’urar USB da ke haɗe da tashar tashar ba. Wannan yana faruwa ne sakamakon halin gaggawa da C41 ke haifarwa lokacin da aka kunna mai kula da kebul kuma aka kunna wutar VBUS (IC9).
Lura cewa idan ƙirarka tana amfani da tashar USB Mai watsa shiri (sakawa ko manufa ɗaya), to Arty Z7 yakamata ayi amfani dashi ta hanyar batir ko adaftan bango wanda zai iya samar da ƙarin ƙarfi (kamar wanda aka haɗa a cikin kayan haɗin kayan Arty Z7).
Ethernet PHY
Arty Z7 yana amfani da Realtek RTL8211E-VL PHY don aiwatar da tashar Ethernet ta 10/100/1000 don haɗin hanyar sadarwa. PHY yana haɗuwa da MIO Bank 501 (1.8V) da kuma musayar ra'ayi zuwa Zynq-7000 APSoC ta hanyar RGMII don bayanai da MDIO don gudanarwa. Katsewar taimakon (INTB) da sake saita siginar (PHYRSTB) suna haɗuwa da MIO fil MIO10 da MIO9, bi da bi.
Hoto 9.1. Ethernet PHY sigina
Bayan haɓakawa, PHY yana farawa tare da kunna Tattaunawar atomatik, tallata saurin haɗin 10/100/1000 da cikakken-duplex. Idan akwai abokin haɗin Ethernet mai iya haɗin gwiwa, PHY yana kafa mahaɗi ta atomatik tare da shi, koda tare da Zynq ba a daidaita shi ba.
Layi mai nuna alama matsayi biyu suna kan jirgin kusa da mahaɗin RJ-45 wanda ke nuna zirga-zirga (LD9) da ingantacciyar hanyar haɗin mahaɗi (LD8). Tebur 9.1 yana nuna halin tsoho.
| Aiki | Mai tsarawa | Jiha | Bayani |
| MAHADI | LD8 | A tsaye Kunna | Haɗa 10/100/1000 |
| Linkaran haske 0.4s ON, 2s KASHE | Haɗi, Yanayin Ingantaccen Ethernet (EEE) | ||
| ACT | LD9 | Linirƙiri | Watsawa ko Karba |
Tebur 9.1. Yanayin Ethernet.
Zynq ya ƙunshi Gigabit Ethernet Controllers biyu masu zaman kansu. Suna aiwatar da 10/100/1000 rabin / cikakken-duplex Ethernet MAC. Daga cikin waɗannan biyun, ana iya tsara GEM 0 zuwa fil ɗin MIO inda aka haɗa PHY. Tunda ana amfani da bankin MIO daga 1.8V, ƙirar RGMII tana amfani da direbobi 1.8V HSTL Class 1. Don wannan ma'auni na I/O, ana ba da bayanin waje na 0.9V a banki 501 (PS_MIO_VREF). Ana aiwatar da taswirar madaidaitan fil tare da daidaita ma'amala ta hanyar Arty Z7 Zynq Presets file, samuwa a kan Arty Z7 Cibiyar Sadarwa (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start).
Kodayake daidaitaccen tsarin haɓakawa na PHY na iya isa a yawancin aikace-aikace, ana samun motar MDIO don gudanarwa. An sanya RTL8211E-VL adireshin 5-bit 00001 akan bas ɗin MDIO. Tare da rijista mai sauƙi karantawa da rubuta umarni, ana iya karanta bayanan halin ko kuma canza canje-canje. Realtek PHY yana bin taswirar daidaitattun masana'antu don daidaitaccen tsari.
Bayanin RGMII ya kira karɓa (RXC) kuma yana watsa agogo (TXC) don jinkirta dangane da siginar bayanai (RXD [0: 3], RXCTL da TXD [0: 3], TXCTL). Ka'idodin PCB na Xilinx suma suna buƙatar a ƙara wannan jinkirin. RTL8211E-VL na iya shigar da jinkirin 2ns akan TXC da RXC saboda alamun jirgin baya buƙatar tsawan lokaci.
PHY yana aiki daga wannan 50 MHz () oscillator wanda yake rufe Zynq PS. Thearfin ƙarfin parasitic na lodi biyu ya yi ƙaranci don a fitar da shi daga tushe guda.
A kan hanyar sadarwar Ethernet, kowane kumburi yana buƙatar adireshin MAC na musamman. A karshen wannan, an tsara yanki-lokaci-programmable (OTP) na Quad-SPI flash a masana'anta tare da 48-bit na musamman na EUI-48/64 ifier mai ganowa mai jituwa. Kewayon adireshin OTP [0x20; 0x25] ya ƙunshi mai ganowa tare da baiti na farko a cikin tsarin baiti mai ba da sanarwa kasancewa a mafi ƙarancin adireshi. Koma zuwa ga Takaddun bayanan ƙwaƙwalwar ajiya Flash (http://www.cypress.com/file/177966/download) don bayani kan yadda ake samun damar shiga yankuna OTP. Lokacin amfani da Petalinux, ana sarrafa wannan ta atomatik a cikin U-boot boot-loader, kuma ana daidaita tsarin Linux ta atomatik don amfani da wannan adireshin MAC ɗin na musamman.
Don ƙarin bayani game da amfani da Gigabit Ethernet MAC, koma zuwa Zynq Bayanin Fasaha
( ug585-Zynq-7000-TRM [PDF]).
HDMI
Arty Z7 ya ƙunshi tashoshin HDMI guda biyu waɗanda ba a saka su ba: tashar tashar J11 guda ɗaya (fitarwa), da tashar jirgi ɗaya J10 (shigarwa). Dukansu tashar jiragen ruwa suna amfani da nau'in HDMI- A akwatunan ajiya tare da bayanan da siginar agogo da aka ƙare kuma an haɗa su kai tsaye zuwa Zynq PL.
Dukansu HDMI da tsarin DVI suna amfani da daidaitattun siginar TMDS iri ɗaya, kai tsaye ta kayan aikin I / O mai amfani na Zynq PL. Hakanan, tushen HDMI sun dace da baya tare da nutsewar DVI, kuma akasin haka. Don haka, ana iya amfani da adaftan masu saurin wucewa (ana samun su a mafi yawan shagunan lantarki) don fitar da saka idanu na DVI ko karɓar shigarwar DVI. Gidan HDMI kawai ya haɗa da sigina na dijital, don haka kawai yanayin DVI-D mai yiwuwa ne.
Masu haɗin 19-pin HDMI masu haɗawa sun haɗa da tashoshin bayanai daban-daban guda uku, tashar agogo daban daban biyar GND () haɗi, motar waya mai amfani da Waya mai Lantarki guda ɗaya (CEC), bas ɗin Tashar Bayar da Waya mai waya biyu (DDC) wacce da gaske ita ce motar I2C, siginar Toshe Mai Gano (HPD), siginar 5V da ke iya isar da har zuwa 50mA , kuma wanda aka adana (RES) fil. Duk siginonin da ba su da ƙarfi an haɗa su da waya zuwa Zynq PL ban da RES.
| Pin/Signal | J11 (tushe) | J10 (nutse) | ||
| Bayani | Farashin FPGA fil | Bayani | Farashin FPGA fil | |
| D [2] _P, D [2] _N | Fitar bayanai | J18, H18 | Shigar da bayanai | N20, P20 |
| D [1] _P, D [1] _N | Fitar bayanai | K19, J19 | Shigar da bayanai | T20, U20 |
| D [0] _P, D [0] _N | Fitar bayanai | K17, ku 18 | Shigar da bayanai | V20, W20 |
| CLK_P, CLK_N | Fitowar agogo | L16, L17 | Shigar da agogo | N18, P19 |
| CEC | Mai amfani da wutar lantarki mai amfani da lantarki (na zabi) | G15 | Mai amfani da wutar lantarki mai amfani da lantarki (na zabi) | H17 |
| SCL, SDA | Tsarin DDC na zabi (na zabi) | M17, M18 | DDC mai gabatarwa | U14, ku 15 |
| HPD / HPA | Hot-toshe yana gano shigarwar (an juye, zaɓi) | R19 | Hot-toshe ya tabbatar da fitarwa | Saukewa: T19 |
Tebur 10.1. Bayanin HDMI da aiki.
Alamar TMDS
HDMI / DVI babban keɓaɓɓen kewayon bidiyo ne na dijital ta amfani da siginar-da rage girman sigina (TMDS). Don yin cikakken amfani da ɗayan ɗayan tashar ta HDMI, ana buƙatar aiwatar da daidaitaccen mai watsawa ko mai karɓa a cikin Zynq PL. Bayanin aiwatarwa baya ga iyakar wannan littafin. Duba gidan ajiyar bidiyo-laburaren IP Core akan GitHub na Digilent (https://github.com/Digilent) don shirye-shiryen amfani da IP.
Sakonnin karin taimako
Duk lokacin da wanka ya shirya kuma yake son sanar da kasancewar sa, zai haɗu da pin na 5V0 zuwa lambar HPD. A kan Arty Z7, ana yin wannan ta tuki siginar Hot ɗin Toshe mai ƙarfi. Lura wannan yakamata ayi bayan an aiwatar da bawan tashar DDC a cikin Zynq PL kuma a shirye yake don watsa bayanan nuni.
Tashar Bayanan Nuni, ko DDC, tarin ladabi ne waɗanda ke ba da damar sadarwa tsakanin nuni (nutsewa) da adaftan zane (asalin). Bambance-bambancen DDC2B ya dogara ne akan I2C, maigidan bas ɗin shine asalin kuma bawan bas ɗin wanka ne. Lokacin da wata majiya ta gano babban matakin akan fil ɗin HPD, tana tambayar nutsewa akan motar DDC don damar bidiyo. Yana yanke hukunci ko kwatami yana DVI ko HDMI mai iyawa kuma waɗanne shawarwari ake tallafawa. Bayan haka ne za a fara watsa bidiyo. Duba bayanan VESA E-DDC don ƙarin bayani.
Gudanar da Kayan Wutar Lantarki, ko CEC, yarjejeniya ce ta zaɓi wacce ke ba da damar zartar da saƙonnin sarrafawa akan sarkar HDMI tsakanin samfuran daban-daban. Shari'ar amfani da ita ita ce saƙonnin kula da wucewa na TV wanda ya samo asali daga nesa ta duniya zuwa DVR ko mai karɓar tauraron ɗan adam. Yarjejeniya ce ta waya ɗaya a matakin 3.3V wanda aka haɗa zuwa mai amfani I / O pin na Zynq PL. Za'a iya sarrafa wayar a cikin yanayin buɗewa don ba da dama ga na'urori da yawa da ke raba wayar CEC gama gari. Koma zuwa ƙarin CEC na HDMI 1.3 ko bayanan dalla-dalla don ƙarin bayani.
Tushen agogo
Arty Z7 yana ba da 50 MHz () agogo zuwa shigarwar Zynq PS_CLK, wanda ake amfani dashi don samar da agogo ga kowane tsarin tsarin PS. Da 50 MHz () shigarwa yana bawa mai sarrafa damar yin aiki a iyakar mita 650 MHz () da kuma mai sarrafa ƙwaƙwalwar ajiyar DDR3 don yin aiki a iyakar 525 MHz () (1050 Mbps). Abubuwan da aka tsara na Arty Z7 Zynq file samuwa a kan Arty Z7 Cibiyar Sadarwa (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start) ana iya shigo dashi cikin Tsarin Zynq Processing System IP core a cikin aikin Vivado don daidaita Zynq yadda yakamata yayi aiki tare da 50 MHz () agogon shigarwa.
PS yana da kwazo na PLL wanda zai iya samar da agogo hudu masu tunani, kowane daya tare da mitar saiti, wanda za'a iya amfani dashi don agogo dabaru na al'ada wanda aka aiwatar a cikin PL. Bugu da ƙari, Arty Z7 yana ba da 125 na waje MHz () agogon tunani kai tsaye don fil H16 na PL. Agogon tunani na waje yana ba da damar amfani da PL gaba ɗaya daga PS, wanda zai iya zama da amfani ga aikace-aikace masu sauƙi waɗanda basa buƙatar mai sarrafawa.
PL na Zynq ya hada da MMCM da PLL's wanda za'a iya amfani dashi don samar da agogo tare da madaidaitan mitoci da alaƙar lokaci. Duk wani agogon tunani huɗu na PS ko 125 MHz () za a iya amfani da agogon tunani na waje azaman shigar da MMCMs da PLLs. Arty Z7-10 ya haɗa da 2 MMCM da 2 PLL, kuma Arty Z7-20 sun haɗa da 4 MMCM da 4 PLL. Don cikakken kwatancen iyawar ayyukan albarkatun Zynq PL, koma zuwa “7 Series FPGAs Clocking Resources Guide” da ke samuwa daga Xilinx.
Hoto 11.1 tana bayyana makunnin agogo wanda aka yi amfani da shi akan Arty Z7. Lura cewa ana amfani da fitowar agogo mai nuni daga Ethernet PHY azaman 125 MHz () agogon tunani zuwa PL, don yanke farashin hada da mai kishin oscillator don wannan dalili. Ka tuna cewa CLK125 za ta iya aiki lokacin da aka gudanar da Ethernet PHY (IC1) a cikin sake saiti na kayan aiki ta hanyar tuka siginar PHYRSTB ƙasa.
Hoto 11.1. Arty Z7 agogo.
Asali I / O
Shafin Arty Z7 ya haɗa da ledodi masu launuka uku-uku, maɓallan 2, maɓallin turawa 4, da kuma ledojin mutum 4 kamar yadda aka nuna a Hoto 12.1. Maballin maballin turawa da sauya zamiya suna hade da Zynq PL ta hanyar jerin masu adawa don hana lalacewa daga gajerun hanyoyin da ba a sani ba (wani gajeren zango zai iya faruwa idan aka sanya pin na FPGA zuwa maɓallin turawa ko sauya sifa ba da gangan ba a matsayin fitarwa). Maballin Bututun guda huɗu masu sauyawa ne na '' ɗan lokaci '' waɗanda ke samar da ƙaramar fitarwa lokacin da suke hutawa, kuma babbar fitarwa kawai lokacin da aka matsa su. Sauye-sauyen slide suna samar da kayan aiki mai tsayi ko ƙarami dangane da matsayin su.
Hoto 12.1. Arty Z7 GPIO ().
LEDs masu inganci guda huɗu suna da haɗin kai zuwa Zynq PL ta hanyar masu tsayayyar 330-ohm, don haka za su kunna lokacin da ma'ana mai ƙarfi.tage ana amfani da shi a kan nau'in I/O nasu. Ƙarin LEDs waɗanda ba masu amfani da su ba suna nuna ikon kunnawa, matsayin shirye-shiryen PL, da kebul da tashar tashar tashar Ethernet.
Ledan Tri-Launi
Jirgin Arty Z7 ya ƙunshi ledodi masu launuka uku-uku. Kowane mai launi uku LED () yana da siginar shigar da abubuwa guda uku wadanda suke tuka cathodes na kananan ledojin ciki uku: daya ja, daya shudi, da kuma koren kore. Motsa siginar da ta dace da ɗayan waɗannan launuka masu girma zai haskaka na ciki LED (). Ana shigar da siginar shigarwa ta hanyar Zynq PL ta hanyar transistor, wanda ke juya siginar. Saboda haka, don haskaka launin launi uku LED (), Siginan da suka dace suna buƙatar hawa da ƙarfi. Launi uku-uku LED () za su fitar da launi da ke dogara da haɗuwa da LEDs na ciki waɗanda ake haskakawa a halin yanzu. Domin misaliampto, idan siginonin ja da shuɗi suna kora sama da kore kuma an kore ƙasa kaɗan, launuka uku LED () zai fitar da launi mai launi.
Digilent yayi matuƙar ba da shawarar yin amfani da yanayin ƙarfin bugun jini (PWM) yayin tuƙa ledodi masu launi uku. Tuki kowane ɗayan abubuwan shigarwar zuwa madaidaiciyar ma'ana '1' zai haifar da LED () ana haskaka shi a matakin haske mara dadi. Kuna iya kauce wa wannan ta hanyar tabbatar da cewa babu ɗayan siginar launuka masu launuka uku da ake tukawa tare da fiye da ƙimar aiki na 50%. Amfani da PWM yana haɓaka fayel ɗin launuka masu yuwuwa na manyan launuka masu sau uku. Daidaita kowane ɗayan aikin kowane launi tsakanin 50% da 0% yana haifar da haske launuka daban-daban a cikin ƙarfi daban-daban, yana barin kusan kowane launi don nunawa.
Fitowar Sauti na Mono
Jakin audio na kan kan jirgi (J13) ana sarrafa shi ta Sallen-Key Butterworth Low-pass 4th Order Filter wanda ke ba da fitarwar sauti guda ɗaya. Ana nuna da'irar matatar ƙarancin wucewa a cikin Hoto 14.1. An haɗa shigar da tacewa (AUD_PWM) zuwa Zynq PL fil R18. Shigarwar dijital yawanci za ta kasance gyare-gyaren bugun bugun jini (PWM) ko siginar buɗaɗɗen ruwa (PDM) wanda FPGA ke samarwa. Ana buƙatar fitar da siginar ƙasa don ma'ana '0' kuma a bar shi cikin babban tasiri don dabaru' '1'. Mai jujjuyawar kan jirgi zuwa dogo mai tsaftar analog na 3.3V zai tabbatar da ingantaccen vol.tage don ma'ana '1'. Tace mai ƙarancin wucewa akan shigarwar zai yi aiki azaman tacewa na sake ginawa don canza siginar dijital da aka daidaita nisan bugun bugun zuwa analog vol.tage a kan fitarwa jack audio.
(Hoto 13.1. Yanayin fitar da sauti.
Ana amfani da siginar saukar da sauti (AUD_SD) don kashe fitowar sauti. An haɗa shi da Zynq PL fil T17. Don amfani da fitowar sauti, dole ne a kunna wannan sigina zuwa ga hankali.
Mitar mitar SK Butterworth Low-Pass Filter an nuna shi a cikin Hoto 13.2. Ana yin nazarin AC na da'irar ta amfani da NI Multisim 12.0.
Hoto 13.2. Amsar Yawan Yanayin Audio.
Maganin Pulse-Nisa
Siginar bugun bugun-nisa-modulated (PWM) sigina ce ta bugun jini a wasu ƙayyadaddun mitoci, tare da kowane bugun jini mai yuwuwar samun faɗin daban-daban. Ana iya wuce wannan siginar dijital ta hanyar tace mai sauƙi mai sauƙi wanda ke haɗa nau'in igiyar dijital don samar da analog voltage daidai da matsakaicin matsakaicin bugun bugun jini akan wasu tazara (an ƙayyade tazarar ta hanyar yanke yankewar 3dB na matatar ƙarancin wucewa da mitar bugun jini). Domin misaliample, idan bugun jini ya yi girma na matsakaita na 10% na lokacin bugun bugun da ke akwai, to mai haɗawa zai samar da ƙimar analog wanda shine 10% na Vdd vol.tage. Hoto 13.1.1 yana nuna siginar igiyar ruwa da aka wakilta azaman siginar PWM.
Hoto 13.1.1. PWM Waveform.
Dole ne a haɗa siginar PWM don ayyana juzu'in analogtage. Mitar 3dB mai ƙarancin wucewa yakamata ya zama tsari na girma ƙasa da mitar PWM don ana tace ƙarfin sigina a mitar PWM daga siginar. Domin misaliample, idan siginar sauti dole ne ya ƙunshi har zuwa 5 kHz na bayanin mitar, to, mitar PWM yakamata ya zama aƙalla 50 kHz (kuma zai fi dacewa ma mafi girma). Gabaɗaya, dangane da amincin siginar analog, mafi girman mitar PWM, mafi kyau. Hoto 13.1.2 yana nuna wakilcin mai haɗa PWM wanda ke samar da fitarwa voltage ta hanyar haɗa jirgin kasan bugun jini. Kula da siginar fitowar tace a tsaye ampMatsakaicin litude zuwa Vdd daidai yake da zagayowar aikin bugun jini-nisa (ana ayyana zagayowar aikin azaman lokacin bugun jini da aka raba ta lokacin bugun bugun-taga).
Figure 13.1.2. PWM Output Voltage.
Sake saita kafofin
Sake saita Sake kunnawa
Zynq PS na goyan bayan siginar sake saita sigina na ikon-kan waje. Sake-kunnawa mai kunnawa shine sake saiti na ainihi na dukkan guntu. Wannan siginar tana sake saita kowane rijista a cikin na'urar da za a iya sake saiti. Arty Z7 yana fitar da wannan siginar daga siginar PGOOD na mai kula da wutar lantarki na TPS65400 don riƙe tsarin cikin sake saiti har sai duk wadatar wutar ta zama mai inganci.
Canja Button Sauya
Maɓallin tura PROG, mai lakabin PROG, yana jujjuya Zynq PROG_B. Wannan yana sake saitin PL kuma yana sa AIKATA ya daina tabbatarwa. PL ba za ta kasance ba a daidaita shi har sai an sake tsara shi ta hanyar sarrafawa ko ta hanyar JTAG.
Sake Sake Siyarwa na Tsarin tsari
Sake saitin tsarin waje, mai lakabin SRST, yana sake saita na'urar Zynq ba tare da dagula yanayin gyara matsala ba. Domin misaliampHar ila yau, wuraren hutu na baya da mai amfani ya saita sun kasance masu inganci bayan sake saitin tsarin. Saboda matsalolin tsaro, sake saitin tsarin yana goge duk abun ciki na ƙwaƙwalwar ajiya a cikin PS, gami da OCM. Hakanan ana share PL yayin sake saitin tsarin. Sake saitin tsarin baya haifar da madaidaicin madauri don zama sake-sampjagoranci.
Maballin SRST kuma yana haifar da siginar CK_RST don kunnawa don haifar da sake saitawa akan kowane garkuwar da aka haɗe.
Pmod Ports
Tashoshin Pmod sune 2 × 6, kusurwar dama, masu haɗin mata masu mil mil 100 waɗanda suka dace da daidaitattun fil na 2 × 6. Kowace tashar Pmod mai lamba 12 ta samar da 3.3V biyu VCC () sigina (pin 6 da 12), sigina na ƙasa guda biyu (fil 5 da 11), da sigina guda takwas, kamar yadda aka nuna a Hoto 15.1. Da VCC () kuma fil na ƙasa na iya bayarwa har zuwa 1A na yanzu, amma dole ne a kula kada a wuce kowane kasafin kuɗi na ikon masu sarrafa jirgin ko samar da wutar lantarki ta waje (duba iyakokin titin jirgin ƙasa na 3.3V da aka jera a cikin sashin “Kayan Wuta”) .
(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-pmod.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)
Hoto 15.1. Taswirar tashar Pmod
Digilent yana samar da tarin allon kayan haɗin Pmod waɗanda zasu iya haɗawa zuwa haɗin haɗin Pmod don ƙara ayyukan da aka shirya kamar A / D's, D / A's, direbobin motar, firikwensin, da sauran ayyuka. Duba www.digilentinc.com (http://www.digilentinc.com) don ƙarin bayani.
Kowace tashar Pmod da aka samo akan allon Digilent FPGA ta faɗi cikin ɗayan rukunoni huɗu: daidaitacce, MIO haɗi, XADC, ko saurin-sauri. Arty Z7 yana da tashar jiragen ruwa Pmod guda biyu, waɗanda duka nau'ikan su ne masu saurin gaske. Sashe na gaba yana bayanin nau'in sauri mai sauri na tashar Pmod.
Pmods mai sauri
Pmods masu sauri suna da alamun siginar su wanda aka juya kamar yadda impedance ya dace da nau'i-nau'i daban-daban don iyakar saurin sauyawa. Suna da gammaye don ɗora wutar adawar don ƙarin kariya, amma jiragen Arty Z7 tare da waɗannan an ɗora su azaman 0-Ohm shunts. Tare da raguwar jerin masu tsayayya, waɗannan Pmods ba su da kariya daga gajerun da'irori amma suna ba da damar saurin sauyawa da sauri. Siginonin suna haɗuwa da siginan da ke kusa da su a cikin jeri ɗaya: fil 1 da 2, fil 3 da 4, pin 7 da 8, da fil 9 da 10.
Ana biye da hanyoyi 100 ohms (+/- 10%) bambanci.
Idan ana amfani da fil a kan wannan tashar jiragen ruwa azaman siginoni masu ƙarewa ɗaya, masu haɗuwa guda biyu na iya nuna hanyar wucewa. A cikin aikace-aikacen da wannan abin damuwa ne, ɗayan siginar ya kamata a faɗi (kore shi ƙasa daga FPGA) kuma yi amfani da ma'aurata biyu don siginar ƙarar sigina.
Tunda High-Speed Pmods suna da 0-ohm shunts maimakon masu tsayayya kariya, dole ne afareta ya kiyaye don tabbatar da cewa basu haifar da gajeren wando ba.
Mai haɗin Garkuwar Arduino / chipKIT
Ana iya haɗa Arty Z7 zuwa daidaitaccen Arduino da garkuwar chipKIT don ƙara haɓaka aiki. An ba da kulawa ta musamman yayin tsara Arty Z7 don tabbatar da cewa ya dace da yawancin garkuwar Arduino da chipKIT a kasuwa. Mai haɗin garkuwar yana da fuloti 49 da aka haɗa zuwa Zynq PL don manufa-I / O dijital akan Arty Z7-20 da 26 akan Arty Z7-10. Saboda sassauƙan FPGAs, yana yiwuwa a yi amfani da waɗannan fil don kawai game da komai gami da karanta / rubuta dijital, haɗin SPI, haɗin UART, haɗin I2C, da PWM. Shida daga cikin wadannan fil din (wanda ake wa lakabi da AN0-AN5) ana iya amfani da su azaman kayan aikin analog mai ƙare ɗaya tare da kewayon shigarwa na 0V- 3.3V, kuma wasu shida (mai suna AN6-11) ana iya amfani dasu azaman kayan aikin analog na daban.
Lura: Arty Z7 bai dace da garkuwar da ke fitar da sigar dijital 5V ba ko siginar analog. Tuka fil akan mahaɗin garken Arty Z7 da ke sama da 5V na iya haifar da lalacewa ga Zynq.
(https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty-z7-shield.png)
Hoto 16.1. Hoton Garkuwan Fil.
| Sunan Pin | Aikin Garkuwa | Haɗin Arty Z7 |
| IO0–IO13 | Babban manufar I / O fil | Duba Sashe mai taken "Garkuwan I / O" |
| IO26–IO41, A (IO42) | Arty Z7-20 Babban manufar I / O fil | Duba Sashe mai taken "Garkuwan I / O" |
| SCL | I2C agogo | Duba Sashe mai taken "Garkuwan I / O" |
| SDA | Bayanin I2C | Duba Sashe mai taken "Garkuwan I / O" |
| SCLK () | SPI agogo | Duba Sashe mai taken "Garkuwan I / O" |
| MOSI () | Bayanin SPI ya fita | Duba Sashe mai taken "Garkuwan I / O" |
| MISO () | Bayanai na SPI a cikin | Duba Sashe mai taken "Garkuwan I / O" |
| SS | SPI Bawa Zaɓi | Duba Sashe mai taken "Garkuwan I / O" |
| A0–A5 | Shigar da Analog na Singlearshe | Duba Sashe mai taken "Garken Analog I / O" |
| A6–A11 | Bambancin Analog Input | Duba Sashe mai taken "Garken Analog I / O" |
| Sunan Pin | Aikin Garkuwa | Haɗin Arty Z7 |
| V_P, V_N | Addamar da Analog Mai Banbancin Bambanci | Duba Sashe mai taken "Garken Analog I / O" |
| XGND | XADC Analog Ground | An haɗa shi da layin yanar gizo wanda aka yi amfani da shi don fitar da bayanin ƙasar XADC akan Zynq (VREFN) |
| XVREF | XADC Analog Voltage Magana | Haɗa zuwa 1.25 V, 25mA dogo da aka yi amfani da shi don fitar da XADC voltage tunani akan Zynq (VREFP) |
| N/C | Ba a Haɗe ba | Ba a Haɗe ba |
| IOREF | Digital I/O Voltage reference | Haɗa zuwa Arty Z7 3.3V Rail Rail (Dubi sashin "Kayan Wutar Lantarki") |
| RST | Sake saita zuwa Garkuwa | An haɗa shi da maɓallin ja “SRST” da MIO pin 12 na Zynq. Lokacin da JP1 ya gajarta, ana kuma haɗa ta da siginar DTR na gadar FTDI USB-UART. |
| 3V3 | 3.3V Rail Rail | Haɗa zuwa Arty Z7 3.3V Rail Rail (Dubi sashin "Kayan Wutar Lantarki") |
| 5V0 | 5.0V Rail Rail | Haɗa zuwa Arty Z7 5.0V Rail Rail (Dubi sashin "Kayan Wutar Lantarki") |
| GND (), G | Kasa | Haɗa zuwa jirgin saman ƙasa na Arty Z7 |
| VIN | Shigar da Wuta | An haɗa shi a layi daya tare da mai haɗa wutar lantarki na waje (J18). |
Tebur 16.1. Bayanin Garkuwan Fil.
Garkuwan I / O
Za a iya amfani da fil ɗin da aka haɗa kai tsaye zuwa Zynq PL azaman maƙasudi na gaba ɗaya ko abubuwan fitarwa. Waɗannan fil ɗin sun haɗa da I2C, SPI, da maƙasudin I/O gabaɗaya. Akwai 200 Ohm series resistors tsakanin FPGA da dijital I/O fil don taimakawa wajen samar da kariya daga gajerun da'irori na bazata (ban da siginar AN5-AN0, waɗanda ba su da jerin masu tsayayya, da alamun AN6-AN12, waɗanda suke da su. 100 Ohm jerin resistors). Madaidaicin madaidaicin da shawarar aiki voltages don waɗannan fil an tsara su a cikin tebur da ke ƙasa.
IO26-IO41 da A (IO42) ba a samun damar su akan Arty Z7-10. Hakanan, AN0-AN5 ba za a iya amfani dashi azaman I / O na Dijital akan Arty Z7-10 ba. Wannan saboda karancin fil na I / O da ake samu akan Zynq-7010 fiye da na Zynq-7020.
| Cikakken Mafi ƙarancin Voltage | Nasihar Mafi ƙarancin Aiki Voltage | Nasihar Matsakaicin Aiki Voltage | Cikakken Mafi Girma Voltage | |
| Mai ƙarfi | -0.4 V | -0.2 V | 3.4 V | 3.75 V |
| Ba da izini ba | -0.4 V | N/A | N/A | 0.55 V |
Table 16.1.1. Garkuwar Dijital Voltages.Don ƙarin bayani kan halayen lantarki na fil ɗin da aka haɗa da Zynq PL, da fatan za a duba Zynq-7000 takaddun bayanai
(ds187-XC7Z010-XC7Z020-Data-Sheet) da Xilinx.
Garkuwan Analog I / O
Ana amfani da fil ɗin da aka yiwa lakabin A0-A11 da V_P/V_N azaman abubuwan shigar analog zuwa tsarin XADC na Zynq. Zynq yana tsammanin cewa abubuwan da aka shigar sun kasance daga 0-1 V. A kan fil ɗin da aka yiwa lakabin A0-A5 muna amfani da da'irar waje don ƙaddamar da ƙaddamarwar shigarwa.tagda 3.3v. Ana nuna wannan kewayawa a cikin Hoto 16.2.1. Wannan kewayawa yana ba da damar tsarin XADC don auna daidai kowane voltage tsakanin 0V da 3.3V (dangane da Arty Z7's GND ()) wanda ake amfani da shi ga ɗayan waɗannan maɓallan. Idan kanaso kayi amfani da fil din da aka yiwa lakabi da A0-A5 azaman kayan masarufi ko kayan aikin Dijital, suma suna da alaƙa kai tsaye zuwa Zynq PL kafin maɓallin rarraba maɓallin adawa (wanda aka nuna a cikin Hoto na 16.2.1) akan Arty Z7-20. Ba a yin wannan ƙarin haɗin kan Arty Z7-10 ba, wanda shine dalilin da ya sa za a iya amfani da waɗannan alamun azaman abubuwan analog ɗin analog a kan wannan bambancin.
(https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty-z7-shield-an.png)
Hoto 16.2.1. Abubuwan Analog guda Endarshe.
Fil ɗin da aka yiwa lakabin A6-A11 an haɗa kai tsaye zuwa nau'i-nau'i 3 na fitilun analog masu iya aiki akan Zynq PL ta hanyar tacewa ta anti-aliasing. Ana nuna wannan kewayawa a cikin Hoto 16.2.2. Ana iya amfani da waɗannan nau'i-nau'i na fil azaman abubuwan shigar analog na banbanta tare da voltage bambanci tsakanin 0-1V. Hatta lambobi suna haɗe zuwa madaidaitan fil na biyun kuma ƙananan lambobi suna haɗa su zuwa maƙallan maɗaukaki (don haka A6 da A7 suna samar da nau'in shigarwar analog tare da A6 kasancewa tabbatacce kuma A7 mara kyau). Lura cewa ko da yake pads na capacitor suna nan, ba a loda su don waɗannan fil ɗin ba. Tunda madaidaitan fil na FPGA kuma ana iya amfani da su kamar fil na FPGA na dijital na yau da kullun, yana yiwuwa kuma a yi amfani da waɗannan fil don Digital I/O.
An haɗa fil ɗin da aka yiwa lakabin V_P da V_N zuwa VP_0 da VN_0 keɓaɓɓen abubuwan shigar analog na FPGA. Hakanan ana iya amfani da wannan nau'in fil biyu azaman shigarwar analog na bambanta tare da voltage tsakanin 0-1V, amma ba za a iya amfani da su azaman Digital I/O. Capacitor a cikin da'irar da aka nuna a cikin Hoto 16.2.2 don wannan nau'in fil ɗin ana ɗora shi akan Arty Z7.
Hoto 16.2.2. Abubuwan Analog daban-daban.
Babban XADC da ke cikin Zynq shine tashoshi biyu-biyu 12-bit analog-zuwa-dijital mai canzawa mai iya aiki a 1 MSPS. Ko wanne tashoshi na iya tafiyar da kowane abu na analog ɗin da aka haɗa da fil ɗin garkuwa. Ana sarrafa ainihin XADC kuma ana samun dama daga ƙirar mai amfani ta hanyar tashar Reconfiguration Dynamic (DRP). DRP kuma tana ba da dama ga voltage suna saka idanu akan kowane tashar wutar lantarki ta FPGA, da firikwensin zafin jiki wanda ke cikin FPGA. Don ƙarin bayani kan amfani da ainihin XADC, koma zuwa takaddar Xilinx mai taken "7 Series FPGAs da Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". Hakanan yana yiwuwa a sami dama ga maɓallin XADC kai tsaye ta amfani da PS, ta hanyar “PS-XADC” dubawa. An kwatanta wannan haɗin gwiwar gabaɗaya a cikin babi na 30 na Zynq
Bayanin fasaha na fasaha ( ug585-Zynq-7000-TRM [PDF]). rm (dahttps://reference.digilentinc.com/tag/rm?do=showtag&tag=rm), dokar (https://reference.digilentinc.com/tag/doc?do=showtag&tag=doc), art-z7
(https://reference.digilentinc.com/tag/arty-z7?do=showtag&tag=arty-z7)
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Bayanin Kamfanin
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Takardu / Albarkatu
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DIGILENT Board Development Arty Z7 [pdf] Manual mai amfani Ci gaban Hukumar Arty Z7 |
