DIGILENT Atinaʻe Atinaʻe Arty Z7 Tagata Faʻaoga Tusi Lesona

Tusi Lesona Tusitaiala Arty Z7

O le Arty Z7 o se sauni-e-faʻaaoga tulaga atinae fuafuaina i le Zynq-7000 ™ Uma Programmable System-i-Chip (AP SoC) mai Xilinx. O le Zynq-7000 tusiata fale o loʻo tuʻufaʻatasia se lua-autu, 650 MHz () ARM Cortex-A9 gaosiga ma Xilinx 7-series Field Programmable Gate Array (FPGA) manatu. O lenei paga faʻaavanoaina le mafai e faʻataʻamilomilo ai se malosi gaioiga ma se tulaga ese seti o polokalama-faʻamatalaina peripherals ma tagata faʻatonutonu, fetuʻunaʻi e oe mo le sini autu.
O mea faigaluega a le Vivado, Petalinux, ma le SDSoC e maua ai se auala faigofie i le va o le faʻauigaina o lau seti itu taʻitasi ma aumaia ai le galuega e oʻo atu i le Linux OS () poʻo le leai o se polokalame uʻamea o loʻo tamoʻe i luga o le masini. Mo i latou o loʻo suʻesuʻeina se poto masani e masani ai, e mafai foi ona le amanaʻia le ARM ma faʻagaioia le Zynq's FPGA pei ona e faia i isi Xilinx FPGA. Digilent maua ai le tele o mea ma punaoa mo le Arty Z7 o le a ala ai oe i luga ma tamoʻe ma lau mea faigaluega o filifiliga vave.

(https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty-z7_-_obl_-_600.png)

Tusi Lesona Tusitaiala Arty Z7 [Faʻamatalaga.Digilentinc]

Lalotoso Lenei Tusi Faʻasino Tusi

Lenei tusi faʻasino tusi lesona e leʻi avanoa mo download.

Mataupu lalafi

1 Vaega

2 Filifiliga Fa'atau

3 Eseesega mai le PYNQ-Z1

4 Lagolago Polokalame

5 Sapalai Malosiaga

6 Zynq APSoC Tusiata fale

7 Fetuunaiga a Zynq

8 Quad SPI Flash

9 Manatu DDR

10 Alalaupapa UART USB (Serial Port)

16 Mono Audio Galuega Faatino

17 Toe seti Punaoa

18 Taulaga Pmod

19 Arduino / chipKIT Shield Connector

20 Pepa / Punaoa

20.1 Fa'asinomaga

21 Fa'amatalaga Fa'atatau

Vaega

ZYNQ Faʻagaioiga

650MHz lua-autu Cortex-A9 faʻagasologa
DDR3 manatua faʻatonutonu ma 8 DMA auala ma 4 Maualuga Galuega AXI3 pologa uafu

Maualuga-bandwidth peripheral pule: 1G Ethernet, USB 2.0, SDIO
Fa'atonu fa'aoga pito i lalo ole bandwidth: SPI, UART, CAN, I2C

Polokalame mai ia JTAG, Quad-SPI flash, ma le microSD card
Faʻamaonia polokalame e tutusa ma Artix-7 FPGA

Manatu

512MB DDR3 ma le 16-siva pasi @ 1050Mbps

16MB Quad-SPI Flash ma fale gaosi-polokalame 48-bit tulaga ese i le lalolagi EUI-48/64 ™ faʻailoga talafeagai
microSD avanoa

Malosiaga

Faʻaola mai le USB poʻo se isi faʻavae eletise 7V-15V i fafo

USB ma Ethernet

Gigabit Ethernet PHY

USB-JTAG Polokalame matagaluega
Alalaupapa USB-UART

USB OTG PHY (lagolagoina naʻo le talimalo)

Leo ma Vitio

Uafu magoto HDMI (sao)
Uafu punavai HDMI (galuega faatino)

PWM tulia mono leo leo ma 3.5mm jack

Suiga, Tulei-faʻamau, ma moliuila

4 fa'amau fa'amau
2 faasolosolo ki
4 LED
2 RGB Moli

Faʻalautelega fesoʻotaʻiga

Lua taulaga Pmod
16 Aofaʻi FPGA I / O
Fesoʻotaʻiga Arduino / chipKIT Shield
E oʻo atu i le 49 Aofaʻi FPGA I / O (vaʻai le laulau i lalo)
6 Nofofua-faʻamutaina 0-3.3V Analog sao i XADC
4 Eseesega 0-1.0V Faʻamatalaga faʻaulu i XADC

Filifiliga Fa'atau

E mafai ona faʻatau le Arty Z7 ma le Zynq-7010 poʻo le Zynq-7020 ua utaina. O nei ituaiga lua Arty Z7 oloa eseese ua taʻua o le Arty Z7-10 ma le Arty Z7-20, i le faasologa. Pe a faʻamatalaina e faʻamaumauga a le Digilent, o mea masani e masani ai nei tuʻaiga uma, e taua uma lava o le "Arty Z7". A o faʻamatalaina se mea e masani ai i se ituaiga eseese, o le fesuiaʻiga o le a valaʻau valaʻau mai i lona igoa.
Pau lava le 'eseʻesega i le va o le Arty Z7-10 ma le Arty Z7-20 o gafatia o le Zynq vaega ma le aofaʻi o I / O avanoa i luga o le talita fesoʻotaʻiga. E tutusa uma agavaʻa a le Zynq processors, peitaʻi o le -20 e tusa ma le 3 taimi tele atu FPGA i totonu nai lo le -10. O eseesega i le va o ituaiga eseese e lua o loʻo otooto mai i lalo:

Vasega Oloa	Arty Z7-10	Arty Z7-20
Zynq Vaega	XC7Z010-1CLG400C	XC7Z020-1CLG400C
1 MSPS Luga-chips ADC ()	Ioe	Ioe
Vaʻai i luga (LUTs)	17,600	53,200
Flip-Flops	35,200	106,400
Poloka RAM ()	270 KB	630 KB
Uati Faʻatonutonu maa	2	4
Avanoa maua I/O	26	49

I luga o le Arty Z7-10, o le laina i totonu o le digital digit (IO26-IO41) ma le IOA (e faʻaigoa foʻi ia IO42) e le fesoʻotaʻi i le FPGA, ma le A0-A5 e faʻatoa mafai ona faʻaaogaina e fai ma analog input. Ole mea lea e le afaina ai le faʻatinoga ole tele o talita Arduino oloo iai, ona ole toʻatele e le faʻaaogaina lenei laina i totonu ole numera faʻailo.
E mafai ona faʻatau naʻo oe le laupapa pe faʻatasi foʻi ma se siaki e tatala ai le Xilinx SDSoC mea faigaluega. E tatala e le faʻamaoniga a le SDSoC le laisene 1-tausaga ma naʻo le Arty Z7 e mafai ona faʻaaogaina ai. A maeʻa le laisene, soʻo se faʻamatalaga a le SDSoC lea na faʻamatuʻu mai i lenei vaitaimi e 1 tausaga, e mafai ona faʻaauau pea ona faʻaaoga e faʻavavau. Mo nisi faʻamatalaga i luga o le faʻatau, vaʻai i le Arty Z7 Oloa Itulau (http://store.digilentinc.com/artyz7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/).
I le taimi o le faʻatau, e mafai foi ona faʻaopopo ona microSD card, 12V 3A mana sapalai, ma micro USB cable pe a manaʻomia.
Manatua talu ai o le laʻititi FPGA i le Zynq-7010, e le fetaui lelei e faʻaoga i le SDSoC mo faʻaaogaina vaʻai vaʻai. Matou te fautuaina tagata faʻatau le Arty Z7-20 pe a fai latou te fiafia i nei ituaiga o apalai.

Eseesega mai le PYNQ-Z1

Arty Z7-20 faʻasoa tutusa le tutusa SoC ma le PYNQ-Z1. Feololo-atamai, Arty Z7-20 o loʻo misia le masini faaleo leo, ae faʻaopopo le Power-on Reset button. Polokalama tusia mo PYNQ-Z1 tatau ona tamoʻe le suia seʻi vagana ai le faʻaaogaina o masini faaleotele leo, o lana FPGA pine e tuʻu le fesoʻotaʻi.

Lagolago Polokalame

O le Arty Z7 e fetaui lelei ma le Xilinx's maualuga-faʻaalia Vivado Design Suite. O lenei mea faigaluega e faʻafefiloia ai le FPGA logic design ma tuʻufaʻatasia ai le ARM software development i totonu o se faigofie-e-faʻaaoga, intuitive flow flow. E mafai ona faʻaaogaina mo le fuafuainaina o soʻo se mea faigata, mai se faʻagaioiga atoa o polokalame e faʻatautaia ai le tele o mea e tuʻufaʻatasia i ai, e oʻo atu i se polokalame uʻamea faigofie e faʻatonutonuina ai LED.
E mafai foi ona togafitia le Zynq AP SoC o se FPGA tutoʻatasi mo i latou e le fiafia e faʻaaoga le masini i le latou mamanu. E pei o le Vivado faʻamalolo 2015.4, o le Logic Analyzer ma Maualuga-tulaga Synthesis foliga o Vivado e saoloto e faʻaaoga mo uma WebPACK sini, lea e aofia ai le Arty Z7. O le Logic Analyzer e fesoasoani i le faʻaleaʻoaʻoga o manatu, ma le mea faigaluega HLS faʻatagaina oe e tuʻufaʻatasia C code saʻo i le HDL.
Zynq fausaga opea e fetaui lelei e faʻapipiʻi ai Linux sini, ma Arty Z7 e leai se tuusaunoa. Ina ia fesoasoani ia te oe e amata, Digilent saunia se Petalinux poloketi o le a faʻatulai ai oe i luga ma tamoʻe ma se Linux faiga vave. Mo nisi faʻamatalaga, vaʻai i le Arty Z7 Punaoa Autu (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start).
O le Arty Z7 e mafai foi ona faʻaaogaina i le Xilinx's SDSoC siʻosiʻomaga, e faʻatagaina ai oe ona mamanuina FPGA televave polokalama ma vitio faʻataʻavaleina ma faigofie i se atoa C / C ++ siʻosiʻomaga. Mo nisi faʻamatalaga luga SDSoC, vaʻai i le Nofoaga Xilinx SDSoC
(https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html). Digilent o le a faʻasaʻolotoina se Vitio tulaga gafatia ma Linux lagolago i le taimi mo le SDSoC 2017.1 faʻamalolo. Manatua talu ai o le laititi FPGA i le Arty Z7-10, na o le matua taua tele vitio faʻagasologa o loʻo aofia ai ma lena tulaga. Ua fautuaina e le Digilent le Arty Z7-20 mo i latou e fiafia i le gaosiaina o ata.
O i latou e masani ma matutua Xilinx ISE / EDK mea faigaluega mai luma Vivado na faʻasaʻolotoina mafai foi ona filifili e faʻaaoga le Arty Z7 i lena mea faigaluega. Digilent e le tele ni mea e lagolago ai lenei, ae e mafai lava ona e fesili mo se fesoasoani i le Digilent Fono (https://forum.digilentinc.com).

Sapalai Malosiaga

E mafai ona faʻamalosi le Arty Z7 mai le Digilent USB-JTAG-UART port (J14) pe mai nisi ituaiga o mana eletise pei o se maa poʻo se sapalai o le paoa i fafo atu. Jumper JP5 (latalata i le ki eletise) fuafua pe o le a le punavai eletise e faʻaaogaina.
O le USB 2.0 port e mafai ona kilivaina le maualuga o le 0.5A o le taimi nei e tusa ai ma faʻamatalaga. O lenei e tatau ona maua ai lava le paoa mo maualalo laʻasaga faigata. O isi talosaga e manaʻomia tele, e aofia ai soʻo se mea e unaʻi ai le tele o laupapa lautele poʻo isi masini USB, e ono manaʻomia ai le sili atu o le paoa nai lo le taulaga e mafai ona tuʻuina atu i le USB port. I lenei tulaga, o le faʻaaogaina eletise o le a faʻateleina seʻia faʻatapulaʻaina e le USB talimalo. Lenei tapulaʻa eseese tele i le va o gaosi o talimalo komepiuta ma faʻalagolago i le tele o mea taua. A o i le taimi nei tapulaʻa, tasi le voltagu laina uʻu ifo i lalo ifo o latou tau taua, o le Zynq ua toe setiina e le Malosiaga-i luga o le Reset faʻailoga ma le paoa taumafaina toe foʻi i lona tau le aoga. Faʻapea foi, nisi talosaga ono manaʻomia e tamoʻe aunoa ma le fesoʻotaʻi i le PC a USB port. I nei taimi, e mafai ona faʻaaogaina se paoa i fafo atu poʻo se pati.
O se sapalai o le eletise i fafo atu (eg wall wart) e mafai ona faʻaaogaina e ala i le tuʻuina i totonu o le power jack (J18) ma faʻatutu le jumper JP5 i le "REG". O le sapalai e tatau ona faʻaaogaina le totoa, ogatotonu-lelei 2.1mm i totonu totonu lapoa, ma tuʻuina 7VDC i le 15VDC. O sapalai talafeagai e mafai ona faʻatau mai le Digilent web'upega tafaʻilagi e ala i tusi faʻatau e pei o le DigiKey. Paoa sapalai voltages luga 15VDC ono mafua ai faʻaleagaina tumau. O se sapalai talafeagai eletise i fafo atu o loʻo aofia ai ma le pusa fesoasoani a Arty Z7.
Tutusa i le faʻaaogaina o se sapalai o le paoa mai fafo, e mafai ona faʻaaogaina le maa e faʻamalosi ai le Arty Z7 e ala i le faʻapipiʻi atu i le talita fesoʻotaʻiga ma seti le jumper JP5 i le "REG". O le itu lelei o le maa e tatau ona faʻafesoʻotaʻi i le pine ua faʻaigoaina "VIN" i luga o le J7, ma le itu leaga e tatau ona faʻafesoʻotaʻi i le pine ua faʻaigoaina GND () i le J7.
O luga ole Texas Instruments TPS65400 PMU na fausia le 3.3V, 1.8V, 1.5V, ma le 1.0V sapalai mai le mea autu mana. Lisi 1.1 faʻaopoopo faʻamatalaga (masani masani faalagolago faʻalagolago lava i Zynq faʻatulagaina ma le taua faʻatulagaina e masani ai o feololo tele / saoasaoa tisaini).
E leai se ki a le Arty Z7, o lona uiga a faʻafesoʻotaʻi le eletise ma filifili ma le JP5 o le a faʻamalosia lava. Ina ia toe seti le Zynq e aunoa ma le motusia ma toe fesoʻotaʻi le paoa sapalai, e mafai ona faʻaaoga le faʻamau SRST mumu. O le eletise faʻailoga TAITAI () (LD13) o loʻo ola peʻa oʻo atu sapalai o auala i le latou volional nomtage.

Sapalai	Li'o	Current (max/typical)
3.3V	FPGA I / O, USB port, Clocks, Ethernet, SD slot, Flash, HDMI	1.6A / 0.1A i le 1.5A
1.0V	FPGA, Ethernet Koru	2.6A / 0.2A i le 2.1A
1.5V	DDR3	1.8A / 0.1A i le 1.2A
1.8V	FPGA Ausilali, Ethernet I / O, USB Pule	1.8A / 0.1A i le 0.6A

Laulau 1.1. Sapalai eletise Arty Z7.

Zynq APSoC Tusiata fale

Ua vaevaeina le Zynq APSoC i ni vaega eseʻese se lua: Le Faʻagasologa o Faʻagaioiga (PS) ma le Polokalame Faʻamaonia (PL). Ata 2.1 faʻaalia se sili atuview o le Zynq APSoC tusiata fale, ma le PS lanu malamalama lanumeamata ma le PL i samasama. Manatua o le PCIe Gen2 pule ma Multi-gigabit transceivers e le avanoa i luga o le Zynq-7020 poʻo le Zynq-7010 masini.

(https://reference.digilentinc.com/_detail/zybo/zyng1.png?id=reference%3Aprogrammable-logic%3Aarty-z7%3Areference-manual)
Ata 2.1 Zynq APSoC tusiata fale
O le PL e toeititi lava tutusa ma le Xilinx 7-series Artix FPGA, seʻi vagana ai o loʻo iai ni uafu tuʻufaʻatasia ma pasi e fusia faʻatasi i le PS. E leʻo iai foʻi i le PL mea tutusa e pei o le masani 7-series FPGA, ma e tatau ona faʻatonu saʻo i le gaosi poʻo le JTAG uafu.
O le PS e aofia ai le tele o vaega, e aofia ai le Application Processing Unit (APU, lea e aofia ai le 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, ma le tele o peripheral controlers ma a latou sao ma galuega faatino faʻateleina i le 54 tuʻuina atu pine (taʻua o Multiplexed I / O, poʻo MIO pine). Peripheral pulea e leai ni a latou sao ma galuega faatino fesoʻotaʻi i MIO pine mafai nai lo auala latou latou I / O e ala i le PL, ala i le Extended-MIO (EMIO) interface. O le peripheral pulea e fesoʻotaʻi i le masini faʻapipiʻi e pei o pologa e ala ile AMBA soʻotaga ma o loʻo mafai ona faitauina / tusitusi faʻatonutonu resitara e mafai ona faʻamatalaina i le gaioiga. O le polokalame e mafai ona malamalama i ai e fesoʻotaʻi foʻi i le fesoʻotaʻiga o se pologa, ma mamanu mafai ona faʻaaogaina tele autu i le FPGA ie o loʻo i ai foʻi ma le mafai ona faʻatonutonuina resitala resitala. E le gata i lea, o faʻataʻitaʻiga o loʻo faʻatinoina i le PL e mafai ona faʻatupuina le faʻalavelave i mea gaosi (fesoʻotaʻiga e le o faʻaalia i le Ata 3) ma faatino DMA ulufale i le DDR3 manatua.

E tele itu o le Zynq APSoC tusiata fale e i tala atu o le lautele o lenei pepa. Mo se faʻamatalaga maeʻaeʻa ma maeʻa, tagaʻi i le Zynq Tekinolosi Tusitaiala tusi lesona ug585-Zynq-7000TRM [PDF]

O le siata 2.1 o loʻo faʻaalia mai ai vaega mai fafo e fesoʻotaʻi i pine MIO o le Arty Z7. Le Zynq Presets File maua i luga o le Arty Z7 Punaoa Autu (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start) mafai ona faʻaulufale mai i EDK ma Vivado Designs e faʻalelei lelei ai le PS e galue ai ma nei peripherals.

MIO 500 3.3 V

Peripherals

Pin	ENET 0	SPI Flash	USB 0	Talita	UART 0
0 (N / C)
1		CS ()
2		DQ0
3		DQ1
4		DQ2
5		DQ3
6		SCLK ()
7 (N / C)
8		SLCK FB
9	Ethernet toe setiina
10	Ethernet faʻalavelave
11			USB I Taimi Nei
12				Talita toe setiina
13 (N / C)
14					UART sao
15					UART Galue

MIO 501 1.8V	Peripherals
Pin	ENET 0	USB 0	SDIO 0
16	TXCK
17	TXD0
18	TXD1
19	TXD2
20	TXD3
21	TXCTL
22	RXCK
23	RXD0
24	RXD1
25	RXD2

26	RXD3
27	RXCTL
28		FAʻAMATALAGA4
29		DIR
30		STP
31		NXT
32		FAʻAMATALAGA0
33		FAʻAMATALAGA1
34		FAʻAMATALAGA2
35		FAʻAMATALAGA3
36		CLK
37		FAʻAMATALAGA5
38		FAʻAMATALAGA6
39		FAʻAMATALAGA7
40			CCLK
41			CMD
42			D0
43			D1
44			D2
45			D3
46		Toe Faʻaleleia
47			CD
48 (N / C)
49 (N / C)
50 (N / C)
51 (N / C)
52	MDC
53	MDIO

Fetuunaiga a Zynq

E le pei o Xilinx FPGA masini, APSoC masini e pei o le Zynq-7020 o loʻo fuafuaina faataamilo i le masini e gaosi ai, lea e avea o se aliʻi i le ie mafai ona faʻatulagaina masini ma isi uma on-chips peripherals i le faiga faʻagasologa. O lenei mafuaʻaga o le Zynq boot process e sili atu tutusa ma le microcontroller nai lo le FPGA. Lenei faiga e aofia ai le gaosiga utaina ma le faʻataunuʻuina o le Zynq Boot Image, lea e aofia ai le Muamua S.tage Bootloader (FSBL), o se mea taua mo le faʻatulagaina o le polokalame e mafai ona fai (filifiliga), ma le faʻaoga a le tagata. O le seevae gaioiga e vaevaeina i le tolu stage:
Stage 0
A maeʻa ona faʻaola le Arty Z7 poʻo ua toe seti le Zynq (i le polokalama poʻo le oomiina o le SRST), o se tasi o faʻagaioiga (CPU0) e amata ona faʻatinoina se vaega i totonu o le faitau-naʻo le code ua faʻaigoaina o le BootROM. Afai ma naʻo le Zynq na faʻamalosia, o le BootROM o le a muamua setiina le setete o le mode pin i totonu o le mode register (o le mode pin o faʻapipiʻi ia JP4 i le Arty Z7). Afai o le BootROM o loʻo faʻatinoina ona o se toe setiina gaioiga, o lona uiga o pine auala e le faʻamaʻaina, ma le tulaga muamua o le auala resitara o loʻo faʻaaogaina. O lona uiga o le Arty Z7 manaʻomia se uila taʻamilosaga e lesitala ai soʻo se suiga i le polokalame mode jumper (JP4). Le isi mea, o le BootROM kopiina se FSBL mai le fomu o le leai-le mautonu manatua faʻamaotiina e le auala lesitala i le 256 KB o totonu RAM () i totonu o le APU (taʻua On-Chip Memory, poʻo OCM). O le FSBL tatau ona afifi i totonu o le Zynq Boot Image ina ia mafai ai e le BootROM ona kopi lelei ia. O le mea mulimuli a BootROM o loʻo tuʻuina atu le faʻataunuʻuina i le FSBL i le OCM.
Stage 1
I le taimi o lenei stagu, o le FSBL muamua faʻamaeʻaina configuring le PS vaega, pei o le DDR manatua pule. Ma, afai o loʻo i ai se vaʻa i le Zynq Boot Image, e faitau ma faʻaaoga e configure le PL. I le iuga, o le tagata faʻaaoga talosaga o loʻo avea ma manatuaina mai le Zynq Boot Image, ma o le faʻasalaga e tuʻuina atu ia te ia.

Stage 2
O le mulimuli stagu o le faʻatinoina o le tagata faʻaaoga talosaga na utaina e le FSBL. Lenei mafai ona avea ma soʻo se ituaiga o polokalama, mai se faigofie "Talofa Lalolagi" mamanu i le Lua Stagu Boot loader e faʻaaoga e puʻe ai se faʻagaioiga pei o Linux. Mo se faʻamatalaga auiliili o le faiga o seevae, faʻasino i le Mataupu 6 o le Zynq Tomai Faapitoa Tusitaiala Tusitusiga (Lagolago [PDF]).

O le Zynq Boot Image na faia pese Vivado ma Xilinx Polokalama Atinaʻe Pusa (Xilinx SDK). Mo faʻamatalaga i le fatuina o lenei ata faʻamolemole tagaʻi i le avanoa Xilinx pepa faʻamaumauga mo nei mea faigaluega.
E lagolagoina e le Arty Z7 ni ituaiga eseese se tolu: microSD, Quad SPI Flash, ma le JTAG. O le boot mode ua filifilia e faʻaaoga ai le Mode jumper (JP4), lea e aʻafia ai le setete o Zynq configurges pin pe a maeʻa le power-on. O le Ata 3.1 o loʻo faʻamatala mai ai le faʻafesoʻotaʻiga o le Zynq config i luga o le Arty Z7.

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-config.png?d=reference%3Aprogrammable-ogic%3Aartyz7%3Areference-manual)
Ata 3.1. Arty Z7 faʻatulagaina pine.
O ituaiga seevae e tolu o loʻo faʻamatalaina i vaega nei.

MicroSD Boot Mode
O le Arty Z7 o loʻo lagolagoina le faʻatupuina o le card mai le microSD card ua faʻaofi i totonu o le J9. O le gaioiga o loʻo mulimuli mai o le a faʻatagaina ai oe ona fagota le Zynq mai le microSD ma le ata masani a le Zynq Boot Image na faia ma mea faigaluega a le Xilinx.

Faʻatulaga le microSD card ma le FAT32 file faiga.

Kopi le Zynq Boot Image faia ma Xilinx SDK i le microSD card.
Toe faaigoa le Zynq Boot Image i luga o le microSD card i le BOOT.bin.
Aveʻese le microSD card mai lau komipiuta ma tuʻu i totonu i le fesoʻotaʻiga J9 i le Arty Z7.

Faʻapipiʻi se punaoa mana i le Arty Z7 ma filifili e faʻaaoga ai le JP5.
Faʻamau se solofanua se tasi i luga o le JP4, faʻapuʻupuʻu ia pito i luga pine (faʻaigoaina "SD").
Ki le laupapa. O le laupapa o le a seevae nei le ata i luga o le microSD card.

Quad SPI Boot Mode

O le Arty Z7 o loʻo i luga o le laupapa 16MB Quad-SPI Flash e mafai e le Zynq ona oso mai. O faʻamatalaga avanoa mai Xilinx e faʻamatalaina ai auala e faʻaaoga ai le Xilinx SDK e faʻapolokalameina ai le Zynq Boot Image i totonu o le Flash masini e faʻapipiʻi i le Zynq. O le taimi lava na utaina ai le Quad SPI Flash ma le Zynq Boot Image, o auala nei e mafai ona mulimulitaʻia e amata mai i luga:

Faʻapipiʻi se punaoa mana i le Arty Z7 ma filifili e faʻaaoga ai le JP5.

Faʻamau se solofanua se tasi i luga o le JP4, faʻapuʻupuʻu ia ogatotonu e lua pine (faʻaigoaina "QSPI").
Ki le laupapa. O le laupapa o le a seevae nei le ata na teuina i le Quad SPI flash.

JTAG Faiga Fa'avae

A tuʻu i le JTAG boot mode, o le a faʻatali le masini faʻagaioiga seʻi vagana ua utaina le polokalame e le komipiuta talimalo faʻaaoga le Xilinx mea faigaluega. A maeʻa ona utaina le polokalame, e mafai ona faʻataga ona faʻatinoina le polokalame, pe laa i lea laina ma lea laina e faʻaaoga ai le Xilinx SDK.
E mafai foʻi ona faʻatulaga saʻo le PL i luga ole JTAG, tutoʻatasi mai le masini gaioiga. Lenei mafai ona faia i le faʻaaogaina o le Vivado Hardware Server.
O le Arty Z7 ua faʻatulagaina e faʻamau i Cascaded JTAG faiga, e faʻatagaina ai le PS ona faʻaaogaina e ala ile tutusa JTAG uafu pei ole PL. E mafai foʻi ona faʻatau le Arty Z7 i le Independent JTAG auala i le utaina o se jumper i le JP2 ma faʻapuʻupuʻuina. Lenei o le a mafua ai le PS e le mafai ona maua mai luga o le laupapa JTAG circuitry, ma naʻo le PL o le a vaʻaia i le scan scan. Ia faʻaaoga le PS i luga o le JTAG a o tutoatasi JTAG auala, tagata e tatau ona uia auala mo le PJTAG peripheral over EMIO, ma faʻaaoga se masini i fafo e fesoʻotaʻi ma ia.

Quad SPI Flash

O le Arty Z7 o loʻo faʻaalia ai le Quad SPI serial NOR flash. O le Spansion S25FL128S o loʻo faʻaaogaina luga o lenei laupapa. O le Multi-I / O SPI Flash manatua e faʻaaoga e maua ai le le-fesuiaʻi tulafono ma faʻamaumauga teuina. E mafai ona faʻaaogaina e faʻamautu ai le subsystem PS faʻapea foi ma le faʻatulagaina o le PL subsystem. O uiga talafeagai o masini e:

16 MB ()

x1, x2, ma le x4 lagolago
O le pasi e oʻo atu i le 104 MHz (), e lagolagoina le Zynq faʻatulagaina tau @ 100 MHz (). I le Quad SPI mode, e faʻaliliuina lenei i le 400Mbs
Afi mai le 3.3V

O le SPI Flash fesoʻotaʻi i le Zynq-7000 APSoC ma lagolagoina le Quad SPI interface. Ole mea lea e manaʻomia ai le fesoʻotaʻiga i pine maoti i le MIO Bank 0/500, faʻapitoa le MIO [1: 6,8] e pei ona otooto atu i le Zynq datasheet. Quad-SPI feedback mode o loʻo faʻaaogaina, o lea ua tuʻu ai le qspi_sclk_fb_out / MIO [8] e feʻaveaʻi fua ma ua naʻo le 20K toso-i luga resistor i le 3.3V. Lenei e faʻatagaina ai le Quad SPI uati taimi tele nai lo FQSPICLK2 (Vaʻai le tusi lesona Zynq Technical Reference

( ug585-Zynq-7000-TRM [PDF]) mo nisi mea e uiga i lenei).

Manatu DDR

O le Arty Z7 aofia ai IS43TR16256A-125KBL DDR3 mea e manatuaina ai fausiaina se tulaga e tasi, 16-bit lautele lautele, ma le aofaʻi o 512MiB o gafatia. O le DDR3 e fesoʻotaʻi i le faigata manatua pule i le Processor Subsystem (PS), e pei ona otooto atu i le Zynq pepa.
O le PS o loʻo tuʻufaʻatasia le AXI port port interface, o le DDR pule, o le PHY fesoʻotaʻi, ma le faʻapitoa I / O faletupe. O le DDR3 memory interface e televave i luga i le 533 MHz () / 1066 Mbps e lagolagoina¹.
O Arty Z7 na faʻataʻamilomiloina ma le 40 ohm (+/- 10%) o faʻalavelave faʻafuaseʻi mo faʻailo e tasi le iʻuga, ma le uati faʻataʻavalevale ma strobes seti i le 80 ohm (+/- 10%). O se faʻaaliga ua faʻaigoaina DCI (Digitally Controlled Impedance) e faʻaaoga e faʻafetaui le malosi o le taʻavale ma le faʻamutaina impedance o le PS pine i le trace impedance. I le itu manatua, o chips taʻitasi calibrates lona on-oti faʻamutaina ma aveina le malosi e faʻaaoga ai le 240-ohm resistor i luga o le ZQ pin.

Ona o mafuaʻaga faʻatulagaina, na suia ai le lua faʻamatalaga byte kulupu (DQ [0-7], DQ [8-15]). I le tutusa aafiaga, o faʻamatalaga i totonu byte kulupu na fesuiaʻi faʻapea foi. O nei suiga e manino i le tagata faʻaoga. I le taimi atoa o le gasologa o le ata, na mulimulitaʻia le Xilinx PCB taiala.

Uma le manatua chips ma le PS DDR faletupe afi mai le 1.5V sapalai. O le ogatotonu-faʻasino tusi o le 0.75V na faia ma se faigofie resistor vaevaeina ma o loʻo avanoa i le Zynq o se faʻasino i fafo.
Mo le faʻagaioiga tatau, e taua tele le faʻatonutonu saʻo o le PS memory controller. O tulaga e amata mai i le mea e manatua ai le tofo i le laupapa faʻasolosolo tuai. Mo lou faigofie, o le Zynq presets file mo le Arty Z7 o loʻo avatua luga o le nofoaga autu o punaoa
(https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start) ma otometi faʻatulagaina le Zynq Processing System IP autu ma le saʻo tapulaʻa.
Mo sili atu DDR3 gaioiga, DRAM toleniga mafai ai mo tusitusiga faʻavasega, faitau faitotoʻa, ma faitau faʻamaumauga mata filifiliga i le PS Configuration Tool i Xilinx mea faigaluega. O toleniga e faia faʻamalosi e le pule e faʻatonutonu ai mo le tuai ai o le laupapa, fesuiaiga o gaioiga ma le faʻasolosolo vevela. Tulaga maualuga amata amata mo le toleniga gaioiga o le laupapa tolopo (faasalalauina tuai) mo nisi manatua manatuaina.
O le tolopoina o le komiti e faʻamaoti mai mo vaega taʻitasi uma. Nei tapulaʻa e laupapa-faʻapitoa ma na fuafuaina mai le PCB faʻasologa umi lipoti. Ole taua ole DQS ile CLK Delay ma le Board Delay o loʻo fuafuaina faʻapitoa i le Arty Z7 memory interface PCB design.
Mo nisi faʻamatalaga e uiga i le faʻagaioia o mea e faʻatonutonu ai le mafaufau, tagaʻi i le Xilinx Zynq Tomai Faapitoa Tusitaiala Tusitusiga ( ug585-Zynq-7000-TRM [PDF]).
¹O le aofaʻi o uati masani o le 525 MHz () ile Arty Z7 e mafua mai ile tapulaʻa ole PLL.

Alalaupapa UART USB (Serial Port)

O le Arty Z7 e aofia ai le FTDI FT2232HQ USB-UART alalaupapa (faʻapipiʻi i le fesoʻotaʻiga J14) e faʻatagaina ai oe e faʻaaoga PC apalai i
fesoʻotaʻi ma le laupapa faʻaaogaina tulafono masani COM port (poʻo le TTY interface i Linux). Avetaavale e otometi lava ona faapipiiina i Windows ma fou fou o Linux. O fesuiaiga o faamaumauga o uafu e fesuiaʻi ma le Zynq e faʻaaoga ai le uaea serial e lua-uaea (TXD / RXD). A maeʻa ona faʻapipiʻi avetaavale, e mafai ona faʻaaoga au / O faʻatonuga mai le PC faʻatonu atu i le COM port e fausia ai faʻamatalaga o fefaʻatauaiga i luga o pine a Zynq. O le uafu e nonoa i PS (MIO) pine ma e mafai ona faʻaaogaina faʻatasi ma le UART pule.

O preset le Zynq file (maua i le Arty Z7 Punaoa Autu (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start))
vaʻaia le faʻafanua o saʻo MIO pine i le UART 0 pule ma faʻaogaina le mulimuli mai aiaiga tapulaʻa: 115200 baud fua faatatau, 1 taofi sina, leai se tutusa, 8-si umi uiga.

Lua tulaga i luga o le laupapa tulaga LED o loʻo maua ai ni faʻaaliga vaʻaia i feoaʻiga o loʻo tafe atu i totonu o le taulaga: o le lafoina LED () (LD11) ma le mauaina LED () (LD10). O igoa faʻailo e taʻu mai ai le faʻasino mai le itu-o-view o le DTE (Data Terminal Equipment), i lenei tulaga le PC.

O le FT2232HQ o loʻo faʻaaogaina foi e avea ma pule mo le Digilent USB-JTAG matagaluega, ae o le USB-UART ma le USB-JTAG gaioiga amio tutoatasi tutoatasi o le tasi i le isi. O tagata fai polokalame e fiafia e faʻaaoga le UART aoga o le FT2232 i totonu o a latou mamanu e le tau popole fua i le JTAG circuitry faʻalavelave i le UART faʻaliliuina faʻamatalaga, ma vice-versa. O le tuʻufaʻatasia o nei vaega e lua i totonu o le tasi masini e faʻatagaina ai le Arty Z7 ona faʻapolokalameina, fesoʻotaʻi ma ala atu i le UART, ma le afi mai se komepiuta faʻapipiʻi ma se tasi uaea Micro USB.
O le faʻailoga DTR mai le UART pule i le FT2232HQ e fesoʻotaʻi atu i le MIO12 o le Zynq masini e ala i le JP1. A faʻapea e ave le Arduino IDE e galue ma le Arty Z7, e mafai ona faʻapuʻupuʻu lenei jumper ma MIO12 e mafai ona faʻaaoga e tuʻu ai le Arty Z7 i se "sauni e maua se seti fou" setete. Lenei e faʻataʻitaʻia le amio a masani Arduino IDE seevae-uta.

MicroSD Slot

O le Arty Z7 o loʻo faʻaavanoaina ai le MicroSD slot (J9) mo le le fesuisuiaʻi o manatuaina i fafo e faʻapea foi ma le faʻatauaina o le Zynq. O le slot uaea i le Bank 1/501 MIO [40-47], e aofia ai Card Detect. I le itu a le PS, o le SDIO 0 peripheral o loʻo faʻatafa atu i nei pine ma faʻatonutonu fesoʻotaʻiga ma le SD card. O le pine e mafai ona vaaia i le Laulau 7.1. O le peripheral pule e lagolagoina le 1-bit ma le 4- bit SD transfer mode ae le lagolagoina le SPI mode. Faavae i le Zynq Tomai Faapitoa Tusitaiala Tusitusiga ( Lagolago [PDF]), O le SDIO host mode e naʻo le pau lea o le auala e lagolagoina.

Igoa Faailoga	Fa'amatalaga	Zynq Pin	SD Slot Pin
SD_D0	Faʻamatalaga [0]	MIO42	7
SD_D1	Faʻamatalaga [1]	MIO43	8
SD_D2	Faʻamatalaga [2]	MIO44	1
SD_D3	Faʻamatalaga [3]	MIO45	2

SD_CCLK	Uati	MIO40	5
SD_CMD	Poloaiga	MIO41	3
SD_CD	Faʻailoa Card	MIO47	9

Siata 7.1. piniki microSD
O le SD slot e afi mai le 3.3V ae e fesoʻotaʻi atu i le MIO Bank 1/501 (1.8V). O le mea lea, o le TI TXS02612 level shifter na te faia lenei faʻaliliuga. O le TXS02612 o le mea moni o le 2-port SDIO port expander, ae naʻo lona tulaga shifter function e faʻaaogaina. O le fesoʻotaʻiga ata e mafai ona vaʻaia i le Ata 7.1. Faʻafanuaina saʻo pine ma configuring le Ofisa e faʻatautaia e le Arty 7 Zynq presets file, avanoa i luga o le Arty Z7 Punaoa Autu (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start).

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-microsd.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)
Ata 7.1. faailo o le microSD slot
Uma maualalo-saosaoa ma maualuga-saosaoa pepa e lagolagoina, o le maualuga uati taimi masani o le 50 MHz (). O le Vasega 4 vasega pe sili atu
fautuaina.
Vaʻai ile vaega 3.1 mo faʻamatalaga pe faʻafefea ona togi mai se SD card. Mo nisi faʻamatalaga, faʻafesoʻotaʻi le Zynq Tomai Faapitoa Tusitaiala Tusitusiga ( ug585-Zynq-7000-TRM [PDF]).

USB Host

O le Arty Z7 faʻaogaina se tasi o lua avanoa PS USB OTG fesoʻotaʻiga luga o le Zynq masini. O le Microchip USB3320 USB 2.0 Transceiver Chip ma le 8-bit ALPI interface o loʻo faʻaaogaina o le PHY. O loʻo faʻaalia e le PHY le saoasaoa o le HS-USB Physical Front-End lagolago oʻo atu i le 480Mbs. O le PHY e fesoʻotaʻi i le MIO Bank 1/501, lea e faʻaaogaina i le 1.8V. O le usb0 peripheral o loʻo faʻaaogaina luga ole PS, fesoʻotaʻi ala ile MIO [28-39]. O le USB OTG interface ua maeʻa faʻatulagaina e avea o se hostaced host. USB OTG ma USB masini auala e le lagolagoina.
O le Arty Z7 ose tekinolosi o se "host embed" aua e le maua ai le manaʻomia 150 µF o capacitance luga VBUS manaʻomia e agavaʻa o se lautele-faʻamoemoe talimalo. E mafai ona faʻafetaui le Arty Z7 ina ia mafai ona usitaʻia le manaʻoga masani ole USB host e ala ile utaina ole C41 ma le 150 µF capacitor. Naʻo latou poto masani ile faʻapipiʻiina o mea laiti ile PCBs e tatau ona faʻataʻitaʻia lenei toefaʻaleleia. Tele USB masini siʻosiʻomaga o le a galulue lelei lava aunoa ma le utaina C41. Pe o le Arty Z7 ua faʻatulagaina e avea o se tamai talimalo talimalo poʻo se lautele-faʻamoemoe talimalo, e mafai ona maua ai le 500 mA luga o le 5V VBUS laina. Manatua o le utaina o C41 e ono mafua ai le Arty Z7 e toe setiina pe a osoina i totonu Linux faʻapipiʻiina afi mai le USB port, tusa lava pe i ai se USB masini e fesoʻotaʻi i le talimalo taulaga. O lenei mafuaʻaga e ala i le faanatinati galu e mafua mai C41 pe a mafai le USB talimalo pule mafai ai ma le VBUS mana ki (IC9) ua ki.

Manatua afai o lau tisaini faʻaaogaina le USB Host port (faʻapipiʻi pe lautele-faʻamoemoe), ona tatau ai lea ona faʻaola le Arty Z7 e ala i le maa poʻo le palaka palaka mafai ona maua ai le tele o le paoa (pei o le tasi o loʻo aofia i le Arty Z7 mea faʻaaoga pusa).

Ethernet PHY

O le Arty Z7 o loʻo faʻaaogaina le Realtek RTL8211E-VL PHY e faʻatino ai le 10/100/1000 Ethernet port mo fesoʻotaʻiga fesoʻotaʻiga. O le PHY fesoʻotaʻi i le MIO Bank 501 (1.8V) ma fesoʻotaʻiga i le Zynq-7000 APSoC ala i le RGMII mo faʻamaumauga ma MDIO mo le pulega. O faʻalavelave fesoasoani (INTB) ma toe seti (PHYRSTB) faʻailoga fesoʻotaʻi i MIO pine MIO10 ma MIO9, faʻatulagaina.

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-eth.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)

Ata 9.1. Faailoga Ethernet PHY

A maeʻa le malosiʻaga, e amata le PHY i le Auto-Negotiation e mafai ai, faʻasalalau le 10/100/1000 fesoʻotaʻiga saoasaoa ma atoa-duplex. Afai e i ai se paʻaga Ethernet-gafatia fesoʻotaʻi, o le PHY otometi lava faʻatuina se fesoʻotaʻiga ma ia, e oʻo lava i le Zynq e le faʻavasega.

Lua faʻailo tulaga LED o loʻo i luga o le laupapa latalata i le RJ-45 fesoʻotaʻiga o loʻo faʻailoa mai ai feoaʻi (LD9) ma le soʻotaga fesoʻotaʻiga (LD8). O le siata 9.1 o loʻo faʻaalia mai ai amioga le lelei.

Galuega	Tufuga	Setete	Fa'amatalaga
SOSO'OGA	LD8	Tumau i luga	Soʻotaga 10/100/1000
SOSO'OGA	LD8	Faʻapapipi 0.4s ON, 2s OFF	Link, Malosiaga Malosiaga Ethernet (EEE) faiga
GALUEGA	LD9	Fa emoemo	Auina atu pe Mauaina

Siata 9.1. Ethernet tulaga moliuila.

Ua tuʻufaʻatasia e le Zynq ni pulega tutoatasi Gigabit Ethernet. Latou faʻatinoina le 10/100/1000 afa / atoa-duplex Ethernet MAC. Mai nei mea e lua, GEM 0 mafai ona faʻafanua i pine MIO o loʻo fesoʻotaʻi ai le PHY. Talu ai o le MIO faletupe e afi mai le 1.8V, o le RGMII interface faʻaaogaina 1.8V HSTL Vasega 1 avetaʻavale. Mo lenei tulaga I / O, o se faʻamatalaga mai fafo o le 0.9V o loʻo saunia i le faletupe 501 (PS_MIO_VREF). O le faʻavasegaina o saʻo pine ma configuring le Ofisa o loʻo faʻatautaia e le Arty Z7 Zynq Presets file, avanoa i luga o le Arty Z7 Punaoa Autu (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start).

E ui lava o le faaletonu o le malosiaga o le PHY atonu e lava i le tele o tusi talosaga, o le MDIO pasi o avanoa mo le pulega. O le RTL8211E-VL ua tofia i ai le 5-bit address 00001 i luga o le pasi MDIO. Faatasi ai ma le faigofie lesitala faitau ma tusi tulafono, tulaga tulaga mafai ona faitauina i fafo pe faʻatulagaina suia. O le Realtek PHY mulimuli i se pisinisi-tulaga faʻafanua faʻafanua mo faʻavae faʻavae.

Ole faʻamatalaga a le RGMII e manaʻomia le maua (RXC) ma faʻasalalau le uati (TXC) e faʻatuai e faʻatatau i faʻamaumauga (RXD [0: 3], RXCTL ma TXD [0: 3], TXCTL). Xilinx PCB taiala e manaʻomia foi lenei tuai ona faʻaopopo. E mafai e le RTL8211E-VL ona faʻaofi se 2n tuai i luga uma o le TXC ma le RXC ina ia le manaʻomia ona fai umi ia faʻailoga o le laupapa.

O le PHY e faʻasolo mai i le 50 tutusa MHz () oscillator e uati le Zynq PS. O le parasite capacitance o le lua uta e maualalo lava e tuleia mai se tasi faʻavae.

I luga o se fesoʻotaʻiga Ethernet, e manaʻomia node uma se tuatusi MAC tulaga ese. I lenei tulaga, o le tasi-taimi-programmable (OTP) itulagi o le Quad-SPI flash ua faʻapolokalameina i le fale gaosi ma le 48-bit tulaga ese EUI-48/64 ™ talafeagai faʻailoaina. O le OTP tuatusi laina [0x20; 0x25] o loʻo iai le faʻailoga ma le muamua byte i le faʻasalalauga byte okaina o loʻo i le tuatusi sili ona maualalo. Faasino i le Tusitusiga pepa manatua manatua (http://www.cypress.com/file/177966/download) mo faʻamatalaga pe faʻafefea ona ulufale i itulagi OTP. A o faʻaaogaina le Petalinux, e otometi ona faʻatautaia lenei i le U-boot boot-loader, ma o le Linux system e otometi lava ona faʻavasegaina e faʻaaoga ai lenei tuatusi MAC tulaga ese.

Mo nisi faʻamatalaga e uiga i le faʻaaogaina o le Gigabit Ethernet MAC, faʻasino i le Zynq Tekinolosi Tusitaiala tusi lesona
( ug585-Zynq-7000-TRM [PDF]).

HDMI

O le Arty Z7 o loʻo iai ni uafu HDMI e lua e leʻo faʻamalosia: tasi le uafu i lalo o le J11 (output), ma le tasi le sink J10 (input). O uafu uma e lua o loʻo faʻaaogaina le ituaiga HDMI- O ni ato faʻatumu ma faʻamaumauga ma uati na faʻamutaina ma fesoʻotaʻi saʻo i le Zynq PL.

Uma HDMI ma DVI faiga faʻaaoga tutusa TMDS faʻailoga tulaga masani, tuusao lagolagoina e le Zynq PL tagata faʻaoga I / O atinaʻe tetele. Faʻapea foi, o fesoʻotaʻiga a HDMI e faʻafetaui i tua ma DVI sinks, ma le isi foʻi itu. O le mea lea, faigofie faigofie adapters adaptive (avanoa i tele eletise faleoloa) mafai ona faʻaaogaina e aveina ai se DVI mataʻitu pe talia se faʻauluina DVI. E naʻo le numera o numera e aofia ai faʻailoga numera, o lea e naʻo le DVI-D mode e mafai ai.

O le 19-pin HDMI fesoʻotaʻiga aofia tolu eseesega faʻamatalaga auala, tasi eseʻesega uati auala lima GND () sootaga, o le tasi-uaea Consumer Electronics Control (CEC) pasi, o le lua-uaea Faʻaalia Faʻamatalaga Channel (DDC) pasi o le mea moni o le I2C pasi, o le Hot Plug Detect (HPD) faʻailoga, o le 5V faʻailoga mafai ona kilivaina atu i le 50mA , ma le tasi faʻasao (RES) pine. O faailo uma e le o se paoa uaea i le Zynq PL sei vagana ai RES.

Pin/Signal	J11 (punavai)		J10 (magoto)
	Fa'amatalaga	FPGA pine	Fa'amatalaga	FPGA pine
D [2] _P, D [2] _N	Fa'amatalaga fa'amatalaga	J18, H18	Tuuina atu o faamatalaga	N20, P20
D [1] _P, D [1] _N	Fa'amatalaga fa'amatalaga	K19, J19	Tuuina atu o faamatalaga	T20, U20
D [0] _P, D [0] _N	Fa'amatalaga fa'amatalaga	K17, K18	Tuuina atu o faamatalaga	V20, W20
CLK_P, CLK_N	Galuega faatino a le uati	L16, L17	Ulufale mai le uati	N18, P19
CEC	Tagata faʻatonu eletise faʻatonutonu lua (filifiliga)	G15	Tagata faʻatonu eletise faʻatonutonu lua (filifiliga)	H17
SCL, SDA	DDC faʻalua filifiliga (tuu i le faitalia)	M17, M18	DDC faʻalua	U14, U15
HPD / HPA	Mauaina e le vevela-plug le sao (fesuiaʻi, tuu i le faitalia)	R19	Vevela-plug faʻamaonia galuega faatino	T19

Siata 10.1. HDMI pine faʻamatalaga ma tofiga.

Faailoga a le TMDS

HDMI / DVI o se televave televave numera telefoni feaveaʻi fesoʻotaʻiga faʻaaogaina suiga-faʻaititia eseesega faʻailo (TMDS). Ina ia faʻaaoga saʻo se tasi o uafu HDMI, e manaʻomia ona faʻatinoina se fesoʻotaʻiga masani-faʻatonutonu poʻo se tagata e taliaina i le Zynq PL. O faʻamatalaga faʻatinoina e i fafo atu ole lautele ole tusi lesona lenei. Siaki le ata vitio IP potu teuina i luga o le Digilent GitHub (https://github.com/Digilent) mo sauni IP e faʻaaoga.

Faailo ausilali

Soʻo se taimi e sauni ai se sink ma manaʻo e faʻalauiloa mai lona i ai, na te fesoʻotaʻi le 5V0 sapalai pine i le HPD pin. I luga o le Arty Z7, o lenei e faia i le aveina o le Hot Plug Faʻailoa faailo maualuga. Manatua e tatau ona faia lenei mea pe a maeʻa ona faʻaogaina le poloka a le DDC channel i le Zynq PL ma ua sauni e tuʻuina atu faʻamatalaga faʻaali.

O le Faʻaaliga Faʻamatalaga Channel, poʻo le DDC, o se faʻaputuga o tulafono faʻapitoa e mafai ai fesoʻotaʻiga i le va o le faʻaaliga (magoto) ma kalafi adapter (punavai). O le DDC2B eseʻese e faʻavae i luga o le I2C, o le pasi pasi o ia lea o le puna ma o le pasi pologa le magoto. A maua e se mafuaʻaga se tulaga maualuga i luga o le pine HPD, na te fesiligia le tapu i luga o le pasi DDC mo mea e mafai ona fai i le vitio. E fuafua pe o le tapu e DVI poʻo le HDMI-agavaʻa ma o a faʻaiuga e lagolagoina. Naʻo se taimi mulimuli ane o le a amata ai ona faʻasalalau le ata. Vaʻai ile VESA E-DDC faʻamatalaga faʻapitoa mo nisi faʻamatalaga.

O le Consumer Electronics Control, poʻo le CEC, o se filifiliga e faʻatagaina e faʻatonutonu ai feau tusitusia i luga o le filifili filifili HDMI i le va o oloa eseese. O le faʻaaoga masani mataupu o se TV pasi faʻatonutonu feʻau feaveaʻi amata mai le lautele taumamao i se DVR poʻo le satelite e taliaina. O se tasi-uaea aiaiga i se tulaga 3.3V fesoʻotaʻi i le Zynq PL tagata faʻaaoga I / O pine. E mafai ona faʻatonutonu le uaea i se auala tatala avanoa e faʻatagaina ai le tele o masini e tufatufaina le uaea CEC masani. Vaai i le CEC faʻaopoopoga o HDMI 1.3 pe mulimuli ane faʻamatalaga mo nisi faʻamatalaga.

Punaoa o le Uati

O le Arty Z7 maua ai se 50 MHz () uati i le Zynq PS_CLK sao, lea e faʻaaoga e gaosi ai uati mo vaega taʻitasi o PS. O le 50 MHz () sao e faʻatagaina ai le masini faʻagaioia ona faʻagaioia i se maualuga maualuga o le 650 MHz () ma le DDR3 manatua pule e faʻagaioia i le maualuga o le 525 MHz () (1050 Mbps). Le Arty Z7 Zynq Presets file avanoa ile Arty Z7 Punaoa Autu (https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start) mafai ona faʻaulufale mai i totonu o le Zynq Processing System IP autu i se poloketi Vivado e faʻalelei lelei le Zynq e galue ai ma le 50 MHz () uati sao

O le PS o loʻo iai le PLL faʻapitoa e mafai ona gaosia e oʻo atu i le fa o uati, e tofu ma le auala e mafai ai ona toe faʻaleleia, e mafai ona faʻaaoga e uati ai le agavaʻa o loʻo faʻatinoina i le PL. E le gata i lea, o le Arty Z7 o loʻo maua ai se 125 fafo MHz () Faasino tonu le uati i le H16 o le PL. O le uati e faʻasino i fafo e faʻatagaina le PL e faʻaaoga tutoʻatasi le PS, lea e mafai ona aoga mo faigofie polokalama e le manaʻomia se gaosiga.

O le PL o le Zynq o loʻo iai foʻi ma MMCM's ma PLL e mafai ona faʻaaogaina e faʻatupu ai uati ma taimi saʻo ma va fealofani. Soʻo se fa o uati a le PS e faʻamatala atu poʻo le 125 MHz () e mafai ona faʻaaogaina le uati faʻasino i fafo e fai ma sao i MMCMs ma PLLs. O le Arty Z7-10 aofia ai 2 MMCM's ma 2 PLL's, ma le Arty Z7-20 aofia ai 4 MMCM's ma 4 PLL's. Mo se faʻamatalaga atoa o agavaʻa o le Zynq PL uati faʻasoa, vaʻai i le "7 Series FPGAs Clocking Resources User Guide" avanoa mai Xilinx.

O le Ata 11.1 o loʻo faʻamatalaina mai ai le uati polokalame i le Arty Z7. Manatua o le faʻasino uati galuega faatino mai le Ethernet PHY o loʻo faʻaaogaina e pei o le 125 MHz () Faasino le uati i le PL, ina ia mafai ai ona tipi le tau o le aofia ai o se oscillator tuuto mo lenei faamoemoe. Manatua o le CLK125 o le a le atoatoa pe a fai o le Ethernet PHY (IC1) o loʻo taofia i le toe setiina o masini e le aveina o le faʻailoga PHYRSTB maualalo.

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-clocking.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)

Ata 11.1. Arty Z7 uati

Faʻavae I / O

O le Arty Z7 laupapa e aofia ai LED e tolu-lanu, 2 ki, 4 pushbuttons, ma le 4 taʻitaʻi moli e pei ona faʻaalia i le Ata 12.1. O le pushbuttons ma slide switch e fesoʻotaʻi i le Zynq PL e ala i resistors faʻasologa e puipuia ai le faʻaleagaina mai le vave iloa auala matagaluega (o se puʻupuʻu matagaluega ono tupu pe a fai o le FPGA pine tofia i le tulei faʻamau poʻo le sifi ki na faʻamatalaina le iloa faʻapea o se galuega faatino). O le fa tekanomiina o le "puʻupuʻu" ki e masani ai ona maua ai se maualalo galuega faatino pe a latou o malolo, ma o se maualuga galuega faatino pe a oomiina. Faʻasolo ki e faʻaaluina ai i luga maualalo pe maualalo faʻaofi faʻalagolago i lo latou tulaga.

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-gpio.png?id=reference%3Aprogrammable-logic%3Aarty-z7%3Areference-manual)

Ata 12.1. Arty Z7 GPIO ().

O le fa faitoatasi maualuga-lelei LEDs o loʻo fesoʻotaʻi fesoʻotaʻi ma le Zynq PL ala i le 330-ohm resistors, o lea o le a latou kiina peʻa o se mafaufau maualuga voltagu e faʻaaogaina ia latou I / O pine. O isi moli uila e le o faʻaaogaina e tagata e faʻaalia ai le paoa, tulaga o polokalame a le PL, ma le tulaga o le taulaga o USB ma Ethernet.

Tri-Valivali Uila

O le Arty Z7 laupapa o loʻo iai moliila moli e lua. Taʻitasi lanu-lanu Taitaiina () e tolu faʻailoga faʻaulufaleina e faʻatosina ai laina o tolu laʻititi LED i totonu: tasi mumu, tasi lanumoana, ma tasi lanumeamata. Avea le faʻailoga e fetaui i se tasi o nei lanu maualuga o le a faʻamalamalamaina totonu o totonu LED (). O faʻailoga o loʻo faʻaulufaleina o loʻo unaʻia e le Zynq PL e ala atu ile transistor, e feliuliuaʻi faʻailo. O le mea lea, ia susulu le tolu-lanu LED (), o faʻailoga e tatau ona tuleia e maualuga. O le tolu-lanu Taitaiina () o le a faʻailoa mai se lanu faʻamoemoeina i le tuʻufaʻatasia o totonu LED o loʻo faʻamalamalamaina nei. Mo example, afai o le mumu ma lanumoana faʻailo e tulia maualuga ma lanumeamata e tulia maualalo, o le tolu-lanu Taitaiina () o le a faʻailoa mai se lanu viole.

Ua fautuaina malosi e le Digilent le faʻaaogaina o fuataga o le pulse-lautele (PWM) peʻa aveina le taʻitaʻi lanu e tolu lanu. Avea se mea o faʻapipiʻiina i se mautu mafaufauga '1' o le a iʻu i le Taitaiina () susulu i se tulaga le lelei susulu. Oe mafai ona aloese mai lenei i le mautinoa e leai se tasi o le tri-lanu faʻailo e tuleia ma sili atu i le 50% tiute taʻamilosaga. Faʻaaogaina PWM faʻateleina foi faʻalauteleina le ono lanu palette o le tri-lanu taʻitaʻia. Taʻitoʻatasi fetuʻunaʻi le tiute taʻamilosaga o lanu taʻitasi i le va o le 50% ma le 0% mafua ai le eseʻese lanu e faʻamalamalamaina i eseese malosiaga, faʻatagaina toetoe lava soʻo se lanu e faʻaali.

Mono Audio Galuega Faatino

O le leo leo luga (J13) o loʻo unaʻia e le Sallen-Key Butterworth Low-pass 4th Order Filter e maua ai le leo leo. O le faʻasologa o le faamama maualalo pasi o loʻo faʻaalia i le Ata 14.1. O le sao o le faʻamama (AUD_PWM) e fesoʻotaʻi i le Zynq PL pin R18. O le numera numera o le a masani lava ona avea ma pulse-lautele modulated (PWM) poʻo pulse density modulated (PDM) matala-alavai faailo gaosia e le FPGA. O le faailo e manaʻomia ona tulia maualalo mo mafuaaga '0' ma tuua i maualuga-impedance mo mafuaaga '1'. O se i luga o le laupapa toso-i luga resistor i se mama analog 3.3V nofoaafi o le a faʻatuina le vol talafeagaitagu mo mafuaaga '1'. O le faamama maualalo pasi luga o le sao o le a avea o se toefaʻamama faamama e faʻaliliu ai le pao-lautele modulated faʻailoga numera i se analog voltagu luga o le leo leo galuega faatino.

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-audio-sch.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)

Ata 13.1. Leo matagaluega galuega faatino.

O le Faʻaliga leo pupuni lalo (AUD_SD) o loʻo faʻaaogaina e faʻagugu ai le leo leo. E fesoʻotaʻi i le Zynq PL pin T17. Ina ia faʻaaogaina le leo leo, o lenei faʻailo e tatau ona unaʻia e logolelei maualuga.

Ole tali masani a le SK Butterworth Low-Pass Filter o loʻo faʻaalia ile Ata 13.2. O le suʻesuʻega AC o le matagaluega ua maeʻa faʻaaogaina le NI Multisim 12.0.

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-audio-chart-nolabel.png?id=reference%3Aprogrammablelogic%3Aarty-z7%3Areference-manual)

Ata 13.2. Tali Faʻafia masani a Galuega Faʻasalalau.

Uiga-lautele lautele Modulasi

O le faailo o le lautele-lautele-fesuiaʻi (PWM) o se filifili o uaua i nisi taimi faʻatulagaina, ma paʻaga uma ono i ai se eseese lautele. O lenei numera numera e mafai ona pasia e ala i se faigofie maualalo-pasi faʻamama e tuʻufaʻatasia ai le numera o galu e fausia ai se analog voltagu faʻatusatusa i le averesi pulse-lautele i luga o ni vaitaimi (o le va na fuafuaina e le 3dB tipi-ese taimi o le maualalo-pasi faʻamama ma le taimi o uaua). Mo example, pe afai o pulusili e maualuga mo le averesi o le 10% o le avanoa paʻu avanoa, ona avea ai lea o le tuʻufaʻatasia se fua faʻatusatusa o le 10% o le Vdd voltagu Ata 13.1.1 o loʻo faʻaalia ai se fesuiaiga o galu e fai ma faʻailoga o le PWM.

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-audio-pdm.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)

Ata 13.1.1. PWM Waveform.

O le faʻailoga a le PWM e tatau ona tuʻufaʻatasia e faʻamatala ai se analog voltagu O le maualalo pasi pasi 3dB taimi tatau tatau ona avea ma se faʻatonuga o le maualuga maualalo nai lo le PWM taimi masani ina ia faʻailo malosiaga i le PWM taimi masani ua faʻamamaina mai le faʻailo. Mo example, pe a fai o se leo faʻailo tatau ona aofia ai oʻo i le 5 kHz o taimi masani faʻamatalaga, o lona uiga o le PWM taimi e tatau ona le itiiti ifo ma le 50 kHz (ma sili atu ona maualuga). I se tulaga lautele, i tulaga o faʻailo faʻamaoni faʻamaoni, o le maualuga o le PWM taimi, o le sili atu lea. Ata 13.1.2 o loʻo faʻaalia ai se sui o le PWM tuʻufaʻatasia gaosia se galuega faatino voltagu e ala i le tuʻufaʻatasia o le nofoa afi Matau le mautu-tulaga faamama galuega faatino faailo ampLatio fua faʻatusatusa i le Vdd e tutusa lava ma le lapoʻa o le mamafa o le tiute (o le taʻamilosaga o le taʻamilosaga o le taimi o le pao-maualuga e vaevaeina i le taimi o le pulus-window).

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-audio-pwm.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)

Figure 13.1.2. PWM Output Voltage.

Toe seti Punaoa

Mana-i le toe setiina

O le Zynq PS e lagolagoina malosiaga i fafo-o toe faʻailo faailo. O le malosiʻaga toe setiina o le toe setiina sili o le malamala atoa. O lenei faailo toe setiina uma lesitala i le masini mafai ona toe setiina. O le Arty Z7 na te faʻateʻaina lenei faʻailo mai le faʻailoga PGOOD o le TPS65400 paoa faʻatonutonu ina ia mafai ona taofia le sisitema seʻia faʻamaonia uma sapalai o le eletise.

Faʻamau Tulei Faʻamau ki

O le PROG tulei ki, faʻailoga PROG, suia Zynq PROG_B Lenei toe setiina le PL ma mafua ai ona faia de-taʻutino. O le PL o le a tumau pea le le faʻavasegaina seʻia oʻo ia toe faʻapolokalamaina e le masini gaosi poʻo ala atu ia JTAG.

Faʻagasologa Laʻasaga Laiti toe setiina

O le faiga i fafo toe setiina, faʻaigoaina SRST, toe setiina le Zynq masini e aunoa ma le faʻalavelaveina o le debug siosiomaga. Mo example, o breakpoints muamua seti e le tagata faʻaaoga tumau faʻamaonia pe a maeʻa le toe setiina o le tino. Ona o atugaluga o le puipuiga, o le system reset e tineia uma ai mea e manatua i totonu ole PS, e aofia ai ma le OCM. O le PL e faʻamamaina foi i le taimi o le toe setiina o le tino. O le toe setiina o le polokalame e le mafua ai ona toefaʻamau le metotia o le nonoaamptaitaiina

O le faʻamau SRST e mafua ai foʻi ona suia le faʻailoga a le CK_RST ina ia mafai ai ona toe faʻapipiʻi soʻo se talipupuni faʻapipiʻiina.

Taulaga Pmod

Pmod ports o 2 × 6, taumatau-tulimanu, 100-mil avanoa vavalalata fafine fesoʻotaʻiga ma paʻaga ma masani 2 × 6 pine ulutala. Taitasi 12-pine Pmod taulaga maua lua 3.3V VCC () faailo (pine 6 ma le 12), lua Faʻailoga eleele (pine 5 ma 11), ma faʻailoga valu e pei ona faʻaalia i le Ata 15.1. O le VCC () ma Eleele pine mafai ona lafoina atu i le 1A o taimi nei, ae tatau ona faʻaeteete ia aua neʻi sili atu i soʻo se paketi o paoa a le pulega faʻatonutonu poʻo le sapalai o le paoa eletise (vaʻai le 3.3V nofoaafi o loʻo iai tapulaʻa o loʻo lisiina i le vaega o le "sapalaiina o le paoa") .

(https://reference.digilentinc.com/_detail/reference/programmable-logic/arty-z7/arty-z7-pmod.png?id=reference%3Aprogrammable-logic%3Aartyz7%3Areference-manual)
Ata 15.1. Pmod Port Ata

Digilent gaosia se tele faʻaputuputuga o Pmod fesoasoani mea laupapa e mafai ona faʻapipiʻi i le Pmod faʻalautele fesoʻotaʻiga e faʻaopopo saunia-faia galuega e pei o A / D's, D / A's, afi ave taʻavale, masini faʻapitoa, ma isi gaioiga. Vaai www.digilentinc.com (http://www.digilentinc.com) mo nisi faamatalaga.

Taitasi Pmod taulaga maua i luga Digilent FPGA laupapa pa'ū i totonu o se tasi o le fa vaega: tulaga faatonuina, MIO fesoʻotaʻi, XADC, po o maualuga-saosaoa. O le Arty Z7 e lua Pmod ports, o mea uma e lua o le televave ituaiga. O le vaega o loʻo sosoʻo mai e faʻamatalaina le saoasaoa o le ituaiga Pmod port.

Pmods televave

O le maualuga-saoasaoa Pmods ua i ai a latou faʻailo faʻailoaina faʻatonutonuina pei impedance faʻafetaui paʻaga eseese mo maualuga fegasoloaʻi saoasaoa. Latou i ai pads mo le utaina o teteʻe mo puipuiga faaopoopo, ae o le Arty Z7 vaʻa ma nei utaina o 0-Ohm shunts. Faatasi ai ma le faasologa resistors shunted, nei Pmods ofoina leai se puipuiga mai puupuu liʻo ae faʻatagaina mo sili atu vave fesuiaʻi saoasaoa. O faʻailo e tuʻufaʻatasia i faʻailoga lata ane i le laina tutusa: pine 1 ma le 2, pine 3 ma le 4, pine 7 ma le 8, ma pine 9 ma le 10.

E faʻasolosolo faʻasolosolo 100 ohm (+/- 10%) eseʻesega.

A faʻapea o pine i luga o lenei uafu e faʻaaogaina o faʻailoga e tasi le iʻuga, e faʻaalia e crosstalk paga soʻosoʻo. I tusi apalai o loʻo avea ma mea e faʻapopoleina ai, o se tasi o faʻailo e tatau ona faʻavaeina (aveina maualalo mai le FPGA) ma faʻaaoga lana paga mo le faʻailo ua maeʻa faʻailo.

Talu ai o le High-Speed Pmods e i ai 0-ohm shunts nai lo le puipuia resistors, e tatau i le tagata faʻataʻitaʻi ona faia puipuiga e mautinoa ai latou te le mafuaʻaga ni pupuʻu.

Arduino / chipKIT Shield Connector

E mafai ona faʻafesoʻotaʻi le Arty Z7 ile masani Arduino ma chipsKIT talipupuni e faʻaopopo ai le faʻalauteleina o galuega. Faʻapitoa tausiga na faia a o fuafuaina le Arty Z7 ia mautinoa e fetaui ma le tele o Arduino ma chipKIT talita i luga o le maketi. O le fesoʻotaʻiga puipuia e 49 pine e fesoʻotaʻi i le Zynq PL mo le lautele-faʻatekinolosi I / O luga o le Arty Z7-20 ma le 26 i le Arty Z7-10. Ona o le fetuutuunai o FPGAs, ua mafai ai ona faʻaaoga nei pine mo soʻo se mea e aofia ai numera faitau / tusitusi, fesoʻotaʻiga SPI, UART fesoʻotaʻiga, I2C faʻafesoʻotaʻiga, ma PWM. Ono o nei pine (faʻaigoaina AN0-AN5) mafai foi ona faʻaaogaina o faʻatasi analog i totonu ma le aofaʻi o le 0V- 3.3V, ma le isi ono (faʻaigoaina AN6-11) e mafai ona faʻaaogaina o faʻaeseesega faʻaopoopoga faʻaofi.

Faʻaaliga: O le Arty Z7 e le fetaui ma talita e faʻatino ai 5V numera faʻanumera pe faʻatusa. Avea pine o le Arty Z7 talita fesoʻotaʻiga luga 5V ono mafua ai le faʻaleagaina o le Zynq.

(https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty-z7-shield.png)

Ata 16.1. Shield Pin Diagram.

Igoa Pin	Galuega Talita	Sootaga Arty Z7
IO0–IO13	Faʻamoemoe lautele I / O pine	Vaʻai le vaega faʻaulutalaina "Shield Digital I / O"
IO26–IO41, A (IO42)	Arty Z7-20 Lautele mafuaʻaga Oʻu / O pine	Vaʻai le vaega faʻaulutalaina "Shield Digital I / O"
SCL	Uati I2C	Vaʻai le vaega faʻaulutalaina "Shield Digital I / O"
SDA	I2C Faʻamatalaga	Vaʻai le vaega faʻaulutalaina "Shield Digital I / O"
SCLK ()	Uati SPI	Vaʻai le vaega faʻaulutalaina "Shield Digital I / O"
MOSI ()	SPI Faʻamatalaga mai	Vaʻai le vaega faʻaulutalaina "Shield Digital I / O"
MISO ()	SPI Faʻamatalaga i	Vaʻai le vaega faʻaulutalaina "Shield Digital I / O"
SS	SPI Filifili Filifili	Vaʻai le vaega faʻaulutalaina "Shield Digital I / O"
A0–A5	Ulufale Igoa Faʻavae Nofofua	Vaʻai le vaega faʻaulutalaina "Shield Analog I / O"
A6–A11	Eseesega Faʻamatalaga Faʻaopopo	Vaʻai le vaega faʻaulutalaina "Shield Analog I / O"

Igoa Pin	Galuega Talita	Sootaga Arty Z7
V_P, V_N	Tuʻufaʻatasia o Faʻamatalaga Eseesega Igoa	Vaʻai le vaega faʻaulutalaina "Shield Analog I / O"
XGND	XADC Analog Ground	Fesoʻotaʻi i upega faʻaaoga e tulia le XADC eleele faʻasino luga o le Zynq (VREFN)
XVREF	XADC Analog Voltagu Tusitusiga	Fesoʻotaʻi i le 1.25 V, o le nofoaafi 25mA e faʻaalu ai le XADC voltagu faʻamatalaga i luga o le Zynq (VREFP)
N/C	Le Feso'ota'i	Le Feso'ota'i
IOREF	Digital I / O Voltagu faasinomaga	Fesoʻotaʻi i le Arty Z7 3.3V Malosi afi (Vaʻaia le "Sapalai Mana" vaega)
RST	Toe setiina i le talita	Fesoʻotaʻi i le mumu "SRST" faʻamau ma MIO pin 12 o le Zynq. A puʻupuʻu JP1, e fesoʻotaʻi foʻi i le faʻailoga DTR o le FTDI USB-UART alalaupapa.
3V3	3.3V Malosiaga afi	Fesoʻotaʻi i le Arty Z7 3.3V Malosi afi (Vaʻaia le "Sapalai Mana" vaega)
5V0	5.0V Malosiaga afi	Fesoʻotaʻi i le Arty Z7 5.0V Malosi afi (Vaʻaia le "Sapalai Mana" vaega)
GND (), G	eleele	Fesoʻotaʻi i le Eleele vaʻalele a Arty Z7
VIN	Malosiaga Ulufale	Fesoʻotaʻi faʻatasi ma le paoa sapalai sapalai paipa (J18).

Siata 16.1. Shield Pin Faʻamatalaga.

Shield Faʻafuainumera Ou / Le

O pine e fesoʻotaʻi tuʻusaʻo i le Zynq PL e mafai ona faʻaaogaina o mea lautele poʻo mea e faʻaulu ai. O nei pine e aofia ai le I2C, SPI, ma le lautele-faʻamoemoe I / O pine. E i ai le 200 Ohm series resistors i le va o le FPGA ma le digital I / O pine e fesoasoani e tuʻu ai le puipuiga mai faʻalavelave pupuʻu faʻafuaseʻi (seʻi vagana ai faʻailoga AN5-AN0, ia e leai ni puipuiga, ma faʻailoga AN6-AN12, e iai 100 Ohm faasologa tetee). Le maualuga atoatoa ma fautuaina faʻagaioiga voltages mo nei pine o loʻo otooto atu i le laulau i lalo.

IO26-IO41 ma le A (IO42) e le mafai ona maua i luga o le Arty Z7-10. E le gata i lea, ole AN0-AN5 e le mafai ona faʻaaogaina ole Digital I / O ile Arty Z7-10. E mafua lenei mea ona o le toʻaitiiti o au / O pine o avanoa i luga o le Zynq-7010 nai lo le Zynq-7020.

	Atoatoa Maualalo Voltage	Fautuaina Maualalo Galue Galuetage	Fautuaina Maximum Operating Voltage	Atoatoa Tapulaa maualuga Voltage
Malosi	-0.4 V	-0.2 V	3.4 V	3.75 V
Le faʻamaonia	-0.4 V	N/A	N/A	0.55 V

Siata 16.1.1. Shield Digital VoltagMo nisi faʻamatalaga i luga o le eletise uiga o pine fesoʻotaʻi i le Zynq PL, faʻamolemole vaʻai i le Zynq-7000 laupepa
(ds187-XC7Z010-XC7Z020-Data-Sheet) mai Xilinx

Shield Analog I / O

O pine ua faʻaigoaina A0-A11 ma V_P / V_N o loʻo faʻaaogaina e fai ma analog input i le XADC module o le Zynq. O loʻo manatu le Zynq o mea e ulufale ai e amata mai ile 0-1 V. I luga o pine ua faʻaigoaina A0-A5 matou te faʻaaogaina ai se matagaluega i fafo e fua ai i lalo le sao voltagu mai le 3.3V. Lenei matagaluega o loʻo faʻaalia i le Ata 16.2.1. Lenei matagaluega faʻatagaina le XADC module e faʻatatau saʻo se voltagu i le va 0V ma le 3.3V (faʻatatau i le Arty Z7's GND ()) e faʻapipiʻi i soʻo se tasi o nei pine. Afai e te manaʻo e faʻaoga pine ua faʻaigoaina A0-A5 o Digital inputs poʻo galuega, o loʻo fesoʻotaʻi saʻo foʻi i le Zynq PL i luma o le resistor divider circuit (o loʻo faʻaalia foi i le Ata 16.2.1) i luga o le Arty Z7-20. Lenei fesoʻotaʻiga faʻaopoopo e le faia i luga o le Arty Z7-10, o le mafuaʻaga lea e mafai ai ona faʻaaogaina nei faʻailoga e pei o analog inputs i luga o lena variant.

(https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty-z7-shield-an.png)

Ata 16.2.1. Ulufale Igoa Faʻavae Nofofua.

O pine ua faʻaigoaina A6-A11 e fesoʻotaʻi saʻo i 3 paga o analog mafai pine i luga o le Zynq PL ala i le teteʻe anti-aliasing. Lenei matagaluega o loʻo faʻaalia i le Ata 16.2.2. O nei paga o pine e mafai ona faʻaaogaina o faʻaʻeseʻese analog faʻaopoopoga ma le voltagu eseʻesega i le va 0-1V. O numera o fesoʻotaʻi e fesoʻotaʻi i pine lelei o le paga ma numera laʻititi e fesoʻotaʻi i le le lelei pine (o lea A6 ma A7 fausia se analog faʻaopopo paʻaga ma A6 lelei ma A7 le lelei). Manatua e ui lava o pads mo le capacitor o loʻo iai, latou te le utaina mo nei pine. Talu ai o le analog-mafai pine o le FPGA mafai foi ona faʻaaogaina e pei o masani numera FPGA pine, e mafai foi ona faʻaaoga nei pine mo Digital I / O.

O pine ua faʻaigoaina V_P ma V_N e fesoʻotaʻi i le VP_0 ma VN_0 tuʻufaʻatasia analog faʻaaogaina o le FPGA. Lenei pea pine e mafai foi ona faʻaaogaina o se eseʻesega faʻaopoopo analog ma se voltagu i le va 0-1V, ae le mafai ona faʻaaogaina o le Digital I / O. O le capacitor i le matagaluega faʻaalia i le Ata 16.2.2 mo lenei pea o pine o loʻo utaina i luga o le Arty Z7.

(https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty-z7-shield-diff-an.png)

Ata 16.2.2. Eseesega Faʻamatalaga Galue.

O le XADC autu i totonu o le Zynq o se lua-auala 12-bit analog-to-digital converter mafai ona faʻagaioia i le 1 MSPS. A le o se auala mafai ona tulia e soʻo se mea faʻaopoopo analog fesoʻotaʻi i le talita pine. O le XADC autu o loʻo faʻatonutonuina ma faʻaavanoaina mai se mamanu o loʻo faʻaaogaina e ala ile Dynamic Reconfiguration Port (DRP). O le DRP o loʻo iai foʻi avanoa i voltagu siaki o loʻo iai i luga o laina paoa taʻitasi a le FPGA, ma le sensor vevela o loʻo i totonu o le FPGA. Mo nisi faʻamatalaga e uiga i le faʻaaogaina o le XADC autu, faʻasino i le Xilinx pepa faʻaulutalaina "7 Series FPGAs ma Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". E mafai foʻi ona sao atu i le autu o le XADC i le faʻaaogaina o le PS, e ala atu i le "PS-XADC" interface. Lenei fesoʻotaʻiga o loʻo faʻamatalaina atoa i le mataupu 30 o le Zynq
Tusi lesona Tusitaiala Faʻapitoa ( ug585-Zynq-7000-TRM [PDF]). rm (https://reference.digilentinc.com/tag/rm?do=showtag&tag=rm), faʻamatalaga (https://reference.digilentinc.com/tag/doc?do=showtag&tag=doc), arty-z7
(https://reference.digilentinc.com/tag/arty-z7?do=showtag&tag=arty-z7)

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