ALPHA DATA ADM-PCIE-9H3 High Performance FPGA Processing Card
Pambuka
ADM-PCIE-9H3 minangka kertu komputasi sing bisa dikonfigurasi ulang kanthi kinerja dhuwur sing ditujokake kanggo aplikasi Pusat Data, kanthi Xilinx Virtex UltraScale + Plus FPGA kanthi Memori Bandwidth Tinggi (HBM).
Fitur Utama
- PCIe Gen1/2/3 x1/2/4/8/16 capable
- Konfigurasi manajemen termal pasif lan aktif
- 1/2 dawa, kurang profile, x16 pinggiran PCIe wangun faktor
- 8GB HBM on-die memori saged 460GB/s
- Siji kandhang QSFP-DD sing nduweni tingkat data nganti 28 Gbps saben 8 saluran (224 Gbps)
- Siji 8 lane Ultraport SlimSAS konektor tundhuk karo OpenCAPI lan cocok kanggo expansion IO
- Ndhukung VU33P utawa VU35P Virtex UltraScale + FPGAs
- Panel ngarep lan pinggir mburi JTAG akses liwat port USB
- FPGA bisa dikonfigurasi liwat USB/JTAG lan lampu kilat konfigurasi SPI
- Voltage, ngawasi arus, lan suhu
- 8 sinyal GPIO lan 1 input wektu terisolasi
Kode Order
ADM-PCIE-9H3
ADM-PCIE-9H3/NF (tanpa kipas opsional)
Delengen http://www.alpha-data.com/pdfs/adm-pcie-9h3.pdf kanggo opsi pesenan lengkap.
Informasi Papan
Spesifikasi Fisik
ADM-PCIE-9H3 tundhuk karo revisi PCI Express CEM 3.0.
Tabel 1: Dimensi Mekanik (Inc. Panel Depan)
| Katrangan | Ngukur |
| Total Dy | 80.1 mm |
| Total Dx | 181.5 mm |
| Total Dz | 19.7 mm |
| Bobot | 350g wuh |
Requirements sasis
PCI Express
ADM-PCIE-9H3 saged PCIe Gen 1/2/3 karo 1/2/4/8/16 dalan, nggunakake Xilinx Integrated Block kanggo PCI Express.
Syarat Mekanik
A slot PCIe fisik 16-lane dibutuhake kanggo kompatibilitas mechanical.
Keperluan Daya
ADM-PCIE-9H3 ndudohke kabeh daya saka PCIe Edge. Miturut spesifikasi PCIe, iki mbatesi konsumsi daya kertu nganti maksimal 75W.
Perkiraan konsumsi daya mbutuhake panggunaan spreadsheet Xilinx XPE lan alat taksiran daya sing kasedhiya saka Alpha Data. Hubungi support@alpha-data.com kanggo entuk alat iki.
Daya sing kasedhiya kanggo rel sing diwilang nggunakake XPE yaiku:
Tabel 2: Daya Kasedhiya Miturut Rel
| Voltage | Jeneng Sumber | Kapabilitas Saiki |
| 0.72-0.90 | VCC_INT + VCCINT_IO + VCC_BRAM | 42A |
| 0.9 | MGTAVCC | 5A |
| 1.2 | MGTAVTT | 9A |
| 1.2 | VCC_HBM * VCC_IO_HBM | 14A |
| 1.8 | VCCAUX + VCCAUX_IO + VCCO_1.8V | 1.5A |
| 1.8 | MGTVCCAUX | 0.5A |
| 2.5 | VCCAUX_HBM | 2.2A |
| 3.3 | 3.3V kanggo Optik | 3.6A |
Kinerja termal
Yen suhu inti FPGA ngluwihi 105 derajat Celsius, desain FPGA bakal dibusak kanggo nyegah kertu dadi panas banget.
ADM-PCIE-9H3 dilengkapi sink panas kanggo nyuda suhu FPGA, sing biasane titik paling panas ing kertu. Suhu mati FPGA kudu tetep ing sangisore 100 derajat Celsius. Kanggo ngetung suhu mati FPGA, njupuk daya aplikasi, multiply dening Theta JA saka tabel ing ngisor iki, lan nambah kanggo suhu lingkungan internal sistem. Grafik ing ngisor iki nuduhake rong garis, siji dites ing saluran kanthi shrouds dipasang, lan liyane dites tanpa shrouds. Kinerja umume luwih apik tanpa shroud, nanging nyedhiyakake penanganan sing luwih apik lan nyuda sirkulasi udara ing server kompak. Kafan bisa dicopot nggunakake driver hex 1/16″. Yen sampeyan nggunakake penggemar kasedhiya karo Papan, sampeyan bakal nemokake theta JA kira-kira 1.43 degC / W kanggo Papan ing isih online karo utawa tanpa shroud diinstal.
Boros daya bisa dikira kanthi nggunakake estimator daya Alpha Data bebarengan karo Xilinx Power Estimator (XPE) sing bisa didownload ing http://www.xilinx.com/products/technology/power/xpe.html. Ngundhuh
alat UltraScale lan nyetel piranti kanggo Virtex UltraScale +, VU33P, FSVH2104, -2, -2L, utawa -3, ditambahi. Setel suhu sekitar menyang lingkungan sistem lan pilih 'user override' kanggo theta JA sing efektif lan ketik angka sing ana gandhengane karo sistem LFM ing kolom kosong. Terusake kanggo ngetik kabeh unsur desain sing ditrapake lan panggunaan ing tab spreadsheet ing ngisor iki. Sabanjure entuk estimator daya 9H3 saka Alpha Data kanthi ngubungi
support@alpha-data.com. Sampeyan banjur bakal plug ing tokoh daya FPGA bebarengan karo tokoh modul Optical kanggo njaluk ngira tingkat Papan.
Manajemen Termal Aktif VS Pasif
ADM-PCIE-9H3 dikirim nganggo blower opsional cilik kanggo pendinginan aktif ing sistem kanthi aliran udara sing ora apik. Yen ADM-PCIE-9H3 bakal diinstal ing server karo aliran udara kontrol, pilihan pesenan / NF bisa digunakake kanggo nampa kertu tanpa Piece ekstra iki. Penggemar duwe wektu sing luwih cendhek antarane kegagalan (MTBF) tinimbang liyane saka perakitan, mula kertu pasif duwe pangarep-arep urip luwih suwe sadurunge mbutuhake pangopènan. ADM-PCIE-9H3 uga kalebu pengontrol kacepetan penggemar, ngidini kacepetan penggemar variabel adhedhasar suhu mati, lan
deteksi penggemar gagal (ndeleng bagean Pengontrol Fan).
Kustomisasi
Alpha Data nyedhiyakake pilihan kustomisasi ekstensif kanggo produk komersial sing wis ana (COTS).
Sawetara opsi kalebu, nanging ora winates kanggo: kandhang jaringan tambahan ing jejer slot utawa pro lengkapfile, sinks panas meningkat, baffles, lan tambahan sirkuit.
Mangga kontak sales@alpha-data.com kanggo njaluk penawaran lan miwiti proyek sampeyan dina iki.
Deskripsi Fungsional
Swaraview
ADM-PCIE-9H3 minangka platform komputasi serbaguna sing bisa dikonfigurasi ulang kanthi Virtex UltraScale + VU33P/VU35P FPGA, antarmuka Gen3x16 PCIe, memori HBM 8GB, siji kandhang QSFP-DD, konektor Ultraport SlimSAS sing kompatibel karo OpenCAPI uga bisa 28G/channel. input terisolasi kanggo pulsa sinkronisasi wektu, header 12 pin kanggo tujuan umum (clocking, pin kontrol, debug, etc.), LED panel ngarep, lan monitor sistem kuat.
Ngalih
ADM-PCIE-9H3 wis octal DIP ngalih SW1, dumunung ing sisih mburi Papan. Fungsi saben switch ing SW1 rinci ing ngisor iki:
Tabel 3: Fungsi Ngalih
| Ngalih | Pabrik Default | Fungsi | Negara OFF | Negara ON |
| SW1-1 | OFF | Ngalih pangguna 0 | Pin AW33 = '1' | Pin BF52 = '0' |
| SW1-2 | OFF | Ngalih pangguna 1 | Pin AY36 = '1' | Pin BF47 = '0' |
| SW1-3 | OFF | dilindhungi | dilindhungi | dilindhungi |
| SW1-4 | OFF | Power Off | Papan bakal daya munggah | Langsung mudhun daya |
| SW1-5 | OFF | Mode Layanan | Operasi Biasa | Mode layanan nganyari firmware |
| SW1-6 | ON | HOST_I2 C_EN | Sysmon liwat PCIe I2C | Sysmon diisolasi |
| SW1-7 | ON | CAPI_VP D_EN | OpenCAPI VPD kasedhiya | OpenCAPI VPD diisolasi |
| SW1-8 | ON | CAPI_VP D_WP | CAPI VPD dilindhungi nulis | CAPI VPD bisa ditulis |
Gunakake IO Standard "LVCMOS18" nalika constraining pin ngalih pangguna.
LED
Ana 7 LED ing ADM-PCIE-9H3, 4 saka iku umum waé lan makna bisa ditetepake dening pangguna. 3 liyane duwe fungsi tetep sing diterangake ing ngisor iki:
Tabel 4: Rincian LED
| Comp. Ref. | Fungsi | Negara ON | Negara OFF |
| D1 | LED_G1 | Ditetepake pangguna '0' | Ditetepake pangguna '1' |
| D3 | LED_A1 | Ditetepake pangguna '0' | Ditetepake pangguna '1' |
| D4 | Rampung | FPGA wis diatur | FPGA ora diatur |
| D5 | Status 1 | Delengen Definisi LED Status | |
| D6 | Status 0 | Delengen Definisi LED Status | |
| D7 | LED_A0 | Ditetepake pangguna '0' | Ditetepake pangguna '1' |
| D9 | LED_G0 | Ditetepake pangguna '0' | Ditetepake pangguna '1' |
Waca Bagean Tabel Pinout Lengkap kanggo dhaptar lengkap jaring LED lan pin sing dikontrol pangguna
Jaman
ADM-PCIE-9H3 menehi solusi jam referensi fleksibel kanggo akeh quads transceiver multi-gigabit lan kain FPGA. Sembarang jam metu saka Si5338 Jam Synthesizer bisa maneh configurable saka salah siji panel ngarep USB Interface USB utawa Alpha Data sysmon FPGA port serial. Iki ngidini pangguna kanggo ngatur meh kabeh frekuensi jam sembarang sak wektu aplikasi mbukak. Frekuensi jam maksimal yaiku 312.5MHz.
Ana uga sing kasedhiya Si5328 jitter attenuator. Iki bisa nyedhiyakake jam sing resik lan sinkron menyang lokasi kotak QSFP-DD lan OpenCAPI (SlimSAS) ing akeh frekuensi jam. Piranti kasebut mung nggunakake memori sing molah malih, mula desain FPGA kudu ngatur maneh peta register sawise acara siklus daya.
Kabeh jeneng jam ing bagean ing ngisor iki bisa ditemokake ing Tabel Pinout Lengkap.
Si5328
Yen atenuasi jitter dibutuhake, deleng dokumentasi referensi kanggo Si5328.
https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5328.pdf
Sambungan sirkuit pangilon Xilinx VCU110 lan VCU108, deleng Xilinx Dev Boards kanggo referensi
Jam Referensi PCIe
16 jalur MGT sing disambungake menyang pinggiran kertu PCIe nggunakake kothak MGT 224 nganti 227 lan nggunakake sistem jam 100 MHz (jeneng net PCIE_REFCLK).
Utawa, jam 100MHz onboard sing resik uga kasedhiya (jeneng net PCIE_LCL_REFCLK).
Jam Kain
Desain nawakake jam kain (jeneng net FABRIC_SRC_CLK) kang standar kanggo 300 MHz. Jam iki dimaksudaké kanggo digunakake kanggo unsur IDELAY ing desain FPGA. Jam kain disambungake menyang pin Jam Global (GC).
DIFF_TERM_ADV = TERM_100 dibutuhake kanggo mandap LVDS
Jam Bantu
Desain nawakake jam tambahan (jeneng net AUX_CLK) kang standar kanggo 300 MHz. Jam iki bisa digunakake kanggo maksud apa wae lan disambungake menyang pin Jam Global (GC).
DIFF_TERM_ADV = TERM_100 dibutuhake kanggo mandap LVDS
Jam Pemrograman (EMCCLK)
A jam 100MHz (jeneng net EMCCLK_B) dipakani menyang pin EMCLK kanggo drive piranti lampu kilat SPI sak konfigurasi saka FPGA. Elinga yen iki dudu pin IO sing bisa jam global.
QSFP-DD
Kandhang QSFP-DD dumunung ing kothak MGT 126 lan 127 lan nggunakake jam referensi standar 161.1328125MHz.
Elinga yen frekuensi jam iki bisa diganti dadi frekuensi jam sembarang nganti 312MHz kanthi program maneh osilator jam Si5338 sing bisa diprogram liwat monitor sistem. Iki bisa ditindakake kanthi nggunakake Alpha Data API utawa liwat USB kanthi piranti Piranti Lunak Data Alpha sing cocog.
Deleng jeneng net QSFP_CLK * kanggo lokasi pin.
Kandhang QSFP-DD uga dumunung supaya bisa clocked saka Si5328 jitter attenuator jam multiplier.
Deleng jeneng net SI5328_OUT_1 * kanggo lokasi pin.
Ultraport SlimSAS (OpenCAPI)
Konektor Ultraport SlimSAS dumunung ing kothak MGT 124 lan 125.
Kanggo OpenCAPI jam eksternal 156.25MHz diwenehake liwat kabel. Deleng jeneng net CAPI_CLK_0 * kanggo lokasi pin jam kabel.
Sumber jam alternatif liyane kanggo antarmuka iki yaiku synthesizer jam Si5338 sing defaulted kanggo 161.1328125MHz. Deleng jeneng net CAPI_CLK_1* kanggo lokasi pin. Elinga yen frekuensi jam iki bisa diganti dadi frekuensi jam sembarang nganti 312MHz kanthi program maneh osilator jam Si5338 sing bisa diprogram liwat monitor sistem. Iki bisa ditindakake kanthi nggunakake Alpha Data API utawa liwat USB kanthi piranti Piranti Lunak Data Alpha sing cocog.
Kanggo aplikasi sensitif jitter, antarmuka iki bisa clocked saka attenuator jitter Si5328. Deleng jeneng net SI5328_OUT_0 * kanggo lokasi pin.
PCI Express
ADM-PCIE-9H3 saged PCIe Gen 1/2/3 karo 1/2/4/8/16 jalur. FPGA drive dalan iki langsung nggunakake pamblokiran Integrated PCI Express saka Xilinx. Negosiasi kacepetan link PCIe lan nomer dalan sing digunakake umume otomatis lan ora mbutuhake campur tangan pangguna.
PCI Express reset (PERST #) disambungake menyang FPGA ing rong lokasi. Waca sinyal Tabel Pinout Lengkap PERST0_1V8_L lan PERST1_1V8_L.
Tugas pin liyane kanggo jalur kacepetan dhuwur diwenehake ing pinout sing dipasang ing Tabel Pinout Lengkap
Spesifikasi PCI Express mbutuhake kabeh kertu tambahan siap kanggo enumerasi ing 120ms sawise daya bener (100ms sawise daya bener + 20ms sawise PERST dirilis). ADM-PCIE-9H3 nyukupi syarat iki nalika dikonfigurasi saka bitstream tandem kanthi watesan SPI sing tepat sing rinci ing bagean kasebut:
Konfigurasi Saka Memori Flash. Kanggo rincian liyane babagan konfigurasi tandem, waca Xilinx xapp 1179.
Cathetan:
Motherboard / backplane sing beda-beda bakal entuk manfaat saka skema ekualisasi RX sing beda ing inti PCIe IP sing diwenehake dening Xilinx. Alpha Data nyaranake nggunakake setelan ing ngisor iki yen pangguna ngalami kesalahan link utawa masalah latihan karo sistem: ing generator inti IP, ganti mode menyang "Lanjutan" lan bukak tab "GT Settings", ganti "form factor driven insertion loss". imbuhan" saka "Add-in Card" kanggo "Chip-to-Chip" (Waca Xilinx PG239 kanggo rincian liyane).
QSFP-DD
Siji kandhang QSFP-DD kasedhiya ing panel ngarep. Kandhang iki bisa ngemot kabel QSFP28 utawa QSFP-DD (kompatibel mundur). Loro-lorone model kompatibel QSFP-DD/QSFP28 tembaga aktif lan pasif sing kompatibel. Antarmuka komunikasi bisa mlaku nganti 28Gbps saben saluran. Ana 8 saluran ing kandhang QSFP-DD (total bandwidth maksimal 224Gbps). Kandhang iki saenipun cocog kanggo 8x 10G/25G, 2x 100G Ethernet, utawa protokol liyane sing didhukung dening Xilinx GTY Transceiver. Mangga deleng Xilinx User Guide UG578 kanggo rincian liyane babagan kapabilitas transceiver.
Kandhang QSFP-DD nduweni sinyal kontrol sing disambungake menyang FPGA. Konektivitas wis rinci ing Tabel Pinout Lengkap ing mburi document iki. Notasi sing digunakake ing tugas pin yaiku QSFP * kanthi lokasi sing dijlentrehake ing diagram ing ngisor iki.
Gunakake pin QSFP_SCL_1V8 lan QSFP_SDA_1V8 minangka rinci ing Tabel Pinout Lengkap kanggo komunikasi karo papan ndhaftar QSFP28.
Cathetan:
LP_MODE (Mode Daya Low) menyang kandhang disambungake menyang lemah, nggunakake antarmuka manajemen kanggo nyetel aturan daya.
Bisa kanggo Alpha Data wis pas karo ADM-PCIE-9H3 karo komponen QSFP-DD lan QSFP28. Tabel ing ngisor iki nuduhake nomer part kanggo transceiver dipasang nalika dhawuh karo Papan iki.
Tabel 5: Nomer Bagean QSFP28
| Kode Order | Katrangan | Nomer Part | Produsen |
| Q10 | 40G (4×10) QSFP Optical Transceiver | FTL410QE2C | Finisar |
| Q14 | 56G (4×14) QSFP Optical Transceiver | FTL414QB2C | Finisar |
| Q25 | 100G (4×25) QSFP28 Transceiver Optik | FTLC9558REPM | Finisar |
OpenCAPI Ultraport SlimSAS
Wadah Ultraport SlimSAS ing sisih mburi papan ngidini antarmuka sing cocog karo OpenCAPI sing mlaku ing 200G (8 saluran ing 25G). Hubungi support@alpha-data.com utawa wakil IBM kanggo rincian liyane babagan OpenCAPI lan keuntungane.
konektor SlimSAS uga bisa digunakake kanggo nyambungake Papan breakout 2x QSFP28 tambahan, kontak sales@alpha-data.com kanggo rincian liyane. Utawa, kabin kabel digunakake kanggo nyambungake sawetara kertu ADM-PCIE-9H3 ing sasis.
Sistem Monitor
ADM-PCIE-9H3 nduweni kemampuan kanggo ngawasi suhu, voltage, lan saiki sistem kanggo mriksa ing operasi saka Papan. Pemantauan ditindakake nggunakake mikrokontroler Atmel AVR.
Yen suhu inti FPGA ngluwihi 105 derajat Celsius, FPGA bakal dibusak kanggo nyegah karusakan ing kertu.
Algoritma kontrol ing mikrokontroler kanthi otomatis mriksa baris voltages lan ing Papan Suhu lan Enggo bareng ndadekake informasi kasedhiya kanggo FPGA liwat antarmuka serial darmabakti dibangun ing paket desain referensi Alpha Data (didol dhewe). Informasi kasebut uga bisa diakses langsung saka mikrokontroler liwat antarmuka USB ing panel ngarep utawa liwat antarmuka IPMI sing kasedhiya ing pinggiran kertu PCIe.
Tabel 6: Voltage, Monitor Saiki, lan Suhu
| Monitor | Indeks | Tujuan / Katrangan |
| DLL | DLL | Penghitung wektu sing wis suwe (detik) |
| EC | EC | Penghitung acara (siklus daya) |
| 12V | ADC00 | Pasokan input Papan |
| 12V_I | ADC01 | 12V input saiki ing amps |
| 3.3V | ADC02 | Pasokan input Papan |
| 3.3V_I | ADC03 | 3.3V input saiki ing amps |
| 3.3V | ADC05 | Papan input daya tambahan |
| 3.3V | ADC05 | 3.3V kanggo optik QSFP |
| 2.5V | ADC06 | Jam lan DRAM voltage pasokan |
| 1.8V | ADC07 | FPGA IO voltage (VCCO) |
| 1.8V | ADC08 | Daya transceiver (AVCC_AUX) |
| 1.2V | ADC09 | Daya HBM |
| 1.2V | ADC10 | Daya Transceiver (AVTT) |
| 0.9V | ADC11 | Daya Transceiver (AVCC) |
| 0.85-0.90V | ADC12 | BRAM + INT_IO (VccINT_IO) |
| 0.72-0.90V | ADC13 | Pasokan Inti FPGA (VccINT) |
| uC_Temp | TMP00 | Suhu on-die FPGA |
| Papan0_Temp | TMP01 | Suhu Papan cedhak panel ngarep |
| Papan1_Temp | TMP02 | Suhu Papan cedhak pojok ndhuwur mburi |
| FPGA_Temp | TMP03 | Suhu on-die FPGA |
Sistem Monitor Status LED
LED D5 (Abang) lan D6 (Ijo) nuduhake status kesehatan kertu.
Tabel 7: Definisi LED Status
| LED | Status |
| Ijo | Mlaku lan ora weker |
| Ijo + Abang | Siaga (Pateni) |
| Flashing Green + Flashing Red (bebarengan) | Manungsa waé - weker kritis aktif |
| Kelip-kelip Ijo + Kelip-kelip Abang (ganti-ganti) | Mode Layanan |
| Flashing Green + Red | Manungsa waé - weker aktif |
| abang | Firmware aplikasi ilang utawa perangkat kukuh ora valid |
| Kelip-kelip Abang | Konfigurasi FPGA dibusak kanggo nglindhungi papan |
Pengontrol Fan
Bus USB onboard sing dikontrol dening monitor sistem nduweni akses menyang pengontrol penggemar MAX6620. Piranti iki bisa dikontrol liwat macem-macem antarmuka komunikasi monitor sistem onboard, kalebu USB, PCIe Edge SMBUS, lan port komunikasi seral sysmon FPGA. Pengontrol penggemar ana ing bis I2C 1 ing alamat 0x2a. Kanggo pitakonan tambahan. Kontak support@alpha-data.com karo pitakonan tambahan ing nggenepi controller iki.
Antarmuka USB
FPGA bisa diatur langsung saka sambungan USB ing salah siji panel ngarep utawa pinggiran kertu mburi.
ADM-PCIE-9H3 nggunakake Digilent USB-JTAG kothak konverter sing didhukung dening piranti lunak Xilinx suite. Cukup sambungake kabel micro-USB AB ing antarane port USB ADM-PCIE-9H3 lan komputer host sing diinstal Vivado. Vivado Hardware Manager bakal kanthi otomatis ngenali FPGA lan ngidini sampeyan ngatur FPGA lan PROM konfigurasi SBPI.
Konektor USB sing padha digunakake kanggo ngakses langsung sistem monitor sistem. Kabeh voltages, arus, suhu, lan setelan konfigurasi jam non-molah malih bisa diakses nggunakake piranti lunak avr2util Alpha Data ing antarmuka iki.
Avr2util kanggo Windows lan driver USB sing gegandhengan bisa didownload ing kene:
https://support.alpha-data.com/pub/firmware/utilities/windows/
Avr2util kanggo Linux bisa didownload ing kene:
https://support.alpha-data.com/pub/firmware/utilities/linux/
Gunakake "avr2util.exe /?" kanggo ndeleng kabeh opsi.
Kanggo example "avr2util.exe / usbcom com4 display-sensors" bakal nampilake kabeh nilai sensor.
Kanggo example "avr2util.exe /usbcom com4 setclknv 1 156250000" bakal nyetel jam QSFP dadi 156.25MHz. indeks setclk 0 = CAPI_CLK_1, indeks 1 = QSFP_CLK, indeks 2 = AUX_CLK, indeks 3 = FABRIC_CLK.
Ganti 'com4' kanggo cocog karo nomer port com sing diwenehake ing manajer piranti windows
Konfigurasi
Ana rong cara utama kanggo ngatur FPGA ing ADM-PCIE-9H3:
- Saka memori Flash, ing daya-on, minangka diterangake ing bagean 3.8.1
- Nggunakake kabel USB disambungake ing salah siji port USB Section 3.8.2
Konfigurasi Saka Memori Flash
FPGA bisa kanthi otomatis diatur ing daya-on saka rong piranti memori lampu kilat 256 Mbit QSPI diatur minangka piranti x8 SPI (nomer part Micron MT25QU256ABA8E12-0). Piranti lampu kilat iki biasane dipérang dadi rong wilayah saben 32 MiByte, ing ngendi saben wilayah cukup gedhe kanggo nyekel bitstream sing ora dikompres kanggo VU33P FPGA.
ADM-PCIE-9H3 dikirim nganggo bitstream endpoint PCIe prasaja sing ngemot bitstream Alpha Data ADXDMA dhasar. Data Alpha bisa dimuat ing bitstream khusus liyane sajrone tes produksi, hubungi sales@alpha-data.com kanggo rincian liyane.
Sampeyan bisa nggunakake Multiboot karo gambar fallback ing hardware iki. Antarmuka konfigurasi master SPI lan Fallback MultiBoot dibahas kanthi rinci ing Xilinx UG570. Nalika power-on, FPGA nyoba ngatur dhewe kanthi otomatis ing mode master serial adhedhasar isi header ing programing. file. Multibook lan ICAP bisa digunakake kanggo milih antarane rong wilayah konfigurasi sing bakal dimuat menyang FPGA. Waca Xilinx UG570 MultiBoot kanggo rincian.
Gambar sing dimuat uga bisa ndhukung tandem PROM utawa tandem PCIE kanthi metode konfigurasi nganyari lapangan.
Opsi iki nyuda wektu mbukak daya kanggo mbantu nyukupi syarat wektu reset PCIe. Tandem karo lapangan uga mbisakake sistem inang kanggo ngatur maneh logika FPGA pangguna tanpa kelangan link PCIe, fitur migunani nalika sistem ngreset lan siklus daya ora pilihan.
Monitor Sistem Data Alpha uga bisa ngonfigurasi ulang memori lampu kilat lan reprograming FPGA.
Iki menehi mekanisme failsafe migunani kanggo program maneh FPGA sanajan irungnya mati bus PCIe. Monitor sistem bisa diakses liwat USB ing panel ngarep lan pinggir mburi, utawa liwat sambungan SMBUS ing pinggiran PCIe.
Gambar Konfigurasi Bangunan lan Pemrograman
Generate sethitikfile kanthi watesan kasebut (pirsani xapp1233):
- set_property BITSTREAM.GENERAL.COMPRESS TRUE [desain_kini]
- set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [desain_saiki]
- set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [desain_saiki]
- set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [desain_saiki]
- set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [desain_saiki]
- set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
- set_property CFGBVS GND [desain_kini]
- set_property CONFIG_VOLTAGE 1.8 [desain_saiki]
- set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Aktifake [current_design]
Nggawe MCS file kanthi properti kasebut (write_cfgmem):
- - format MCS
- - Ukuran 64
- - antarmuka SPIx8
- -loadbit "munggah 0x0000000file/filename.bit>” (lokasi 0)
- -loadbit "munggah 0x2000000file/filename.bit>” (lokasi 1, opsional)
Program karo manajer hardware vivado kanthi setelan iki (pirsani xapp1233):
- SPI part: mt25qu256-spi-x1_x2_x4_x8
- Negara non-config mem I / O pin: Narik-ora ana
- Target papat files kui saka printah write_cfgmem tcl.
Konfigurasi liwat JTAG
Kabel AB mikro-USB bisa uga dipasang ing panel ngarep utawa port USB pinggir mburi. Iki ngidini FPGA dikonfigurasi ulang nggunakake Manajer Perangkat Keras Xilinx Vivado liwat Digilent J sing terintegrasi.TAG kothak konverter. Piranti bakal kanthi otomatis dikenali ing Vivado Hardware Manager.
Kanggo instruksi sing luwih rinci, deleng bagean "Nggunakake Manajer Perangkat Keras Vivado kanggo Program Piranti FPGA" saka Xilinx UG908: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf
Konektor GPIO
Pilihan GPIO kasusun saka konektor shrouded Versatile saka Molex karo nomer part 87832-1222 sing menehi pangguna karo syarat IO adat papat langsung nyambung menyang sinyal FPGA.
Plug kawin sing disaranake: Molex 0875681273 utawa 0511101260
Langsung Sambungake Sinyal FPGA
8 jaring dipecah menyang header GPIO, minangka papat set pasangan diferensial. Sinyal iki cocog kanggo standar sinyal sing didhukung 1.8V sing didhukung dening arsitektur Xilinx UltraScale. Waca Xilinx UG571 kanggo opsi IO.
LVDS lan 1.8 CMOS minangka pilihan populer. Indeks sinyal GPIO 0 cocok kanggo sambungan jam global.
Sinyal GPIO sambungan langsung diwatesi nganti 1.8V kanthi quickswitch (74CBTLVD3245PW) kanggo nglindhungi FPGA saka overvoltage ing pin IO. Quickswitch iki ngidini sinyal kanggo lelungan ing salah siji arah karo mung 4 ohm impedansi seri lan kurang saka 1ns wektu tundha propagasi. Jaring langsung disambungake menyang FPGA sawise quickswitch.
Jeneng sinyal nyambung langsung diwenehi label GPIO_0_1V8_P / N lan GPIO_1_1V8_P / N, etc kanggo nuduhake polaritas lan klompok. Alokasi pin sinyal bisa ditemokake ing Tabel Pinout Lengkap
Wektu Input
J1.1 lan J1.2 bisa digunakake minangka sinyal input wektu terisolasi (nganti 25MHz). Aplikasi bisa langsung nyambung menyang konektor GPIO, utawa Alpha Data bisa nyedhiyani solusi kabel karo SMA utawa konektor padha ing panel ngarep. Hubungi sales@alpha-data.com kanggo pilihan konektor panel ngarep.
Kanggo lokasi pin, deleng jeneng sinyal ISO_CLK ing Tabel Pinout Lengkap.
Sinyal kasebut diisolasi liwat nomer bagean isolator optik TLP2367 kanthi resistensi seri 220 ohm.
Panganggo EEPROM
EEPROM pangguna 2Kb I2C kasedhiya kanggo nyimpen alamat MAC utawa informasi pangguna liyane. EEPROM minangka nomer bagean CAT34C02HU4IGT4A
Pin alamat A2, A1, lan A0 kabeh diikat menyang '0' sing logis.
Tulis nglindhungi (WP), Jam Serial (SCL), lan Data Serial (SDA) tugas pin bisa ditemokaké ing Tabel Pinout Lengkap karo jeneng SPARE_WP, SPARE_SCL, lan SPARE_SDA mungguh.
Sinyal WP, SDA, lan SCL kabeh duwe resistor pull-up eksternal ing kertu.
Lampiran A: Tabel Pinout Lengkap
Tabel 8: Tabel Pinout Lengkap (terus ing kaca sabanjure)
| Nomer Pin | Jeneng Sinyal | Jeneng Pin | Bank Voltage |
| BC18 | AUX_CLK_PIN_N | IO_L11N_T1U_N9_GC_64 | 1.8 (LVCMOS18) |
| BB18 | AUX_CLK_PIN_P | IO_L11P_T1U_N8_GC_64 | 1.8 (LVCMOS18) |
| BF33 | AVR_B2U_1V8 | IO_L2P_T0L_N2_66 | 1.8 (LVCMOS18) |
| BF31 | AVR_HS_B2U_1V8 | IO_L1P_T0L_N0_DBC_66 | 1.8 (LVCMOS18) |
| BB33 | AVR_HS_CLK_1V8 | IO_L12N_T1U_N11_GC_66 | 1.8 (LVCMOS18) |
| BF32 | AVR_HS_U2B_1V8 | IO_L1N_T0L_N1_DBC_66 | 1.8 (LVCMOS18) |
| BA33 | AVR_MON_CLK_1V8 | IO_L12P_T1U_N10_GC_66 | 1.8 (LVCMOS18) |
| BF34 | AVR_U2B_1V8 | IO_L2N_T0L_N3_66 | 1.8 (LVCMOS18) |
| AK39 | CAPI_CLK_0_PIN_N | MGTREFCLK0N_124 | MGT REFCLK |
| AK38 | CAPI_CLK_0_PIN_P | MGTREFCLK0P_124 | MGT REFCLK |
| AF39 | CAPI_CLK_1_PIN_N | MGTREFCLK0N_125 | MGT REFCLK |
| AF38 | CAPI_CLK_1_PIN_P | MGTREFCLK0P_125 | MGT REFCLK |
| BF17 | CAPI_I2C_SCL_1V8 | IO_L1P_T0L_N0_DBC_64 | 1.8 (LVCMOS18) |
| BF16 | CAPI_I2C_SDA_1V8 | IO_L1N_T0L_N1_DBC_64 | 1.8 (LVCMOS18) |
| BF19 | CAPI_INT/RESET_1V8 | IO_L2P_T0L_N2_64 | 1.8 (LVCMOS18) |
| BF43 | CAPI_RX0_N | MGTYRXN0_124 | MGT |
| BF42 | CAPI_RX0_P | MGTYRXP0_124 | MGT |
| BD44 | CAPI_RX1_N | MGTYRXN1_124 | MGT |
| BD43 | CAPI_RX1_P | MGTYRXP1_124 | MGT |
| BB44 | CAPI_RX2_N | MGTYRXN2_124 | MGT |
| BB43 | CAPI_RX2_P | MGTYRXP2_124 | MGT |
| AY44 | CAPI_RX3_N | MGTYRXN3_124 | MGT |
| AY43 | CAPI_RX3_P | MGTYRXP3_124 | MGT |
| BC46 | CAPI_RX4_N | MGTYRXN0_125 | MGT |
| BC45 | CAPI_RX4_P | MGTYRXP0_125 | MGT |
| BA46 | CAPI_RX5_N | MGTYRXN1_125 | MGT |
| BA45 | CAPI_RX5_P | MGTYRXP1_125 | MGT |
| AW46 | CAPI_RX6_N | MGTYRXN2_125 | MGT |
| AW45 | CAPI_RX6_P | MGTYRXP2_125 | MGT |
| AV44 | CAPI_RX7_N | MGTYRXN3_125 | MGT |
| AV43 | CAPI_RX7_P | MGTYRXP3_125 | MGT |
| AT39 | CAPI_TX0_N | MGTYTXN0_124 | MGT |
| AT38 | CAPI_TX0_P | MGTYTXP0_124 | MGT |
| Nomer Pin | Jeneng Sinyal | Jeneng Pin | Bank Voltage |
| AR41 | CAPI_TX1_N | MGTYTXN1_124 | MGT |
| AR40 | CAPI_TX1_P | MGTYTXP1_124 | MGT |
| AP39 | CAPI_TX2_N | MGTYTXN2_124 | MGT |
| AP38 | CAPI_TX2_P | MGTYTXP2_124 | MGT |
| AN41 | CAPI_TX3_N | MGTYTXN3_124 | MGT |
| AN40 | CAPI_TX3_P | MGTYTXP3_124 | MGT |
| AM39 | CAPI_TX4_N | MGTYTXN0_125 | MGT |
| AM38 | CAPI_TX4_P | MGTYTXP0_125 | MGT |
| AL41 | CAPI_TX5_N | MGTYTXN1_125 | MGT |
| AL40 | CAPI_TX5_P | MGTYTXP1_125 | MGT |
| AJ41 | CAPI_TX6_N | MGTYTXN2_125 | MGT |
| AJ40 | CAPI_TX6_P | MGTYTXP2_125 | MGT |
| AG41 | CAPI_TX7_N | MGTYTXN3_125 | MGT |
| AG40 | CAPI_TX7_P | MGTYTXP3_125 | MGT |
| AV26 | EMCCLK_B | IO_L24P_T3U_N10_EMCCLK_65 | 1.8 (LVCMOS18) |
| BA31 | FABRIC_CLK_PIN_N | IO_L13N_T2L_N1_GC_QBC_66 | 1.8 (LVDS karo DIFF_TERM_ADV) |
| AY31 | FABRIC_CLK_PIN_P | IO_L13P_T2L_N0_GC_QBC_66 | 1.8 (LVDS karo DIFF_TERM_ADV) |
| BA8 | FPGA_FLASH_CE0_L | RDWR_FCS_B_0 | 1.8 (LVCMOS18) |
| AW24 | FPGA_FLASH_CE1_L | IO_L2N_T0L_N3_FWE_FCS2_B_65 | 1.8 (LVCMOS18) |
| AW7 | FPGA_FLASH_DQ0 | D00_MOSI_0 | 1.8 (LVCMOS18) |
| AV7 | FPGA_FLASH_DQ1 | D01_DIN_0 | 1.8 (LVCMOS18) |
| AW8 | FPGA_FLASH_DQ2 | D02_0 | 1.8 (LVCMOS18) |
| AV8 | FPGA_FLASH_DQ3 | D03_0 | 1.8 (LVCMOS18) |
| AV28 | FPGA_FLASH_DQ4 | IO_L22P_T3U_N6_DBC_AD0P
_D04_65 |
1.8 (LVCMOS18) |
| AW28 | FPGA_FLASH_DQ5 | IO_L22N_T3U_N7_DBC_AD0N
_D05_65 |
1.8 (LVCMOS18) |
| BB28 | FPGA_FLASH_DQ6 | IO_L21P_T3L_N4_AD8P_D06_65 | 1.8 (LVCMOS18) |
| BC28 | FPGA_FLASH_DQ7 | IO_L21N_T3L_N5_AD8N_D07_65 | 1.8 (LVCMOS18) |
| BA19 | GPIO_0_1V8_N | IO_L13N_T2L_N1_GC_QBC_64 | 1.8 (LVCMOS18 utawa LVDS) |
| AY19 | GPIO_0_1V8_P | IO_L13P_T2L_N0_GC_QBC_64 | 1.8 (LVCMOS18 utawa LVDS) |
| AY20 | GPIO_1_1V8_N | IO_L15N_T2L_N5_AD11N_64 | 1.8 (LVCMOS18 utawa LVDS) |
| AY21 | GPIO_1_1V8_P | IO_L15P_T2L_N4_AD11P_64 | 1.8 (LVCMOS18 utawa LVDS) |
| AW20 | GPIO_2_1V8_N | IO_L16N_T2U_N7_QBC_AD3N_64 | 1.8 (LVCMOS18 utawa LVDS) |
| Nomer Pin | Jeneng Sinyal | Jeneng Pin | Bank Voltage |
| AV20 | GPIO_2_1V8_P | IO_L16P_T2U_N6_QBC_AD3P_64 | 1.8 (LVCMOS18 utawa LVDS) |
| AW18 | GPIO_3_1V8_N | IO_L17N_T2U_N9_AD10N_64 | 1.8 (LVCMOS18 utawa LVDS) |
| AW19 | GPIO_3_1V8_P | IO_L17P_T2U_N8_AD10P_64 | 1.8 (LVCMOS18 utawa LVDS) |
| BA27 | IBM_PERST_1V8_L | IO_L20P_T3L_N2_AD1P_D08_65 | 1.8 (LVCMOS18) |
| BA18 | ISO_CLK_1V8 | IO_L14P_T2L_N2_GC_64 | 1.8 (LVCMOS18) |
| AD8 | PCIE_LCL_REFCLK_PIN_N | MGTREFCLK0N_226 | MGT REFCLK |
| AD9 | PCIE_LCL_REFCLK_PIN_P | MGTREFCLK0P_226 | MGT REFCLK |
| AF8 | PCIE_REFCLK_1_PIN_N | MGTREFCLK0N_225 | MGT REFCLK |
| AF9 | PCIE_REFCLK_1_PIN_P | MGTREFCLK0P_225 | MGT REFCLK |
| AB8 | PCIE_REFCLK_2_PIN_N | MGTREFCLK0N_227 | MGT REFCLK |
| AB9 | PCIE_REFCLK_2_PIN_P | MGTREFCLK0P_227 | MGT REFCLK |
| AL1 | PCIE_RX0_N | MGTYRXN3_227 | MGT |
| AL2 | PCIE_RX0_P | MGTYRXP3_227 | MGT |
| AM3 | PCIE_RX1_N | MGTYRXN2_227 | MGT |
| AM4 | PCIE_RX1_P | MGTYRXP2_227 | MGT |
| BA1 | PCIE_RX10_N | MGTYRXN1_225 | MGT |
| BA2 | PCIE_RX10_P | MGTYRXP1_225 | MGT |
| BC1 | PCIE_RX11_N | MGTYRXN0_225 | MGT |
| BC2 | PCIE_RX11_P | MGTYRXP0_225 | MGT |
| AY3 | PCIE_RX12_N | MGTYRXN3_224 | MGT |
| AY4 | PCIE_RX12_P | MGTYRXP3_224 | MGT |
| BB3 | PCIE_RX13_N | MGTYRXN2_224 | MGT |
| BB4 | PCIE_RX13_P | MGTYRXP2_224 | MGT |
| BD3 | PCIE_RX14_N | MGTYRXN1_224 | MGT |
| BD4 | PCIE_RX14_P | MGTYRXP1_224 | MGT |
| BE5 | PCIE_RX15_N | MGTYRXN0_224 | MGT |
| BE6 | PCIE_RX15_P | MGTYRXP0_224 | MGT |
| AK3 | PCIE_RX2_N | MGTYRXN1_227 | MGT |
| AK4 | PCIE_RX2_P | MGTYRXP1_227 | MGT |
| AN1 | PCIE_RX3_N | MGTYRXN0_227 | MGT |
| AN2 | PCIE_RX3_P | MGTYRXP0_227 | MGT |
| AP3 | PCIE_RX4_N | MGTYRXN3_226 | MGT |
| AP4 | PCIE_RX4_P | MGTYRXP3_226 | MGT |
| AR1 | PCIE_RX5_N | MGTYRXN2_226 | MGT |
| AR2 | PCIE_RX5_P | MGTYRXP2_226 | MGT |
| Nomer Pin | Jeneng Sinyal | Jeneng Pin | Bank Voltage |
| AT3 | PCIE_RX6_N | MGTYRXN1_226 | MGT |
| AT4 | PCIE_RX6_P | MGTYRXP1_226 | MGT |
| AU1 | PCIE_RX7_N | MGTYRXN0_226 | MGT |
| AU2 | PCIE_RX7_P | MGTYRXP0_226 | MGT |
| AV3 | PCIE_RX8_N | MGTYRXN3_225 | MGT |
| AV4 | PCIE_RX8_P | MGTYRXP3_225 | MGT |
| AW1 | PCIE_RX9_N | MGTYRXN2_225 | MGT |
| AW2 | PCIE_RX9_P | MGTYRXP2_225 | MGT |
| Y4 | PCIE_TX0_PIN_N | MGTYTXN3_227 | MGT |
| Y5 | PCIE_TX0_PIN_P | MGTYTXP3_227 | MGT |
| AA6 | PCIE_TX1_PIN_N | MGTYTXN2_227 | MGT |
| AA7 | PCIE_TX1_PIN_P | MGTYTXP2_227 | MGT |
| AL6 | PCIE_TX10_PIN_N | MGTYTXN1_225 | MGT |
| AL7 | PCIE_TX10_PIN_P | MGTYTXP1_225 | MGT |
| AM8 | PCIE_TX11_PIN_N | MGTYTXN0_225 | MGT |
| AM9 | PCIE_TX11_PIN_P | MGTYTXP0_225 | MGT |
| AN6 | PCIE_TX12_PIN_N | MGTYTXN3_224 | MGT |
| AN7 | PCIE_TX12_PIN_P | MGTYTXP3_224 | MGT |
| AP8 | PCIE_TX13_PIN_N | MGTYTXN2_224 | MGT |
| AP9 | PCIE_TX13_PIN_P | MGTYTXP2_224 | MGT |
| AR6 | PCIE_TX14_PIN_N | MGTYTXN1_224 | MGT |
| AR7 | PCIE_TX14_PIN_P | MGTYTXP1_224 | MGT |
| AT8 | PCIE_TX15_PIN_N | MGTYTXN0_224 | MGT |
| AT9 | PCIE_TX15_PIN_P | MGTYTXP0_224 | MGT |
| AB4 | PCIE_TX2_PIN_N | MGTYTXN1_227 | MGT |
| AB5 | PCIE_TX2_PIN_P | MGTYTXP1_227 | MGT |
| AC6 | PCIE_TX3_PIN_N | MGTYTXN0_227 | MGT |
| AC7 | PCIE_TX3_PIN_P | MGTYTXP0_227 | MGT |
| AD4 | PCIE_TX4_PIN_N | MGTYTXN3_226 | MGT |
| AD5 | PCIE_TX4_PIN_P | MGTYTXP3_226 | MGT |
| AF4 | PCIE_TX5_PIN_N | MGTYTXN2_226 | MGT |
| AF5 | PCIE_TX5_PIN_P | MGTYTXP2_226 | MGT |
| AE6 | PCIE_TX6_PIN_N | MGTYTXN1_226 | MGT |
| AE7 | PCIE_TX6_PIN_P | MGTYTXP1_226 | MGT |
| AH4 | PCIE_TX7_PIN_N | MGTYTXN0_226 | MGT |
| Nomer Pin | Jeneng Sinyal | Jeneng Pin | Bank Voltage |
| AH5 | PCIE_TX7_PIN_P | MGTYTXP0_226 | MGT |
| AG6 | PCIE_TX8_PIN_N | MGTYTXN3_225 | MGT |
| AG7 | PCIE_TX8_PIN_P | MGTYTXP3_225 | MGT |
| AJ6 | PCIE_TX9_PIN_N | MGTYTXN2_225 | MGT |
| AJ7 | PCIE_TX9_PIN_P | MGTYTXP2_225 | MGT |
| AW27 | PERST0_1V8_L | IO_T3U_N12_PERSTN0_65 | 1.8 (LVCMOS18) |
| AY27 | PERST1_1V8_L | IO_L23N_T3U_N9_PERSTN1_I 2C_SDA_65 | 1.8 (LVCMOS18) |
| AD39 | QSFP_CLK_PIN_N | MGTREFCLK0N_126 | MGT REFCLK |
| AD38 | QSFP_CLK_PIN_P | MGTREFCLK0P_126 | MGT REFCLK |
| AV16 | QSFP_INT_1V8_L | IO_L24P_T3U_N10_64 | 1.8 (LVCMOS18) |
| BA14 | QSFP_MODPRS_L | IO_L22N_T3U_N7_DBC_AD0N_64 | 1.8 (LVCMOS18) |
| AV15 | QSFP_RST_1V8_L | IO_L24N_T3U_N11_64 | 1.8 (LVCMOS18) |
| AU46 | QSFP_RX0_N | MGTYRXN0_126 | MGT |
| AU45 | QSFP_RX0_P | MGTYRXP0_126 | MGT |
| AT44 | QSFP_RX1_N | MGTYRXN1_126 | MGT |
| AT43 | QSFP_RX1_P | MGTYRXP1_126 | MGT |
| AR46 | QSFP_RX2_N | MGTYRXN2_126 | MGT |
| AR45 | QSFP_RX2_P | MGTYRXP2_126 | MGT |
| AP44 | QSFP_RX3_N | MGTYRXN3_126 | MGT |
| AP43 | QSFP_RX3_P | MGTYRXP3_126 | MGT |
| AN46 | QSFP_RX4_N | MGTYRXN0_127 | MGT |
| AN45 | QSFP_RX4_P | MGTYRXP0_127 | MGT |
| AK44 | QSFP_RX5_N | MGTYRXN1_127 | MGT |
| AK43 | QSFP_RX5_P | MGTYRXP1_127 | MGT |
| AM44 | QSFP_RX6_N | MGTYRXN2_127 | MGT |
| AM43 | QSFP_RX6_P | MGTYRXP2_127 | MGT |
| AL46 | QSFP_RX7_N | MGTYRXN3_127 | MGT |
| AL45 | QSFP_RX7_P | MGTYRXP3_127 | MGT |
| AW15 | QSFP_SCL_1V8 | IO_L23P_T3U_N8_64 | 1.8 (LVCMOS18) |
| AW14 | QSFP_SDA_1V8 | IO_L23N_T3U_N9_64 | 1.8 (LVCMOS18) |
| AH43 | QSFP_TX0_N | MGTYTXN0_126 | MGT |
| AH42 | QSFP_TX0_P | MGTYTXP0_126 | MGT |
| AE41 | QSFP_TX1_N | MGTYTXN1_126 | MGT |
| AE40 | QSFP_TX1_P | MGTYTXP1_126 | MGT |
| AF43 | QSFP_TX2_N | MGTYTXN2_126 | MGT |
| Nomer Pin | Jeneng Sinyal | Jeneng Pin | Bank Voltage |
| AF42 | QSFP_TX2_P | MGTYTXP2_126 | MGT |
| AD43 | QSFP_TX3_N | MGTYTXN3_126 | MGT |
| AD42 | QSFP_TX3_P | MGTYTXP3_126 | MGT |
| AC41 | QSFP_TX4_N | MGTYTXN0_127 | MGT |
| AC40 | QSFP_TX4_P | MGTYTXP0_127 | MGT |
| AB43 | QSFP_TX5_N | MGTYTXN1_127 | MGT |
| AB42 | QSFP_TX5_P | MGTYTXP1_127 | MGT |
| AA41 | QSFP_TX6_N | MGTYTXN2_127 | MGT |
| AA40 | QSFP_TX6_P | MGTYTXP2_127 | MGT |
| Y43 | QSFP_TX7_N | MGTYTXN3_127 | MGT |
| Y42 | QSFP_TX7_P | MGTYTXP3_127 | MGT |
| AV36 | SI5328_1V8_SCL | IO_L24N_T3U_N11_66 | 1.8 (LVCMOS18) |
| AV35 | SI5328_1V8_SDA | IO_L24P_T3U_N10_66 | 1.8 (LVCMOS18) |
| AE37 | SI5328_OUT_0_PIN_N | MGTREFCLK1N_125 | MGT REFCLK |
| AE36 | SI5328_OUT_0_PIN_P | MGTREFCLK1P_125 | MGT REFCLK |
| AB39 | SI5328_OUT_1_PIN_N | MGTREFCLK0N_127 | MGT REFCLK |
| AB38 | SI5328_OUT_1_PIN_P | MGTREFCLK0P_127 | MGT REFCLK |
| BB19 | SI5328_REFCLK_IN_N | IO_L12N_T1U_N11_GC_64 | 1.8 (LVDS) |
| BB20 | SI5328_REFCLK_IN_P | IO_L12P_T1U_N10_GC_64 | 1.8 (LVDS) |
| AV33 | SI5328_RST_1V8_L | IO_L22P_T3U_N6_DBC_AD0P_66 | 1.8 (LVCMOS18) |
| BE30 | SPARE_SCL | IO_L5N_T0U_N9_AD14N_66 | 1.8 (LVCMOS18) |
| BC30 | SPARE_SDA | IO_L6P_T0U_N10_AD6P_66 | 1.8 (LVCMOS18) |
| BD30 | SPARE_WP | IO_L6N_T0U_N11_AD6N_66 | 1.8 (LVCMOS18) |
| BE31 | SRVC_MD_L_1V8 | IO_L3P_T0L_N4_AD15P_66 | 1.8 (LVCMOS18) |
| AV32 | USER_LED_A0_1V8 | IO_L18N_T2U_N11_AD2N_66 | 1.8 (LVCMOS18) |
| AW32 | USER_LED_A1_1V8 | IO_T2U_N12_66 | 1.8 (LVCMOS18) |
| AY30 | USER_LED_G0_1V8 | IO_L17N_T2U_N9_AD10N_66 | 1.8 (LVCMOS18) |
| AV31 | USER_LED_G1_1V8 | IO_L18P_T2U_N10_AD2P_66 | 1.8 (LVCMOS18) |
| AW33 | USR_SW_0 | IO_L22N_T3U_N7_DBC_AD0N_66 | 1.8 (LVCMOS18) |
| AY36 | USR_SW_1 | IO_L23P_T3U_N8_66 | 1.8 (LVCMOS18) |
Riwayat Revisi
| Tanggal | Revisi | Diganti dening | Sifat Ewah-ewahan |
| 24 Sep 2018 | 1.0 | K. Roth | Rilis dhisikan |
|
31 Oktober 2018 |
1.1 |
K. Roth |
Dianyari gambar produk, diganti standar frekuensi jam programable kanggo CAPI_CLK_1 kanggo 161MHz |
|
14 Dhésèmber 2018 |
1.2 |
K. Roth |
Nomer bagean lampu kilat konfigurasi sing dianyari, diganti tembung katrangan gpio kanggo akurasi, nambah bobot. |
|
24 Oktober 2019 |
1.3 |
K. Roth |
Dianyari Konfigurasi kanggo mbusak map alamat lan gambaran bener saka kapasitas part memori. |
|
25 Januari 2022 |
1.4 |
K. Roth |
Dianyari Thermal Kinerja kanggo kalebu tokoh efisiensi termal lan komentar babagan impact saka kain kafan, mbusak referensi kanggo QSFP0 lan QSFP1 saka bagean QSFP-DD lan dianyari 25Gb nomer part transceiver. |
Layanan Pelanggan
© 2022 Hak Cipta Alpha Data Parallel Systems Ltd.
Kabeh hak dilindhungi undhang-undhang.
Publikasi iki dilindhungi dening Hukum Hak Cipta, kanthi kabeh hak dilindhungi undhang-undhang. Ora ana bagean saka publikasi iki bisa diprodhuksi, ing wangun utawa wangun, tanpa idin sadurunge ditulis saka Alpha Data Parallel Systems Ltd.
Kantor Pusat
Alamat: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telpon: +44 131 558 2600
Fax: +44 131 558 2700
email: sales@alpha-data.com
websitus: http://www.alpha-data.com
Kantor AS
Alamat: 10822 West Toller Drive, Suite 250
Littleton, CO 80127
No. Telpon : (303) 954
Fax: (866) 820 9956 – bebas pulsa
email: sales@alpha-data.com
websitus: http://www.alpha-data.com
Kabeh merek dagang minangka properti saka sing nduweni.
Alamat: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telpon: +44 131 558 2600
Fax: +44 131 558 2700
email: sales@alpha-data.com
websitus: http://www.alpha-data.com
Alamat: 10822 West Toller Drive, Suite 250
Littleton, CO 80127
No. Telpon : (303) 954
Fax: (866) 820 9956 – bebas pulsa
email: sales@alpha-data.com
websitus: http://www.alpha-data.com
Dokumen / Sumber Daya
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ALPHA DATA ADM-PCIE-9H3 High Performance FPGA Processing Card [pdf] Manual pangguna ADM-PCIE-9H3 Kartu Pangolahan FPGA Kinerja Tinggi, ADM-PCIE-9H3, Kartu Pangolahan FPGA Kinerja Tinggi, Kartu Pangolahan FPGA, Kartu Pangolahan |
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ALPHA DATA ADM-PCIE-9H3 High Performance FPGA Processing Card [pdf] Manual pangguna ADM-PCIE-9H3 Kertu Pangolahan FPGA Kinerja Tinggi, ADM-PCIE-9H3, Kartu Pangolahan FPGA Kinerja Tinggi, Kartu Pangolahan FPGA Kinerja, Kartu Pangolahan FPGA, Kartu Pangolahan |
