ALPHA DATA ADM-PCIE-9H3 High Performance FPGA Processing Card
ALPHA DATA ADM-PCIE-9H3 High Performance FPGA Processing Card

Introduction

The ADM-PCIE-9H3 is a high-performance reconfigurable computing card intended for Data Center applications, featuring a Xilinx Virtex UltraScale+ Plus FPGA with High Bandwidth Memory (HBM).
Introduction

Key Features

  • PCIe Gen1/2/3 x1/2/4/8/16 capable
  • Passive and active thermal management configuration
  • 1/2 length, low profile, x16 edge PCIe form factor
  • 8GB HBM on-die memory capable of 460GB/s
  • One QSFP-DD cage capable of data rates up to 28 Gbps per 8 channels (224 Gbps)
  • One 8 lane Ultraport SlimSAS connectors compliant with OpenCAPI and suitable for IO expansion
  • Supports either VU33P or VU35P Virtex UltraScale+ FPGAs
  • Front panel and rear edge JTAG access via USB port
  • FPGA configurable over USB/JTAG and SPI configuration flash
  • Voltage, current, and temperature monitoring
  • 8 GPIO signals and 1 isolated timing input

Order Code
ADM-PCIE-9H3
ADM-PCIE-9H3/NF (without optional fan)
See http://www.alpha-data.com/pdfs/adm-pcie-9h3.pdf for complete ordering options.

Board Information

Physical Specifications
The ADM-PCIE-9H3 complies with PCI Express CEM revision 3.0.
Table 1 : Mechanical Dimensions (Inc. Front Panel)

DescriptionMeasure
Total Dy80.1 mm
Total Dx181.5 mm
Total Dz19.7 mm
Weight350 grams

Physical Specifications

Chassis Requirements

PCI Express
The ADM-PCIE-9H3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes, using the Xilinx Integrated Block for PCI Express.

Mechanical Requirements
A 16-lane physical PCIe slot is required for mechanical compatibility.

Power Requirements
The ADM-PCIE-9H3 draws all power from the PCIe Edge. As per PCIe specification, this limits the power consumption of the card to a maximum 75W.
Power consumption estimation requires the use of the Xilinx XPE spreadsheet and a power estimator tool available from Alpha Data. Please contact support@alpha-data.com to obtain this tool.
The power available to the rails calculated using XPE are as follows:

Table 2 : Available Power By Rail

VoltageSource NameCurrent Capability
0.72-0.90VCC_INT + VCCINT_IO + VCC_BRAM42A
0.9MGTAVCC5A
1.2MGTAVTT9A
1.2VCC_HBM * VCC_IO_HBM14A
1.8VCCAUX + VCCAUX_IO + VCCO_1.8V1.5A
1.8MGTVCCAUX0.5A
2.5VCCAUX_HBM2.2A
3.33.3V for Optics3.6A

Thermal Performance
If the FPGA core temperature exceeds 105 degrees Celsius, the FPGA design will be cleared to prevent the card from over-heating.
The ADM-PCIE-9H3 comes with a heat sink to reduce the temperature of the FPGA, which is typically the hottest point on the card. The FPGA die temperature must remain under 100 degrees Celsius. To calculate the FPGA die temperature, take your application power, multiply by Theta JA from the table below, and add to your system internal ambient temperature. The graph below shows two lines, one was tested in a duct with the shrouds installed, and the other was tested without the shrouds. The performance is generally better without the shrouds, but they do provide improved handling and reduce air re-circulation in compact servers. The shroud can be removed using a 1/16″ hex driver. If you are using the fan provided with the board, you will find theta JA is approximately 1.43 degC/W for the board in still air with or without the shroud installed.
The power dissipation can be estimated by using the Alpha Data power estimator in conjunction with the Xilinx Power Estimator (XPE) downloadable at http://www.xilinx.com/products/technology/power/xpe.html. Download
the UltraScale tool and set the device to Virtex UltraScale+, VU33P, FSVH2104, -2, -2L, or -3, extended. Set the ambient temperature to your system ambient and select ‘user override’ for the effective theta JA and enter the figure associated with your system LFM in the blank field. Proceed to enter all applicable design elements and utilization in the following spreadsheet tabs. Next aquire the 9H3 power estimator from Alpha Data by contacting
support@alpha-data.com. You will then plug in the FPGA power figures along with Optical module figures to get a board level estimate.
Thermal Performance

Active VS Passive Thermal Management
The ADM-PCIE-9H3 ships with a small optional blower for active cooling in systems with poor airflow. If the ADM-PCIE-9H3 will be installed in a server with controlled airflow, the order option /NF can be used to receive cards without this extra piece. The fans have a much shorter mean time between failure (MTBF) than the rest of the assembly, so passive cards have much longer life expectance before requiring maintenance. The ADM-PCIE-9H3 also includes a fan speed controller, allowing variable fan speed based on die temperature, and
detection of a failed fan (see section Fan Controllers).
Active VS Passive Thermal Management

Customizations
Alpha Data provides extensive customization options to existing commercial off-the-shelf (COTS) products.
Some options include, but are not limited to: additional networking cages in adjacent slots or full profile, enhanced heat sinks, baffles, and circuit additions.
Please contact sales@alpha-data.com to get a quote and start your project today.
Customizations

Functional Description

Overview
The ADM-PCIE-9H3 is a versatile reconfigurable computing platform with a Virtex UltraScale+ VU33P/VU35P FPGA, a Gen3x16 PCIe interface, 8GB of HBM memory, one QSFP-DD cage, an OpenCAPI compatible Ultraport SlimSAS connector also capable of 28G/channel, an isolated input for a timing synchronization pulse, a 12 pin header for general purpose use (clocking, control pins, debug, etc.), front panel LEDs, and a robust system monitor.
Overview

Switches
The ADM-PCIE-9H3 has an octal DIP switch SW1, located on the rear side of the board. The function of each switch in SW1 is detailed below:
Switches
Table 3 : Switch Functions

SwitchFactory DefaultFunctionOFF StateON State
SW1-1OFFUser Switch 0Pin AW33 = ‘1’Pin BF52 = ‘0’
SW1-2OFFUser Switch 1Pin AY36 = ‘1’Pin BF47 = ‘0’
SW1-3OFFReservedReservedReserved
SW1-4OFFPower OffBoard will power upImmediately power down
SW1-5OFFService ModeRegular OperationFirmware update service mode
SW1-6ONHOST_I2­ C_ENSysmon over PCIe I2CSysmon isolated
SW1-7ONCAPI_VP­ D_ENOpenCAPI VPD availableOpenCAPI VPD isolated
SW1-8ONCAPI_VP­ D_WPCAPI VPD is write protectedCAPI VPD is writable

Use IO Standard “LVCMOS18” when constraining the user switch pins.

LEDs
There are 7 LEDs on the ADM-PCIE-9H3, 4 of which are general purpose and whose meaning can be defined by the user. The other 3 have fixed functions described below:
LEDs

Table 4 : LED Details

Comp. Ref.FunctionON StateOFF State
D1LED_G1User defined ‘0’User defined ‘1’
D3LED_A1User defined ‘0’User defined ‘1’
D4DONEFPGA is configuredFPGA is not configured
D5Status 1See Status LED Definitions
D6Status 0See Status LED Definitions
D7LED_A0User defined ‘0’User defined ‘1’
D9LED_G0User defined ‘0’User defined ‘1’

See Section Complete Pinout Table for full list of user controlled LED nets and pins

Clocking
The ADM-PCIE-9H3 provides flexible reference clock solutions for the many multi-gigabit transceiver quads and FPGA fabric. Any clock out of the Si5338 Clock Synthesizer is re-configurable from either the front panel USB USB Interface or the Alpha Data sysmon FPGA serial port. This allows the user to configure almost any arbitrary clock frequency during application run time. Maximum clock frequency is 312.5MHz.
There is also an available Si5328 jitter attenuator. This can provide clean and synchronous clocks to the QSFP-DD and OpenCAPI (SlimSAS) quad locations at many clock frequencies. These devices only use volatile memory, so the FPGA design will need to re-configure the register map after any power cycle event.
All clock names in the section below can be found in Complete Pinout Table.
Clocking

Si5328
If jitter attenuation is required please see the reference documentation for the Si5328.
https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5328.pdf
The circuit connections mirror Xilinx VCU110 and VCU108, please see Xilinx Dev Boards for references
Si5328

PCIe Reference Clocks
The 16 MGT lanes connected to the PCIe card edge use MGT tiles 224 through 227 and use the system 100 MHz clock (net name PCIE_REFCLK).
Alternatively, a clean, onboard 100MHz clock is available as well (net name PCIE_LCL_REFCLK).

Fabric Clock
The design offers a fabric clock (net name FABRIC_SRC_CLK) which defaults to 300 MHz. This clock is intended to be used for IDELAY elements in FPGA designs. The fabric clock is connected to a Global Clock (GC) pin.
DIFF_TERM_ADV = TERM_100 is required for LVDS termination

Auxiliary Clock
The design offers a auxiliary clock (net name AUX_CLK) which defaults to 300 MHz. This clock can be used for any purpose and is connected to a Global Clock (GC) pin.
DIFF_TERM_ADV = TERM_100 is required for LVDS termination

Programming Clock (EMCCLK)
A 100MHz clock (net name EMCCLK_B) is fed into the EMCCLK pin to drive the SPI flash device during configuration of the FPGA. Note that this is not a global clock capable IO pin.

QSFP-DD
The QSFP-DD cage is located in MGT tiles 126 and 127 and use a 161.1328125MHz default reference clock.
Note that this clock frequency can be changed to any arbitrary clock frequency up to 312MHz by re-programing the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha Data API or over USB with the appropriate Alpha Data Software tools.
See net names QSFP_CLK* for pin locations.
The QSFP-DD cage is also located such that it can be clocked from the Si5328 jitter attenuator clock multiplier.
See net names SI5328_OUT_1* for pin locations.

Ultraport SlimSAS (OpenCAPI)
The Ultraport SlimSAS connector is located in MGT tile 124 and 125.
For OpenCAPI an external 156.25MHz clock is provided over the cable. See net names CAPI_CLK_0* for cable clock pin locations.
Another alternative clock source for this interface is the Si5338 clock synthesizer which is defaulted to 161.1328125MHz. See net names CAPI_CLK_1* for pin locations. Note that this clock frequency can be changed to any arbitrary clock frequency up to 312MHz by re-programing the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha Data API or over USB with the appropriate Alpha Data Software tools.
For jitter sensitive applications, this interface can be clocked from the Si5328 jitter attenuator. See net names SI5328_OUT_0* for pin locations.

PCI Express

The ADM-PCIE-9H3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes. The FPGA drives these lanes directly using the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and number of lanes used is generally automatic and does not require user intervention.
PCI Express reset (PERST#) connected to the FPGA at two location. See Complete Pinout Table signals PERST0_1V8_L and PERST1_1V8_L.
The other pin assignments for the high speed lanes are provided in the pinout attached to the Complete Pinout Table
The PCI Express specification requires that all add-in cards be ready for enumeration within 120ms after power is valid (100ms after power is valid + 20ms after PERST is released). The ADM-PCIE-9H3 does meet this requirement when configured from a tandem bitstream with the proper SPI constraints detailed in the section:
Configuration From Flash Memory. For more details on tandem configuration, see Xilinx xapp 1179.

Note:
Different motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core provided by Xilinx. Alpha Data recommends using the following setting if a user experiences link errors or training issues with their system: within the IP core generator, change the mode to “Advanced” and open the “GT Settings” tab, change the “form factor driven insertion loss adjustment” from “Add-in Card” to “Chip-to-Chip” (See Xilinx PG239 for more details).

QSFP-DD
One QSFP-DD cage is available at the front panel. This cage is capable of housing either QSFP28 or QSFP-DD cables (backwards compatible). Both active optical and passive copper QSFP-DD/QSFP28 compatible models are fully compliant. The communication interface can run at up to 28Gbps per channel. There are 8 channels across the QSFP-DD cage (total maximum bandwidth of 224Gbps). This cage is ideally suited for 8x 10G/25G, 2x 100G Ethernet, or any other protocol supported by the Xilinx GTY Transceivers. Please see Xilinx User Guide UG578 for more details on the capabilities of the transceivers.
The QSFP-DD cage has control signals connected to the FPGA. The connectivity is detailed in the Complete Pinout Table at the end of this document. The notation used in the pin assignments is QSFP* with locations clarified in the diagram below.
Use the QSFP_SCL_1V8 and QSFP_SDA_1V8 pins as detailed in Complete Pinout Table to communicate with QSFP28 register space.

Note:
The LP_MODE (Low Power Mode) to the cage is tied to ground, use the management interface to set power rules.
QSFP-DD

It is possible for Alpha Data to pre-fit the ADM-PCIE-9H3 with QSFP-DD and QSFP28 components. The table below shows the part number for the transceivers fitted when ordered with this board.
Table 5 : QSFP28 Part Numbers

Order CodeDescriptionPart NumberManufacturer
Q1040G (4×10) QSFP Optical TransceiverFTL410QE2CFinisar
Q1456G (4×14) QSFP Optical TransceiverFTL414QB2CFinisar
Q25100G (4×25) QSFP28 Optical TransceiverFTLC9558REPMFinisar

OpenCAPI Ultraport SlimSAS

An Ultraport SlimSAS receptacles along the back of the board allow for OpenCAPI compliant interfaces running at 200G (8 channels at 25G). Please contact support@alpha-data.com or your IBM representative for more details on OpenCAPI and its benefits.
The SlimSAS connector can also be used to connect an additional 2x QSFP28 breakout board, contact sales@alpha-data.com for more details. Alternatively, cabling cab be used to connect multiple ADM-PCIE-9H3 cards within a chassis.
OpenCAPI Ultraport SlimSAS

System Monitor
The ADM-PCIE-9H3 has the ability to monitor temperature, voltage, and current of the system to check on the operation of the board. The monitoring is implemented using an Atmel AVR microcontroller.
If the core FPGA temperature exceeds 105 degrees Celsius, the FPGA will be cleared to prevent damage to the card.
Control algorithms within the microcontroller automatically check line voltages and on board temperatures and shares makes the information available to the FPGA over a dedicated serial interface built into the Alpha Data reference design package (sold separately). The information can also be accessed directly from the microcontroller over the USB interface on the front panel or via the IPMI interface available at the PCIe card edge.

Table 6 : Voltage, Current, and Temperature Monitors

MonitorsIndexPurpose/Description
ETCETCElapsed time counter (seconds)
ECECEvent counter (power cycles)
12VADC00Board input supply
12V_IADC0112V input current in amps
3.3VADC02Board input supply
3.3V_IADC033.3V input current in amps
3.3VADC05Board input auxiliary power
3.3VADC053.3V for QSFP optics
2.5VADC06Clock and DRAM voltage supply
1.8VADC07FPGA IO voltage (VCCO)
1.8VADC08Transceiver power (AVCC_AUX)
1.2VADC09HBM Power
1.2VADC10Transceiver Power (AVTT)
0.9VADC11Transceiver Power (AVCC)
0.85-0.90VADC12BRAM + INT_IO (VccINT_IO)
0.72-0.90VADC13FPGA Core Supply (VccINT)
uC_TempTMP00FPGA on-die temperature
Board0_TempTMP01Board temperature near front panel
Board1_TempTMP02Board temperature near back top corner
FPGA_TempTMP03FPGA on-die temperature

System Monitor Status LEDs
LEDs D5 (Red) and D6 (Green) indicate the card health status.

Table 7 : Status LED Definitions

LEDsStatus
GreenRunning and no alarms
Green + RedStandby (Powered off)
Flashing Green + Flashing Red (together)Attention – critical alarm active
Flashing Green + Flashing Red (alternating)Service Mode
Flashing Green + RedAttention – alarm active
RedMissing application firmware or invalid firmware
Flashing RedFPGA configuration cleared to protect board

Fan Controllers
The onboard USB bus controlled by the system monitor has access to a MAX6620 fan controller. This device can be controlled through the multiple onboard system monitor communication interfaces, including USB, PCIe Edge SMBUS, and FPGA sysmon seral communication port. The fan controller is on I2C bus 1 at address 0x2a. For additional questions. Contact support@alpha-data.com with additional questions on utilizing these controllers.

USB Interface
The FPGA can be configured directly from the USB connection on either the front panel or the rear card edge.
The ADM-PCIE-9H3 utilizes the Digilent USB-JTAG converter box which is supported by the Xilinx software tool suite. Simply connect a micro-USB AB type cable between the ADM-PCIE-9H3 USB port and a host computer with Vivado installed. Vivado Hardware Manager will automatically recognize the FPGA and allow you to configure the FPGA and the SBPI configuration PROM.
The same USB connector is used to directly access the system monitor system. All voltages, currents, temperatures, and non-volatile clock configuration settings can be accessed using Alpha Data’s avr2util software at this interface.
Avr2util for Windows and the associated USB driver is downloadable here:
https://support.alpha-data.com/pub/firmware/utilities/windows/
Avr2util for Linux is downloadable here:
https://support.alpha-data.com/pub/firmware/utilities/linux/
Use “avr2util.exe /?” to see all options.
For example “avr2util.exe /usbcom com4 display-sensors” will display all sensor values.
For example “avr2util.exe /usbcom com4 setclknv 1 156250000” will set the QSFP clock to 156.25MHz. setclk index 0 = CAPI_CLK_1, index 1 = QSFP_CLK, index 2 = AUX_CLK, index 3 = FABRIC_CLK.
Change ‘com4’ to match the com port number assigned under windows device manager

Configuration
There are two main ways of configuring the FPGA on the ADM-PCIE-9H3:

  • From Flash memory, at power-on, as described in Section 3.8.1
  • Using USB cable connected at either USB port Section 3.8.2

Configuration From Flash Memory
The FPGA can be automatically configured at power-on from two 256 Mbit QSPI flash memory device configured as an x8 SPI device (Micron part numbers MT25QU256ABA8E12-0). These flash devices are typically divided into two regions of 32 MiByte each, where each region is sufficiently large to hold an uncompressed bitstream for a VU33P FPGA.
The ADM-PCIE-9H3 is shipped with a simple PCIe endpoint bitstream containing a basic Alpha Data ADXDMA bitstream. Alpha Data can load in other custom bitstreams during production test, please contact sales@alpha-data.com for more details.
It is possible to use Multiboot with a fallback image on this hardware. The master SPI configuration interface and the Fallback MultiBoot are discussed in detail in Xilinx UG570. At power-on, the FPGA attempts to configure itself automatically in serial master mode based on the contents of the header in the programing file. Multibook and ICAP can be used to selected between the two configuration regions to be loaded into the FPGA. See Xilinx UG570 MultiBoot for details.
The image loaded can also support tandem PROM or tandem PCIE with field update configuration methods.
These options reduce power-on load times to help meet the PCIe reset timing requirements. Tandem with field also enables a host system to reconfigure the user FPGA logic without losing the PCIe link, a useful feature when system resets and power cycles are not an option.
The Alpha Data System Monitor is also capable of reconfiguring the flash memory and reprograming the FPGA.
This provides a useful failsafe mechanism to re-program the FPGA even if it drops off the PCIe bus. The system monitor can be accessed over USB at the front panel and rear edge, or over the SMBUS connections on the PCIe edge.

Building and Programming Configuration Images

Generate a bitfile with these constraints (see xapp1233):

  • set_property BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ]
  • set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
  • set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
  • set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
  • set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
  • set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
  • set_property CFGBVS GND [ current_design ]
  • set_property CONFIG_VOLTAGE 1.8 [ current_design ]
  • set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]

Generate an MCS file with these properties (write_cfgmem):

  • -format MCS
  • -size 64
  • -interface SPIx8
  • -loadbit “up 0x0000000 <directory/to/file/filename.bit>” (0th location)
  • -loadbit “up 0x2000000 <directory/to/file/filename.bit>” (1st location, optional)

Program with vivado hardware manager with these settings (see xapp1233):

  • SPI part: mt25qu256-spi-x1_x2_x4_x8
  • State of non-config mem I/O pins: Pull-none
  • Target the four files generated from the write_cfgmem tcl command.

Configuration via JTAG
A micro-USB AB Cable may be attached to the front panel or rear edge USB port. This permits the FPGA to be reconfigured using the Xilinx Vivado Hardware Manager via the integrated Digilent JTAG converter box. The device will be automatically recognized in Vivado Hardware Manager.
For more detailed instructions, please see “Using a Vivado Hardware Manager to Program an FPGA Device” section of Xilinx UG908: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf

GPIO Connector
The GPIO option consists of a versatile shrouded connector from Molex with part number 87832-1222 that give users with custom IO requirements four direct connect to FPGA signals.
Recommended mating plug: Molex 0875681273 or 0511101260
GPIO Connector
GPIO Connector

Direct Connect FPGA Signals
8 nets are broken out to the GPIO header, as four sets of differential pairs. These signal are suitable for any 1.8V supported signaling standards supported by the Xilinx UltraScale architecture. See Xilinx UG571 for IO options.
LVDS and 1.8 CMOS are popular options. The 0th GPIO signal index is suitable for a global clock connection.
The direct connect GPIO signals are limited to 1.8V by a quickswitch (74CBTLVD3245PW) in order to protect the FPGA from overvoltage on IO pins. This quickswitch allows the signals to travel in either direction with only 4 ohms of series impedance and less than 1ns of propagation delay. The nets are directly connected to the FPGA after the quickswitch.
Direct connect signal names are labeled GPIO_0_1V8_P/N and GPIO_1_1V8_P/N, etc. to show polarity and grouping. The signal pin allocations can be found in Complete Pinout Table

Timing Input
J1.1 and J1.2 can be used as an isolated timing input signal (up to 25MHz). Applications can either directly connect to the GPIO connector, or Alpha Data can provide a cabled solution with an SMA or similar connector on the front panel. Contact sales@alpha-data.com for front panel connector options.
For pin locations, see signal name ISO_CLK in Complete Pinout Table.
The signal is isolated through a optical isolator part number TLP2367 with a 220 ohm of series resistance.

User EEPROM
A 2Kb I2C user EEPROM is provided for storing MAC addresses or other user information. The EEPROM is part number CAT34C02HU4IGT4A
The address pins A2, A1, and A0 are all strapped to a logical ‘0’.
Write protect (WP), Serial Clock (SCL), and Serial Data (SDA) pin assignments can be found in Complete Pinout Table with the names SPARE_WP, SPARE_SCL, and SPARE_SDA respectively.
WP, SDA, and SCL signals all have external pull-up resistors on the card.

Appendix A: Complete Pinout Table

Table 8 : Complete Pinout Table (continued on next page)

Pin NumberSignal NamePin NameBank Voltage
BC18AUX_CLK_PIN_NIO_L11N_T1U_N9_GC_641.8 (LVCMOS18)
BB18AUX_CLK_PIN_PIO_L11P_T1U_N8_GC_641.8 (LVCMOS18)
BF33AVR_B2U_1V8IO_L2P_T0L_N2_661.8 (LVCMOS18)
BF31AVR_HS_B2U_1V8IO_L1P_T0L_N0_DBC_661.8 (LVCMOS18)
BB33AVR_HS_CLK_1V8IO_L12N_T1U_N11_GC_661.8 (LVCMOS18)
BF32AVR_HS_U2B_1V8IO_L1N_T0L_N1_DBC_661.8 (LVCMOS18)
BA33AVR_MON_CLK_1V8IO_L12P_T1U_N10_GC_661.8 (LVCMOS18)
BF34AVR_U2B_1V8IO_L2N_T0L_N3_661.8 (LVCMOS18)
AK39CAPI_CLK_0_PIN_NMGTREFCLK0N_124MGT REFCLK
AK38CAPI_CLK_0_PIN_PMGTREFCLK0P_124MGT REFCLK
AF39CAPI_CLK_1_PIN_NMGTREFCLK0N_125MGT REFCLK
AF38CAPI_CLK_1_PIN_PMGTREFCLK0P_125MGT REFCLK
BF17CAPI_I2C_SCL_1V8IO_L1P_T0L_N0_DBC_641.8 (LVCMOS18)
BF16CAPI_I2C_SDA_1V8IO_L1N_T0L_N1_DBC_641.8 (LVCMOS18)
BF19CAPI_INT/RESET_1V8IO_L2P_T0L_N2_641.8 (LVCMOS18)
BF43CAPI_RX0_NMGTYRXN0_124MGT
BF42CAPI_RX0_PMGTYRXP0_124MGT
BD44CAPI_RX1_NMGTYRXN1_124MGT
BD43CAPI_RX1_PMGTYRXP1_124MGT
BB44CAPI_RX2_NMGTYRXN2_124MGT
BB43CAPI_RX2_PMGTYRXP2_124MGT
AY44CAPI_RX3_NMGTYRXN3_124MGT
AY43CAPI_RX3_PMGTYRXP3_124MGT
BC46CAPI_RX4_NMGTYRXN0_125MGT
BC45CAPI_RX4_PMGTYRXP0_125MGT
BA46CAPI_RX5_NMGTYRXN1_125MGT
BA45CAPI_RX5_PMGTYRXP1_125MGT
AW46CAPI_RX6_NMGTYRXN2_125MGT
AW45CAPI_RX6_PMGTYRXP2_125MGT
AV44CAPI_RX7_NMGTYRXN3_125MGT
AV43CAPI_RX7_PMGTYRXP3_125MGT
AT39CAPI_TX0_NMGTYTXN0_124MGT
AT38CAPI_TX0_PMGTYTXP0_124MGT
Pin NumberSignal NamePin NameBank Voltage
AR41CAPI_TX1_NMGTYTXN1_124MGT
AR40CAPI_TX1_PMGTYTXP1_124MGT
AP39CAPI_TX2_NMGTYTXN2_124MGT
AP38CAPI_TX2_PMGTYTXP2_124MGT
AN41CAPI_TX3_NMGTYTXN3_124MGT
AN40CAPI_TX3_PMGTYTXP3_124MGT
AM39CAPI_TX4_NMGTYTXN0_125MGT
AM38CAPI_TX4_PMGTYTXP0_125MGT
AL41CAPI_TX5_NMGTYTXN1_125MGT
AL40CAPI_TX5_PMGTYTXP1_125MGT
AJ41CAPI_TX6_NMGTYTXN2_125MGT
AJ40CAPI_TX6_PMGTYTXP2_125MGT
AG41CAPI_TX7_NMGTYTXN3_125MGT
AG40CAPI_TX7_PMGTYTXP3_125MGT
AV26EMCCLK_BIO_L24P_T3U_N10_EMCCLK_651.8 (LVCMOS18)
BA31FABRIC_CLK_PIN_NIO_L13N_T2L_N1_GC_QBC_661.8 (LVDS with DIFF_TERM_ADV)
AY31FABRIC_CLK_PIN_PIO_L13P_T2L_N0_GC_QBC_661.8 (LVDS with DIFF_TERM_ADV)
BA8FPGA_FLASH_CE0_LRDWR_FCS_B_01.8 (LVCMOS18)
AW24FPGA_FLASH_CE1_LIO_L2N_T0L_N3_FWE_FCS2_B_651.8 (LVCMOS18)
AW7FPGA_FLASH_DQ0D00_MOSI_01.8 (LVCMOS18)
AV7FPGA_FLASH_DQ1D01_DIN_01.8 (LVCMOS18)
AW8FPGA_FLASH_DQ2D02_01.8 (LVCMOS18)
AV8FPGA_FLASH_DQ3D03_01.8 (LVCMOS18)
AV28FPGA_FLASH_DQ4IO_L22P_T3U_N6_DBC_AD0P­

_D04_65

1.8 (LVCMOS18)
AW28FPGA_FLASH_DQ5IO_L22N_T3U_N7_DBC_AD0N­

_D05_65

1.8 (LVCMOS18)
BB28FPGA_FLASH_DQ6IO_L21P_T3L_N4_AD8P_D06_651.8 (LVCMOS18)
BC28FPGA_FLASH_DQ7IO_L21N_T3L_N5_AD8N_D07_651.8 (LVCMOS18)
BA19GPIO_0_1V8_NIO_L13N_T2L_N1_GC_QBC_641.8 (LVCMOS18or LVDS)
AY19GPIO_0_1V8_PIO_L13P_T2L_N0_GC_QBC_641.8 (LVCMOS18or LVDS)
AY20GPIO_1_1V8_NIO_L15N_T2L_N5_AD11N_641.8 (LVCMOS18or LVDS)
AY21GPIO_1_1V8_PIO_L15P_T2L_N4_AD11P_641.8 (LVCMOS18or LVDS)
AW20GPIO_2_1V8_NIO_L16N_T2U_N7_QBC_AD3N_641.8 (LVCMOS18or LVDS)
Pin NumberSignal NamePin NameBank Voltage
AV20GPIO_2_1V8_PIO_L16P_T2U_N6_QBC_AD3P_641.8 (LVCMOS18or LVDS)
AW18GPIO_3_1V8_NIO_L17N_T2U_N9_AD10N_641.8 (LVCMOS18or LVDS)
AW19GPIO_3_1V8_PIO_L17P_T2U_N8_AD10P_641.8 (LVCMOS18or LVDS)
BA27IBM_PERST_1V8_LIO_L20P_T3L_N2_AD1P_D08_651.8 (LVCMOS18)
BA18ISO_CLK_1V8IO_L14P_T2L_N2_GC_641.8 (LVCMOS18)
AD8PCIE_LCL_REFCLK_PIN_NMGTREFCLK0N_226MGT REFCLK
AD9PCIE_LCL_REFCLK_PIN_PMGTREFCLK0P_226MGT REFCLK
AF8PCIE_REFCLK_1_PIN_NMGTREFCLK0N_225MGT REFCLK
AF9PCIE_REFCLK_1_PIN_PMGTREFCLK0P_225MGT REFCLK
AB8PCIE_REFCLK_2_PIN_NMGTREFCLK0N_227MGT REFCLK
AB9PCIE_REFCLK_2_PIN_PMGTREFCLK0P_227MGT REFCLK
AL1PCIE_RX0_NMGTYRXN3_227MGT
AL2PCIE_RX0_PMGTYRXP3_227MGT
AM3PCIE_RX1_NMGTYRXN2_227MGT
AM4PCIE_RX1_PMGTYRXP2_227MGT
BA1PCIE_RX10_NMGTYRXN1_225MGT
BA2PCIE_RX10_PMGTYRXP1_225MGT
BC1PCIE_RX11_NMGTYRXN0_225MGT
BC2PCIE_RX11_PMGTYRXP0_225MGT
AY3PCIE_RX12_NMGTYRXN3_224MGT
AY4PCIE_RX12_PMGTYRXP3_224MGT
BB3PCIE_RX13_NMGTYRXN2_224MGT
BB4PCIE_RX13_PMGTYRXP2_224MGT
BD3PCIE_RX14_NMGTYRXN1_224MGT
BD4PCIE_RX14_PMGTYRXP1_224MGT
BE5PCIE_RX15_NMGTYRXN0_224MGT
BE6PCIE_RX15_PMGTYRXP0_224MGT
AK3PCIE_RX2_NMGTYRXN1_227MGT
AK4PCIE_RX2_PMGTYRXP1_227MGT
AN1PCIE_RX3_NMGTYRXN0_227MGT
AN2PCIE_RX3_PMGTYRXP0_227MGT
AP3PCIE_RX4_NMGTYRXN3_226MGT
AP4PCIE_RX4_PMGTYRXP3_226MGT
AR1PCIE_RX5_NMGTYRXN2_226MGT
AR2PCIE_RX5_PMGTYRXP2_226MGT
Pin NumberSignal NamePin NameBank Voltage
AT3PCIE_RX6_NMGTYRXN1_226MGT
AT4PCIE_RX6_PMGTYRXP1_226MGT
AU1PCIE_RX7_NMGTYRXN0_226MGT
AU2PCIE_RX7_PMGTYRXP0_226MGT
AV3PCIE_RX8_NMGTYRXN3_225MGT
AV4PCIE_RX8_PMGTYRXP3_225MGT
AW1PCIE_RX9_NMGTYRXN2_225MGT
AW2PCIE_RX9_PMGTYRXP2_225MGT
Y4PCIE_TX0_PIN_NMGTYTXN3_227MGT
Y5PCIE_TX0_PIN_PMGTYTXP3_227MGT
AA6PCIE_TX1_PIN_NMGTYTXN2_227MGT
AA7PCIE_TX1_PIN_PMGTYTXP2_227MGT
AL6PCIE_TX10_PIN_NMGTYTXN1_225MGT
AL7PCIE_TX10_PIN_PMGTYTXP1_225MGT
AM8PCIE_TX11_PIN_NMGTYTXN0_225MGT
AM9PCIE_TX11_PIN_PMGTYTXP0_225MGT
AN6PCIE_TX12_PIN_NMGTYTXN3_224MGT
AN7PCIE_TX12_PIN_PMGTYTXP3_224MGT
AP8PCIE_TX13_PIN_NMGTYTXN2_224MGT
AP9PCIE_TX13_PIN_PMGTYTXP2_224MGT
AR6PCIE_TX14_PIN_NMGTYTXN1_224MGT
AR7PCIE_TX14_PIN_PMGTYTXP1_224MGT
AT8PCIE_TX15_PIN_NMGTYTXN0_224MGT
AT9PCIE_TX15_PIN_PMGTYTXP0_224MGT
AB4PCIE_TX2_PIN_NMGTYTXN1_227MGT
AB5PCIE_TX2_PIN_PMGTYTXP1_227MGT
AC6PCIE_TX3_PIN_NMGTYTXN0_227MGT
AC7PCIE_TX3_PIN_PMGTYTXP0_227MGT
AD4PCIE_TX4_PIN_NMGTYTXN3_226MGT
AD5PCIE_TX4_PIN_PMGTYTXP3_226MGT
AF4PCIE_TX5_PIN_NMGTYTXN2_226MGT
AF5PCIE_TX5_PIN_PMGTYTXP2_226MGT
AE6PCIE_TX6_PIN_NMGTYTXN1_226MGT
AE7PCIE_TX6_PIN_PMGTYTXP1_226MGT
AH4PCIE_TX7_PIN_NMGTYTXN0_226MGT
Pin NumberSignal NamePin NameBank Voltage
AH5PCIE_TX7_PIN_PMGTYTXP0_226MGT
AG6PCIE_TX8_PIN_NMGTYTXN3_225MGT
AG7PCIE_TX8_PIN_PMGTYTXP3_225MGT
AJ6PCIE_TX9_PIN_NMGTYTXN2_225MGT
AJ7PCIE_TX9_PIN_PMGTYTXP2_225MGT
AW27PERST0_1V8_LIO_T3U_N12_PERSTN0_651.8 (LVCMOS18)
AY27PERST1_1V8_LIO_L23N_T3U_N9_PERSTN1_I­ 2C_SDA_651.8 (LVCMOS18)
AD39QSFP_CLK_PIN_NMGTREFCLK0N_126MGT REFCLK
AD38QSFP_CLK_PIN_PMGTREFCLK0P_126MGT REFCLK
AV16QSFP_INT_1V8_LIO_L24P_T3U_N10_641.8 (LVCMOS18)
BA14QSFP_MODPRS_LIO_L22N_T3U_N7_DBC_AD0N_641.8 (LVCMOS18)
AV15QSFP_RST_1V8_LIO_L24N_T3U_N11_641.8 (LVCMOS18)
AU46QSFP_RX0_NMGTYRXN0_126MGT
AU45QSFP_RX0_PMGTYRXP0_126MGT
AT44QSFP_RX1_NMGTYRXN1_126MGT
AT43QSFP_RX1_PMGTYRXP1_126MGT
AR46QSFP_RX2_NMGTYRXN2_126MGT
AR45QSFP_RX2_PMGTYRXP2_126MGT
AP44QSFP_RX3_NMGTYRXN3_126MGT
AP43QSFP_RX3_PMGTYRXP3_126MGT
AN46QSFP_RX4_NMGTYRXN0_127MGT
AN45QSFP_RX4_PMGTYRXP0_127MGT
AK44QSFP_RX5_NMGTYRXN1_127MGT
AK43QSFP_RX5_PMGTYRXP1_127MGT
AM44QSFP_RX6_NMGTYRXN2_127MGT
AM43QSFP_RX6_PMGTYRXP2_127MGT
AL46QSFP_RX7_NMGTYRXN3_127MGT
AL45QSFP_RX7_PMGTYRXP3_127MGT
AW15QSFP_SCL_1V8IO_L23P_T3U_N8_641.8 (LVCMOS18)
AW14QSFP_SDA_1V8IO_L23N_T3U_N9_641.8 (LVCMOS18)
AH43QSFP_TX0_NMGTYTXN0_126MGT
AH42QSFP_TX0_PMGTYTXP0_126MGT
AE41QSFP_TX1_NMGTYTXN1_126MGT
AE40QSFP_TX1_PMGTYTXP1_126MGT
AF43QSFP_TX2_NMGTYTXN2_126MGT
Pin NumberSignal NamePin NameBank Voltage
AF42QSFP_TX2_PMGTYTXP2_126MGT
AD43QSFP_TX3_NMGTYTXN3_126MGT
AD42QSFP_TX3_PMGTYTXP3_126MGT
AC41QSFP_TX4_NMGTYTXN0_127MGT
AC40QSFP_TX4_PMGTYTXP0_127MGT
AB43QSFP_TX5_NMGTYTXN1_127MGT
AB42QSFP_TX5_PMGTYTXP1_127MGT
AA41QSFP_TX6_NMGTYTXN2_127MGT
AA40QSFP_TX6_PMGTYTXP2_127MGT
Y43QSFP_TX7_NMGTYTXN3_127MGT
Y42QSFP_TX7_PMGTYTXP3_127MGT
AV36SI5328_1V8_SCLIO_L24N_T3U_N11_661.8 (LVCMOS18)
AV35SI5328_1V8_SDAIO_L24P_T3U_N10_661.8 (LVCMOS18)
AE37SI5328_OUT_0_PIN_NMGTREFCLK1N_125MGT REFCLK
AE36SI5328_OUT_0_PIN_PMGTREFCLK1P_125MGT REFCLK
AB39SI5328_OUT_1_PIN_NMGTREFCLK0N_127MGT REFCLK
AB38SI5328_OUT_1_PIN_PMGTREFCLK0P_127MGT REFCLK
BB19SI5328_REFCLK_IN_NIO_L12N_T1U_N11_GC_641.8 (LVDS)
BB20SI5328_REFCLK_IN_PIO_L12P_T1U_N10_GC_641.8 (LVDS)
AV33SI5328_RST_1V8_LIO_L22P_T3U_N6_DBC_AD0P_661.8 (LVCMOS18)
BE30SPARE_SCLIO_L5N_T0U_N9_AD14N_661.8 (LVCMOS18)
BC30SPARE_SDAIO_L6P_T0U_N10_AD6P_661.8 (LVCMOS18)
BD30SPARE_WPIO_L6N_T0U_N11_AD6N_661.8 (LVCMOS18)
BE31SRVC_MD_L_1V8IO_L3P_T0L_N4_AD15P_661.8 (LVCMOS18)
AV32USER_LED_A0_1V8IO_L18N_T2U_N11_AD2N_661.8 (LVCMOS18)
AW32USER_LED_A1_1V8IO_T2U_N12_661.8 (LVCMOS18)
AY30USER_LED_G0_1V8IO_L17N_T2U_N9_AD10N_661.8 (LVCMOS18)
AV31USER_LED_G1_1V8IO_L18P_T2U_N10_AD2P_661.8 (LVCMOS18)
AW33USR_SW_0IO_L22N_T3U_N7_DBC_AD0N_661.8 (LVCMOS18)
AY36USR_SW_1IO_L23P_T3U_N8_661.8 (LVCMOS18)

Revision History

DateRevisionChanged ByNature of Change
24 Sep 20181.0K. RothInitial Release
 

31 Oct 2018

 

1.1

 

K. Roth

Updated product images, changed default programable clock frequency for CAPI_CLK_1 to 161MHz
 

14 Dec 2018

 

1.2

 

K. Roth

Updated configuration flash part number, changed wording of gpio description for accuracy, added weight.
 

24 Oct 2019

 

1.3

 

K. Roth

Updated Configuration to remove address map and correct description of memory part capacity.
 

 

25 Jan 2022

 

 

1.4

 

 

K. Roth

Updated Thermal Performance to include thermal efficiency figures and comments about the impact of the shroud, removed references to QSFP0 and QSFP1 from section QSFP-DD and updated 25Gb transceiver part number.

Customer Service

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All rights reserved.
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Telephone: +44 131 558 2600
Fax: +44 131 558 2700
email: sales@alpha-data.com
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Telephone: (303) 954 8768
Fax: (866) 820 9956 – toll free
email: sales@alpha-data.com
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All trademarks are the property of their respective owners.
Address: Suite L4A, 160 Dundee Street,
Edinburgh, EH11 1DQ, UK
Telephone: +44 131 558 2600
Fax: +44 131 558 2700
email: sales@alpha-data.com
website: http://www.alpha-data.com
Address: 10822 West Toller Drive, Suite 250
Littleton, CO 80127
Telephone: (303) 954 8768
Fax: (866) 820 9956 – toll free
email: sales@alpha-data.com
website: http://www.alpha-data.com

ALPHA DATA logo

Documents / Resources

ALPHA DATA ADM-PCIE-9H3 High Performance FPGA Processing Card [pdf] User Manual
ADM-PCIE-9H3 High Performance FPGA Processing Card, ADM-PCIE-9H3, High Performance FPGA Processing Card, FPGA Processing Card, Processing Card
ALPHA DATA ADM-PCIE-9H3 High Performance FPGA Processing Card [pdf] User Manual
ADM-PCIE-9H3 High Performance FPGA Processing Card, ADM-PCIE-9H3, High Performance FPGA Processing Card, Performance FPGA Processing Card, FPGA Processing Card, Processing Card

References

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