Litaba pata
1 intel AN 805 Hierarchical Partial Reconfiguration of a Design on Arria 10 SoC Development Board
2 Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board
3 Reference Design Overview
3.1 Reference Design Walkthrough
3.2 Lintlha Tse Amanang
3.3 Lintlha Tse Amanang
3.4 Ho Nchafatsa Moralo oa Boemo bo Phahameng
3.5 Lintlha Tse Amanang
3.6 Ho theha Liphetoho tsa Synthesis-Feela
4 E Hlalosa Mofuta oa Phetoho
4.1 Lintlha Tse Amanang
5 Lintlha Tse Amanang
6 Ho Fetola Motho ea Teng
7 Ho Eketsa Motho e Mocha Moahong
8 Nalane ea Phetoho ea Litokomane
9 Litokomane / Lisebelisoa
9.1 Litšupiso
10 Related Posts

intel-LOGO

intel AN 805 Hierarchical Partial Reconfiguration of a Design on Arria 10 SoC Development Board

intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-PRODUCT

Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board

Molaetsa ona oa ts'ebeliso o bonts'a ho fetola moralo o bonolo hore e be moralo o ka hlophisoang ka mokhoa o sa fellang, le ho kenya tšebetsong moralo ho boto ea nts'etsopele ea Intel® Arria® 10 SoC. Hierarchical partial reconfiguration (HPR) ke mofuta o ikhethileng oa tlhophiso e itseng (PR), moo o nang le sebaka sa PR ka har'a sebaka se seng sa PR. U ka theha batho ba bangata bakeng sa likarolo tsa ngoana le tsa motsoali. U kenya li-partitions tsa bana ka har'a likarolo tsa bona tsa batsoali. Ho hlophisa bocha karohano ea bana ha ho ame ts'ebetso ho motsoali kapa libakeng tse sa fetoheng. Ho hlophisa bocha karohano ea motsoali ha ho ame ts'ebetso sebakeng se sa fetoheng, empa ho nka sebaka sa likarolo tsa bana tsa sebaka sa motsoali ka batho ba kamehla ba karohano ea bana. Mokhoa ona o sebetsa hantle lits'ebetsong moo mesebetsi e mengata e arolelanang lisebelisoa tse tšoanang tsa FPGA.
Phetoho e sa fellang e fana ka lintlafatso tse latelang ho moralo o bataletseng:

  • E lumella tlhophiso ea moralo oa nako e mathang
  • E eketsa scalability ea moralo
  • E fokotsa nako ea ho senya tsamaiso
  • E ts'ehetsa mesebetsi e mengata ea ho kopanya nako ka har'a moralo
  • E fokotsa litšenyehelo le tšebeliso ea matla ka tšebeliso e nepahetseng ea sebaka sa boto
  • Hlokomela:
  • Ts'ebetsong ea moralo ona oa litšupiso ho hloka tsebo ea mantlha le phallo ea ts'ebetso ea Intel Quartus® Prime FPGA le tsebo ea projeke ea mantlha ea Intel Quartus Prime. files.

Lintlha Tse Amanang

  • Intel Arria 10 SoC Development Kit User Guide
  • Mehopolo ea Phetoho e sa Feleng
  • Phallo ea Moralo oa Litlhophiso tse sa Feleng
  • Litlhahiso tsa Moralo oa Litlhophiso tse sa Feleng
  • Mehopolo ea Moralo oa Reconfiguration e sa Feleng

Litlhoko tsa Moralo oa Reference

Moralo ona oa litšupiso o hloka tse latelang:

  • Intel Quartus Prime Pro Edition software version 17.1 bakeng sa ts'ebetsong ea moralo.
  • Intel Arria 10 SoC kit ea nts'etsopele bakeng sa ts'ebetsong ea FPGA.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.

  • Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

Reference Design Overview

  • Moralo ona oa litšupiso o na le khaontara e le 'ngoe ea 32-bit. Boemong ba boto, moralo o hokahanya oache le mohloli oa 50MHz mme o hokahanya tlhahiso ho li-LED tse 'ne ho FPGA. Ho khetha sehlahisoa ho tsoa ho li-counter bits ka tatellano e itseng ho etsa hore li-LED li benye ka maqhubu a itseng.
    Setšoantšo sa 1. Flat Reference Design ntle le PR Partitioningintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-1

Moqapi oa Litšupiso Files

Thupelo ea ho lokisa bocha e fumaneha sebakeng se latelang: https://github.com/intel/fpga-partial-reconfig
Ho khoasolla thuto:

  1. Tobetsa Clone kapa download.
  2. Tobetsa Download ZIP. Unzip FPGA-partial-config-master.zip file.
  3. Tsamaea ho li-tutorials/a10_soc_devkit_blinking_led_hpr sub-folders ho fihlella moralo oa litšupiso.

Sephutheli se bataletseng se na le tse latelang files: 

Lethathamo la 1. Moqapi oa Litšupiso Files

File Lebitso Tlhaloso
holimo. SV Boemo bo holimo file e na le ts'ebetsong e bataletseng ea moralo. Mojule ona o tiisa karohano ea blinking_led le top_counter module.
top_counter.sv K'haonte ea boemo bo holimo ea 32-bit e laolang LED[1] ka kotloloho. Sephetho se ngolisitsoeng sa k'haontareng se laola LED[0], hape se matlafatsa LED[2] le LED[3] ka mojule oa blinking_led.
blinking_led.sdc E hlalosa litšitiso tsa nako bakeng sa morero.
e tsoela pele…
File Lebitso Tlhaloso
blinking_led.SV Thutong ena, o fetolela mojule ona ho ba karolo ea motsoali oa PR. Mojule o fumana tlhahiso e ngolisitsoeng ea top_counter module, e laolang LED[2] le LED[3].
blinking_led.qpf Morero oa mantlha oa Intel Quartus file e nang le lethathamo la lintlafatso tsohle tsa morero.
blinking_led.qsf Litlhophiso tsa Intel Quartus Prime file e nang le likabelo le litlhophiso tsa morero.

Hlokomela: Foldara ea hpr e na le sete e felletseng ea files o theha o sebelisa molaetsa ona oa kopo. Sheba tsena files ka nako efe kapa efe nakong ea ho tsamaea.

Setšoantšo sa 2. Moqapi oa Litšupiso Filesintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-2

Reference Design Walkthrough

Mehato e latelang e hlalosa ts'ebeliso ea tlhophiso e sa fellang ho moralo o bataletseng. Thupelo e sebelisa software ea Intel Quartus Prime Pro Edition bakeng sa boto ea nts'etsopele ea Intel Arria 10 SoC:

  • Mohato oa 1: Ho qala leqepheng la 6
  • Mohato oa 2: Theha Sub-Mojule ea Boemo ba Ngoana leqepheng la 6
  • Mohato oa 3: Ho theha likarolo tsa moralo leqepheng la 7
  • Mohato oa 4: Ho Abela Sebaka le Sebaka sa Tsamaiso bakeng sa Likarolo tsa PR leqepheng la 9
  • Mohato oa 5: Ho kenyelletsa Intel Arria 10 Setsi sa Reconfiguration Controller IP Core leqepheng la 10
  • Mohato oa 6: Ho Hlalosa Batho leqepheng la 13
  • Mohato oa 7: Ho theha Liphetoho leqepheng la 15
  • Mohato oa 8: Ho Hlahisa Sengoloa sa Phallo e Felletseng ea Sekheo se Felletseng leqepheng la 20
  • Mohato oa 9: Ho tsamaisa Sengoloa sa Phallo ea Karolo e Ntle ea Hierarchical leqepheng la 21
  • Mohato oa 10: Ho hlophisa Boto leqepheng la 22

Mohato oa 1: Ho Qala

Ho kopitsa moralo oa litšupiso files sebakeng sa hau sa ts'ebetso 'me u hlophise moralo oa sephara sa blinking_led:

  • Theha bukana sebakeng seo u sebetsang ho sona, a10_soc_devkit_blinking_led_hpr.
  • Kopitsa lithupelo tse jarollotsoeng/a10_soc_devkit_blinking_led_hpr/flat sub-folders bukeng, a10_soc_devkit_blinking_led_hpr.
  • Ho software ea Intel Quartus Prime Pro Edition, tobetsa File ➤ Open Project ebe u khetha blinking_led.qpf.
  • Ho hlophisa moralo o bataletseng, tobetsa Ho sebetsa ➤ Qala ho Kopanya.

Mohato oa 2: Ho theha Sub-mojule ea Boemo ba Ngoana

Ho fetolela moralo ona o bataletseng hore e be moralo oa maemo a holimo oa PR, o tlameha ho theha mojule o monyenyane oa ngoana (blinking_led_child. SV) o kentsoeng ka har'a mojule-potlana oa motsoali (blinking_led.sv).

  1. Etsa moralo o mocha file, blinking_led_child.sv, 'me u kenye mela e latelang ea khoutu ho sena file: timescale 1 ps / 1 ps `default_nettype none module blinking_led_child (// oache ea ho kenya oache, terata ea ho kenya [31:0] counter, // Laola matšoao a li-LEDintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-3intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-4
  2. Fetola blinking_led.sv file ho hokahanya led_two_on ho bit 23 ea k'haontareng ho tloha sebakeng se tsitsitseng, le ho tiisa mojule oa blinking_led_child. Ka mor'a liphetoho, blinking_led.sv ea hau file e tlameha ho hlaha ka tsela e latelang:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-5
  3. Ka ho fetola moralo oohle files, bokella morero hape ka ho tobetsa Ts'ebetso ➤ Qala Kopano

Mohato oa 3: Ho theha likarolo tsa moralo

U tlameha ho theha likarolo tsa moralo bakeng sa sebaka se seng le se seng sa PR seo u batlang ho se hlophisa bocha. O ka theha palo efe kapa efe ea likarolo tse ikemetseng kapa libaka tsa PR moqapong oa hau. Thupelo ena e theha likarolo tse peli tsa moralo bakeng sa maemo a u_blinking_led_child le u_blinking_led.
Ho theha li-partitions tsa moralo bakeng sa phetisetso ea karolo ea maemo a holimo:

  1. Tobetsa ka ho le letona mohlala oa u_blinking_led_child ho Project Navigator ebe u tobetsa Karolo ea Moqapi ➤ Beha e le Karolo ea Moralo. Letšoao la karohano ea moralo le hlaha haufi le ketsahalo ka 'ngoe e behiloeng joalo ka karohano.

Setšoantšo sa 3. Ho theha Likarolo tsa Moqapi ho tloha ho Project Navigatorintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-6

  1. Ho hlalosa Mofuta oa karohano, tobetsa ka ho le letona u_blinking_led_child ho tab ea Hierarchy, tobetsa Karolo ea Moqapi ➤ E Reconfigurable. O ka hlalosa feela Mofuta oa karohano ka mor'a ho beha mohlala joalo ka karohano. Karohano ea moralo e hlaha ho Mesebetsi View tab ya Fesetere ya Dikarolo tsa Moralo.

Setšoantšo sa 4. Fensetere ea Likarolo tsa Moqapiintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-7

  1. Fetola lebitso la karohano Fesetereng ea Likaroloana tsa Moralo ka ho tobetsa lebitso habeli. Bakeng sa moralo ona oa litšupiso, reha lebitso la karohano ho pr_partition.
    Hlokomela: Ha o theha karohano, software ea Intel Quartus Prime e iketsetsa lebitso la karohano, ho latela lebitso la mohlala le tsela ea maemo. Lebitso lena la karohano la kamehla le ka fapana ho latela mohlala ka mong.
  2. Pheta mehato ea 1 le ea 2 ho abela likarolo tsa meralo tse lokiselitsoeng ho mohlala oa u_blinking_led. Reha karolo ena bocha ho pr_parent_partition.
    Netefatsa hore blinking_led.qsf e na le mesebetsi e latelang, e tsamaellanang le likarolo tsa moralo tse lokisehang hape:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-8
Lintlha Tse Amanang

Theha Likarolo tsa Moralo bakeng sa Phetoho e 'Ngoe ea Karolo

Mohato oa 4: Ho Abela Sebaka le Sebaka sa Tsela bakeng sa Likarolo tsa PR

Ha o theha ntlafatso ea mantlha, phallo ea moralo oa PR e sebelisa kabo ea sebaka sa hau sa PR ho beha motheo o lumellanang oa motho sebakeng se boloketsoeng. Ho fumana le ho abela sebaka sa PR sebakeng sa meralo ea lisebelisoa bakeng sa tlhahlobo ea hau ea mantlha:

  1. Tobetsa ka ho le letona setšoantšong sa u_blinking_led_child ho Sebatli sa Morero ebe u tobetsa Sebaka sa Lock Lock ➤ Theha Sebaka se Secha sa Lock Lock. Sebaka sena se hlaha fensetereng ea Logic Lock Regions.
  2. Sebaka seo u leng ho sona se tlameha ho kenyeletsa blinking_led_child logic. Khetha sebaka seo u se behileng ka ho fumana node ho Chip Planner. Tobetsa ka ho le letona lebitsong la sebaka sa u_blinking_led_child ho Project Navigator ebe o tobetsa Fumana Node ➤ Fumana ho Chip Planner.
    Setšoantšo sa 5. Chip Planner Node Location bakeng sa blinking_ledintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-9
  3. Fensetereng ea Logic Lock Regions, hlakisa sebaka sa sebaka sa ho beoa khokahanyo kholumong ea Origin. Tšimoloho e lumellana le sekhutlo se ka tlaase ho le letšehali la sebaka seo. Bakeng sa mohlalaample, ho beha sebaka sa ho beoa ka (X1 Y1) likhokahano joalo ka (69 10), hlakisa Tšimoloho joalo ka X69_Y10. Software ea Intel Quartus Prime e ikemela ka bo eona (X2 Y2) likhokahano (holimo ka ho le letona) bakeng sa sebaka seo e beiloeng ho sona, ho latela bolelele le bophara boo u bo boletseng.
    Hlokomela: Thupelo ena e sebelisa likhokahano tsa (X1 Y1) - (69 10), le bolelele le bophara ba 20 bakeng sa sebaka sa ho beoa. Hlalosa boleng bofe kapa bofe bakeng sa sebaka seo ho behoang ho sona, ha feela sebaka se akaretsa blinking_led_child logic.
  4. Numella likhetho tsa Reserved le tsa Core-Feela.
  5. Tobetsa habeli khetho ea Sebaka sa Routing. Lebokose la puisano la Litlhophiso tsa Sebaka sa Logic Lock Routing lea hlaha.
  6. Kgetha E tsitsitseng le katoloso bakeng sa mofuta wa Routing. Ho khetha khetho ena ho fana ka bolelele ba katoloso ea 1.
    Hlokomela: Sebaka sa litsela se tlameha ho ba seholo ho feta sebaka seo ho behoang ho sona, ho fana ka maemo a eketsehileng bakeng sa Fitter ha enjene e tsamaisa batho ba fapaneng.
  7. Pheta mehato ea 1 -6 bakeng sa mohlala oa u_blinking_led. Ho beha boemo ba motsoali Pheta mehato ea 1 -6 bakeng sa mohlala oa u_blinking_led. Sebaka sa boemo ba motsoali se tlameha ho koala ka botlalo libaka tse tsamaellanang le boemo ba ngoana ha li ntse li lumella sebaka se lekaneng bakeng sa ho beha mabaka ho latela batsoali. Thupelo ena e sebelisa likhokahano tsa (X1 Y1) - (66 7), bolelele ba 47, le bophara ba 26 bakeng sa sebaka sa sebaka sa mohlala oa u_blinking_led.

Setšoantšo sa 6.Logic Lock Libaka Fesetereintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-10

Netefatsa hore blinking_led.qsf e na le mesebetsi e latelang, e tsamaellanang le floorplanning ea hau:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-11

Lintlha Tse Amanang
  • Etsa Moralo oa Phatlalatso ea Karolo e Ncha
  • Phethahatso e sa Feleng ea Phethahatso e sa Feleng

Mohato oa 5: Ho eketsa Intel Arria 10 Sekhetho sa Sebopeho sa Sebopeho sa IP Core

  • Sebelisa konokono ea IP ea Intel Arria 10 ea Karolo ea Reconfiguration Reconfiguration ho hlophisa bocha karohano ea PR. Setsi sena sa IP se sebelisa JTAG ho hlophisa bocha karohano ea PR. Ho kenyelletsa Intel Arria 10 Partial Reconfiguration Controller IP core morerong oa hau oa Intel Quartus Prime:
  1. Tlanya Reconfiguration ka Karolo e 'ngoe lethathamong la IP.
  2. Ho qala fensetere ea IP Parameter Editor Pro, khetha "Intel Arria 10 Partial Reconfiguration Controller IP core" ho laeborari ea IP, ebe o tobetsa Eketsa.
  3. Ka lebokoseng la puisano la New IP Variant, thaepa pr_ip joalo ka file lebitso ebe o tobetsa Create. Sebelisa parameterization ea kamehla bakeng sa pr_ip. Netefatsa hore Enable JTAG Debug mode 'me E nolofalletsa likhetho tsa sehokelo sa freeze lia buloa, 'me Enable Avalon-MM slave interface e koetsoe.

Setšoantšo sa 7. Intel Arria 10 Molaoli oa Phatlalatso ea Karolo ea IP Core Parametersintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-12

  1. Tobetsa Qetella, 'me u tsoe ho parameter ntle le ho hlahisa sistimi. Software ea Intel Quartus Prime e theha pr_ip.ip IP ho fapana file, mme e eketsa le file ho morero oa blinking_led.

Hlokomela:

  1. Haeba u kopitsa pr_ip.ip file ho tsoa ho sephutheli sa hpr, ka bowena fetola blinking_led.qsf file ho kenyelletsa mola o latelang: set_global_assignment -name IP_FILE pr_ip.ip
  2. Beha IP_FILE mosebetsi ka mora SDC_FILE likabelo (jtag.sdc le blinking_led.sdc) ho blinking_led.qsf ea hau file. Taelo ena e netefatsa tšitiso e nepahetseng ea mantlha ea IP ea Phetoho e Ncha.
    Hlokomela: Ho lemoha lioache, SDC file hobane PR IP e tlameha ho latela SDC efe kapa efe e etsang lioache tseo IP core e li sebelisang. U tsamaisa taelo ena ka ho netefatsa hore .ip file bakeng sa PR IP core e tla ka mor'a leha e le efe .ip files kapa SDC files sebelisoa ho theha lioache tsena ho QSF file bakeng sa ntlafatso ea projeke ea hau ea Intel Quartus Prime. Bakeng sa tlhaiso-leseling e batsi, sheba karolo ea Thiming Constraints ho Tataiso ea Mosebelisi ea Phethahatso e sa Feleng ea IP.

Lintlha Tse Amanang

  • Tataiso ea Mosebelisi ea Litharollo tsa IP tsa Reconfiguration
    • Bakeng sa tlhaiso-leseling e mabapi le karolo ea IP ea Molaoli oa Sebaka sa Litlhophiso tsa Karolo.
  • Tataiso ea Mosebelisi ea Phethahatso e sa Feleng ea IP Core
    • Bakeng sa lintlha tse mabapi le litšitiso tsa nako.
Ho Nchafatsa Moralo oa Boemo bo Phahameng

Ho nchafatsa holimo.SV file ka mohlala oa PR_IP:

  1. Ho kenya mohlala oa PR_IP moralong oa boemo bo holimo, hlakola khoutu e latelang ka holimo.SV file:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-13
  2. Ho qobella likou tsa tlhahiso ho logic 1 nakong ea peakanyo bocha, sebelisa lets'oao la ho emisa ho tsoa ho PR_IP. Leha ho le joalo, ho bona LED e tsoela pele ho panya ho tloha karolong ea motsoali ea PR ha PR e ntse e hlophisa karohano ea bana, lets'oao la ho laola ho hoama ha le tima led_two_on. Netefatsa hore pr_led_two_on e nepahetse intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-14
  3. Ho abela mohlala oa motho ea kamehla oa motsoali (blinking_led), nchafatsa top.SV file ka boloko e latelang ea khoutu: intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-15

Setšoantšo sa 8. Tšebeliso e sa Feleng ea IP Core Integrationintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-16

Mohato oa 6: Ho Hlalosa Batho

Moralo ona oa litšupiso o hlalosa batho ba bahlano ba arohaneng bakeng sa likarolo tsa PR tsa motsoali le ngoana. Ho hlalosa le ho kenyelletsa batho ba projeke ea hau:

  1. Etsa tse 'nè SystemVerilog files, blinking_led_child.sv, blinking_led_child_slow.sv, blinking_led_child_empty.sv, le blinking_led_slow.sv bukeng ea hau ea ho sebetsa bakeng sa batho ba bahlano.
    Hlokomela: Haeba u theha SystemVerilog files ho tsoa ho Intel Quartus Prime Text Editor, thibela Add file ho ea hona joale morero kgetho, ha ho boloka le files.

Lethathamo la 2. Reference Design Personas

File Lebitso Tlhaloso Khoutu
blinking_led_child.sv Sebopeho sa kamehla bakeng sa moralo oa boemo ba ngoana  

`nako ea nako 1 ps / 1 maq

`Default_nettype none module blinking_led_child (

// oache

ho kenya oache ea mohala,

terata e kenang [31:0] counter,

 

// Laola matšoao bakeng sa terata e hlahisoang ke LED led_three_on

 

);

localparam COUNTER_TAP = 23; reg led_three_on_r;

 

abela led_three_on = led_three_on_r; always_ff @(podge clock) qala

led_three_on_r <= counter[COUNTER_TAP]; QETA

 

endmodule
e tsoela pele…
File Lebitso Tlhaloso Khoutu
blinking_led_child_slow.sv The

LED_THARO

panya butle

  

`nako ea nako 1 ps / 1 maq

`Default_nettype ha ho letho

 

mojule blinking_led_child_butle (

 

// oache

ho kenya oache ea mohala,

terata e kenang [31:0] counter,

 

// Laola matšoao bakeng sa terata e hlahisoang ke LED led_three_on

);

 

localparam COUNTER_TAP = 27; reg led_three_on_r;

 

abela led_three_on = led_three_on_r; always_ff @(podge clock) qala

led_three_on_r <= counter[COUNTER_TAP];

QETA

 

endmodule
blinking_led_child_empty.sv The

LED_THARO

lula ON

  

`nako ea nako 1 ps / 1 maq

`Default_nettype ha ho letho

 

module blinking_led_child_letho (

 

// oache

ho kenya oache ea mohala,

terata e kenang [31:0] counter,

 

// Laola matšoao bakeng sa terata e hlahisoang ke LED led_three_on

 

);

 

// LED e sebetsa ka tlase

abela led_three_on = 1'b0;

 

endmodule
blinking_led_slow.sv LED_TWO

panya butle.

  

`nako ea nako 1 ps / 1 maq

`Default_nettype none module blinking_led_slow(

// oache

ho kenya oache ea mohala,

terata e kenang [31:0] counter,

 

// Laola matšoao bakeng sa terata e hlahisoang ke LED e led_two_on,

terata ya tlhahiso led_three_on

 

);

 

localparam COUNTER_TAP = 27; reg led_two_on_r;

abela led_two_on = led_two_on_r;

 

// K'hamphani:

always_ff @(posedge clock) qala led_two_on_r <= counter[COUNTER_TAP];

QETA

 

ngoana_ea panya-panyang

.lebisitsoe_tse_tse_tse_tsararo,

.counter (counter),

.oache (ts'ebetso)
File Lebitso Tlhaloso Khoutu
); mojule
Lintlha Tse Amanang

Mohato oa 3: Ho theha likarolo tsa moralo leqepheng la 7

Mohato oa 7: Etsa Liphetoho

Phallo ea moralo oa PR e sebelisa karolo ea ntlafatso ea projeke ho software ea Intel Quartus Prime. Moralo oa hau oa pele ke ntlafatso ea mantlha, moo o hlalosang meeli ea sebaka se sa fetoheng le libaka tse ka lokisoang bocha ho FPGA. Ho tsoa tlhahlobong ea mantlha, u theha lintlafatso tse ngata. Lintlafatso tsena li na le ts'ebetsong e fapaneng bakeng sa libaka tsa PR. Leha ho le joalo, lintlafatso tsohle tsa ts'ebetso ea PR li sebelisa liphetho tse tšoanang tsa boemo bo holimo le liphetho tsa tlhahlobo ea mantlha. Ho hlophisa moralo oa PR, o tlameha ho theha tlhahlobo ea ts'ebetsong ea PR le tlhahlobo ea sebopeho bakeng sa motho ka mong. Moqaping ona oa litšupiso, ntle le tokiso ea motheo (blinking_led), batho ba bararo ba boemo ba bana le batho ba babeli ba boemo ba batsoali ba na le lintlafatso tse hlano tse arohaneng le liphetoho tse hlano tse arohaneng tsa ts'ebetsong:
Lethathamo la 3. Liphetoho bakeng sa Batho ba Batsoali ba babeli le Batho ba Bana ba Bararo

Synthesis Revision Phethahatso ea Phethahatso
motsoali_ea_ea_ea_ho panya, ea_le_le_le_le_le_mohau blinking_led_pr_alpha
Motsoali_ea_ea_ea_ea_ea panyang, ngoana_ea panyang_ea liehang blinking_led_pr_bravo
Motsoali_ea_ea_ea_ea_ea panyang, ngoana_ea panyang_ha a na letho blinking_led_pr_charlie
panya_eled_motsoali_ea liehang, ea panyang_ea lepeletsoeng_ngoana_ea liehang blinking_led_pr_delta
panya_eled_motswadi_e butle, ngwana_ea panyang_a se nang letho blinking_led_pr_emma

Ho theha Liphetoho tsa Phethahatso

Ho theha lintlafatso tsa ts'ebetsong ea PR:

  1. Ho bula lebokose la lipuisano la Revisions, tobetsa Morero ➤ Liphetoho.
  2. Ho theha phetolelo e ncha, tobetsa habeli < >.
  3. Hlalosa lebitso la Phetolelo e le blinking_led_pr_alpha 'me u khethe blinking_led bakeng sa Based on Revision.
  4. Tlosa Setha joalo ka khetho ea hajoale ea ntlafatso ebe o tobetsa OK.
  5. Ka mokhoa o ts'oanang, etsa lintlafatso tsa blinking_led_pr_bravo, blinking_led_pr_charlie, blinking_led_pr_delta, le blinking_led_pr_emma lintlafatso, ho ipapisitsoe le tokiso ea blinking_led.
    Hlokomela: Se ke oa beha lintlafatso tse kaholimo e le tsa hajoale.

Setšoantšo sa 9. Ho theha Liphetohointel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-17

Ho theha Liphetoho tsa Synthesis-Feela

Ho theha lintlafatso tsa synthesis-feela bakeng sa batho, o tlameha ho abela setheo sa boemo bo holimo le SystemVerilog e tsamaellanang. file bakeng sa motho e mong le e mong:

  1. Ho software ea Intel Quartus Prime, tobetsa Project ➤ Revisions.
  2. Etsa tlhahlobo ea blinking_led_default ho latela tlhahlobo ea blinking_led. Se ke oa beha ntlafatso ena e le ea hajoale.
  3. Fetola blinking_led_default.qsf file ho kenyelletsa mesebetsi e latelang:
    set_global_assignment -lebitso TOP_LEVEL_ENTITY blinking_led_child
    set_global_assignment -lebitso SYSTEMVERILOG_FILE
  4. Ka mokhoa o ts'oanang, etsa lintlafatso tsa blinking_led_child_slow, blinking_led_child_leption, blinking_led_parent, le blinking_led_parent_conds liphetolelo tse thehiloeng ho blinking_led revision. Se ke oa beha lintlafatso tsena e le lintlafatso tsa hajoale.
  5. Kaonefatsa blinking_led_child_slow.qsf, blinking_led_child_empty.qsf, blinking_led_parent.qsf, le blinking_led_parent_slow.qsf files le tsona tse ngollanang
    TOP_LEVEL_ENTITY le SYSTEMVERILOG_FILE likabelo: intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-18
  6. Ho qoba liphoso tsa synthesis, etsa bonnete ba hore tlhahlobo ea synthesis fileLi-partitions tsa bana ha li na karohano ea moralo, likabelo tsa phini, kapa Logic Lock.
    likabelo tsa libaka. Hape, ntlafatso ea synthesis files bakeng sa likarolo tsa motsoali li tlameha ho ba le likabelo tsa likarolo tsa moralo bakeng sa likarolo tse tsamaellanang tsa bana. Tlosa likabelo tsena, haeba li teng, ho blinking_led_default.qsf, blinking_led_child_slow.qsf, blinking_led_child_empty.qsf, blinking_led_parent.qsf, le blinking_led_parent_slow.pdf filesintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-19
  7. Kenyelletsa likabelo tse latelang ho blinking_led_parent.qsf le blinking_led_parent_slow.qsf files: intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-20
  8. Netefatsa hore blinking_led.qpf file e na le lintlafatso tse latelang, ha ho tatellano e itseng:
  • intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-21
  • Hlokomela: Haeba u ntse u kopitsa phetolelo files ho tsoa ho hpr foldareng, ka bowena ntjhafatsa blinking_led.qpf file ka mela e ka holimo ea khoutu.

E Hlalosa Mofuta oa Phetoho

U tlameha ho fana ka mofuta oa ntlafatso bakeng sa e 'ngoe le e 'ngoe ea lintlafatso tsa hau. Ho na le mefuta e meraro ea ntlafatso:

  • Phetoho e sa Feleng - Motheo
  • Phetoho e 'Ngoe e sa Feleng - Persona Synthesis
  • Phetoho e sa Lekaneng - Phethahatso ea Motho
  • Tafole e latelang e thathamisa likabelo tsa mofuta oa ntlafatso bakeng sa e 'ngoe le e 'ngoe ea lintlafatso:

Lethathamo la 4. Mefuta ea Phetoho

Lebitso la Phetoho Mofuta oa ntlafatso
blinking_led.qsf Phetoho e sa Feleng - Motheo
blinking_led_default.qsf Phetoho e 'Ngoe e sa Feleng - Persona Synthesis
blinking_led_child_empty.qsf Phetoho e 'Ngoe e sa Feleng - Persona Synthesis
blinking_led_child_slow.qsf Phetoho e 'Ngoe e sa Feleng - Persona Synthesis
blinking_led_parent.qsf Phetoho e 'Ngoe e sa Feleng - Persona Synthesis
blinking_led_parent_slow.qsf Phetoho e 'Ngoe e sa Feleng - Persona Synthesis
blinking_led_pr_alpha.qsf Phetoho e sa Lekaneng - Phethahatso ea Motho
blinking_led_pr_bravo.qsf Phetoho e sa Lekaneng - Phethahatso ea Motho
blinking_led_pr_charlie.qsf Phetoho e sa Lekaneng - Phethahatso ea Motho
blinking_led_pr_delta.qsf Phetoho e sa Lekaneng - Phethahatso ea Motho
blinking_led_pr_emma.qsf Phetoho e sa Lekaneng - Phethahatso ea Motho
  1. Tobetsa Morero ➤ Liphetoho. Lebokose la lipuisano la Revisions lea hlaha.
  2. Khetha blinking_led ka har'a Kholumo ea Lebitso la Revision, ebe o tobetsa Set Current.
  3. Tobetsa Etsa kopo. Blinking_led revision ea bula.
  4. Ho seta mofuta oa ntlafatso bakeng sa blinking_led, tobetsa Mosebetsi ➤ Litlhophiso ➤ Kakaretso.
  5. Khetha Mofuta oa Phetoho joalo ka Phetoho e sa Feleng - Base.
  6. Ka mokhoa o ts'oanang, beha mefuta ea ntlafatso bakeng sa litokiso tse ling tse leshome, joalo ka ha li thathamisitsoe tafoleng e kaholimo.
  • Hlokomela: U tlameha ho seta ntlafatso e 'ngoe le e' ngoe e le ea morao-rao pele u abela mofuta oa ntlafatso. Netefatsa hore e 'ngoe le e 'ngoe .qsf file e na le mosebetsi o latelang: intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-22
  • Hlokomela: Kenya litlhophiso life kapa life tse ikhethileng tsa Fitter tseo u batlang ho li sebelisa molemong oa ho kenya tšebetsong PR ho lintlafatso tsa ts'ebetso ea motho. Litlhophiso tse ikhethileng tsa Fitter li ama ho lekana ha motho, empa ha li ame sebaka se sa fetoheng se tsoang kantle ho naha. U ka boela ua kenya litlhophiso life kapa life tse ikhethileng tsa synthesis ho lintlafatso tsa motho ka mong.
Lintlha Tse Amanang

Etsa Liphetoho bakeng sa Batho

Mohato oa 8: E Hlahisa Mongolo oa Phallo ea Phallo ea Karolo ea Hierarchical

Ho hlahisa sengoloa sa maemo a holimo sa phepelo ea tlhophiso:

  1. Ho tsoa ho Intel Quartus Prime command shell, theha template ea phallo ka ho sebelisa taelo e latelang:
  2. Intel Quartus Prime e hlahisa a10_hier_partial_reconfig/flow.tcl file.intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-23
  3. Reha lebitso bocha a10_hier_partial_reconfig/setup.tcl.exampLebisa ho a10_hier_partial_reconfig/setup.tcl, 'me u fetole sengoloa ho hlakisa lintlha tse sa fellang tsa projeke ea hau:
    a. Ho hlalosa lebitso la morero, ntlafatsa mola o latelang:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-24b. Ho hlalosa phetolelo ea motheo, ntlafatsa mola o latelang:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-25
  4. Ho hlalosa e 'ngoe le e 'ngoe ea lintlafatso tse ling tsa ts'ebetso ea tlhophiso, hammoho le mabitso a karohano ea PR le ntlafatso ea mohloli e sebelisang lintlafatso, ntlafatsa mela e latelang:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-26

Hlokomela: Mesebetsi eohle ea ntlafatso e tlameha ho ba bukeng e tšoanang le blinking_led.qpf. Ho seng joalo, ntlafatsa script ka tsela e nepahetseng.intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-27

Mohato oa 9: E tsamaisa Sengoloa sa Phallo ea Karolo ea Hierarchical Partial Reconfiguration

Ho tsamaisa sengoloa sa tlhabollo ea karolo ea maemo a holimo:

  1. Tobetsa Lisebelisoa ➤ Tcl Mengolo. Lebokose la puisano la Tcl Scripts lea hlaha.
  2. Tobetsa Eketsa ho Morero, sheba 'me u khethe a10_hier_partial_reconfig/flow.tcl.
  3. Kgetha a10_hier_partial_reconfig/flow.tcl fenstereng ya Libraries, ebe o tobetsa Matha.
    Mongolo ona o tsamaisa pokello ea batho ba bararo. Intel Quartus Prime e hlahisa Ntho ea SRAM File (.sof), Sesebediswa sa SRAM se Apehilweng ka Karolo File (.pmsf), le Binary e tala File (.rbf) bakeng sa motho ka mong.

Tlhokomeliso: Ho tsamaisa sengoloa ho tsoa ho khetla ea taelo ea Intel Quartus Prime, thaepa taelo e latelang:

Lintlha Tse Amanang

  • Kopanya Moralo oa Phetoho e Ncha
  • Ho sebelisa Sengoloa sa Phallo ea Karolo ea Reconfiguration
  • Ho lokisa Sengoloa sa Phallo ea Phethahatso e sa Feleng
  • Hlahisa Programming Files

Mohato oa 10: Lenaneo la Boto

Pele o qala:

  1. Hokela phepelo ea motlakase ho boto ea nts'etsopele ea Intel Arria 10 SoC.
  2. Hokela thapo ea USB Blaster pakeng tsa koung ea USB ea PC ea hau le kou ea USB Blaster botong ea nts'etsopele.

Ho tsamaisa moralo ho boto ea nts'etsopele ea Intel Arria 10 SoC:

  1. Bula software ea Intel Quartus Prime ebe o tobetsa Tools ➤ Programmer.
  2. Ho Programmer, tobetsa Setupo sa Hardware ebe u khetha USB-Blaster.
  3. Tobetsa Auto Detect ebe u khetha sesebelisoa, 10AS066N3.
  4. Tobetsa OK. Software ea Intel Quartus Prime e lemoha le ho nchafatsa Programmer ka li-chips tse tharo tsa FPGA botong.
  5. Khetha sesebelisoa sa 10AS066N3, tobetsa Fetola File ebe o kenya blinking_led_pr_alpha.sof file.
  6. Numella Lenaneo/Configure bakeng sa blinking_led_pr_alpha.sof file.
  7. Tobetsa Qala 'me u emetse hore sebaka sa tsoelo-pele se fihle ho 100%.
  8. Sheba li-LED tse botong li ntse li panya ka makhetlo a tšoanang le a moralo oa pele o bataletseng.
  9. Ho etsa lenaneo feela sebakeng sa PR sa bana, tobetsa ka ho le letona ho blinking_led_pr_alpha.sof file ho Programmer ebe o tobetsa Add PR Programming File.
  10. Khetha blinking_led_pr_bravo.pr_parent_partition.pr_partition.rbf file.
  11. Thibela Lenaneo/Configure bakeng sa blinking_led_pr_alpha.sof file.
  12. Numella Lenaneo/Configure bakeng sa blinking_led_pr_bravo.pr_parent_partition.pr_partition.rbf file ebe o tobetsa Qala. Holima boto, sheba LED[0] le LED[1] li tsoela pele ho panya. Ha sebaka sa tsoelo-pele se fihla ho 100%, LED[2] e panya ka lebelo le tšoanang, 'me LED[3] e panya butle.
  13. Ho etsa mananeo a sebaka sa PR sa motsoali le ngoana, tobetsa ka ho le letona ho .rbf file ho Programmer ebe o tobetsa Change PR Programing File.
  14. Khetha blinking_led_pr_delta.pr_parent_partition.rbf file.
  15. Tobetsa Qala. Holima boto, hlokomela hore LED[0] le LED[1] li ntse li tsoela pele ho panya. Ha sebaka sa tsoelopele se fihla ho 100%, LED[2] le LED[3] li panya butle.
  16. Pheta mehato e kaholimo ho hlophisa bocha sebaka sa PR sa ngoana, kapa libaka tsa PR tsa motsoali le ngoana ka nako e le 'ngoe.

Setšoantšo sa 10. Lenaneo la Intel Arria 10 SoC Development Boardintel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-28

Ho Fetola Motho ea Teng

  • U ka fetola motho ea seng a ntse a le teng, le ka mor'a ho bokella ka botlalo phetolelo ea motheo.
  • Bakeng sa mohlalaample, ho etsa hore blinking_led_child_slow persona ho panye le ho feta:
  1. Ho blinking_led_child_slow.sv file, fetola COUNTER_TAP parameter ho tloha ho 27 ho isa ho 28.
  2. Ho kopanya hape le ho kenya ts'ebetsong motho ona hape, o tlameha ho bokella lintlafatso tsohle tsa synthesis-feela le litokiso tsa ts'ebetsong tse anngoeng ke phetoho. Fetola sengoloa sa setup.tcl ho kenyelletsa mela e latelang:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-29Hlokomela: Ha u hlalosa pr_parent_parition bakeng sa blinking_led_pr_delta revision, o kenya setšoantšo sa ho qetela sa motho eo bakeng sa ts'ebetsong. Ka lebaka leo, ts'ebetsong ea logic ea karohano ea motsoali e ntse e tšoana, ha e ntse e fetola le ho kenya ts'ebetsong karohano e lumellanang ea bana.intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-30 Taelo ena e kopanya bocha blinking_led_child_slow synthesis revision, ebe e tsamaisa pokello ea ts'ebetso ea PR e sebelisa blinking_led_pr_bravo.
  3. Ho etsa pokello ea lintlafatso tsa li-synthesis-feela, tsamaisa taelo e latelang: Taelo ena ha e bokelle phetolelo ea motheo.intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-32
  4. Ho etsa pokello ea lintlafatso tsa ts'ebetsong, tsamaisa taelo e latelang:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-32
  5. Taelo ena ha e boele e ntlafatse phetolelo ea motheo.
  6. Latela mehato e Mohatong oa 10: Ho hlophisa Boto leqepheng la 22 ho hlophisa RBF e hlahisoang file ho FPGA.
    Hlokomela: Ho qoba ho tsamaisa phallo eohle bakeng sa tokiso e 'ngoe le e 'ngoe, hlalosa lintlafatso tsa synthesis-feela le lintlafatso tsa ts'ebetsong ho setup.tcl script, 'me u tsamaise mongolo.

Ho Eketsa Motho e Mocha Moahong

Kamora ho hlophisa lintlafatso tsa hau ka botlalo, o ntse o ka eketsa batho ba bacha 'me ka bomong oa bokella batho bana.
Bakeng sa mohlalaample, ho hlalosa ngoana e mocha bakeng sa blinking_led_parent_slow, e timang led_three:

  1. Kopitsa blinking_led_child_empty.sv ho blinking_led_chdild_off.sv.
  2. Ho blinking_led_child_off.sv file, fetola kabelo, abela led_three_on = 1'b0; ho abela led_three_on = 1'b1;. Netefatsa hore o fetola lebitso la karolo ho tloha ho blinking_led_child_empty ho ea blinking_led_child_off.
  3. Theha phetolelo e ncha, blinking_led_child_off, ka ho latela mehato ea ho Etsa Liphetoho tsa Synthesis-Feela leqepheng la 16.
    Hlokomela: Phetolelo ea blinking_led_child_off e tlameha ho sebelisa blinking_led_child_off.sv file.
  4. Theha ntlafatso e ncha ea ts'ebetsong, blinking_led_pr_foxtrot, ka ho latela mehato ea ho Etsa Liphetoho tsa Ts'ebetsong leqepheng la 15.
  5. Nchafatsa a10_hier_partial_reconfig/setup.tcl file ho hlalosa ts'ebetsong e ncha ea PR:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-33
  6. Kopanya feela tlhabollo ena e ncha le ts'ebetsong ka ho sebelisa taelo e latelang:intel-AN-805-Hierarchical-Partial-Reconfiguration-of-a-Design-on-Arria-10-SoC-Development-Board-FIG-34

Bakeng sa tlhaiso-leseling e felletseng mabapi le phetisetso ea karolo ea maemo a holimo bakeng sa lisebelisoa tsa Intel Arria 10, sheba ho Ho theha Moralo oa Phetoho e Ntle ho Bolumo 1 ea Intel Quartus Prime Pro Edition Handbook.

Lintlha Tse Amanang

  • Ho theha Moralo oa Phetoho e sa Feleng
  • Karolo e sa Feleng Reconfiguration Online Koetliso

Nalane ea Phetoho ea Litokomane

Tafole ea 5. Nalane ea Nchafatso ea Tokomane

Tokomane Version Software Software Liphetoho
2017.11.06 17.1.0 • Ntjhafatswa Litlhoko tsa Moralo oa Reference karolo e nang le mofuta oa software

• Ntjhafatswa Flat Reference Design ntle le PR Partitioning setšoantšo se nang le liphetoho tsa block block

• Ntjhafatswa Moqapi oa Litšupiso Files tafole e nang le tlhahisoleseding e mabapi le

Top_counter.sv module

• Ntjhafatswa Phetoho e sa Feleng ea Kopano ea IP Core setšoantšo se nang le liphetoho tsa block block

• E ntlafalitse lipalo- Moralo Partitions Window le Logic Lock Libaka Fesetere ho bonahatsa GUI e ncha

•    File mabitso a fetoha

• Liphetoho tsa mongolo
2017.05.08 17.0.0 Phatlalatso ea pele ea tokomane

Litokomane / Lisebelisoa

intel AN 805 Hierarchical Partial Reconfiguration of a Design on Arria 10 SoC Development Board [pdf] Bukana ea Mosebelisi
AN 805 Hierarchical Partial Reconfiguration of a Design on Arria 10 SoC Development Board, AN 805, Hierarchical Partial Reconfiguration of Design on Arria 10 SoC Development Board, Reconfiguration of Design on Arria 10 SoC Development Board, Arria 10 SoC Development Board, 10 SoC Boto ea Nts'etsopele

Litšupiso

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