Interlaken (Augatupulaga Lona Lua) Intel ®
Agilex™ FPGA IP Design Example
Fa'aoga Taiala

Taiala vave amata

O le Interlaken (2nd Generation) FPGA IP autu e maua ai se suʻega faʻataʻitaʻiga ma se faʻataʻitaʻiga meafaigaluegaampe lagolagoina le tu'ufa'atasiga ma su'ega meafaigaluega. A e gaosia le mamanu example, e otometi lava ona fatuina e le faatonu parameter le files e manaʻomia e faʻataʻitaʻi, faʻapipiʻi, ma suʻe le mamanu i meafaigaluega. Le mamanu exampo lo'o avanoa fo'i mo le Interlaken Look-aside feature.
Le su'ega ma le mamanu exampe lagolagoina le NRZ ma le PAM4 mode mo masini E-tile. O le Interlaken (2nd Generation) FPGA IP autu e fa'atupuina fa'ata'ita'igaamples mo tu'ufa'atasiga lagolago uma o numera o laina ma fua fa'amaumauga.

Ata 1. Laasaga Atina'e mo le Fuafuaga Example

Le Interlaken (Augatupulaga lona lua) IP mamanu autu example lagolagoina vaega nei:

• TX i totonu i le RX faasologa loopback mode
• Otometi ona fa'atupu fa'aputu lapopo'a
• Gafatia masani siaki siaki
• Malosiaga e fa'aoga ai le System Console e toe setiina ai le mamanu mo le toe su'ega
• PMA fetuutuunaiga

Ata 2. Fa'ailoga Poloka maualuga mo Interlaken (Augatupulaga Lona Lua) Design Example

Fa'amatalaga Fa'atatau

• Interlaken (Augatupulaga Lona Lua) FPGA IP User Guide
• Interlaken (Augatupulaga Lona Lua) Intel FPGA IP Fa'amatalaga Fa'amatalaga

1.1. Meafaigaluega ma Polokalama Manaoga
Ina ia tofotofoina le example mamanu, faʻaaoga meafaigaluega ma polokalama nei:

• Intel® Prime Pro Edition polokalama faakomepiuta version 21.3
• System Console
• Simulators lagolago:
  - Siemens * EDA ModelSim * SE poʻo QuestaSim *
  — Synopsys* VCS*
  — Cadence* Xcelium*
• Intel Agilex® Quartus™ F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Fa'amatalaga Fa'atatau
Intel Agilex F-Series Transceiver-SoC Development Kit Guide Guide
1.2. Fa'atonuga Fa'atonu
Le Interlaken (Augatupulaga lona lua) IP mamanu autu example file fa'atonuga o lo'o i ai mea nei na gaosia files mo le mamanu example.
Ata 3. Fa'asologa o Fa'atonuga o le Generated Interlaken (2nd Generation) Example Lisiina

Le faʻatulagaina o meafaigaluega, faʻataʻitaʻiga, ma suʻega files o loʻo i totonuample_installation_dir>/uflex_ilk_0_example_design.
Laulau 1. Interlaken (Augatupulaga Lona Lua) IP Core Hardware Design Example File Fa'amatalaga
O nei files i totonu o leample_installation_dir>/uflex_ilk_0_example_design/ example_design/quartus directory.

File Igoa	Fa'amatalaga
example_design.qpf	Poloketi Intel Quartus Prime file.
example_design.qsf	Fa'atonuga ole poloketi Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc	Synopsys Design Fa'agata file. E mafai ona e kopiina ma sui mo lau lava mamanu.
sysconsole_testbench.tcl	Autu file mo le mauaina o le System Console

Laulau 2. Interlaken (2nd Generation) IP Core Testbench File Fa'amatalaga
Lenei file o lo'o i totonu o leample_installation_dir>/uflex_ilk_0_example_design/ example_design/rtl directory.

File Igoa	Fa'amatalaga
top_tb.sv	Tulaga maualuga su'ega file.

Laulau 3. nterlaken (2nd Generation) IP Core Testbench Scripts
O nei files i totonu o leample_installation_dir>/uflex_ilk_0_example_design/ example_design/testbench directory.

File Igoa	Fa'amatalaga
vcstest.sh	Le VCS tusitusiga e faʻatautaia le suʻega suʻega.
vlog_pro.do	O le ModelSim SE poʻo le QuestaSim script e faʻatautaia le suʻega suʻega.
xcelium.sh	Le tusitusiga Xcelium e faʻatautaia le suʻega suʻega.

1.3. Fuafuaga Meafaigaluega Example Vaega
O le example mamanu feso'ota'i faiga ma PLL fa'asino uati ma vaega mamanu mana'omia. O le example mamanu configures le IP autu i totonu loopback mode ma gaosia afifi i luga o le IP autu TX tagata faʻafesoʻotaʻi faʻamatalaga faʻamatalaga. O le IP autu e auina atu nei afifi i luga o le auala loopback i totonu e ala i le transceiver.
A maeʻa ona maua e le IP core receiver ia paʻu i luga o le auala loopback, na te faʻagasolo le Interlaken packet ma faʻasalalau atu i luga o le RX user data transfer interface. O le example mamanu siaki na maua ma auina atu e fetaui.
O meafaigaluega example mamanu e aofia ai PLLs fafo. E mafai ona e suʻesuʻeina le tusitusiga manino files ia view sample code lea e faʻaaogaina se tasi auala e mafai ona faʻafesoʻotaʻi PLLs fafo i le Interlaken (2nd Generation) FPGA IP.
O le Interlaken (2nd Generation) mea faigaluega fa'ata'ita'igaample aofia ai vaega nei:

1. Interlaken (Augatupulaga Lona Lua) FPGA IP
2. Fa'atupu Fa'aputu ma le Su'esu'ega
3. JTAG pule e feso'ota'i ma System Console. E te fa'afeso'ota'i ma le tagata o tausia e ala i le System Console.

Ata 4. Interlaken (Augatupulaga Lona Lua) Fuafuaga Meafaigaluega Example Fa'ata'ita'iga Poloka Tulaga Maualuga mo E-tile NRZ Faiga Fa'asologa

O le Interlaken (2nd Generation) mea faigaluega fa'ata'ita'igaampO le fa'amoemoeina o le E-tile PAM4 mode fesuiaiga e mana'omia ai se uati fa'aopoopo mac_clkin e gaosia e le IO PLL. O lenei PLL e tatau ona faʻaogaina le uati faʻasino tutusa e faʻaulu ai le pll_ref_clk.

Ata 5. Interlaken (Augatupulaga Lona Lua) Fuafuaga Meafaigaluega Example Tulaga Maualuga
Ata poloka mo E-tile PAM4 Faiga Fa'asologa

Mo suiga ole faiga ole E-tile PAM4, pe a e mafaia le Fa'asao le fa'aaogaina o alalaupapa transceiver mo le PAM4 parakalafa, e fa'aopoopoina se isi uati fa'asinoga uati (pll_ref_clk [1]). O lenei uafu e tatau ona ave i le taimi tutusa e pei ona faʻamatalaina i le faʻatonuina o le IP (Faʻasinoga taimi o le uati mo auala faʻasaoina). O le Fa'asao le fa'aogaina o alaleo transceiver mo PAM4 e filifili. O le pine ma faʻalavelave faʻapitoa e tuʻuina atu i lenei uati e iloa i le QSF pe a e filifilia le Intel Stratix® 10 poʻo le Intel Agilex development kit mo le gaosiga o mamanu.
Mo mamanu exampI le fa'ata'ita'iga, o le su'ega e fa'amatalaina i taimi uma le taimi tutusa mo pll_ref_clk[0] ma pll_ref_clk[1].
Fa'amatalaga Fa'atatau
Intel Agilex F-Series Transceiver-SoC Development Kit Guide Guide
1.4. Fausiaina o le Fuafuaga

Ata 6. Taualumaga

Mulimuli i laasaga nei e fa'atupuina ai meafaigaluega e iaiample mamanu ma su'ega:

1. I le polokalama Intel Quartus Prime Pro Edition, kiliki File ➤ New Project Wizard e fatu ai se poloketi fou Intel Quartus Prime, pe kiliki File ➤ Tatala Poloketi e tatala ai se poloketi Intel Quartus Prime. E fa'atonu oe e le wizard e fa'ailoa se masini.
2. Fa'ailoa le masini aiga Agilex ma filifili masini mo lau mamanu.
3. I le IP Catalog, su'e ma fa'alua-kiliki Interlaken (2nd Generation) Intel FPGA IP. Ua aliali mai le fa'amalama New IP Variant.
4. Fa'ailoa se igoa pito i luga mo lau suiga masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .ip.
5. Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
   Ata 7. Esample Design Tab i le Interlaken (2nd Generation) Intel FPGA IP Parameter Editor
6. I luga o le IP tab, faʻamaonia le faʻasologa mo lau fesuiaiga autu IP.
7. I luga o le PMA Adaptation tab, faʻamaonia le PMA fetuunaiga faʻamaufaʻailoga pe afai e te fuafua e faʻaoga PMA fetuunaiga mo au fesuiaiga masini E-tile.
   Ole la'asaga lea e filifili iai:
   • Filifili le Enable adaptation load soft IP filifiliga.
   Fa'aaliga: E tatau ona e fa'aagaoioi le Native PHY Debug Master Endpoint (NPDME) filifiliga i luga o le IP tab pe a mafai le PMA adaptation.
   • Filifili se seti PMA fetuutuunai mo PMA fetuunaiga Filifili parakalafa.
   • Kiliki le PMA Adaptation Preload e uta ai le fa'asologa o le fetuutuuna'iga muamua ma fa'aauau.
   • Fa'ailoa le aofa'i o fa'atonuga PMA e lagolagoina pe a fa'agaoioi le tele o fa'atonuga PMA e fa'aaoga ai le Numera o le fa'asologa o le PMA.
   • Filifili po'o le fea PMA fa'apipi'i e uta pe teuina e fa'aaoga Filifili se fa'atonu PMA e uta pe teu.
   • Kiliki Uta fetuunaiga mai le seti PMA filifilia e utaina le seti PMA filifilia.
   Mo nisi fa'amatalaga e uiga i le PMA fetuutuunaiga tapula'a, tagai ile E-tile Transceiver PHY User Guide.
8. I le Example Design tab, filifili le filifiliga Simulation e faʻatupu ai le suʻega suʻega, ma filifili le filifiliga Synthesis e faʻatupuina ai meafaigaluega faʻapitoaampmamanu.
   Fa'aaliga: E tatau ona e filifilia a itiiti ifo ma le tasi o le Simulation po'o le Synthesis filifiliga e fa'atupuina ai le Example Lisiina Files.
9. Mo Fuafuaina HDL, na'o Verilog o lo'o avanoa.
10. Mo Atina'e Atina'e Kit filifili le filifiliga talafeagai.
    Fa'aaliga: Ole filifiliga ole Intel Agilex F-Series Transceiver SoC Development Kit e na'o avanoa pe a fa'ailoa e lau poloketi le igoa ole masini Intel Agilex e amata ile AGFA012 po'o le AGFA014. A e filifilia le filifiliga Atina'e Pusa, o le pine o tofiga e fa'atulaga e tusa ai ma le Intel Agilex Development Kit numera vaega masini AGFB014R24A2E2V ma atonu e ese mai lau masini filifilia. Afai e te faʻamoemoe e faʻataʻitaʻi le mamanu i luga o meafaigaluega i luga o se PCB ese, filifili le leai se atinaʻe pusa filifiliga ma fai le pine talafeagai i le .qsf file.
11. Kiliki Fausia Example Design. O le Filifilia Example fa'amalama o le Design Directory e aliali mai.
12. Afai e te manaʻo e sui le mamanu example ala fa'atonu po'o le igoa mai fa'aletonu ua fa'aalia (uflex_ilk_0_example_design), suʻesuʻe i le ala fou ma faʻaoga le mamanu fou example igoa fa'atonu.
13. Kiliki OK.

Fa'amatalaga Fa'atatau

• Intel Agilex F-Series Transceiver-SoC Development Kit Guide Guide
• E-tile Transceiver PHY User Guide

1.5. Fa'ata'ita'iina o le Fa'ata'ita'iga Example Testbench
Va'ai ile Interlaken (2nd Generation) Hardware Design Example Polokalama Tulaga Maualuga mo E-tile NRZ Mode Variations ma Interlaken (2nd Generation) Design Hardware Example High Level Block mo E-tile PAM4 Mode Variations poloka ata o le simulation testbench.

Ata 8. Taualumaga

Mulimuli i laasaga nei e faʻataʻitaʻi ai le suʻega:

1. I le faʻatonuga vave, sui i le suʻega faʻataʻitaʻiga directory. O le lisi o leample_installation_dir>/example_design/ testbench mo masini Intel Agilex.
2. Fa'asolo le fa'asologa fa'ata'ita'iga mo le simulator lagolago o lau filifiliga. O le tusitusiga e tuufaatasia ma faʻatautaia le suʻega suʻega i le simulator. E tatau ona siaki lau tusitusiga pe fetaui le numera o le SOP ma le EOP pe a maeʻa faʻataʻitaʻiga. Va'ai i le laulau Laasaga e Fa'atino Fa'ata'ita'iga.
   Laulau 4. La'asaga e Fa'atino Fa'ata'ita'iga

   Simulator	Faatonuga
   ModelSim SE poʻo QuestaSim	I le laina faʻatonu, faʻaoga -do vlog_pro.do. Afai e te manaʻo e faʻataʻitaʻi e aunoa ma le aumaia o le ModelSim GUI, faʻaoga vsim -c -do vlog_pro.do
   VCS	I le laina faʻatonu, faʻaoga sh vcstest.sh
   Xcelium	I le laina o le faʻatonuga, faʻaoga sh xcelium.sh

3. Iloilo i'uga. O se faʻataʻitaʻiga manuia e auina atu ma maua pepa, ma faʻaalia le "Suʻega PASSED".

Le su'ega mo le mamanu example fa'auma galuega nei:

• Fa'atupuina le Interlaken (Augatupulaga Lona Lua) Intel FPGA IP.
• Lolomi tulaga PHY.
• Siaki le feso'ota'iga metaframe (SYNC_LOCK) ma le upu (poloka) tuaoi (WORD_LOCK).
• Fa'atali mo auala ta'itasi e loka ma fa'aoga tutusa.
• Amata le felauaiga o afifi.
• Siaki fa'amaumauga o pepa:
  — CRC24 mea sese
  - SOPs
  - EOPs

O sampO lo'o fa'aalia e le fa'atinoga o se su'ega fa'ata'ita'iga manuia na fa'atautaia i le Interlaken mode:
*****************************************
FA'AMATALAGA: Fa'atali mo le fa'aoga o laina.
O auala uma e tali atu ai ua fetaui lelei ma ua sauni e talia feoaiga.
*************************************************
*************************************************
FA'AMATALAGA: Amata le lafoina o afifi
*************************************************
*************************************************
INFO: Taofi le lafoina o afifi
*************************************************
*************************************************
FA'AMATALAGA: Siakiina fa'amaumauga o pepa
*************************************************
CRC 24 mea sese na lipotia: 0
SOP na lafoina: 100
EOPs auina atu: 100
SOPs maua: 100
EOPs maua: 100
ECC numera sese: 0
*************************************************
INFO: SU'E PASI
*************************************************
Fa'aaliga: O le Interlaken design example simulation testbench auina atu 100 pepa ma maua 100 pepa.
O sampO lo'o fa'aalia e le fa'atinoga o se su'ega fa'ata'ita'iga manuia i le Interlaken Look-aside mode:
Siaki TX ma RX Counter tutusa pe leai.
———————————————————-
READ_MM: tuatusi 4000014 = 00000001.
———————————————————-
Aveese le fa'amaonia o le Counter tutusa bit.
———————————————————-
WRITE_MM: tuatusi 4000001 maua 00000001.
WRITE_MM: tuatusi 4000001 maua 00000000.
———————————————————-
RX_SOP COUNTER.
———————————————————-
READ_MM: tuatusi 400000c = 0000006a.
———————————————————-
RX_EOP COUNTER.
READ_MM: tuatusi 400000d = 0000006a.
———————————————————-
READ_MM: tuatusi 4000010 = 00000000.
———————————————————-
Faaali Lipoti Mulimuli.
———————————————————-
0 Ua iloa le mea sese
0 CRC24 mea sese na lipotia
106 SOPs auina atu
106 EOPs na lafoina
106 SOPs maua
106 EOPs maua
———————————————————-
Fa'auma Fa'atusa
———————————————————-
UA PASI LE SU'EGA
———————————————————-
Fa'aaliga: Ole numera o pepa (SOPs ma EOPs) e eseese ile laina ile Interlaken Lookaside design example simulation sample galuega faatino.
Fa'amatalaga Fa'atatau
Fuafuaga Meafaigaluega Example Vaega i le itulau 6
1.6. Tu'ufa'atasia ma Fa'atulaga le Fa'ata'ita'iga Example i Meafaigaluega

Ata 9. Taualumaga

E fa'aputu ma fa'atino se su'ega fa'ata'ita'iga ile meafaigaluega fa'aample mamanu, mulimuli i laasaga nei:

1. Ia mautinoa meafaigaluega exampua mae'a le fausiaina o mamanu.
2. I le polokalama Intel Quartus Prime Pro Edition, tatala le poloketi Intel Quartus Primeample_installation_dir>/example_design/quartus/ example_design.qpf>.
3. I luga o le Processing menu, kiliki Amata Compilation.
4. A mae'a le fa'aputuga manuia, a .sof file o lo'o avanoa i lau lisi fa'apitoa.
   Mulimuli i laasaga nei e fa'apolokalame ai meafaigaluega fa'apeaampLe mamanu i luga ole masini Intel Agilex:
5. Faʻafesoʻotaʻi le Intel Agilex F-Series Transceiver-SoC Development Kit i le komepiuta talimalo.
   e. Tatala le talosaga Pulea Uati, o se vaega o le pusa atinae, ma seti laina fou mo le mamanu example. O lo'o i lalo le fa'atulagaina o taimi i le talosaga Pulea Uati:
   • Si5338 (U37), CLK1- 100 MHz
   • Si5338 (U36), CLK2- 153.6 MHz
   • Si549 (Y2), OUT- Seti i le tau o le pll_ref_clk (1) mo lou mana'oga.
   i. I luga o le Meafaigaluega lisi, kiliki Programmer.
   o. I le Polokalama, kiliki Hardware Setup.
   u. Filifili se masini polokalame.
   f. Filifili ma fa'aopoopo le Intel Agilex F-Series Transceiver-SoC Development Kit lea e mafai ona fa'afeso'ota'i ai lau vasega Intel Quartus Prime.
   g. Ia mautinoa ua setiina le Faiga i le JTAG.
   h. Filifili le masini Intel Agilex ma kiliki le Add Device. E fa'aalia e le Polokalama se poloka poloka o feso'ota'iga i le va o masini i luga o lau laupapa.
   i. I le laina ma lau .sof, siaki le pusa mo le .sof.
   j. Siaki le pusa i le koluma Polokalama/Configure.
   k. Kiliki Amata.

Fa'amatalaga Fa'atatau

• Polokalama Intel FPGA Devices i le itulau e 0
• Iloiloga ma Debugging Designs ma System Console
• Intel Agilex F-Series Transceiver-SoC Development Kit Guide Guide

1.7. Su'esu'e le Mea Fa'a Meafaigaluega Example
A uma ona e tuufaatasia le Interlaken (2nd Generation) Intel FPGA IP core design exampma fa'atulaga lau masini, e mafai ona e fa'aogaina le System Console e fa'apolokalame ai le IP core ma ana fa'amaufa'ailoga a le Native PHY IP.
Mulimuli i laasaga nei e aumai i luga le System Console ma fa'ata'ita'i le fa'ata'ita'iga o meafaigaluegaampLe:

1. I le polokalama Intel Quartus Prime Pro Edition, i le lisi o Meafaigaluega, kiliki System Debugging Tools ➤ System Console.
2. Suia i leample_installation_dir>example_design/hwtest directory.
3. Ina ia tatalaina se sootaga i le JTAG matai, lolomi le poloaiga lenei: puna sysconsole_testbench.tcl
4. E mafai ona e fa'aola i totonu le fa'asologa fa'asolosolo fa'asologa fa'atasi ma le fa'ata'ita'iga leaample tulafono:
   a. stat: Lolomi fa'amatalaga tulaga lautele.
   e. sys_reset: Toe setiina le faiga.
   i. loop_on: Fa'aola i totonu fa'asologa fa'asologa loopback.
   o. run_example_design: Fa'afoe le mamanu fa'aample.
   Manatua: E tatau ona e taʻavale loop_on poloaiga aʻo leʻi faia le run_example_design poloaiga.
   O le run_example_design e faʻatautaia tulafono nei i se faʻasologa:
   sys_reset->stat->gen_on->stat->gen_off.
   Faʻaaliga: A e filifilia le Faʻafesoʻotaʻi le uta malu IP filifiliga, le run_example_design poloaiga e faʻatino le faʻavasegaina muamua o fetuunaiga ile itu RX e ala ile faʻatonuina o le run_load_PMA_configuration command.
5. E mafai ona e tape le fa'aoga fa'asologa fa'asolosolo fa'atasi ma le fa'ata'ita'iga leaample poloaiga:
   a. loop_off: Tape le laina i totonu loopback.
6. E mafai ona e fa'apolokalameina le IP core ma le fa'asologa fa'aopoopo fa'atasiample tulafono:
   a. gen_on: Fa'aagavaaina le fa'aputuga o pusa.
   e. gen_off: Fa'ate'aina le fa'aputu o pusa.
   i. run_test_loop: Fa'atino le su'ega mo taimi mo E-tile NRZ ma PAM4 fesuiaiga.
   o. clear_err: Fa'amama uma mea sese.
   u. set_test_mode : Fa'atulaga le su'ega e fa'atino i se faiga fa'apitoa.
   f. get_test_mode: Lolomi le faiga su'ega o iai nei.
   g. set_burst_size : Seti le tele o le pa i paita.
   h. get_burst_size: Lolomi fa'amatalaga tetele.

Le su'ega manuia lolomi HW_TEST:PASS fe'au. O lo'o i lalo le ta'iala o le pasi mo se su'ega taufetuli:

• Leai ni mea sese mo CRC32, CRC24, ma siaki.
• O SOP ma EOP e tu'uina atu e tatau ona fetaui ma le mauaina.

O sampO lo'o fa'aalia e le fa'atinoga o se su'ega manuia i le Interlaken mode:
INFO: INFO: Taofi le fa'atupuina o fa'aputu
==== LIPOTI TULAGA ====
TX KHz: 402813
RX KHz: 402813
Loka masani: 0x0000ff
loka TX PLL : 0x000001
Fa'asa'o: 0x00c10f
Rx LOA : 0x000000
Tx LOA : 0x000000
loka upu : 0x0000ff
loka sync: 0x0000ff
CRC32 mea sese: 0
CRC24 mea sese: 0
Fa'ailoga sese: 0
Fu'a sese a le FIFO : 0x000000
SOPs auina atu: 1087913770
EOPs auina atu: 1087913770
SOPs maua: 1087913770
EOPs maua: 1087913770
Fa'asa'o ECC: 0
ECC sese: 0
Ua mavae le 161 sec talu mai le power
HW_TEST : PASI
Le su'ega manuia lolomi HW_TEST : PASS fe'au. O lo'o i lalo le ta'iala o le pasi mo se su'ega taufetuli:

• Leai ni mea sese mo CRC32, CRC24, ma siaki.
• O SOP ma EOP e tu'uina atu e tatau ona fetaui ma le mauaina.

O sampO lo'o fa'aalia e le fa'atinoga o se su'ega manuia ile Interlaken Lookaside mode:
INFO: INFO: Taofi le fa'atupuina o fa'aputu
==== LIPOTI TULAGA ====
TX KHz: 402813
RX KHz: 402812
Loka masani: 0x000fff
loka TX PLL : 0x000001
Fa'asa'o: 0x00c10f
Rx LOA : 0x000000
Tx LOA : 0x000000
loka upu : 0x000fff
loka sync: 0x000fff
CRC32 mea sese: 0
CRC24 mea sese: 0
Fa'ailoga sese: 0
SOPs auina atu: 461
EOPs auina atu: 461
SOPs maua: 461
EOPs maua: 461
Ua mavae le 171 sec talu mai le power
HW_TEST : PASI

Design Example Faʻamatalaga

Le mamanu example fa'aalia galuega a le Interlaken IP core.
Fa'amatalaga Fa'atatau
Interlaken (Augatupulaga Lona Lua) FPGA IP User Guide
2.1. Fuafuaga Example Amio
Ina ia faʻataʻitaʻiina le mamanu i meafaigaluega, faʻaoga tulafono nei i le System Console::

1. Punavai le seti file:
   % punaample>uflex_ilk_0_example_design/example_design/hwtest/sysconsole_testbench.tcl
2. Fai le su'ega:
   % run_example_design
3. O le Interlaken (2nd Generation) mea faigaluega fa'ata'ita'igaample mae'a laasaga nei:
   a. Toe setiina le Interlaken (Augatupulaga Lona Lua) IP.
   e. Fa'atonu le Interlaken (2nd Generation) IP i totonu o le loopback mode.
   i. Auina atu se vaitafe o Interlaken packets ma faʻamatalaga faʻamaonia i le uta i le TX user data transfer interface o le IP core.
   o. Siaki pepa na maua ma lipoti le tulaga. O le siaki siaki o lo'o i totonu o le fa'atulagaina o meafaigaluega e pei oample tu'uina atu tulaga fa'avae e siaki ai pepa:
   • Siaki po'o sa'o le fa'asologa o fa'asologa o afifi.
   • Siaki o fa'amaumauga na maua e fetaui ma tau fa'amoemoeina e ala i le fa'amautinoaina o le amataga o le pepa (SOP) ma le fa'ai'uga o le pepa (EOP) e fetaui lelei a'o fa'asalalauina ma maua fa'amaumauga.

2.2. Fa'ailoga Fa'afeso'ota'i
Laulau 5. Fuafuaga Example Fa'ailoga Fa'amatalaga

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
mgmt_clk	Ulufale	1	Faiga fa'aoga uati. Ole taimi ole uati e tatau ona 100 MHz.
pll_ref_clk /pll_ref_clk[1:0] (2)	Ulufale	2-Ian	Transceiver faasinoupu uati. Aveina le RX CDR PLL.

Igoa o le Taulaga	Fa'atonuga	Lautele (Piti)	Fa'amatalaga
			pll_ref_clk[1] e na'o avanoa pe a e mafai Fa'asao e le'i fa'aaogaina Fa'aaliga: auala transceiver mo PAM4 parakalafa i le E-tile PAM4 mode IP fesuiaiga.
rx_pin	Ulufale	Numera o auala	Receiver SERDES pine fa'amaumauga.
tx_pin	Tuuina atu	Numera o auala	Tu'u atu se pine fa'amaumauga a le SERDES.
rx_pin_n	Ulufale	Numera o auala	Receiver SERDES pine fa'amaumauga. O lenei fa'ailoga e na'o avanoa i le E-tile PAM4 fa'aogaina masini masini.
tx_pin_n	Tuuina atu	Numera o auala	Tu'u atu se pine fa'amaumauga a le SERDES. O lenei fa'ailoga e na'o avanoa i le E-tile PAM4 fa'aogaina masini masini.
mac_clk_pll_ref	Ulufale	1	O lenei faailo e tatau ona ave e le PLL ma e tatau ona faʻaoga le puna lava o le uati e faʻaulu ai le pll_ref_clk. O lenei fa'ailoga e na'o avanoa i le E-tile PAM4 fa'aogaina masini masini.
usr_pb_reset_n	Ulufale	1	Faiga toe setiina.

Fa'amatalaga Fa'atatau
Fa'ailoga Fa'afeso'ota'i
2.3. Resitala Faafanua
Fa'aaliga:

• Design ExampO le tuatusi resitala e amata ile 0x20** ae amata le tuatusi tuatusi IP Interlaken ile 0x10**.
• Fa'ailoga avanoa: RO—Na'o Faitau, ma le RW— Faitau/ Tusi.
• System console faitau le mamanu example resitala ma lipoti le tulaga o le suʻega i luga o le lau.

Laulau 6. Fuafuaga Example Resitala Faafanua mo Interlaken Design Example

Offset	Igoa	Avanoa	Fa'amatalaga
8'h00	Fa'apolopolo
8'h01	Fa'apolopolo
8'h02	Toe setiina PLL faiga	RO	O pito o loʻo mulimuli mai e faʻaalia ai le talosaga toe setiina o le PLL ma faʻatagaina le tau: • Bit [0] – sys_pll_rst_req • Bit [1] – sys_pll_rst_en
8'h03	RX laina laina	RO	Fa'ailoa le laina laina RX.
8'h04	WORD loka	RO	[NUM_LANES–1:0] – Upu (poloka) e iloa ai tuaoi.

(2) A e fa'aagaina Fa'asao le fa'aogaina o alalaupapa transceiver mo le PAM4 parakalafa, e fa'aopoopoina se isi uati fa'asinoga uati e fa'asaoina ai le PAM4 pologa e le'o fa'aaogaina.

Offset	Igoa	Avanoa	Fa'amatalaga
8'h05	Sync loka	RO	[NUM_LANES–1:0] – Metaframe synchronization.
8'h06 - 8'h09	CRC32 numera sese	RO	Fa'ailoa le numera o mea sese CRC32.
8'h0A	CRC24 numera sese	RO	Fa'ailoa le numera o mea sese CRC24.
8'h0B	Fa'ailoga o le Sova/Malalo	RO	O vaega nei e fa'aalia: • Bit [3] – Fa'ailoga lalo ole TX • Bit [2] – Fa'ailoga ova TX • Bit [1] – Fa'ailoga o le RX o lo'o tafe
8'h0C	Faitauga SOP	RO	Fa'ailoa le numera ole SOP.
8'h0D	EOP faitau	RO	Fa'ailoa le numera o le EOP
8'h0E	Fa'ailoga sese	RO	Fa'ailoa le aofa'i o mea sese: • Leiloa o le laina laina • Upu pulea faasolitulafono • Fa'asologa fa'asolitulafono • Leai se fa'ailoga SOP po'o le EOP
8'h0F	auina atu_faamatalaga_mm_clk	RW	Tusi le 1 i le bit [0] ina ia mafai ai le faailo afi.
8'h10	Sese mea siaki		Fa'ailoa mai le sese o siaki. (SOP fa'amatalaga sese, Channel numera sese, ma PLD fa'amatalaga sese)
8'h11	Loka PLL faiga	RO	Bit [0] o lo'o fa'ailoa mai ai le loka PLL.
8'h14	TX SOP faitau	RO	Fa'ailoa le numera o le SOP na fa'atupuina e le pate generator.
8'h15	TX EOP faitau	RO	Fa'ailoa le numera o le EOP na fa'atupuina e le fa'aputu fa'aputu.
8'h16	Fa'aauau pepa	RW	Tusi le 1 i le bit [0] e mafai ai ona faʻaauau le afifi.
8'h39	ECC numera sese	RO	Fa'ailoa le numera o mea sese a le ECC.
8'h40	ECC fa'asa'o le aofa'i o mea sese	RO	Fa'ailoa le numera o fa'asa'oga ECC sese.

Laulau 7. Fuafuaga Example Resitala Faafanua mo Interlaken Look-Aside Design Example
Fa'aoga lenei fa'afanua resitala pe a e fa'atupuina le fa'ata'ita'igaample fa'atasi ma le fa'aagaoio ole Interlaken Look-aside mode parakalafa ua ki.

Offset	Igoa	Avanoa	Fa'amatalaga
8'h00	Fa'apolopolo
8'h01	Toe setiina	RO	Tusi le 1 i le bit [0] e fa'amama TX ma le RX fa'ata'i tutusa.
8'h02	Toe setiina PLL faiga	RO	O pito o loʻo mulimuli mai e faʻaalia ai le talosaga toe setiina o le PLL ma faʻatagaina le tau: • Bit [0] – sys_pll_rst_req • Bit [1] – sys_pll_rst_en
8'h03	RX laina laina	RO	Fa'ailoa le laina laina RX.
8'h04	WORD loka	RO	[NUM_LANES–1:0] – Upu (poloka) e iloa ai tuaoi.
8'h05	Sync loka	RO	[NUM_LANES–1:0] – Metaframe synchronization.
8'h06 - 8'h09	CRC32 numera sese	RO	Fa'ailoa le numera o mea sese CRC32.
8'h0A	CRC24 numera sese	RO	Fa'ailoa le numera o mea sese CRC24.

Offset	Igoa	Avanoa	Fa'amatalaga
8'h0B	Fa'apolopolo
8'h0C	Faitauga SOP	RO	Fa'ailoa le numera ole SOP.
8'h0D	EOP faitau	RO	Fa'ailoa le numera o le EOP
8'h0E	Fa'ailoga sese	RO	Fa'ailoa le aofa'i o mea sese: • Leiloa o le laina laina • Upu pulea faasolitulafono • Fa'asologa fa'asolitulafono • Leai se fa'ailoga SOP po'o le EOP
8'h0F	auina atu_faamatalaga_mm_clk	RW	Tusi le 1 i le bit [0] ina ia mafai ai le faailo afi.
8'h10	Sese mea siaki	RO	Fa'ailoa mai le sese o siaki. (SOP fa'amatalaga sese, Channel numera sese, ma PLD fa'amatalaga sese)
8'h11	Loka PLL faiga	RO	Bit [0] o lo'o fa'ailoa mai ai le loka PLL.
8'h13	Faitauga o le taofi	RO	Fa'ailoa le numera o le taofi.
8'h14	TX SOP faitau	RO	Fa'ailoa le numera o le SOP na fa'atupuina e le pate generator.
8'h15	TX EOP faitau	RO	Fa'ailoa le numera o le EOP na fa'atupuina e le fa'aputu fa'aputu.
8'h16	Fa'aauau pepa	RO	Tusi le 1 i le bit [0] e mafai ai ona faʻaauau le afifi.
8'h17	TX ma RX fa'atau tutusa	RW	Fa'ailoa TX ma RX fa'atau e tutusa.
8'h23	Fa'aaga le taofi	WO	Tusi le 1 i le bit [0] ina ia mafai ai ona fua le umi.
8'h24	Latency sauni	RO	Fa'ailoa mai ua sauni le fuaina o le leo.

Interlaken (Augatupulaga Lona Lua) Intel Agilex FPGA IP Design Example User Guide Archives

Mo lomiga lata mai ma muamua o lenei taiala fa'aoga, tagai i le Interlaken (2 Tupulaga) Intel Agilex FPGA IP Design Example User Guide HTML version. Filifili le lomiga ma kiliki le Download. Afai e le o lisiina se IP po'o se polokalama faakomepiuta, e fa'aoga le ta'iala mo le IP muamua po'o le polokalama faakomepiuta.
IP versions e tutusa ma le Intel Quartus Prime Design Suite software versions up to v19.1. Mai le Intel Quartus Prime Design Suite software version 19.2 poʻo mulimuli ane, IP cores o loʻo i ai se polokalame faʻaliliuga IP fou.

Fa'amatalaga Toe Iloiloga o Pepa mo Interlaken (Augatupulaga Lona Lua) Intel Agilex FPGA IP Design Example User Guide

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
2022.08.03	21.3	20.0.1	Fa'asa'o le masini OPN mo le Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• Faaopoopo le lagolago mo QuestaSim simulator. • Aveesea le lagolago mo NCSim simulator.
2021.02.24	20.4	20.0.1	• Fa'aopoopoina fa'amatalaga e uiga i le fa'asaoina o le auala transceiver e le'i fa'aaogaina mo PAM4 i le vaega: Mea Fa'atonu Fa'amatalagaample Vaega. • Fa'aopoopo le fa'amatalaga fa'ailoga pll_ref_clk[1] i le vaega: Fa'ailoga Fa'afeso'ota'i.
2020.12.14	20.4	20.0.0	• Fa'afouina sample su'ega meafaigaluega mo le Interlaken mode ma le Interlaken Look-aside mode i le vaega Su'ega o le Hardware Design Example. • Fa'afou fa'afanua resitala mo Interlaken Look-aside design example i le vaega Resitala Faafanua. • Fa'aopoopoina se fa'ata'ita'iga e pasia mo se su'ega o meafaigaluega fa'amanuiaina i le vaega o le Su'ega o le Design Design Example.
2020.10.16	20.2	19.3.0	Fa'asa'o le fa'atonuga e fa'agasolo ai le fa'avasegaina muamua o le fetuutuuna'iga ile itu RX ile Su'ega ole Mea Fa'ameamea Example vaega.
2020.06.22	20.2	19.3.0	• Le mamanu example avanoa mo le Interlaken Look-side mode. • Su'ega meafaigaluega o le mamanu fa'ataample avanoa mo Intel Agilex masini fesuiaiga. • Fa'aopoopo Fa'atusa: Fa'ailoga Poloka maualuga mo Interlaken (2nd Generation) Design Example. • Fa'afouina vaega nei: – Meafaigaluega ma Polokalama Manaoga – Fa'atonuga Fa'atonu • Suia fuainumera nei e aofia ai le Interlaken Look-aside fa'afouga fa'atatau: – Ata: Interlaken (Augatupulaga Lona Lua) Fuafuaga Meafaigaluega Example Maualuga La'asaga Poloka Ata mo E-tile NRZ Faiga Fa'asologa – Ata: Interlaken (Augatupulaga Lona Lua) Fuafuaga Meafaigaluega Example Fa'ata'ita'iga Poloka Tulaga Maualuga mo E-tile PAM4 Faiga Fa'asologa • Fa'afou Ata: IP Parameter Editor. • Fa'aopoopoina fa'amatalaga e uiga i fa'asologa o taimi i le fa'atonuga o le fa'atonuga o le uati i le vaega Fa'aopoopo ma Fa'atulaga le Fa'ailoga Fa'atusaample i Meafaigaluega.

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
			• Fa'aopoopo galuega fa'atino o su'ega mo le Interlaken Look-side i vaega nei: – Fa'ata'ita'iina le Fa'ata'ita'iga Example Testbench – Su'esu'eina le Mea Fa'a Meafaigaluega Fa'atasiample • Fa'aopoopo pe a mae'a fa'ailoga fou i le vaega o Fa'ailoga Fa'afeso'ota'i: – mgmt_clk – rx_pin_n – tx_pin_n – mac_clk_pll_ref • Fa'aopoopo le fa'afanua resitala mo le Interlaken Look-aside design example i le vaega: Resitala Faafanua.
2019.09.30	19.3	19.2.1	Aveese clk100. O le mgmt_clk e avea o se uati faʻasino ile IO PLL i mea nei: • Ata: Interlaken (Augatupulaga Lona Lua) Fuafuaga Meafaigaluega Example Fa'ata'ita'iga Poloka Tulaga Maualuga mo E-tile NRZ Faiga Fa'asologa. • Ata: Interlaken (Augatupulaga Lona Lua) Fuafuaga Meafaigaluega Example Fa'afanua Poloka Maualuga Maualuga mo E-tile PAM4 Faiga Fa'asologa.
2019.07.01	19.2	19.2	Fa'asalalauga muamua.

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
*O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
ISO
9001:2015
Resitala
Interlaken (Augatupulaga Lona Lua) Intel® Agilex™ FPGA IP Design Example User Guide

Faʻasinomaga Faʻainitaneti
Lauina Manatu
ID: 683800
UG-20239
Fa'aliliuga: 2022.08.03

Pepa / Punaoa

intel Interlaken (Augatupulaga Lona Lua) Agilex FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga Interlaken 2nd Tupulaga Agilex FPGA IP Design Example, Interlaken, 2nd Tupulaga Agilex FPGA IP Design Example, Agilex FPGA IP Design Example, IP Design Example

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