ALINX-LOGO

ALINX AC7Z020 ZYNQ7000 FPGA Boto ea Nts'etsopele

ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-PRODUCT

Tlhahisoleseding ya Sehlahiswa

Boto ea Nts'etsopele ea ZYNQ7000 FPGA ke boto ea nts'etsopele e nang le chip ea XC7Z100-1CLG400I, e leng karolo ea letoto la ZYNQ7000. E na le ARM dual-core CortexA9-based application processor e nang le lebelo la oache ho fihla ho 800MHz, 256KB on-chip RAM, le sebopeho sa polokelo sa kantle se tšehetsang 16/32 bit DDR2, DDR3 interface. Boto e boetse e na le tšehetso e 'meli ea Gigabit NIC, li-interface tse peli tsa USB2.0 OTG, li-interfaces tse peli tsa libese tsa CAN2.0B, likarete tse peli tsa SD, SDIO, li-control tse lumellanang tsa MMC, 2 SPIs, 2 UARTs, 2 I2C interfaces, le lipara tse 4 tsa 32bit GPIO. Boto e na le boto ea mantlha (AC7Z010) e sebelisang li-chips tse peli tsa Micron's MT41K128M16TW-107 DDR3 tse nang le bokhoni bo kopaneng ba 256MB le bophara ba bese ea data ea 32-bit. Boto e boetse e na le li-LED tsa basebelisi, linotlolo tsa basebelisi, hlooho ea katoloso, JTAG debug port, le phepelo ea motlakase.

Litaelo tsa Tšebeliso ea Sehlahisoa

Ho sebelisa ZYNQ7000 FPGA Development Board, latela mehato ena:

  1. Kopanya phepelo ea motlakase ho boto.
  2. Hokela boto khomphuteng ya hao o sebedisa thapo ya USB.
  3. Kenya li-driver tse hlokahalang bakeng sa boto khomphuteng ea hau.
  4. Bula tikoloho ea hau ea ntlafatso ea software 'me u thehe projeke e ncha.
  5. Beakanya litlhophiso tsa projeke ea hau ho sebelisa Boto ea Ntlafatso ea ZYNQ7000 FPGA.
  6. Ngola khoutu ea hau ebe u e hlophisa.
  7. Kenya khoutu e hlophisitsoeng ho boto u sebelisa sesebelisoa sa JTAG boema-kepe ba ho lokisa.
  8. Lekola khoutu ea hau botong.

Hlokomela: Sheba buka ea mosebelisi bakeng sa tlhaiso-leseling e batsi mabapi le likarolo tsa boto le ts'ebeliso.

Rekoto ea Phetolelo

Phetolelo Letsatsi Lokolloa Ka Tlhaloso
Tšen. 1.0 2019-12-15 Rachel Zhou Phatlalatso ea Pele

Setšoantšo sa AC7Z010

Tlhahiso ea mantlha ea AC7Z010

  • AC7Z010 (mohlala oa boto ea mantlha, e tšoanang ka tlase) FPGA core board, ZYNQ chip e thehiloe ho XC7Z010-1CLG400I ea XILINX company ZYNQ7000 series. Sistimi ea PS ea chip ea ZYNQ e kopanya li-processor tse peli tsa ARM CortexTM-A9, likhokahano tsa AMBA®, mohopolo oa kahare, likhokahano tsa memori tsa kantle le li-peripheral. FPGA ea chip ea ZYNQ e na le lisele tse ngata tse hlophisehileng, DSP le RAM e kahare.
  • Boto ena ea mantlha e sebelisa li-chips tse peli tsa Micron's MT41K128M16TW-107 DDR3, e 'ngoe le e' ngoe e nang le matla a 256MB; li-chips tse peli tsa DDR li kopana ho theha bophara ba bese ea data ea 32-bit, le maqhubu a oache a ho bala le ho ngola data pakeng tsa ZYNQ le DDR3 Ho fihlela ho 533Mhz; tlhophiso ena e ka fihlela litlhoko tsa ts'ebetso ea data e phahameng ea bandwidth
  • E le ho hokahana le boto e tsamaisang thepa, lihokelo tse peli tsa boto ea boto ea boto ena ea mantlha li atolosoa ka likou tsa USB ka lehlakoreng la PS, li-interface tsa Gigabit Ethernet, slot ea karete ea SD, le likou tse ling tse setseng tsa MIO (48). Hape hoo e ka bang likou tsohle tsa IO (100) tsa BANK13 (feela bakeng sa AC7Z010), BAN34 le BANK35 ka lehlakoreng la PL, maemo a IO a BANK34 le BANK35 a ka fanoa ka boto ea carriers ho fihlela litlhoko tsa basebelisi bakeng sa lihokelo tse fapaneng tsa maemo. Bakeng sa basebelisi ba hlokang IO e ngata, boto ena ea mantlha e tla ba khetho e ntle. Le karolo ea khokahano ea IO, chip ea ZYNQ ho sebopeho se pakeng tsa bolelele bo lekanang le ts'ebetso e fapaneng, 'me boholo ba boto ea mantlha ke 35 * 42 (mm), e loketseng haholo nts'etsopele ea bobeli.ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-1

ZYNQ Chip

FPGA core board AC7Z010 e sebelisa Xilinx's Zynq7000 series chip, module XC7Z010-1CLG400I. Sistimi ea PS ea chip e kopanya li-processor tse peli tsa ARM Cortex™-A9, likhokahano tsa AMBA®, memori e kahare, likhokahano tsa memori tsa kantle le li-peripheral. Li-peripherals tsena haholo-holo li kenyelletsa sebopeho sa libese tsa USB, sebopeho sa Ethernet, sebopeho sa SD / SDIO, sebopeho sa libese sa I2C, sehokelo sa libese tsa CAN, UART interface, GPIO joalo-joalo. Setšoantšo sa 2-2-1 se hlalositse Kakaretso ea Block Diagram ea ZYNQ7000 Chip.ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-2

Likarolo tsa mantlha tsa karolo ea sistimi ea PS ke tse latelang:

  • ARM dual-core CortexA9-based application processor, meralo ea ARM-v7, ho fihla ho 800MHz
  • 32KB level 1 taeo le cache ea data ka CPU, 512KB level 2 cache 2 CPU shares
  • On-chip boot ROM le 256KB on-chip RAM
  • Sehokelo sa polokelo ea kantle, se tšehetsa 16/32 bit DDR2, DDR3 interface
  • Ts'ehetso e 'meli ea Gigabit NIC: sebopeho se fapaneng sa DMA, GMII, RGMII, SGMII
  • Likhokahano tse peli tsa USB2.0 OTG, e 'ngoe le e 'ngoe e tšehetsa li-node tse 12
  • Libaka tse peli tsa libese tsa CAN2.0B
  • Likarete tse peli tsa SD, SDIO, li-control tse lumellanang tsa MMC
  • 2 SPIs, 2 UARTs, 2 I2C interfaces
  • Lipara tse 4 tsa 32bit GPIO, 54 (32 + 22) e le PS system IO, 64 e hokahane le PL
  • Khokahano e phahameng ea bandwidth kahare ho PS le PS ho ea ho PL

Lintlha tse ka sehloohong tsa karolo ea PL logic ke tse latelang:

  • Lisele tsa kelello: 28K
  • Litafole tsa ho sheba (LUTs): 17600
  • Flip-flops: 35,200
  • 18x25MACCs: 80
  • Thibela RAM: 240KB
  • Li-converter tse peli tsa AD tsa on-chip voltage, ho utloa mocheso le liteishene tse kenang ka ntle tse 17 tse fapaneng, 1MBPS
  • XC7Z100-1CLG400I lebelo la lebelo la chip ke -1, boemo ba indasteri, sephutheloana ke BGA400, pitch pitch ke 0.8mm tlhaloso e khethehileng ea mohlala oa chip ea letoto la ZYNQ7000 e bonts'itsoe ho Setšoantšo sa 2-2-2ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-3

DDR3 DRAM

  • Boto ea mantlha ea FPGA AC7Z010 e na le lichifi tse peli tsa Micron DDR3 SDRAM (1GB ka kakaretso), mohlala MT41K128M16TW-107 (E lumellana le Hynix
  • H5TQ2G63AFR-PBI). Bophara ba libese kaofela ba DDR3 SDRAM ke 32bit. DDR3 SDRAM e sebetsa ka lebelo le phahameng la 533MHz (data rate1066Mbps). Sistimi ea memori ea DDR3 e hokahane ka kotloloho le sebopeho sa memori sa BANK 502 ea ZYNQ Processing System (PS). Tlhophiso e khethehileng ea DDR3 SDRAM e bontšoa ho Lethathamo la 2-3-1 ka tlase:
Bit Nomoro Mohlala oa Chip Bokhoni Feme
U8,U9 MT41K128M16TW-107 256M x 16bit Micron

Lethathamo la 2-3-1: DDR3 SDRAM Configuration

Moralo oa Hardware oa DDR3 o hloka ho nahanoa ka tieo ka botšepehi ba matšoao. Re se re nahanne ka botlalo mabapi le mohanyetsi o ts'oanang / oa ho hanyetsa, taolo ea ho ts'oara, le taolo ea bolelele ba moralo oa moralo oa potoloho le moralo oa PCB ho netefatsa ts'ebetso e potlakileng le e tsitsitseng ea DDR3.ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-4ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-5

Mosebetsi oa phini oa DDR3 DRAM:

Lebitso la Letshwao Lebitso la Pin la ZYNQ Nomoro ea Pin ea ZYNQ
DDR3_DQS0_P PS_DDR_DQS_P0_502 C2
DDR3_DQS0_N PS_DDR_DQS_N0_502 B2
DDR3_DQS1_P PS_DDR_DQS_P1_502 G2
DDR3_DQS1_N PS_DDR_DQS_N1_502 F2
DDR3_DQS2_P PS_DDR_DQS_P2_502 R2
DDR3_DQS2_N PS_DDR_DQS_N2_502 T2
DDR3_DQS3_P PS_DDR_DQS_P3_502 W5
DDR3_DQS4_N PS_DDR_DQS_N3_502 W4
DDR3_D0 PS_DDR_DQ0_502 C3
DDR3_D1 PS_DDR_DQ1_502 B3
DDR3_D2 PS_DDR_DQ2_502 A2
DDR3_D3 PS_DDR_DQ3_502 A4
DDR3_D4 PS_DDR_DQ4_502 D3
DDR3_D5 PS_DDR_DQ5_502 D1
DDR3_D6 PS_DDR_DQ6_502 C1
DDR3_D7 PS_DDR_DQ7_502 E1
DDR3_D8 PS_DDR_DQ8_502 E2
DDR3_D9 PS_DDR_DQ9_502 E3
DDR3_D10 PS_DDR_DQ10_502 G3
DDR3_D11 PS_DDR_DQ11_502 H3
DDR3_D12 PS_DDR_DQ12_502 J3
DDR3_D13 PS_DDR_DQ13_502 H2
DDR3_D14 PS_DDR_DQ14_502 H1
DDR3_D15 PS_DDR_DQ15_502 J1
DDR3_D16 PS_DDR_DQ16_502 P1
DDR3_D17 PS_DDR_DQ17_502 P3
DDR3_D18 PS_DDR_DQ18_502 R3
DDR3_D19 PS_DDR_DQ19_502 R1
DDR3_D20 PS_DDR_DQ20_502 T4
DDR3_D21 PS_DDR_DQ21_502 U4
DDR3_D22 PS_DDR_DQ22_502 U2
DDR3_D23 PS_DDR_DQ23_502 U3
DDR3_D24 PS_DDR_DQ24_502 V1
DDR3_D25 PS_DDR_DQ25_502 Y3
DDR3_D26 PS_DDR_DQ26_502 W1
DDR3_D27 PS_DDR_DQ27_502 Y4
DDR3_D28 PS_DDR_DQ28_502 Y2
DDR3_D29 PS_DDR_DQ29_502 W3
DDR3_D30 PS_DDR_DQ30_502 V2
DDR3_D31 PS_DDR_DQ31_502 V3
DDR3_DM0 PS_DDR_DM0_502 A1
DDR3_DM1 PS_DDR_DM1_502 F1
DDR3_DM2 PS_DDR_DM2_502 T1
DDR3_DM3 PS_DDR_DM3_502 Y1
DDR3_A0 PS_DDR_A0_502 N2
DDR3_A1 PS_DDR_A1_502 K2
DDR3_A2 PS_DDR_A2_502 M3
DDR3_A3 PS_DDR_A3_502 K3
DDR3_A4 PS_DDR_A4_502 M4
DDR3_A5 PS_DDR_A5_502 L1
DDR3_A6 PS_DDR_A6_502 L4
DDR3_A7 PS_DDR_A7_502 K4
DDR3_A8 PS_DDR_A8_502 K1
DDR3_A9 PS_DDR_A9_502 J4
DDR3_A10 PS_DDR_A10_502 F5
DDR3_A11 PS_DDR_A11_502 G4
DDR3_A12 PS_DDR_A12_502 E4
DDR3_A13 PS_DDR_A13_502 D4
DDR3_A14 PS_DDR_A14_502 F4
DDR3_BA0 PS_DDR_BA0_502 L5
DDR3_BA1 PS_DDR_BA1_502 R4
DDR3_BA2 PS_DDR_BA2_502 J5
DDR3_S0 PS_DDR_CS_B_502 N1
DDR3_RAS PS_DDR_RAS_B_502 P4
DDR3_CAS PS_DDR_CAS_B_502 P5
DDR3_WE PS_DDR_WE_B_502 M5
DDR3_ODT PS_DDR_ODT_502 N5
DDR3_RESET PS_DDR_DRST_B_502 B4
DDR3_CLK0_P PS_DDR_CKP_502 L2
DDR3_CLK0_N PS_DDR_CKN_502 M2
DDR3_CKE PS_DDR_CKE_502 N3

QSPI Flash

Boto ea mantlha ea FPGA AC7Z010 e na le chip e le 'ngoe ea 256MBit Quad-SPI FLASH, mofuta oa flash ke W25Q256FVEI, o sebelisang 3.3V CMOS vol.tage standard. Ka lebaka la tlhaho e sa tsitsang ea QSPI FLASH, e ka sebelisoa e le sesebelisoa sa boot bakeng sa tsamaiso ea ho boloka setšoantšo sa boot sa tsamaiso. Litšoantšo tsena haholo-holo li kenyelletsa FPGA bit files, khoutu ea kopo ea ARM, le lintlha tse ling tsa mosebelisi files. Mefuta e ikhethileng le liparamente tse amanang le QSPI FLASH li bonts'itsoe ho Lethathamo la 2-4-1.

Boemo Mohlala Bokhoni Feme
U15 Tlhaloso: W25Q256FVEI 32M Byte Winbond

Lethathamo la 2-4-1: Tlhaloso ea QSPI FLASH
QSPI FLASH e hokahane le boema-kepe ba GPIO ba BANK500 karolong ea PS ea chip ea ZYNQ. Moralong oa sistimi, mesebetsi ea boema-kepe ea GPIO ea likou tsena tsa PS e hloka ho hlophisoa joalo ka sebopeho sa QSPI FLASH. Setšoantšo sa 2-4-1 se bonts'a QSPI Flash ho schematic.ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-6

Hlophisa likabelo tsa chip pin:

Lebitso la Letshwao Lebitso la Pin la ZYNQ Nomoro ea Pin ea ZYNQ
QSPI_SCK PS_MIO6_500 A5
QSPI_CS PS_MIO1_500 A7
QSPI_D0 PS_MIO2_500 B8
QSPI_D1 PS_MIO3_500 D6
QSPI_D2 PS_MIO4_500 B7
QSPI_D3 PS_MIO5_500 A6

Tlhophiso ea oache

Boto ea mantlha ea AC7Z010 e fana ka oache e sebetsang bakeng sa sistimi ea PS, e le hore sistimi ea PS e ka sebetsa ka boikemelo.
Mohloli oa oache oa sistimi ea PS
Chip ea ZYNQ e fana ka tlhahiso ea oache ea 33.333333MHz bakeng sa karolo ea PS ka kristale ea X1 botong ea mantlha. Kenyelletso ea oache e hokahane le PS_CLK_500 pin ea ZYNQ chip BANK500. Setšoantšo sa eona sa moralo se bontšoa ho Setšoantšo sa 2-5-1:ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-7

Mosebetsi oa phini oa oache:

Lebitso la lets'oao ZYNQ Pin
PS_CLK_500 E7

Phepelo ea motlakase
Phepelo ea motlakase voltage ea boto ea mantlha ea AC7Z010 ke DC5V, e fanoang ka ho hokela boto ea thepa. Ho phaella moo, matla a BANK34 le BANK35 a boetse a fanoa ka boto ea thepa. Setšoantšo sa moralo oa moralo oa phepelo ea motlakase botong ea mantlha e bonts'itsoe ho Setšoantšo sa 2-6-1:ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-8

Boto ea nts'etsopele ea FPGA e tsamaisoa ke + 5V, 'me e fetoloa + 1.0V, + 1.8V, + 1.5V, + 3.3V lisebelisoa tse 'nè tsa matla ka lisebelisoa tse' nè tsa motlakase tsa DC / DC. Phallo ea hona joale ea + 1.0V e ka fihla ho 6A, + 1.8V le + 1.5V ea matla a motlakase hona joale ke 3A, + 3.3V tlhahiso ea hona joale ke 500mA. J29 e boetse e na le liphini tse 4 e 'ngoe le e 'ngoe ea ho fana ka matla ho FPGA BANK34 le BANK35. Ea kamehla ke 3.3V. Basebelisi ba ka fetola matla a BANK34 le BANK35 ka ho fetola VCCIO34 le VCCIO35 ka sefofane se ka morao. 1.5V e hlahisa VTT le VREF voltagtse hlokoang ke DDR3 ka TI's TPS51206. Mesebetsi ea kabo e 'ngoe le e 'ngoe ea matla e bontšoa tafoleng e latelang:

Phepelo ea motlakase Mosebetsi
+1.0V ZYNQ PS le PL karolo ea Core Voltage
+1.8V ZYNQ PS le PL partial axiliary voltage

BANK501 IO voltage

+3.3V ZYNQ Bank0,Bank500,QSIP FLASH

Crystal oache

+1.5V DDR3, ZYNQ Bank501
VREF,VTT(+0.75V) DDR3
VCCIO34/35 Banka34, Banka35

Hobane phepelo ea motlakase ea ZYNQ FPGA e na le litlhoko tsa tatellano ea matla, moralong oa potoloho, re qapile ho latela litlhoko tsa matla tsa chip. Tatelano ea matla ke +1.0V->+1.8V-> (+1.5 V, +3.3V, VCCIO) moralo oa potoloho ho netefatsa ts'ebetso e tloaelehileng ea chip. Hobane litekanyetso tsa boemo ba BANK34 le BANK35 li khethoa ke matla a fanoang ke boto ea thepa, e phahameng ka ho fetisisa ke 3.3V. Ha u rala boto ea thepa ho fana ka matla a VCCIO34 le VCCIO35 bakeng sa boto ea mantlha, tatellano ea matla e lieha ho feta + 5V.

Boholo ba Boto ea Boto ea AC7Z010ALINX-AC7Z020-ZYNQ7000-FPGA-Development-Board-FIG-9

Mosebetsi oa phini oa Board to Board Connectors
Boto ea mantlha e na le kakaretso ea likou tse peli tsa katoloso ea lebelo le holimo. E sebelisa li-connectors tse peli tsa 120-pin inter-board (J29 / J30) ho hokahanya le boto ea thepa. Sebaka sa PIN sa boto ho ea ho sehokelo sa boto ke 0.5mm, har'a tsona, J29 e hokahane le matla a 5V, ho kenya matla a VCCIO, matšoao a mang a IO le J.TAG matšoao, 'me J30 e hokahane le matšoao a setseng a IO le MIO. Boemo ba IO ba BANK34 le BANK35 bo ka fetoloa ka ho fetola ho kenya VCCIO ho sehokelo, boemo bo phahameng ka ho fetisisa ha bo fete 3.3V. Boto e tsamaisang thepa ea AX7Z010 eo re e qapileng ke 3.3V ka ho sa feleng. Hlokomela hore IO ea BANK13 ha e joalo

Kabelo ea phini ea boto ho sehokelo sa boto J29

J29 phini Letshwao

 Lebitso

ZYNQ Pin

Nomoro

J29 phini Lebitso la Letshwao ZYNQ Pin

Nomoro

1 Tlhaloso: VCC5V 2 Tlhaloso: VCC5V
3 Tlhaloso: VCC5V 4 Tlhaloso: VCC5V
5 Tlhaloso: VCC5V 6 Tlhaloso: VCC5V
7 Tlhaloso: VCC5V 8 Tlhaloso: VCC5V
9 GND 10 GND
11 VCCIO_34 12 VCCIO_35
13 VCCIO_34 14 VCCIO_35
15 VCCIO_34 16 VCCIO_35
17 VCCIO_34 18 VCCIO_35
19 GND 20 GND
21 IO34_L10P V15 22 IO34_L7P Y16
23 IO34_L10N W15 24 IO34_L7N Y17
25 IO34_L15N U20 26 IO34_L17P Y18
27 IO34_L15P T20 28 IO34_L17N Y19
29 GND 30 GND
31 IO34_L9N U17 32 IO34_L8P W14
33 IO34_L9P T16 34 IO34_L8N Y14
35 IO34_L12N U19 36 IO34_L3P U13
37 IO34_L12P U18 38 IO34_L3N V13
39 GND 40 GND
41 IO34_L14N P20 42 IO34_L21N V18
43 IO34_L14P N20 44 IO34_L21P V17
45 IO34_L16N W20 46 IO34_L18P V16
47 IO34_L16P V20 48 IO34_L18N W16
49 GND 50 GND
51 IO34_L22N W19 52 IO34_L23P N17
53 IO34_L22P W18 54 IO34_L23N P18
55 IO34_L20N R18 56 IO34_L13N P19
57 IO34_L20P T17 58 IO34_L13P N18
59 GND 60 GND
61 IO34_L19N R17 62 IO34_L11N U15
63 IO34_L19P R16 64 IO34_L11P U14
65 IO34_L24P P15 66 IO34_L5N T15
67 IO34_L24N P16 68 IO34_L5P T14
69 GND 70 GND
71 IO34_L4P V12 72 IO34_L2N U12
73 IO34_L4N W13 74 IO34_L2P T12
75 IO34_L1P T11 76 IO34_L6N R14
77 IO34_L1N T10 78 IO34_L6P P14
79 GND 80 GND
81 IO13_L13P Y7 82 IO13_L21P V11
83 IO13_L13N Y6 84 IO13_L21N V10
85 IO13_L11N V7 86 IO13_L14N Y8
87 IO13_L11P U7 88 IO13_L14P Y9
89 GND 90 GND
91 IO13_L19N U5 92 IO13_L22N W6
93 IO13_L19P T5 94 IO13_L22P V6
95 IO13_L16P W10 96 IO13_L15P V8
97 IO13_L16N W9 98 IO13_L15N W8
99 GND 100 GND
101 IO13_L17P U9 102 IO13_L20P Y12
103 IO13_L17N U8 104 IO13_L20N Y13
105 IO13_L18P W11 106 IO13_L12N U10
107 IO13_L18N Y11 108 IO13_L12P T9
109 GND 110 GND
111 FPGA_TCK F9 112 VP K9
113 FPGA_TMS J6 114 VN L10
115 FPGA_TDO F6 116 PS_POR_B C7
117 FPGA_TDI G6 118 FPGA_E QETILE R11

Kabelo ea phini ea boto ho sehokelo sa boto J30

J30 phini Lebitso la Letshwao ZYNQ Pin

Nomoro

J30 phini Lebitso la Letshwao ZYNQ

Nomoro ea Pin

1 IO35_L1P C20 2 IO35_L15N F20
3 IO35_L1N B20 4 IO35_L15P F19
5 IO35_L18N G20 6 IO35_L5P E18
7 IO35_L18P G19 8 IO35_L5N E19
9 GND T13 10 GND T13
11 IO35_L10N J19 12 IO35_L3N D18
13 IO35_L10P K19 14 IO35_L3P E17
15 IO35_L2N A20 16 IO35_L4P D19
17 IO35_L2P B19 18 IO35_L4N D20
19 GND T13 20 GND T13
21 IO35_L8P M17 22 IO35_L9N L20
23 IO35_L8N M18 24 IO35_L9P L19
25 IO35_L7P M19 26 IO35_L6P F16
27 IO35_L7N M20 28 IO35_L6N F17
29 GND T13 30 GND T13
31 IO35_L17N H20 32 IO35_L16N G18
33 IO35_L17P J20 34 IO35_L16P G17
35 IO35_L19N G15 36 IO35_L13N H17
37 IO35_L19P H15 38 IO35_L13P H16
39 GND T13 40 GND T13
41 IO35_L12N K18 42 IO35_L14N H18
43 IO35_L12P K17 44 IO35_L14P J18
45 IO35_L24N J16 46 IO35_L20P K14
47 IO35_L24P K16 48 IO35_L20N J14
49 GND T13 50 GND T13
51 IO35_L21N N16 52 IO35_L11P L16
53 IO35_L21P N15 54 IO35_L11N L17
55 IO35_L22N L15 56 IO35_L23P M14
57 IO35_L22P L14 58 IO35_L23N M15
59 GND T13 60 GND T13
61 PS_MIO22 B17 62 PS_MIO50 B13
63 PS_MIO27 D13 64 PS_MIO45 B15
65 PS_MIO23 D11 66 PS_MIO46 D16
67 PS_MIO24 A16 68 PS_MIO41 C17
69 GND T13 70 GND T13
71 PS_MIO25 F15 72 PS_MIO7 D8
73 PS_MIO26 A15 74 PS_MIO12 D9
75 PS_MIO21 F14 76 PS_MIO10 E9
77 PS_MIO16 A19 78 PS_MIO11 C6
79 GND T13 80 GND T13
81 PS_MIO20 A17 82 PS_MIO9 B5
83 PS_MIO19 D10 84 PS_MIO14 C5
85 PS_MIO18 B18 86 PS_MIO8 D5
87 PS_MIO17 E14 88 PS_MIO0 E6
89 GND T13 90 GND T13
91 PS_MIO39 C18 92 PS_MIO13 E8
93 PS_MIO38 E13 94 PS_MIO47 B14
95 PS_MIO37 A10 96 PS_MIO48 B12
97 PS_MIO28 C16 98 PS_MIO49 C12
99 GND T13 100 GND T13
101 PS_MIO35 F12 102 PS_MIO52 C10
103 PS_MIO34 A12 104 PS_MIO51 B9
105 PS_MIO33 D15 106 PS_MIO40 D14
107 PS_MIO32 A14 108 PS_MIO44 F13
109 GND T13 110 GND T13
111 PS_MIO31 E16 112 PS_MIO15 C8
113 PS_MIO36 A11 114 PS_MIO42 E12
115 PS_MIO29 C13 116 PS_MIO43 A9
117 PS_MIO30 C15 118 PS_MIO53 C11
119 QSPI_D3_PS_MIO5 A6 120 QSPI_D2_PS_MIO4 B7

www.alinx.com

Litokomane / Lisebelisoa

ALINX AC7Z020 ZYNQ7000 FPGA Boto ea Nts'etsopele [pdf] Bukana ea Mosebelisi
AC7Z020, AC7Z020 ZYNQ7000 FPGA Boto ea Nts'etsopele, ZYNQ7000 FPGA Boto ea Nts'etsopele, Boto ea Ntlafatso ea FPGA, Boto ea Nts'etsopele, Boto

Litšupiso

Tlohela maikutlo

Aterese ea hau ea lengolo-tsoibila e ke ke ea phatlalatsoa. Libaka tse hlokahalang li tšoailoe *