ALINX AC7Z020 ZYNQ7000 FPGA Papa Hoʻomohala

ʻIke Huahana

ʻO ka ZYNQ7000 FPGA Development Board kahi papa hoʻomohala e hōʻike ana i ka chip XC7Z100-1CLG400I, kahi ʻāpana o ka ZYNQ7000 series. Loaʻa iā ia kahi papa hana noiʻi ARM lua-core CortexA9 me ka wikiwiki o ka uaki a hiki i 800MHz, 256KB on-chip RAM, a me kahi kikowaena waihona waho e kākoʻo ana i ka 16/32 bit DDR2, DDR3 interface. Loaʻa i ka papa ke kākoʻo ʻelua Gigabit NIC, ʻelua mau kikowaena USB2.0 OTG, ʻelua mau kaʻa kaʻa CAN2.0B, ʻelua kāleka SD, SDIO, MMC kūpono nā mea hoʻokele, 2 SPI, 2 UART, 2 mau pilina I2C, a me 4 mau pai o 32bit GPIO. He papa koʻikoʻi ka papa (AC7Z010) e hoʻohana ana i ʻelua mau pahu Micron's MT41K128M16TW-107 DDR3 me kahi mana hui o 256MB a me kahi ākea kaʻa kaʻa ʻikepili o 32-bit. Loaʻa i ka papa nā LED mea hoʻohana, nā kī hoʻohana, ke poʻo hoʻonui, JTAG awa debug, a me ka lako mana.

Nā ʻōlelo hoʻohana huahana

No ka hoʻohana ʻana i ka ZYNQ7000 FPGA Development Board, e hahai i kēia mau ʻanuʻu:

1. E hoʻohui i ka mana i ka papa.
2. Hoʻohui i ka papa i kāu kamepiula me ke kelepona USB.
3. E hoʻouka i nā mea hoʻokele pono no ka papa ma kāu kamepiula.
4. E wehe i kāu kaiapuni hoʻomohala polokalamu a hana i kahi papahana hou.
5. E hoʻonohonoho i kāu hoʻonohonoho papahana e hoʻohana i ka ZYNQ7000 FPGA Development Board.
6. Kākau i kāu code a hoʻohui.
7. Hoʻouka i ke code i hōʻuluʻulu ʻia i ka papa me ka JTAG awa debug.
8. E ho'āʻo i kāu code ma ka papa.

Nānā: E nānā i ka manuale hoʻohana no ka ʻike kikoʻī e pili ana i nā hiʻohiʻona a me ka hoʻohana ʻana o ka papa.

Palapala Hoʻolaha

Manao	Lā	Hoʻokuʻu ʻia e	wehewehe
Hōʻike 1.0	2019-12-15	Rachel Zhou	Hoʻokuʻu mua

AC7Z010 papa kumu

AC7Z010 papa kumu hoʻolauna

• AC7Z010 (hoʻohālike papa kumu, like ma lalo) FPGA papa kumu, ZYNQ chip i hoʻokumu ʻia ma XC7Z010-1CLG400I o XILINX hui ZYNQ7000 series. Hoʻohui ka ʻōnaehana PS o ka ZYNQ chip i ʻelua mau kaʻina hana ARM CortexTM-A9, AMBA® interconnects, hoʻomanaʻo i loko, nā pilina hoʻomanaʻo waho a me nā peripheral. Loaʻa i ka FPGA o ka chip ZYNQ ka waiwai o nā polokalamu logic programmable, DSP a me RAM i loko.
• Ke hoʻohana nei kēia papa koʻikoʻi i ʻelua mau pahu Micron's MT41K128M16TW-107 DDR3, ʻo kēlā me kēia me ka mana o 256MB; ʻO nā pahu DDR ʻelua i hui pū ʻia e hana i kahi 32-bit data bus width, a me ka pinepine o ka uaki o ka heluhelu a kākau ʻana i ka ʻikepili ma waena o ZYNQ a me DDR3 A hiki i 533Mhz; hiki i kēia hoʻonohonoho ke hoʻokō i nā pono o ka ʻōnaehana ʻikepili kiʻekiʻe-bandwidth
• No ka hoʻohui ʻana me ka papa lawe, ua hoʻonui ʻia nā mea hoʻohui papa-a-papa ʻelua o kēia papa kumu me nā awa USB ma ka ʻaoʻao PS, nā kikowaena Gigabit Ethernet, ka slot kāleka SD, a me nā awa MIO ʻē aʻe i koe (48). Aneane kokoke i nā awa IO (100) o BANK13 (no AC7Z010 wale nō), BAN34 a me BANK35 ma ka ʻaoʻao PL, hiki ke hāʻawi ʻia nā pae IO o BANK34 a me BANK35 ma o ka papa lawe e hoʻokō i nā koi o nā mea hoʻohana no nā pae pae like ʻole. No nā mea hoʻohana i makemake i ka nui o IO, he koho maikaʻi kēia papa kumu. A ʻo ka ʻāpana pili IO, ʻo ka ZYNQ chip i ke kikowaena ma waena o ka lōʻihi like a me ka hoʻoili ʻokoʻa, a ʻo ka nui o ka papa kumu he 35 * 42 (mm) wale nō, kūpono loa ia no ka hoʻomohala kiʻekiʻe.

ZYNQ Chip

Ke hoʻohana nei ka papa kumu FPGA AC7Z010 i kā Xilinx's Zynq7000 series chip, module XC7Z010-1CLG400I. Hoʻohui ka ʻōnaehana PS o ka chip i ʻelua mau kaʻina hana ARM Cortex™-A9, AMBA® interconnects, hoʻomanaʻo i loko, nā pilina hoʻomanaʻo waho a me nā peripheral. ʻO kēia mau peripheral ka nui o ka USB bus interface, Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus interface, UART interface, GPIO etc. Hiki i ka PS ke hana kūʻokoʻa a hoʻomaka i ka mana a i ʻole ka hoʻonohonoho hou. Hōʻike kikoʻī ka Kiʻi 2-2-1 i ka Diagram Block Overall o ka ZYNQ7000 Chip.

ʻO nā palena nui o ka ʻāpana ʻōnaehana PS penei:

• ARM lua-core CortexA9-mea hoʻohana palapala noi, ARM-v7 hale hana, a hiki i 800MHz
• 32KB pae 1 aʻo a me ka ʻikepili huna no ka CPU, 512KB pae 2 cache 2 kaʻana CPU
• On-chip boot ROM a me 256KB on-chip RAM
• ʻO ke kikowaena mālama waho, kākoʻo i ka 16/32 bit DDR2, DDR3 interface
• Kākoʻo ʻelua Gigabit NIC: DMA divergent-aggregate, GMII, RGMII, SGMII interface
• ʻElua mau kikowaena USB2.0 OTG, e kākoʻo ana kēlā me kēia a hiki i 12 nodes
• ʻElua mau kaʻa kaʻa CAN2.0B
• ʻElua kāleka SD, SDIO, MMC kūpono
• 2 SPI, 2 UART, 2 mau pilina I2C
• 4 mau pai o 32bit GPIO, 54 (32 + 22) e like me PS system IO, 64 pili ia PL
• ʻO ka pilina bandwidth kiʻekiʻe i loko o PS a me PS a PL

ʻO nā palena nui o ka māhele PL logic penei:

• Nā Pūnaehana Loko: 28K
• Nā papa nānā-nānā (LUTs): 17600
• Paʻa-pale: 35,200
• 18x25MACCs: 80
• Pale RAM: 240KB
• ʻElua mau mea hoʻololi AD no on-chip voltage, ʻike wela a hiki i ka 17 mau ala hoʻokomo ʻokoʻa waho, 1MBPS
• ʻO XC7Z100-1CLG400I ka helu wikiwiki chip -1, ʻoihana ʻenehana, ʻo ka pahu BGA400, ʻo ka pin pitch he 0.8mm ka wehewehe kikoʻī kikoʻī o ka moʻo ZYNQ7000 i hōʻike ʻia ma ke Kiʻi 2-2-2

DDR3 DRAM

• Hoʻolako ʻia ka papa kumu FPGA AC7Z010 me ʻelua mau pahu Micron DDR3 SDRAM (1GB i ka huina), ka hoʻohālike MT41K128M16TW-107 (Kupono me Hynix
• H5TQ2G63AFR-PBI). ʻO ka nui o ka laulā kaʻa o DDR3 SDRAM he 32bit. Hoʻohana ʻo DDR3 SDRAM i ka wikiwiki o 533MHz (data rate1066Mbps). Hoʻopili pololei ʻia ka ʻōnaehana hoʻomanaʻo DDR3 i ke kikowaena hoʻomanaʻo o ka BANK 502 o ka ZYNQ Processing System (PS). Hōʻike ʻia ka hoʻonohonoho kikoʻī o DDR3 SDRAM ma ka Papa 2-3-1 ma lalo nei:

Helu Bit	Hoʻohālike Chip	Ka hiki	Hale hana
U8,U9	MT41K128M16TW-107	256M x 16bit	Micron

Papa 2-3-1: Hoʻonohonoho DDR3 SDRAM

Pono ka hoʻolālā ʻenehana o DDR3 e noʻonoʻo pono i ka pono o ka hōʻailona. Ua noʻonoʻo piha mākou i ke kūʻē ʻana o ka resistor/terminal, trace impedance control, a me ka mālama ʻana i ka lōʻihi i ka hoʻolālā kaapuni a me ka hoʻolālā PCB e hōʻoia i ka hana kiʻekiʻe a paʻa o DDR3.

DDR3 DRAM pine pine:

inoa hōʻailona	ZYNQ Pin Name	Helu Pin ZYNQ
DDR3_DQS0_P	PS_DDR_DQS_P0_502	C2
DDR3_DQS0_N	PS_DDR_DQS_N0_502	B2
DDR3_DQS1_P	PS_DDR_DQS_P1_502	G2
DDR3_DQS1_N	PS_DDR_DQS_N1_502	F2
DDR3_DQS2_P	PS_DDR_DQS_P2_502	R2
DDR3_DQS2_N	PS_DDR_DQS_N2_502	T2
DDR3_DQS3_P	PS_DDR_DQS_P3_502	W5
DDR3_DQS4_N	PS_DDR_DQS_N3_502	W4
DDR3_D0	PS_DDR_DQ0_502	C3
DDR3_D1	PS_DDR_DQ1_502	B3
DDR3_D2	PS_DDR_DQ2_502	A2
DDR3_D3	PS_DDR_DQ3_502	A4
DDR3_D4	PS_DDR_DQ4_502	D3
DDR3_D5	PS_DDR_DQ5_502	D1
DDR3_D6	PS_DDR_DQ6_502	C1
DDR3_D7	PS_DDR_DQ7_502	E1
DDR3_D8	PS_DDR_DQ8_502	E2
DDR3_D9	PS_DDR_DQ9_502	E3

DDR3_D10	PS_DDR_DQ10_502	G3
DDR3_D11	PS_DDR_DQ11_502	H3
DDR3_D12	PS_DDR_DQ12_502	J3
DDR3_D13	PS_DDR_DQ13_502	H2
DDR3_D14	PS_DDR_DQ14_502	H1
DDR3_D15	PS_DDR_DQ15_502	J1
DDR3_D16	PS_DDR_DQ16_502	P1
DDR3_D17	PS_DDR_DQ17_502	P3
DDR3_D18	PS_DDR_DQ18_502	R3
DDR3_D19	PS_DDR_DQ19_502	R1
DDR3_D20	PS_DDR_DQ20_502	T4
DDR3_D21	PS_DDR_DQ21_502	U4
DDR3_D22	PS_DDR_DQ22_502	U2
DDR3_D23	PS_DDR_DQ23_502	U3
DDR3_D24	PS_DDR_DQ24_502	V1
DDR3_D25	PS_DDR_DQ25_502	Y3
DDR3_D26	PS_DDR_DQ26_502	W1
DDR3_D27	PS_DDR_DQ27_502	Y4
DDR3_D28	PS_DDR_DQ28_502	Y2
DDR3_D29	PS_DDR_DQ29_502	W3
DDR3_D30	PS_DDR_DQ30_502	V2
DDR3_D31	PS_DDR_DQ31_502	V3
DDR3_DM0	PS_DDR_DM0_502	A1
DDR3_DM1	PS_DDR_DM1_502	F1
DDR3_DM2	PS_DDR_DM2_502	T1
DDR3_DM3	PS_DDR_DM3_502	Y1
DDR3_A0	PS_DDR_A0_502	N2
DDR3_A1	PS_DDR_A1_502	K2
DDR3_A2	PS_DDR_A2_502	M3
DDR3_A3	PS_DDR_A3_502	K3
DDR3_A4	PS_DDR_A4_502	M4
DDR3_A5	PS_DDR_A5_502	L1
DDR3_A6	PS_DDR_A6_502	L4
DDR3_A7	PS_DDR_A7_502	K4
DDR3_A8	PS_DDR_A8_502	K1
DDR3_A9	PS_DDR_A9_502	J4

DDR3_A10	PS_DDR_A10_502	F5
DDR3_A11	PS_DDR_A11_502	G4
DDR3_A12	PS_DDR_A12_502	E4
DDR3_A13	PS_DDR_A13_502	D4
DDR3_A14	PS_DDR_A14_502	F4
DDR3_BA0	PS_DDR_BA0_502	L5
DDR3_BA1	PS_DDR_BA1_502	R4
DDR3_BA2	PS_DDR_BA2_502	J5
DDR3_S0	PS_DDR_CS_B_502	N1
DDR3_RAS	PS_DDR_RAS_B_502	P4
DDR3_CAS	PS_DDR_CAS_B_502	P5
DDR3_WE	PS_DDR_WE_B_502	M5
DDR3_ODT	PS_DDR_ODT_502	N5
DDR3_RESET	PS_DDR_DRST_B_502	B4
DDR3_CLK0_P	PS_DDR_CKP_502	L2
DDR3_CLK0_N	PS_DDR_CKN_502	M2
DDR3_CKE	PS_DDR_CKE_502	N3

QSPI Flash

Hoʻolako ʻia ka papa kumu FPGA AC7Z010 me hoʻokahi puʻupuʻu 256MBit Quad-SPI FLASH, ʻo ke kumu hoʻohālike uila ʻo W25Q256FVEI, e hoʻohana ana i ka vol 3.3V CMOStage maʻamau. Ma muli o keʻanoʻole o ka QSPI FLASH, hiki ke hoʻohanaʻia ma keʻano he pahu pahu no ka pūnaewele e mālama i ke kiʻi boot o ka pūnaewele. Aia kēia mau kiʻi i ka bit FPGA files, code ARM application, a me nā ʻikepili mea hoʻohana ʻē aʻe files. Hōʻike ʻia nā hiʻohiʻona kikoʻī a me nā ʻāpana pili o QSPI FLASH ma ka Papa 2-4-1.

Kūlana	Hoʻohālike	Ka hiki	Hale hana
U15	W25Q256FVEI	32M Byte	Winbond

Papa 2-4-1: QSPI FLASH Specification
Hoʻopili ʻia ʻo QSPI FLASH i ke awa GPIO o ka BANK500 ma ka ʻāpana PS o ka chip ZYNQ. I ka hoʻolālā ʻōnaehana, pono e hoʻonohonoho ʻia nā hana port GPIO o kēia mau awa PS e like me ka QSPI FLASH interface. Hōʻike ka Figure 2-4-1 i ka QSPI Flash i ka schematic.

E hoʻonohonoho i nā hana pin chip:

inoa hōʻailona	ZYNQ Pin Name	Helu Pin ZYNQ
QSPI_SCK	PS_MIO6_500	A5
QSPI_CS	PS_MIO1_500	A7
QSPI_D0	PS_MIO2_500	B8
QSPI_D1	PS_MIO3_500	D6
QSPI_D2	PS_MIO4_500	B7
QSPI_D3	PS_MIO5_500	A6

Hoʻonohonoho uaki

Hāʻawi ka papa kumu AC7Z010 i kahi uaki ikaika no ka ʻōnaehana PS, i hiki i ka ʻōnaehana PS ke hana kūʻokoʻa.
Pūnaehana uaki PS kumu
Hāʻawi ka pahu ZYNQ i ka 33.333333MHz hoʻokomo uaki no ka ʻāpana PS ma o ka aniani X1 ma ka papa kumu. Hoʻopili ʻia ka hoʻokomo uaki i ka pine PS_CLK_500 o ka chip ZYNQ BANK500. Hōʻike ʻia kāna kiʻi kiʻi ma ke Kiʻi 2-5-1:

ʻO ka hana pin uaki:

inoa hōʻailona	ZYNQ Pin
PS_CLK_500	E7

Lako ikehu
Ka mana lako voltage o ka AC7Z010 core papa ʻo DC5V, i hoʻolako ʻia ma ka hoʻopili ʻana i ka papa lawe. Eia kekahi, hāʻawi ʻia ka mana o BANK34 a me BANK35 ma o ka papa lawe. Hōʻike ʻia ke kiʻi schematic o ka hoʻolālā lako mana ma ka papa kumu ma ke Kiʻi 2-6-1:

Hoʻohana ʻia ka papa hoʻomohala FPGA e + 5V, a ua hoʻololi ʻia i + 1.0V, + 1.8V, + 1.5V, + 3.3V ʻehā mau lako mana ma o ʻehā mau pahu mana DC / DC. ʻO ka mea hoʻopuka o kēia manawa o + 1.0V hiki ke hiki i 6A, + 1.8V a me + 1.5V mana puka mana o kēia manawa he 3A, + 3.3V puka i kēia manawa he 500mA. Loaʻa iā J29 he 4 pine i kēlā me kēia e hāʻawi i ka mana iā FPGA BANK34 a me BANK35. ʻO 3.3V ka paʻamau. Hiki i nā mea hoʻohana ke hoʻololi i ka mana o BANK34 a me BANK35 ma ka hoʻololi ʻana iā VCCIO34 a me VCCIO35 ma ka mokulele hope. Hoʻopuka ka 1.5V i ka vol VTT a me VREFtage koi ʻia e DDR3 ma o TPS51206 o TI. Hōʻike ʻia nā hana o kēlā me kēia māhele mana ma ka papa aʻe:

Lako ikehu	Hana
+1.0V	ʻO ZYNQ PS a me PL ʻāpana Core Voltage
+1.8V	ZYNQ PS a me PL kōkua hapa voltage BANK501 IO voltage
+3.3V	Banako ZYNQ0, Baneko500, QSIP FLASH Uaki Crystal

+1.5V	DDR3, ZYNQ Bank501
VREF,VTT(+0.75V)	DDR3
VCCIO34/35	Banako34, Baneko35

No ka mea, loaʻa i ka mana o ka ZYNQ FPGA ka mana o ke kaʻina hana, ma ka hoʻolālā kaapuni, ua hoʻolālā mākou e like me nā koi mana o ka chip. ʻO ke kaʻina hana mana he + 1.0V->+1.8V->(+1.5 V, +3.3V, VCCIO) hoʻolālā kaapuni e hōʻoia i ka hana maʻamau o ka chip. No ka mea, ua hoʻoholo ʻia nā pae kiʻekiʻe o BANK34 a me BANK35 e ka lako mana i hāʻawi ʻia e ka papa lawe lawe, ʻo ka mea kiʻekiʻe loa ʻo 3.3V. Ke hoʻolālā ʻoe i ka papa lawe lawe e hāʻawi i ka mana VCCIO34 a me VCCIO35 no ka papa kumu, ʻoi aku ka lohi o ke kaʻina mana ma mua o + 5V.

AC7Z010 ka nui o ka papa kumu

Hāʻawi ʻia ʻo Board to Board Connectors pin
ʻO ka papa kumu he ʻelua mau awa hoʻonui kiʻekiʻe. Hoʻohana ia i ʻelua 120-pin inter-board connectors (J29/J30) e hoʻopili i ka papa lawe. He 0.5mm ka mamao PIN o ka papa i ka mea hoʻohui papa, ma waena o lākou, pili ʻo J29 i ka mana 5V, VCCIO mana hoʻokomo, kekahi mau hōʻailona IO a me JTAG nā hōʻailona, ​​a pili ʻo J30 i nā hōʻailona IO i koe a me MIO. Hiki ke hoʻololi ʻia ka pae IO o BANK34 a me BANK35 ma ka hoʻoponopono ʻana i ka hoʻokomo VCCIO ma ka mea hoʻohui, ʻaʻole ʻoi aku ka kiʻekiʻe kiʻekiʻe ma mua o 3.3V. ʻO ka papa lawe lawe AX7Z010 a mākou i hoʻolālā ai he 3.3V ma ka paʻamau. E hoʻomaopopo ʻaʻole ka IO o BANK13

Hoʻokaʻina pine o ka papa i ka mea hoʻohui papa J29

J29 Pin	hōʻailona  inoa	ZYNQ Pin Helu	J29 Pin	inoa hōʻailona	ZYNQ Pin Helu
1	VCC5V	–	2	VCC5V	–
3	VCC5V	–	4	VCC5V	–
5	VCC5V	–	6	VCC5V	–
7	VCC5V	–	8	VCC5V	–
9	GND	–	10	GND	–
11	VCCIO_34	–	12	VCCIO_35	–
13	VCCIO_34	–	14	VCCIO_35	–
15	VCCIO_34	–	16	VCCIO_35	–
17	VCCIO_34	–	18	VCCIO_35	–
19	GND	–	20	GND	–
21	IO34_L10P	V15	22	IO34_L7P	Y16
23	IO34_L10N	W15	24	IO34_L7N	Y17
25	IO34_L15N	U20	26	IO34_L17P	Y18
27	IO34_L15P	T20	28	IO34_L17N	Y19
29	GND	–	30	GND	–
31	IO34_L9N	U17	32	IO34_L8P	W14
33	IO34_L9P	T16	34	IO34_L8N	Y14
35	IO34_L12N	U19	36	IO34_L3P	U13
37	IO34_L12P	U18	38	IO34_L3N	V13
39	GND	–	40	GND	–
41	IO34_L14N	P20	42	IO34_L21N	V18
43	IO34_L14P	N20	44	IO34_L21P	V17
45	IO34_L16N	W20	46	IO34_L18P	V16
47	IO34_L16P	V20	48	IO34_L18N	W16
49	GND	–	50	GND	–
51	IO34_L22N	W19	52	IO34_L23P	N17
53	IO34_L22P	W18	54	IO34_L23N	P18
55	IO34_L20N	R18	56	IO34_L13N	P19
57	IO34_L20P	T17	58	IO34_L13P	N18
59	GND	–	60	GND	–

61	IO34_L19N	R17	62	IO34_L11N	U15
63	IO34_L19P	R16	64	IO34_L11P	U14
65	IO34_L24P	P15	66	IO34_L5N	T15
67	IO34_L24N	P16	68	IO34_L5P	T14
69	GND	–	70	GND	–
71	IO34_L4P	V12	72	IO34_L2N	U12
73	IO34_L4N	W13	74	IO34_L2P	T12
75	IO34_L1P	T11	76	IO34_L6N	R14
77	IO34_L1N	T10	78	IO34_L6P	P14
79	GND	–	80	GND	–
81	IO13_L13P	Y7	82	IO13_L21P	V11
83	IO13_L13N	Y6	84	IO13_L21N	V10
85	IO13_L11N	V7	86	IO13_L14N	Y8
87	IO13_L11P	U7	88	IO13_L14P	Y9
89	GND	–	90	GND	–
91	IO13_L19N	U5	92	IO13_L22N	W6
93	IO13_L19P	T5	94	IO13_L22P	V6
95	IO13_L16P	W10	96	IO13_L15P	V8
97	IO13_L16N	W9	98	IO13_L15N	W8
99	GND	–	100	GND	–
101	IO13_L17P	U9	102	IO13_L20P	Y12
103	IO13_L17N	U8	104	IO13_L20N	Y13
105	IO13_L18P	W11	106	IO13_L12N	U10
107	IO13_L18N	Y11	108	IO13_L12P	T9
109	GND	–	110	GND	–
111	FPGA_TCK	F9	112	VP	K9
113	FPGA_TMS	J6	114	VN	L10
115	FPGA_TDO	F6	116	PS_POR_B	C7
117	FPGA_TDI	G6	118	FPGA_PAʻA	R11

Hoʻokaʻina pine o ka papa i ka mea hoʻohui papa J30

J30 Pin	inoa hōʻailona	ZYNQ Pin Helu	J30 Pin	inoa hōʻailona	ZYNQ Helu Pin
1	IO35_L1P	C20	2	IO35_L15N	F20

3	IO35_L1N	B20	4	IO35_L15P	F19
5	IO35_L18N	G20	6	IO35_L5P	E18
7	IO35_L18P	G19	8	IO35_L5N	E19
9	GND	T13	10	GND	T13
11	IO35_L10N	J19	12	IO35_L3N	D18
13	IO35_L10P	K19	14	IO35_L3P	E17
15	IO35_L2N	A20	16	IO35_L4P	D19
17	IO35_L2P	B19	18	IO35_L4N	D20
19	GND	T13	20	GND	T13
21	IO35_L8P	M17	22	IO35_L9N	L20
23	IO35_L8N	M18	24	IO35_L9P	L19
25	IO35_L7P	M19	26	IO35_L6P	F16
27	IO35_L7N	M20	28	IO35_L6N	F17
29	GND	T13	30	GND	T13
31	IO35_L17N	H20	32	IO35_L16N	G18
33	IO35_L17P	J20	34	IO35_L16P	G17
35	IO35_L19N	G15	36	IO35_L13N	H17
37	IO35_L19P	H15	38	IO35_L13P	H16
39	GND	T13	40	GND	T13
41	IO35_L12N	K18	42	IO35_L14N	H18
43	IO35_L12P	K17	44	IO35_L14P	J18
45	IO35_L24N	J16	46	IO35_L20P	K14
47	IO35_L24P	K16	48	IO35_L20N	J14
49	GND	T13	50	GND	T13
51	IO35_L21N	N16	52	IO35_L11P	L16
53	IO35_L21P	N15	54	IO35_L11N	L17
55	IO35_L22N	L15	56	IO35_L23P	M14
57	IO35_L22P	L14	58	IO35_L23N	M15
59	GND	T13	60	GND	T13
61	PS_MIO22	B17	62	PS_MIO50	B13
63	PS_MIO27	D13	64	PS_MIO45	B15
65	PS_MIO23	D11	66	PS_MIO46	D16
67	PS_MIO24	A16	68	PS_MIO41	C17
69	GND	T13	70	GND	T13
71	PS_MIO25	F15	72	PS_MIO7	D8
73	PS_MIO26	A15	74	PS_MIO12	D9

75	PS_MIO21	F14	76	PS_MIO10	E9
77	PS_MIO16	A19	78	PS_MIO11	C6
79	GND	T13	80	GND	T13
81	PS_MIO20	A17	82	PS_MIO9	B5
83	PS_MIO19	D10	84	PS_MIO14	C5
85	PS_MIO18	B18	86	PS_MIO8	D5
87	PS_MIO17	E14	88	PS_MIO0	E6
89	GND	T13	90	GND	T13
91	PS_MIO39	C18	92	PS_MIO13	E8
93	PS_MIO38	E13	94	PS_MIO47	B14
95	PS_MIO37	A10	96	PS_MIO48	B12
97	PS_MIO28	C16	98	PS_MIO49	C12
99	GND	T13	100	GND	T13
101	PS_MIO35	F12	102	PS_MIO52	C10
103	PS_MIO34	A12	104	PS_MIO51	B9
105	PS_MIO33	D15	106	PS_MIO40	D14
107	PS_MIO32	A14	108	PS_MIO44	F13
109	GND	T13	110	GND	T13
111	PS_MIO31	E16	112	PS_MIO15	C8
113	PS_MIO36	A11	114	PS_MIO42	E12
115	PS_MIO29	C13	116	PS_MIO43	A9
117	PS_MIO30	C15	118	PS_MIO53	C11
119	QSPI_D3_PS_MIO5	A6	120	QSPI_D2_PS_MIO4	B7

www.alinx.com

Palapala / Punawai

ALINX AC7Z020 ZYNQ7000 FPGA Papa Hoʻomohala [pdf] Palapala Hoʻohana AC7Z020, AC7Z020 ZYNQ7000 FPGA Development Board, ZYNQ7000 FPGA Development Board, FPGA Development Board, Development Board, Papa

Nā kuhikuhi

• Palapala Hoʻohana