RENESAS ForgeFPGA Software Simulation

Mashoko Akakosha

Simulation inzira yekushandisa akasiyana ekuisa inosimudzira kudhizaini panguva dzakasiyana kutarisa kana iyo RTL kodhi ichiita nenzira yakarongwa. Inoshandiswa kuratidza kusimba kwechigadzirwa. Simulation inobvumira mushandisi kuita view dhiyagiramu yenguva yezviratidzo zvine hukama kuti unzwisise kuti tsananguro yedhizaini mudhizaini file kuzvibata.

Testbenches zvimedu zvekodhi zvinoshandiswa pakuenzanisa. Yakareruka testbench inosimbisa iyo Unit Under Test (UUT) uye inotyaira iyo yekuisa. Go Configure software inoshandisa Icarus Verilog (iVerilog) uye GTKWave kuona masimulation waveform nekurudziro yakapihwa mubhenji rebvunzo.

Gwaro iri rinotsanangura matanho anofanirwa kutorwa paunenge uchiisa Icarus pane yako system uye maitiro ekufambisa akabudirira simulation.

Kuisa Icarus Verilog

a. Isa iyo yazvino vhezheni yeIcarus Verilog (IVerilog) kubva https://bleyer.org/icarus/
b. Iva nechokwadi chekuwedzera IVerilog kuPATH uye rega iise GTKWAve (Ona Mufananidzo 1)

c. Vhura iyo Go Configure Software uye sarudza chikamu: SLG47910 (Rev BB) kuvhura iyo Forge Workshop (ona Mufananidzo 2).

d. Dzvanya paFPGA Mharidzo iri pakati petururira kumusoro kana mushandisi anogona zvakare kudzvanya kaviri paFPGA Core chimiro pakati pehwindo.

e. Hwindo idzva rinovhurwa rinonzi Forge Workshop. Mumenu toolbar pamusoro, tinya Options → Settings. Mubhokisi rebhokisi reZvirongwa, enda kuZvishandiso pasi peMushandisi Settings tab. Usasarudza iyo Shandisa "system yemamiriro bhokisi" kune ese Icarus Verilog uye GTKWave. Wedzera nzira yeIverilog uye GTKWave yakachengetwa muhurongwa hwako munzvimbo yakapihwa (ona Mufananidzo 4).

Mese makagadzikwa pasi kuti mutevedzere testbench uye matanho ari pamusoro anovimbisa kuti GTKWave inotangisa otomatiki paunenge uchitevedzera testbench paGo Configure software.

Testbench

Nhanho inonyanya kukosha pakuita zvinobudirira chero system ndeyekuona dhizaini uye kushanda kwayo. Kuongorora hurongwa hwakaoma mushure mekushandisa iyo hardware haisi sarudzo yehungwaru. Hazvishandi maererano nemari, nguva, uye zviwanikwa. Nekudaro, mune yeFPGA, testbench inoshandiswa kuyedza Verilog source code.

Ngatitii tine yekupinda iyo yegumi nerimwe bhiti, uye isu tinoda kuyedza mudziyo kune ese anobvira ekuisa musanganiswa kukosha kureva (11). Sezvo iyi iri nhamba yakakura kwazvo yekusanganiswa, hazvibviri kuiedza nemaoko. Mumamiriro ezvinhu akadaro, testbenches inobatsira zvikuru sezvo iwe unogona kuedza dhizaini otomatiki kune ese anogoneka kukosha uye nekudaro, simbisa kuvimbika kweiyo bvunzo dhizaini. Verilog Testbenches inoshandiswa kutevedzera uye kuongorora madhizaini pasina kudiwa kwechero mudziyo wehardware.

Dhizaini iri pasi pekuyedzwa, yakapfupikiswa seDUT, iri synthesizeble module yekushanda kwatinoda kuyedza. Mune mamwe mazwi, ndiyo dhizaini yedunhu yatinoda kuyedza. Tinogona kutsanangura DUT yedu tichishandisa imwe yeatatu emhando dzemhando muVerilog - Gate-level, Dataflow, kana Behavioral.

Testbench haigone kugadzirwa, nekudaro inoshandiswa kune yekufananidza chete. Izvi zvinobvumira mushandisi kushandisa huwandu hwakazara hweVerilog constructs eg, mazwi makuru akadai se "for", "$ kuratidza" uye "$monitor" nezvimwewo pakunyora testbenches. Iyo yakapfava testbench inosimbisa iyo Unit Under Test (UUT) kana Chishandiso Chiri Muedzo (DUT) uye dhiraivha mapopu.

Kunzwisisa Testbench

Timecale Tsanangudzo muTestbench

Paunenge uchitevedzera, software inoda kuziva kuti nguva yakatsanangurwa sei. Iyo yekunonoka unit inotsanangurwa uchishandisa iyo `timescale dhairekitori, iyo inotsanangura iyo nguva unit uye nemazvo emamodule anoitevera. Iyo `timescale inobatsira pakuona kuti #1 inorevei maererano nenguva. # inoshandiswa kutsanangura kunonoka kuunzwa muhurongwa zvinoenderana nenguva yeyuniti inotsanangurwa mutimescale. Saka, #1 inoreva 1 ns yekunonoka kana nguva_yuniti iri mu ns.

Syntax:
`nguva / /

time_unit ndiyo nguva yekunonoka kwe #1 inomiririra. Iyo time_precision base inomiririra kuti mangani mapoinzi echokwadi ekushandisa anoenderana nezvikamu zvenguva. (Ona mutsara 23 mumufananidzo 5)

Isu tinogona kushandisa timecale inovaka kushandisa akasiyana nguva mayuniti mudhizaini imwechete. Mushandisi anofanirwa kuyeuka kuti kunonoka kutaurwa hakugone kugadziridzwa uye hakugone kuchinjirwa kune hardware logic. Iwo anononoka mabasa ndeezvekufananidza zvinangwa. $nguva uye $realtime masisitimu mabasa anodzosa nguva iripo uye iyo yekusagadzika yekubika fomati inogona kuchinjwa neimwe system basa $timeformat .

Example: 

`timescale 10us/100ns
`timescale 1ns/1ps
#10 reset = 1; // inononoka chiratidzo ne10 ns
#0.49 $display( “T = %0t at Time #0.49”, $realtime);

Iko kunonoka kunotsanangurwa ndeye #0.49 iyo iri pasi pehafu yenguva yeyuniti. Nekudaro, iyo nguva chaiyo inotsanangurwa kuve 1ps uye nekudaro simulator haigone kuenda idiki pane 1ns izvo zvinoita kuti itenderere yakapihwa yekunonoka chirevo uye goho 0ns. Saka, chirevo ichi chinotadza kupa chero kunonoka.

Simulation Log: 

T = 1 panguva #0.49

Module Declaration

Module kuzivisa mune chero testbench haina kufanana neiyo huru Verilog kodhi. Mune testbench, iyo module inoziviswa pasina chero terminal ports pamwe chete nayo. (Ona mutsara 25 mumufananidzo 5)

Syntax: 

module ;

Iyo module declaration inoteverwa nekutsanangura iyo yekupinza uye yekubuda masiginecha inotsanangurwa kare muhukuru dhizaini file.
Isu tinoshandisa mhando mbiri dzechiratidzo chekutyaira uye chekutarisa masaini panguva yekufananidza. Iyo reg datatype inobata kukosha kusvika kukosha kutsva kupihwa kwairi. Iyi datatype inogona kupihwa kukosha chete mune nguva dzose kana yekutanga block.
Iyo datatype yewaya yakafanana neyekubatana kwemuviri. Ichabata kukosha kunofambiswa nechiteshi, kugovera chirevo, kana reg. Iyi data data haigone kushandiswa pakutanga kana kugara ichivharira. Chero chipi nechipi cheparameter uye chiziviso chakakwana chinoitwawo muchikamu chino.

Example:
Reg a,b; // iyo inopinza muHDL kodhi inotsanangurwa se reg mu testbench
Wire y; // chiratidzo chekubuda muHDL chinotsanangurwa sewaya mu testbench

DUT Instantiation

Chinangwa chebhenji rekuyedza kuona kana module yedu yeDUT iri kushanda. Nekudaro, isu tinofanirwa kusimudzira yedu dhizaini module yekuyedza module.

Syntax: 

(. (chiratidzo1), . chiratidzo1> (chiratidzo2));

Example:

ALU d0 (.a(a), // chiratidzo "a" muALU inofanira kubatana ne"a" muALU_tb module.
.b(b)
.c(c)) ;// chiratidzo “c” muALU chinofanira kubatana ne”c” muALU_tb module

Isu takasimbisa iyo DUT module ALU kune bvunzo module. Zita remuenzaniso (d0) isarudzo yemushandisi. Masaini ane nguva "." pamberi pavo pane mazita ezviratidzo mukati meALU module, nepo waya kana reg yavanosangana nayo mubhenji rekuedza iri pedyo nechiratidzo chiri muparenthesis (). Zvinokurudzirwa kukodha yega yega yekubatanidza chiteshi mumutsara wakasiyana kuitira kuti chero meseji yekukanganisa yekubatanidza inongedze kune iyo mutsara nhamba pakaitika kukanganisa. Nekuda kwekuti kubatanidza uku kunoitwa nemazita, kurongeka kwaanoita hakuna basa.

DUT instantiation inogonawo kuitirwa mamodule apo testbench module ine mazita akasiyana echiratidzo. Iyo mepu chaiyo yemasaini ndiyo yakakosha pakumisikidza.

Example: 

ALU d0 (.a(A), // chiratidzo "a" muALU inofanira kubatana ne "A" muALU_tb module.
.clk(wachi), // chiratidzo "clk" muALU inofanira kubatana ne "wachi" ALU_tb module
.kunze(OUT)); // siginecha "kunze" muALU inofanirwa kubatana ne "OUT" muALU_tb module

Nguva dzose & Yekutanga Block muTestbench

Kune maviri akateedzana mabhuroko muVerilog, yekutanga uye nguva dzose. Mumabhuroko aya ndimo matinoisa stimulus.

Chekutanga block

Iyo yekutanga block inoitwa kamwe chete uye inogumiswa kana mutsara wekupedzisira we block waitwa. Kurudziro inonyorwa mubhuroko rekutanga. (Ona mutsara 54-72 mumufananidzo 5)

Syntax:
..
kutanga kutanga
$ dumpfile();
$dumpvars();
..(pinda stimulus)
end

bhanhire rekutanga rinotanga kuurayiwa kwayo pakutanga kwekufananidza panguva t = 0. Kutanga nemutsara wekutanga pakati pekutanga nekuguma, mutsara wega wega unobata kubva kumusoro kusvika pasi kusvikira kunonoka kwasvika. Kana kunonoka kwasvika, kuurayiwa kwechivharo ichi kunomirira kusvikira nguva yekunonoka (10-time units) yapfuura uye inotora kuurayiwa zvakare.
Mushandisi anogona kutsanangura zvinokurudzira achishandisa zvishwe (zve, nepo, kana-zvimwe) zvakare mukati meiyi yekutanga block pane kupinda musanganiswa wese nemawoko.

 

Example:
Kutanga Kutanga
A = 0; b = 0; // kutanga kuurayiwa
#10 a = 0; b = 1; // kuurayiwa kuri pa t = 10-yuniti nguva
#10 a = 1; b = 0; // kuurayiwa kuri pa t = 20-yuniti nguva
end

Dump Files

Chimwe chinhu chekuchengeta mupfungwa kuziviswa kwe $dumpfiles uye $dumpvars mukati mechikamu chekutanga (ona mutsara 55- 56 muMufananidzo 5). Iyo $dumpfile inoshandiswa kukanda shanduko muhukoshi hwemambure nemarejista mu file iyo inotumidzwa senharo yayo.

For example:

$dumpfile(“alu_tb.vcd”);

icharasa shanduko mu a file inonzi alu_tb.vcd. Shanduko idzi dzakanyorwa mu a file inonzi VCD file izvo zvinomirira kuti value change dump. A VCD (value change dump) inochengetedza ruzivo rwese nezvekuchinja kwekukosha. Hatikwanisi kuva nemadhora anodarika rimwe chetefile zvirevo muVerilog simulation.

Iyo $dumpvars rinoshandiswa kutsanangura kuti ndezvipi zvipembenene zvinoraswa (mu file yakataurwa ne$dumpfile) Nzira iri nyore yekuishandisa haina kana nharo. Iyo yakajairika syntax ye $dumpvars ndeye

$dumpvars ( <, >);

Isu tinogona kutsanangura kuti ndeapi mamodule, uye ndeapi akasiyana mumamodule acharaswa. Nzira iri nyore yekushandisa iyi ndeyekumisa nhanho kusvika ku0 uye zita remodule seyepamusoro module (kazhinji iyo yepamusoro testbench module).

$dumpvars(0, alu_tb);

Kana nhanho yaiswa ku 0, uye chete zita remodule ratsanangurwa, rinorasa ZVINHU zvinosiyana-siyana zvemodule iyoyo uye zvese zvinosiyana mumamodule ESE epasi-chikamu akasimbiswa neiyi module yepamusoro. Kana chero module isina kusimbiswa neiyi yepamusoro module, ipapo shanduko yayo haizofukidzwe. Chimwezve chinhu, kuziviswa kwe $dumpfile inofanira kuuya pamberi pe $ dumpvars kana chero mamwe mabasa ehurongwa anotsanangura kuraswa. Dump idzi files inofanira kuziviswa pamberi pezvimiro zvekusimudzira zvimwe, hapana kukosha kuchachengetwa mukuraswa uku files.

Nguva dzose Vimba

Kusiyana nezvirevo zvekutanga, bhuroka rinogara richidzokorora, kunyangwe kuuraya kunotanga panguva t = 0. For ex.ample, chiratidzo chewachi chakakosha pakushanda kwemasekete akatevedzana seFlip-flops. Inoda kuramba ichipihwa. Nokudaro, tinogona kunyora kodhi yekushanda kwewachi mu testbench se (ona mutsara 52 mumufananidzo 5):

nguva dzose
#10 clk = ~clk;
endmodule

Chirevo chiri pamusoro chinoitwa mushure me10 ns kutanga kubva ku t = 0. Kukosha kwe clk kuchapindurwa mushure me 10 ns kubva pamutengo wekare. Nokudaro, kugadzira chiratidzo chewachi che 20 ns pulse width. Naizvozvo, chirevo ichi chinoburitsa chiratidzo chefrequency 50 MHz. Zvakakosha kuziva kuti, kutanga kwechiratidzo kunoitwa pamberi pekuvhara nguva dzose. Kana tikasaita chikamu chekutanga, chiratidzo che clk chichava x kubva t - 0, uye mushure megumi ns, chinozopinzwa kune imwe x.

Self-Checking Testbench

A self-checking testbench inosanganisira chirevo chekutarisa mamiriro azvino.

• $kuratidza system basa rinonyanya kushandiswa kuratidza debug mameseji kuteedzera kuyerera kwekuenzanisa

kutanga kutanga
A = 0 ; b = 0 ; c = 0; #10; // shandisa kupinza, mirira
kana(y ! == 1) tanga
$ kuratidza("000 yakundikana"); //check
c = 1; #10 ; //shandisa kupinza, mirira
end
zvimwe kana (y ! == 0) akatanga
$ kuratidza ("001 yakundikana") // tarisa
b = 1; c = 0; #10 ; end
zvimwe kana(y!==0)
$ kuratidza (" 010 yakundikana"); //check
end
endmodule

$kuratidza rinoshandiswa kuratidza kukosha kwezvakasiyana, tambo, kana mataurirwo. Kubva pamusoro apa example, pese kana imwe yei-imwe loop ichigutswa, ipapo iyo simulator log icharatidza yayo $kuratidza statement. Pane mutsara mutsva nekusara pamagumo etambo.

$kuratidza (“nguva = %t , A = %b, B = %b, C = % b”, $nguva, A,B,C);

Mavara akataurwa mumashoko achadhindwa sezvaari. Tsamba iri pamwe chete ne% inoreva chimiro chetambo. Isu tinoshandisa %b kumiririra data rebhinari. Tinogona kushandisa %d, %h, %o kumiririra decimal, hexadecimal, uye octal, zvichiteerana. Iyo %g inoshandiswa kuratidza nhamba chaidzo. Izvi zvichatsiviwa nehunhu huri kunze kwekotesheni muhurongwa hwataurwa. For example, chirevo chiri pamusoro chicharatidzwa mugiyo yekufananidza se: nguva = 20, A = 0, B =1, C = 0

Tafura 1. Verilog Tafura Formats

Nharo	Tsanangudzo
%h, %H	Ratidza muHexadecimal fomati
%d, %D	Ratidza muchimiro chedesimali
%b, %B	Ratidza mumhando yebhinari
%m, %M	Ratidza zita renhoroondo
%s, %S	Ratidza setambo
%t, %T	Ratidza mufomati yenguva
%f, %F	Ratidza 'chaiyo' mune decimal fomati
%e, %E	Ratidza 'chaiyo' mune exponential format

$kuratidza kunyanya anodhinda data kana kuchinjika sezvazviri panguva iyoyo yenguva se printf muC. Tinofanira kutaura $kuratidza chero chinyorwa chatinofanira kuita view mune yekufananidza log.

• $nguva

$nguva ibasa rehurongwa rinozodzosa nguva iripo yekufananidza.

• $monitor

$monitor ichaongorora iyo data kana kusiyanisa kwayakanyorerwa uye pese panochinja shanduko, inodhinda
kukosha kwachinja. Iyo inowana mhedzisiro yakafanana yekudaidza $ kuratidza mushure menguva yega yega yega nharo dzayo
updated. $monitor rakafanana nebasa rinoitwa kuti rimhanye kumashure kweshinda huru iyo inotarisisa uye
inoratidza kuchinja kwekukosha kwezvakasiyana-siyana zvenharo. $monitor ine chirevo chakafanana neicho $kuratidza.

$monitor(“ nguva = %t, A = %b, B = %b, C = % b”, $nguva, A,B,C);

Kubva Mufananidzo 7 unogona kuona kuti mitsva mitsva yekodhi yakawedzerwa kuti uzviongorore iwe testbench. Kuiswa kwe $kuratidza uye $monitor zvirevo muzvikamu zvakasiyana zvetestbench zvichapa mhedzisiro dzakasiyana (ona Mufananidzo 8). $nguva yataurwa muzvirevo izvi inodhinda nguva iyo kukosha kuri kudhindwa. Panguva imwecheteyo unit inoti 170000, tinogona kuona kuti kune musiyano sei mukukosha kweA uye B nekuda kwe $.kuratidza uye $monitor mashoko.

GTKWAve Software

GTKWave inoratidzwa zvizere GTK + wave viewer yeUnix, Win32, uye Mac OSX iyo inoti LXT, LXT2, VZT, FST, uye GHW files pamwe neyakajairwa VCD/EVCD files uye inobvumira yavo viewing. Mukuru wayo websaiti iri pa http://gtkwave.sourceforge.net/ . GTKWave ndiyo inokurudzirwa viewer naIcarus Verilog simulation chishandiso.

Kana mushandisi angobudirira kugadzira testbench yekuyedza mashandiro edhizaini, mushandisi anogona kushandisa GTKWave software view the waveforms.

Kuvhura iyo GTKWAve software ku view mafungu esaisai, mushandisi anofanirwa kudzvanya pakanzi Simulate Testbench bhatani pamusoro petururira kana kubva kumenu huru Zvishandiso→ Simulation→ Simulate Testbench. Kana pasina zvikanganiso zvesyntax saka zvichienderana nedhizaini, iyo GTKWave inofanirwa kuvhurwa otomatiki kana mibairo yekukurudzira mutestbench icharatidzwa muLogger chikamu chehwindo.

Iyo GTKWave software inovhura iyo .vcd fomati yekurasirafile automatic. Iyo GTKWave hwindo hairatidze waveform kana yavhurwa. Izvi zvinopa mushandisi mukana wekusarudza masaini aanoda kuita view uye cherechedzai. Kuti usarudze chiratidzo, mushandisi anoda kuratidza, mushandisi anoda kudzvanya pazita remodule yavo / chiitiko kuruboshwe rwehwindo pasi peSST tab. Nekudzvanya iyo + yeese chiitiko, unogona kuona masiginecha ane hukama neiyo muenzaniso muchikamu chepasi. Ipapo iwe unogona kudhonza & kudonhedza chiratidzo chaunoda kana kudzvanya-kaviri kuti zviratidzwe muSiginecha hwindo. Iwe unogonawo kusarudza zvose (CTRL + A) uye uzviise kuhwindo rezviratidzo (ona Mufananidzo 9).

Iwo masiginecha awedzerwa pahwindo rechiratidzo asi richiri kuda kutevedzerwa. Mushure mekuwedzera masaini anodiwa pahwindo rechiratidzo, tinya pa kuti ikwane masaini kuhupamhi hwazvino hwehwindo uye wozorodha masaini kubva pakurodha zvakare chiratidzo chiripo pane toolbar. Iwe unogona ikozvino kuona zvikwangwani zvine maitiro avo.

Signal Values

Nekumisikidza, kukosha kwemasaini ari mune hexadecimal fomati uye ese masaisai ane mavara egirinhi (kana achimhanya nemazvo).

Mushandisi anogona kushandura zvimiro zvechiratidzo ichi nekudzvanya-kurudyi pane chiratidzo uye kusarudza Data Format kana Ruvara Format. Mushandisi anogona zvakare kuisa chiratidzo chisina chinhu kuita zvikamu pakati peboka rezviratidzo. Paunenge uine yaunoda optical mhedzisiro, unogona kuchengetedza zvigadziriso zvako nekuenda File → Nyora Chengeta File.

GTKWave Toolbar

The toolbar (ona Mufananidzo 10) inobvumira mushandisi kuita mabasa ekutanga echiratidzo. Ngatikurukurei sarudzo yega yega patoolbar kubva kuruboshwe kuenda kurudyi.

1. Menu Options: Pasi pechisarudzo ichi tinogona view ese akasiyana maficha esoftware anogona kushandiswa kutamba achitenderedza nesoftware. Iwo mamenu ari pasi peiyi menyu sarudzo akafukidzwa pasi peChikamu 8 chegwaro iri remushandisi.
2. Cheka Traces: Inoshandiswa kudzima/kucheka chiratidzo chekusarudza kubva pahwindo rechiratidzo
3. Copy Traces: Inoshandiswa kukopa chiratidzo chakasarudzwa kubva pahwindo rechiratidzo
4. Paste Traces: Iyo yakakopwa / yakachekwa trace inogona kunamirwa pane imwe nzvimbo muhwindo rechiratidzo
5. Zoom Fit: Inoshandiswa kuenderana nemasaini zvichienderana nehukuru hwehwindo iro mushandisi anosarudza kuratidza
6. Zoom In: Inoshandiswa kuswededza pahwindo rechiratidzo
7. Zoom Out: Inoshandiswa kuswededza kunze kwehwindo rechiratidzo
8. Zoom Undo: inoshandiswa kugadzirisa zoom in/out pahwindo rechiratidzo
9. Zoom to Start: izvi zvichawedzera hwindo rechiratidzo, kuratidza nguva yekutanga kwemasaini.
10. Zoom to End: izvi zvinozosimudza hwindo rechiratidzo rinoratidza nguva yekupedzisira yemasaini
11. Tsvaga kumucheto kwekare: Izvi zvinoshandura chicherechedzo kudivi rekuruboshwe zvichiratidza kumucheto kwapfuura
12. Tsvaga mupendero unotevera: Izvi zvinoshandura chicherechedzo kuenda kurudyi zvichiratidza mupendero unotevera
13. Mupumburu wepasi/pamusoro bond: Tichishandisa izvi tinogona kuseta nguva iyo mushandisi anoda kuratidza. For example, tinogona kuseta nguva ku0 sec kusvika ku500 ns, icharatidza masaini pasi penguva iyoyo chete.
14. Reload: Iyo reload inodzvanywa chero paine shanduko kune yakaratidzwa chiratidzo. Ichaita reload uye kuratidza chiratidzo maererano itsva parameters. For example, mushure mekushandura nguva yechiratidzo, tinoda kurodhazve chiratidzo kuti tiratidze chiratidzo mune itsva yakatarwa nguva.

Menu Options

Kubva kuruboshwe kumusoro kwekona yeGTKWave software, mushandisi anogona kuwana menyu sarudzo nekudzvanya mitsara mitatu yakatwasuka (ona Mufananidzo 11). Mushandisi anogona kuwana zvinotevera sarudzo pasi peMenu sarudzo:

File

The File submenu ine zvinhu zvakasiyana siyana zvine chekuita nekuwana files, kupinza-kutumira kunze VCD files, kudhinda, uye kuverenga/kunyora files uye kubuda.

Edit

Iyo Edit submenu inoshandiswa kuita mabasa akasiyana-siyana ekushandisa akadai sekushandura inomiririra data yehukoshi mune wave subwindow. Uchishandisa sarudzo dziri pasi peKugadzirisa submenu, mushandisi anogona kushandura iyo data fomati yezvikwangwani, kurongazve, kuchinjisa, kudimburira, kuisimbisa, masaini eboka, kutaura pazviratidzo, shandura ruvara rwezviratidzo, nezvimwe.

kutsvaka

Iyo Search submenu inoshandiswa kuita tsvakiridzo pamambure nemakoshero. Inobatsira kuita mabasa pamatunhu akasiyana ezviratidziro uye zviitiko muVCD file.

Nguva

Iyo submenu yenguva ine superset yemabasa akaitwa neNavigations uye mabhatani eStatus Panel.
Inogonesa yakapfava, inoenderana nenguva, inoshanda senge zooming, kuenda kune imwe nguva nguva, kushandura chiratidzo mune imwe nzira, nezvimwe.

Marker

Iyo submenu yemakaki inoshandiswa kuita akasiyana manipulations pachimaka pamwe nekudzora kupuruzira kunze kwescreen.
Inogonesa kushanda kwekuwedzera akawanda mamaki pahwindo rechiratidzo. Mazita anodarika makumi maviri nematanhatu anotenderwa uye nguva dzevose dzinofanira kunge dzakasiyana.

a. Kuwedzera Makoni muhwindo rechiratidzo
Tinya kuruboshwe panzvimbo inodiwa paunoda kuti Mucherechedzo uiswe wodzvanya ALT + N. Izvi zvinoisa chiratidzo chine zita (A,B,C, nezvimwewo) panzvimbo inodiwa. Mushandisi anogona kuenderera mberi nekuita izvi kune 26 nzvimbo dzakasiyana dzenguva.
Kuti uenzanise kukosha kwenguva panzvimbo dzese mamaki, Menyu → Makaki → Ratidza Shandura Mucherechedzo Dhata.
Izvi zvinovhura hwindo rine kukosha kwenguva pane yega Marker. Mushandisi anogona kuona kukosha kwenguva pane imwe neimwe marker yakaiswa uye kuabvisa kuti averenge musiyano wenguva pakati pe2 mamaki.
b. Kubvisa Mucherechedzo muhwindo rechiratidzo

Mushandisi anogona kuenda kuMenu → Makaki → Unganidza Ane Zita Mucherechedzo. Izvi zvinobvisa iyo yekupedzisira-inonzi Marker yakaiswa muhwindo rechiratidzo. Mushandisi anogona kubvisa ese ane mazita Macherechedzo nekuenda kuMenu → Makaki → Unganidza Yese Mazita Mazita (Mufananidzo 12).

Mumufananidzo 13, tinogona kuona kuti mavara echiratidzo akashandurwa sei. Unogona kuona Blank Signal yakawedzerwa pahwindo rechiratidzo pamwe nekutaura - Blank Signal.
Uyewo cherechedza kuvapo kwe6 Mazita Mazita (A - E) uye kusanganiswa kwehuwandu hwenguva pakati peMakaki aya mups.

View

The View submenu inoshandiswa kudzora hunhu hwakasiyana hunobata neiyo graphical kupa yemamiriro ezvinhu pamwe nehunhu muchiratidzo sub hwindo. Kubva pane iyi menyu, unogona kushandura hwindo rechiratidzo kuita Nhema & White kana ruvara zvakare. The View submenu zvakare inoita kuti iwe uchinje nguva Dimension kubva kumasekonzi (secs) kuenda kuficoseconds (fs). Mushandisi anogona kuwana iyi sarudzo View → Kuyera kusvika kuNguva Dimension → fs.

Help

Iyo submenu yekubatsira ine sarudzo dzekugonesa rubatsiro rwepamhepo pamwe nekuratidza ruzivo rwechirongwa chechirongwa.

Mhedziso

Gwaro iri rakagadzirwa kuti ribatsire mushandisi mukubudirira kutevedzera dhizaini yavo uye kuona mashandiro acho nekugadzirisa dhizaini inodiwa testbench uye kushandisa Icarus Verilog pamwe neGTKWave kuratidza masaisai uye kuona mhedzisiro.

Revision History

Kudzokorora	Date	Tsanangudzo
1.00	Chivabvu 20, 2024	Kusunungurwa kwekutanga.

R19US0011EU0100 Rev.1.0
Chivabvu 20, 2024
© 2024 Renesas Electronics

Zvinyorwa / Zvishandiso

RENESAS ForgeFPGA Software Simulation [pdf] Bhuku reMushandisi REN_r19us0011eu0100, ForgeFPGA Software Simulation, ForgeFPGA Software, ForgeFPGA, ForgeFPGA Simulation,Software Simulation,Simulation,Software

References

• User Manual