RENESAS ForgeFPGA Software kwaikwaiyo

Muhimman Bayanai

Kwaikwayo wata dabara ce ta yin amfani da abubuwan ƙara kuzari na shigarwa daban-daban ga ƙira a lokuta daban-daban don bincika ko lambar RTL ta nuna yadda ake so. Ana amfani da shi don tabbatar da ƙarfin ƙira. Simulation yana bawa mai amfani damar view zane na lokaci na sigina masu alaƙa don fahimtar yadda bayanin zane a cikin zane file nuna hali.

Testbenches guda ne na lamba waɗanda ake amfani da su don kwaikwaya. Wurin gwaji mai sauƙi zai kunna Unit Under Test (UUT) kuma yana fitar da shigarwar. Go Configure software yana amfani da Icarus Verilog (iVerilog) da GTKWave don lura da simulation waveforms tare da kara kuzari da aka bayar a cikin testbench.

Wannan takaddar tana bayyana matakan da ake buƙatar ɗauka yayin shigar da Icarus akan tsarin ku da yadda ake gudanar da simulation mai nasara.

Shigar da Icarus Verilog

a. Shigar da sabuwar sigar Icarus Verilog (IVerilog) daga https://bleyer.org/icarus/
b. Tabbatar ƙara IVerilog zuwa PATH kuma bari ya shigar da GTKWave (Duba Hoto 1)

c. Bude Go Configure Software kuma zaɓi sashin: SLG47910(Rev BB) don buɗe taron bita (duba Hoto 2).

d. Danna kan Editan FPGA a tsakiyar kayan aiki a saman ko mai amfani kuma zai iya danna sau biyu akan tsarin FPGA Core a tsakiyar taga.

e. Wani sabon taga yana buɗewa mai suna Forge Workshop. A cikin kayan aiki na menu na sama, danna kan Zabuka → Saituna. A cikin akwatin maganganu na Saituna, je zuwa Kayan aiki karkashin Saitunan Mai amfani shafin. Cire zaɓin Yi amfani da “akwatin muhallin tsarin” don duka Icarus Verilog da GTKWave. Ƙara hanyar zuwa Iverilog da GTKWave da aka adana a cikin tsarin ku cikin sararin da aka bayar (duba Hoto 4).

An saita ku don yin kwatankwacin gwajin gwaji kuma matakan da ke sama suna tabbatar da cewa GTKWave yana buɗewa ta atomatik lokacin da ake yin gwajin benci akan software na Go Configure.

Testbench

Mataki mafi mahimmanci a cikin nasarar aiwatar da kowane tsari shine tabbatar da ƙira da aikin sa. Tabbatar da tsarin hadaddun tsarin bayan aiwatar da kayan aikin ba shine zaɓi mai hikima ba. Ba shi da tasiri ta fuskar kuɗi, lokaci, da albarkatu. Don haka, game da FPGA, ana amfani da testbench don gwada lambar tushen Verilog.

A ce muna da shigarwar da ke 11-bit, kuma muna so mu gwada na'urar don duk ƙimar haɗin haɗin da za ta yiwu watau (211). Kamar yadda wannan babban adadin haɗuwa ne, ba shi yiwuwa a gwada shi da hannu. A irin waɗannan lokuta, benches na gwaji suna da amfani sosai kamar yadda zaku iya gwada ƙirar ta atomatik don duk ƙimar ƙima kuma saboda haka, tabbatar da amincin ƙirar gwajin. Ana amfani da Verilog Testbenches don kwaikwaya da tantance ƙira ba tare da buƙatar kowace na'urar kayan aiki ta zahiri ba.

Zane a ƙarƙashin gwaji, wanda aka gajarta azaman DUT, ƙirar aikin da muke son gwadawa ne. A wasu kalmomi, ƙirar da'ira ce za mu so mu gwada. Zamu iya kwatanta DUT ɗin mu ta amfani da ɗayan nau'ikan ƙirar ƙira guda uku a cikin Verilog - Ƙofar-matakin, Dataflow, ko Halayyar.

Testbench ba zai iya haɗawa ba, don haka ana amfani dashi don dalilai na kwaikwayo kawai. Wannan yana bawa mai amfani damar yin amfani da cikakken kewayon ginin Verilog misali, kalmomi kamar "don", "$ nuni" da "$ saka idanu" da sauransu don rubuta benches. Wurin gwaji mai sauƙi zai kunna Unit Under Test (UUT) ko Na'ura A Ƙarƙashin Gwaji (DUT) da kuma fitar da abubuwan shiga.

Fahimtar Testbench

Ma'anar Sikeli na Lokaci a cikin Testbench

Lokacin yin kwaikwayo, software tana buƙatar sanin yadda aka ayyana lokacin. An kayyade naúrar jinkiri ta hanyar amfani da `manzannin sikelin lokaci, wanda ke ƙayyadaddun naúrar lokaci da madaidaicin samfuran da ke biye da shi. Ma'aunin lokaci yana taimakawa wajen tantance abin da #1 ke nufi dangane da lokaci. Ana amfani da # don ayyana jinkirin da za a gabatar a cikin tsarin daidai da naúrar lokaci da aka kayyade a ma'auni. Don haka, #1 yana nufin 1 ns na jinkirtawa idan rukunin lokaci_na cikin ns.

Daidaitawa:
'lokacin lokaci / /

time_unit shine adadin lokacin da jinkiri na #1 ke wakilta. Tushen time_precision yana wakiltar adadin daidaitattun maki nawa ne don amfani dangane da raka'o'in lokaci. (Duba layi na 23 a hoto na 5)

Za mu iya yin amfani da ginin juzu'i don amfani da raka'o'in lokaci daban-daban a cikin ƙira ɗaya. Mai amfani yana buƙatar tuna cewa ƙayyadaddun ƙididdiga ba su iya haɗawa kuma ba za a iya jujjuya su zuwa dabaru na hardware ba. Ayyukan jinkiri gaba ɗaya don dalilai na kwaikwayo ne. $lokaci kuma $realtime Ayyukan tsarin suna dawo da lokacin yanzu kuma ana iya canza tsarin rahoton tsoho tare da wani aikin tsarin $timeformat .

Exampda: 

Matsakaicin lokaci 10us/100ns
'ma'auni 1ns/1ps
#10 sake saiti = 1; // yana jinkirta siginar da 10 ns
#0.49 $ nuni ("T = %0t a Lokaci #0.49", $ realtime);

An ƙayyade jinkirin shine # 0.49 wanda bai wuce rabin lokacin raka'a ba. Koyaya, an ayyana madaidaicin lokacin ya zama 1ps don haka na'urar kwaikwayo ba zata iya zuwa ƙasa da 1ns ba wanda ya sa ya zagaya bayanin jinkirin da aka bayar kuma ya samar da 0ns. Don haka, wannan magana ta kasa samar da kowane jinkiri.

Log ɗin simulation: 

T = 1 a Lokaci #0.49

Bayanin Module

Bayanin Module a kowane benci na gwaji ya bambanta da babban lambar Verilog. A cikin testbench, ana ayyana tsarin ba tare da tashar tashar jiragen ruwa tare da shi ba. (Duba layi na 25 a hoto na 5)

Daidaitawa: 

module ;

Ana biye da sanarwar ƙirar ta hanyar ayyana shigarwar da siginonin fitarwa da aka ayyana a baya a cikin babban ƙira file.
Muna amfani da nau'ikan sigina guda biyu don tuki da sa ido kan sigina yayin kwaikwayo. The reg datatype zai riƙe darajar har sai an sanya sabon ƙima gare shi. Ana iya sanya wannan nau'in bayanan ƙima kawai a koyaushe ko toshewar farko.
Nau'in bayanan waya kamar na haɗin jiki ne. Zai riƙe ƙimar da tashar jiragen ruwa ke tafiyarwa, sanya sanarwa, ko reg. Ba za a iya amfani da wannan nau'in bayanan ba a farkon ko koyaushe toshewa. Ana kuma yin duk wani ma'auni da bayanin lamba a wannan sashe.

Exampda:
Reg a,b; // shigarwar a cikin lambar HDL an bayyana shi azaman reg a cikin testbench
waya y; // siginar fitarwa a cikin HDL an bayyana shi azaman waya a cikin testbench

Farashin DUT

Dalilin gwajin benci shine don tabbatar da ko tsarin DUT ɗin mu yana aiki. Don haka, muna buƙatar aiwatar da ƙirar ƙirar mu don gwada module.

Daidaitawa: 

(. (sigina 1), . sigina1> (sigina2));

Exampda:

ALU d0 (.a (a), // siginar "a" a cikin ALU yakamata a haɗa shi zuwa "a" a cikin tsarin ALU_tb.
.b(b), // siginar "b" a cikin ALU yakamata a haɗa shi zuwa "b" a cikin tsarin ALU_tb
.c(c)) ;// siginar "c" a cikin ALU yakamata a haɗa shi zuwa "c" a cikin tsarin ALU_tb

Mun sanya DUT module ALU zuwa tsarin gwaji. Misali sunan (d0) shine zabin mai amfani. Alamomin da ke da lokaci "." A gabansu akwai sunayen sigina a cikin tsarin ALU, yayin da waya ko reg ɗin da suke haɗawa a cikin benci na gwaji yana kusa da siginar a cikin baka (). Ana ba da shawarar yin lambar kowane haɗin tashar jiragen ruwa a cikin wani layi daban domin duk wani saƙon kuskuren tattarawa zai yi nuni daidai ga lambar layi inda kuskuren ya faru. Domin ana yin waɗannan haɗin da suna, tsarin da suke bayyana a cikinsa bai dace ba.

Hakanan za'a iya yin saurin DUT don samfuran inda tsarin gwajin gwajin yana da sunayen sigina daban-daban. Madaidaicin taswirar sigina shine abin da ke da mahimmanci yayin yin gaggawa.

Example: 

ALU d0 (.a (A), // siginar "a" a cikin ALU yakamata a haɗa shi zuwa "A" a cikin tsarin ALU_tb.
.clk(agogo), // siginar “clk” a cikin ALU yakamata a haɗa shi zuwa “agogo” ALU_tb module
.fita (FITA)); // siginar "fita" a cikin ALU yakamata a haɗa shi zuwa "OUT" a cikin tsarin ALU_tb

Koyaushe & Toshe Farko a cikin Testbench

Akwai tubalan jeri biyu a cikin Verilog, na farko da koyaushe. A cikin waɗannan tubalan ne muke amfani da abin ƙarfafawa.

Toshewar farko

Tushe na farko wanda aka aiwatar sau ɗaya kawai kuma yana ƙare lokacin da aka aiwatar da layin ƙarshe na toshe. An rubuta abin ƙarfafawa a cikin tubalin farko. (Duba layi na 54-72 a hoto na 5)

Daidaitawa:
..
farkon farawa
$jibfile();
$ dumpvars();
..(shigar da kuzari)
karshen

tubalin farko yana farawa da aiwatar da shi a farkon simulation a lokacin t = 0. Farawa da layin farko tsakanin farawa da ƙarshe, kowane layi yana aiwatarwa daga sama zuwa ƙasa har sai an sami jinkiri. Lokacin da jinkiri ya kai, aiwatar da wannan shingen yana jira har sai lokacin jinkiri (raka'a 10) ya wuce sannan kuma a sake yin kisa.
Mai amfani na iya ayyana abubuwan kuzari ta amfani da madaukai (don, yayin da, in ba haka ba) haka nan a cikin wannan toshewar farko maimakon shigar da duk haɗin gwiwa da hannu.

 

Example:
Farkon Farko
A = 0; b = 0; // fara kisa
#10 a = 0; b = 1; // aiwatarwa yana a t = lokacin raka'a 10
#10 a = 1; b = 0; // aiwatarwa yana a t = lokacin raka'a 20
karshen

Juji Files

Wani abu da ya kamata a tuna shi ne sanarwar $zubarfiles kuma $dumpvars a cikin toshewar farko (duba layi na 55-56 a hoto na 5). Da $zubarfile ana amfani da shi don zubar da canje-canje a cikin ƙimar gidajen yanar gizo da rajista a cikin a file wanda ake suna a matsayin hujjarsa.

Don misaliampda:

$zubarfile("alu_tb.vcd");

zai zubar da canje-canje a cikin a file mai suna alu_tb.vcd. Ana yin rikodin canje-canje a cikin a file ake kira VCD file wanda ke tsaye ga jujjuyar ƙima. VCD (juji canjin ƙima) yana adana duk bayanan game da canjin ƙima. Ba za mu iya samun juji sama da $ ɗaya bafile kalamai a cikin simulation na Verilog.

Da $dumpvars ana amfani dashi don tantance waɗanne canje-canjen da za a zubar (a cikin file an ambata ta $jubafile). Hanya mafi sauƙi don amfani da ita ita ce ba tare da wata hujja ba. Gabaɗaya syntax na $dumpvars shine

$dumpvars ( <, >);

Za mu iya ƙididdige waɗanne kayayyaki, da kuma waɗanne masu canji a cikin kayayyaki za a zubar. Hanya mafi sauƙi don amfani da wannan ita ce saita matakin zuwa 0 da sunan module azaman babban module (yawanci babban module ɗin testbench).

$dumpvars(0, alu_tb);

Lokacin da aka saita matakin zuwa 0, kuma kawai aka ƙayyade sunan module, yana zubar da DUKKAN masu canji na wannan module ɗin da duk masu canji a cikin DUKKAN ƙananan matakan da wannan babban module ɗin ke nan take. Idan kowane module a cikin wannan babban module ɗin ba ya nan take ba, to ba za a rufe canjin sa ba. Wani abu guda, sanarwar $zubarfile dole ne ya zo a gaban $dumpvars ko duk wani aikin tsarin da ya ƙayyade juji. Wadannan juji files dole ne a ayyana kafin shigar da ƙarin abubuwan ƙara kuzari, ba za a adana ƙima a cikin wannan juji ba files.

Koyaushe Toshe

Sabanin maganganun farko, toshe kullun yana aiwatarwa akai-akai, kodayake aiwatarwar yana farawa a lokaci t = 0. Ga ex.ampHar ila yau, siginar agogo yana da mahimmanci don gudanar da ayyukan da'irori kamar Flip-flops. Yana buƙatar a ba shi ci gaba. Don haka, za mu iya rubuta lambar don aiki da agogo a cikin benci na gwaji kamar (duba layi na 52 a cikin hoto 5):

kullum
#10 clk = ~ clk;
endmodule

Ana aiwatar da bayanin da ke sama bayan 10 ns farawa daga t = 0. Darajar clk za ta koma bayan 10 ns daga ƙimar da ta gabata. Don haka, samar da siginar agogo na 20 ns nisa bugun jini. Don haka, wannan bayanin yana haifar da siginar mitar 50 MHz. Yana da mahimmanci a lura cewa, ƙaddamar da siginar ana yin shi kafin kullun kullun. Idan ba mu yi ɓangaren ƙaddamarwa ba, siginar clk zai kasance x daga t – 0, kuma bayan 10 ns, za a juya shi zuwa wani x.

Testbench na Duba kai

Wurin gwajin gwada kansa ya haɗa da sanarwa don bincika halin da ake ciki.

• $nuni Ayyukan tsarin ana amfani da su ne musamman don nuna saƙonnin kuskure don bin diddigin simintin

farkon farawa
A = 0; b = 0; c = 0; #10; // shigar da shigarwa, jira
idan (y! == 1) ya fara
$ nuni ("000 ya kasa"); //duba
c = 1; #10 ; // Aiwatar da shigarwa, jira
karshen
in kuma (y! == 0) ya fara
$ nuni ("001 ya kasa") // duba
b = 1; c = 0; #10; karshen
idan kuma (y!==0)
$ nuni ("010 ya kasa"); //duba
karshen
endmodule

$nuni ana amfani dashi don nuna ƙimar masu canji, kirtani, ko magana. Daga sama exampto, duk lokacin da kowane ɗayan madauki idan ya gamsu, to log ɗin na'urar zai nuna nau'in $ ɗin sa.nuni sanarwa. Akwai sabon layi ta tsohuwa a ƙarshen kirtani.

$nuni ("lokaci = %t , A = %b, B = %b, C = % b", $lokaci, A,B,C);

Za a buga haruffan da aka ambata a cikin furucin kamar yadda suke. Harafin tare da % yana nuna tsarin kirtani. Muna amfani da %b don wakiltar bayanan binary. Za mu iya amfani da %d, %h, %o don wakiltar adadi, hexadecimal, da octal, bi da bi. Ana amfani da %g don bayyana ainihin lambobi. Za a musanya waɗannan tare da ƙimar da ke waje da ƙima a cikin tsari da aka ambata. Domin misaliample, za a nuna bayanin da ke sama a cikin log ɗin simulation kamar: lokaci = 20, A = 0, B = 1, C = 0

Tebur 1. Verilog Table Formats

Hujja	Bayani
%h, %H	Nuna a cikin tsarin Hexadecimal
%d, %D	Nuna a cikin tsari na goma
%b, %B	Nuna a tsarin binary
%m, %M	Nuna sunan matsayi
%s, %S	Nuna azaman kirtani
%t, %T	Nuna a tsarin lokaci
%f, %F	Nuna 'ainihin' a sigar ƙima
%e, %E	Nuna 'hakikanin' a cikin sigar juzu'i

$nuni galibi yana buga bayanai ko mabambanta kamar yadda yake a wannan lokacin kamar bugun a cikin C. Dole ne mu ambaci $nuni ga duk wani rubutu da za mu yi view a cikin simulation log.

• $lokaci

$lokaci aikin tsarin ne wanda zai dawo da lokacin simintin na yanzu.

• $saka idanu

$saka idanu zai saka idanu akan bayanan da aka rubuta don su kuma duk lokacin da canjin ya canza, zai buga
darajar da ta canza. Yana samun irin wannan tasiri na kiran nunin $ bayan duk lokacin da kowace hujja ta samu
sabunta. $saka idanu kamar wani aiki ne da aka haifa don gudana a bayan babban zaren wanda ke sa ido da kuma
yana nuna canjin ƙima na masu canjin gardamar sa. $saka idanu yana da ma'ana ɗaya da $nuni.

$saka idanu("lokaci = %t, A = %b, B = %b, C = % b", $lokaci, A,B,C);

Daga Hoto na 7 zaku iya lura cewa an ƙara sabbin layukan lambobi don tantance kanku na testbench. Matsayin $nuni kuma $saka idanu kalamai a sassa daban-daban na testbench za su ba da sakamako daban-daban (duba hoto 8). $lokaci da aka ambata a cikin waɗannan maganganun suna buga lokacin da ake buga ƙimar. A lokaci guda naúrar ce 170000, za mu iya ganin yadda akwai bambanci a cikin darajar A da B saboda $nuni kuma $saka idanu kalamai.

GTKWave Software

GTKWave cikakkiyar sifa ce ta GTK+ viewer don Unix, Win32, da Mac OSX waɗanda ke karanta LXT, LXT2, VZT, FST, da GHW files da kuma daidaitaccen VCD/EVCD files kuma ya yarda da su viewing. A hukumance website yana nan http://gtkwave.sourceforge.net/ . GTKWave shine shawarar viewer ta Icarus Verilog simulation Tool.

Da zarar mai amfani ya sami nasarar ƙirƙira wurin gwaji don gwada aikin ƙira, mai amfani zai iya amfani da software na GTKwave don view da waveforms.

Don ƙaddamar da software na GTKwave zuwa view da waveforms, mai amfani yana buƙatar danna maɓallin Simulate Testbench a saman kayan aiki ko daga babban menu Tools→ Simulation→ Simulate Testbench. Idan babu kurakurai a cikin tsarin rubutu to ya danganta da zane, yakamata a kaddamar da GTKWave ta atomatik ko kuma a nuna sakamakon abubuwan kara kuzari a cikin testbench a sashin Logger na taga.

Software na GTKWave yana buɗe jujjuya tsarin .vcdfile ta atomatik. Tagan GTKWave ba ya nuna yanayin motsi lokacin buɗewa. Wannan yana ba mai amfani damar zaɓar siginar da yake so view da kuma lura. Don zaɓar siginar, mai amfani yana buƙatar nunawa, mai amfani yana buƙatar danna sunan tsarin su / misali a gefen hagu na taga a ƙarƙashin shafin SST. Ta danna + na kowane misali, zaku iya ganin sigina waɗanda ke da alaƙa da wannan misalin a cikin sashin ƙasa. Sannan zaku iya ja & sauke siginar da kuke so ko danna su sau biyu don nunawa a cikin taga siginar. Hakanan zaka iya zaɓar duk (CTRL + A) kuma saka su a cikin taga sigina (duba hoto 9).

Yanzu ana ƙara sigina zuwa taga siginar amma har yanzu ba a kwaikwayi ta ba. Bayan ƙara siginar da ake so zuwa taga siginar, danna kan don dacewa da sigina zuwa nisa na yanzu na taga sannan kuma sake shigar da sigina daga sake kunnawa alamar da ke kan kayan aiki. Yanzu kuna iya ganin sigina tare da ƙimar su.

Ƙimar siginar

Ta hanyar tsoho, ƙimar sigina suna cikin tsarin hexadecimal kuma duk raƙuman ruwa suna da launin kore (idan yana gudana daidai).

Mai amfani zai iya canza kaddarorin waɗannan siginar ta danna-dama kan siginar da zabar Tsarin Bayanai ko Tsarin Launi. Mai amfani kuma na iya saka siginar da babu komai don yin sassan tsakanin rukunin sigina. Lokacin da kuke da sakamakon gani da ake so, zaku iya ajiye saitunanku ta zuwa File → Rubuta Ajiye File.

GTKWave Toolbar

Kayan aiki (duba Hoto 10) yana bawa mai amfani damar yin ayyuka na asali don siginar. Bari mu tattauna kowane zaɓi akan kayan aiki daga hagu zuwa dama.

1. Zaɓuɓɓukan Menu: A karkashin wannan zabin za mu iya view duk nau'ikan nau'ikan software da za a iya amfani da su don wasa tare da software. Bayanan da ke ƙarƙashin wannan zaɓi na menu an rufe su ƙarƙashin Sashe na 8 na wannan jagorar mai amfani.
2. Yanke Dabarun: Ana amfani da shi don sharewa/yanke siginar zaɓi daga taga siginar
3. Kwafi Dabarun: Ana amfani da shi don kwafe siginar da aka zaɓa daga taga siginar
4. Manna Dabarun: Za a iya manna alamar da aka kwafi/yanke a wani wuri daban a cikin taga siginar
5. Zuƙowa Fit: Ana amfani da shi don dacewa da sigina gwargwadon girman taga mai amfani ya zaɓa don nunawa
6. Zuƙowa: Ana amfani da shi don zuƙowa a cikin taga siginar
7. Zuƙowa waje: Ana amfani da shi don zuƙowa tagar siginar
8. Zuƙowa Gyara: ana amfani da shi don warwarewa/fitar da tagar siginar
9. Zuƙowa don farawa: wannan zai zuƙowa taga siginar, yana nuna lokacin farawa na sigina.
10. Zuƙowa zuwa Ƙarshe: wannan zai zuƙowa taga siginar da ke nuna ƙarshen lokacin sigina
11. Nemo gefen baya: Wannan yana canza alamar zuwa gefen hagu yana nuna gefen baya
12. Nemo gefen gaba: Wannan yana canza alamar zuwa dama yana nuna gefen gaba
13. Gungura ƙasa/babban haɗin gwiwa: ta amfani da wannan za mu iya saita lokacin da mai amfani ke son nunawa. Domin misaliampHar ila yau, za mu iya saita tsarin lokaci zuwa 0 sec zuwa 500 ns, zai nuna sigina a ƙarƙashin wannan tsawon lokaci kawai.
14. Sake kaya: Ana danna sake saukewa a duk lokacin da aka sami canji ga siginar da aka nuna. Zai sake saukewa kuma ya nuna siginar bisa ga sababbin sigogi. Domin misaliample, bayan canza tsarin lokacin siginar, muna buƙatar sake shigar da siginar don nuna siginar a cikin sabon tsarin lokaci.

Zaɓuɓɓukan Menu

Daga saman kusurwar hagu na software na GTKWave, mai amfani zai iya samun damar zaɓin menu ta danna layukan tsaye guda uku (duba Hoto na 11). Mai amfani zai iya samun zaɓuɓɓuka masu zuwa a ƙarƙashin zaɓuɓɓukan Menu:

File

The File ƙaramin menu ya ƙunshi abubuwa daban-daban masu alaƙa da shiga files, VCD mai shigo da-fitarwa files, bugu, da karatu/rubutu files da fita.

Gyara

Ana amfani da ƙaramin menu na Gyara don yin ayyuka masu amfani daban-daban kamar canza wakilcin bayanai na dabi'u a cikin ƙaramin taga igiyar ruwa. Yin amfani da zaɓuɓɓukan da ke ƙarƙashin Editan ƙaramin menu, mai amfani zai iya canza tsarin bayanai na sigina, sake tsara su, canza su, datsa shi, haskaka shi, siginar rukuni, sharhi kan sigina, canza launin sigina, da sauransu.

search

Ana amfani da ƙaramin menu na Bincike don yin bincike akan sunaye da ƙima. Yana taimakawa yin ayyuka akan matakan matsayi daban-daban na sigina da misalai a cikin VCD file.

Lokaci

Ramin menu na lokaci ya ƙunshi babban saitin ayyukan Kewayawa da maɓallan Panel ɗin Matsayi.
Yana ba da damar sauƙi, lokaci mai alaƙa, ayyuka kamar zuƙowa, matsawa zuwa wani lokaci na musamman, canza siginar a wata hanya, da sauransu.

Alamar alama

Ana amfani da ƙaramin menu na alamar don yin magudi daban-daban akan alamar tare da sarrafa gungurawa a gefen allo.
Yana ba da damar aikin ƙara alamomi masu yawa akan taga siginar. Matsakaicin alamun sunaye 26 an ba da izinin kuma lokuta ga kowa dole ne ya bambanta.

a. Don ƙara Alamomi a cikin taga siginar
Danna hagu a wurin da ake buƙata inda kake son sanya alamar kuma danna ALT + N. Wannan zai sanya alamar mai suna (A,B,C, da dai sauransu) a wurin da ake bukata. Mai amfani zai iya ci gaba da yin wannan don wurare 26 daban-daban na lokaci.
Don kwatanta ƙimar lokaci a duk alamomin wurare, Menu → Alamomi → Nuna Canja Bayanan Alama.
Wannan zai buɗe taga tare da ƙimar lokaci a kowace Alama. Mai amfani zai iya lura da ƙimar lokaci da hannu a kowace alamar da aka sanya kuma ya rage su don ƙididdige bambancin lokaci tsakanin alamomi 2.
b. Don cire Alama a cikin taga siginar

Mai amfani zai iya zuwa Menu → Alamomi → Tattara Alamar mai suna. Wannan zai cire alamar mai suna na ƙarshe da aka sanya a cikin taga siginar. Mai amfani zai iya cire duk Alamomi mai suna ta zuwa Menu → Alamomi → Tattara Duk Alamar Mai Suna (Hoto 12).

A cikin hoto na 13, zamu iya ganin yadda aka canza launin siginar. Kuna iya lura da siginar Blank da aka ƙara zuwa taga siginar haka kuma tare da sharhi - Siginar Blank.
Hakanan lura da kasancewar 6 Masu Alamar Suna (A - E) da ƙididdigar ƙimar lokaci tsakanin waɗannan Alamomin a cikin ps.

View

The View Ana amfani da ƙaramin menu don sarrafa halaye daban-daban waɗanda ke ma'amala da zane-zane na abubuwan matsayi da ƙima a cikin ƙaramin taga sigina. Daga wannan menu, zaku iya canza taga siginar zuwa Baƙar fata & Fari ko kuma mai launi. The View menu na ƙasa kuma yana ba ku damar canza lokacin Girman daga daƙiƙa (secs) zuwa ficoseconds (fs). Mai amfani zai iya samun wannan zaɓi View → Ma'auni zuwa Girman Lokaci → fs.

Taimako

Ƙarƙashin menu na taimako ya ƙunshi zaɓuɓɓuka don kunna taimakon kan layi tare da nuna bayanan sigar shirin.

Kammalawa

An ƙirƙiri wannan takarda don taimaka wa mai amfani don samun nasarar kwaikwayon ƙirar su da kuma tabbatar da aikin ta hanyar gyara zayyana abubuwan da ake buƙata da kuma amfani da Icarus Verilog tare da GTKwave don nuna sifofin igiyoyin ruwa da kuma lura da sakamakon.

Tarihin Bita

Bita	Kwanan wata	Bayani
1.00	Mayu 20, 2024	Sakin farko.

Saukewa: R19US0011EU0100
Mayu 20, 2024
© 2024 Renesa Electronics

Takardu / Albarkatu

RENESAS ForgeFPGA Software kwaikwaiyo [pdf] Jagorar mai amfani REN_r19us0011eu0100

Magana

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