MICROCHIP DDR Waca IP
Spesifikasi
- Jeneng produk: DDR Read IP v2.0
- Kompatibel karo Video Arbiter IP
- Digunakake kanggo maca bledosan data terus-terusan saka memori DDR
- Biasane digunakake ing aplikasi video kanggo maca saben baris horisontal pigura video disimpen ing memori DDR
DDR Read IP uga duwe port input lan output ing Arbiter
Antarmuka bus lan AXI4 Stream Interface, kadhaptar ing manual pangguna.
FAQ
- Apa tujuan DDR Read IP?
- Apa kompatibilitas dibutuhake kanggo DDR Read IP?
- Ing aplikasi kang DDR Read IP biasane digunakake?
Pambuka
DDR Read IP maca bledosan data terus-terusan saka memori DDR. DDR Read IP kudu digunakake karo Video Arbiter IP sing ngowahi panjalukan diwaca kanggo transaksi AXI4. DDR Read IP biasane digunakake ing aplikasi video kanggo maca saben baris horisontal pigura video sing disimpen ing memori DDR.
Gambar 1. Antarmuka Arbiter SmartDesign
Fitur Utama
- Biasane digunakake kanggo Maca Video Frame Lines
- Ndhukung Output Video Pixel Width 8, 16, lan 32 bit
- Ndhukung Antarmuka Video Arbiter 128, 256, lan 512 bit
- Ndhukung AXI4 Stream Interface
Implementasi Hardware
IP ngasilake sinyal kontrol menyang IP arbiter Video adhedhasar input pangguna saka alamat wiwitan pigura resolusi horisontal. Rising pinggiran read_en_i miwiti transaksi maca. Data saka wasit video disimpen ing CDC FIFO sing ngowahi data saka domain jam DDR menyang domain jam piksel. Data diwaca saka FIFO ing pojok read_en_i lan dibongkar kanggo ngasilake data piksel. Read_en_i kudu dhuwur kanggo wektu sing cukup kanggo ngrampungake transaksi maca DDR lan durasi sing disaranake kanggo sawetara jam sing padha karo resolusi horisontal. Baris pisanan diwaca saka alamat sing ditetepake dening frame_start_addr_i, lan sawise saben transaksi diwaca, alamat kasebut ditambah karo line_gap_i. Alamat diwaca direset menyang frame_start_addr_i ing saben sinyal frame_end_i. Data output dhuwur kanggo nomer resolusi horisontal jam.
Deskripsi Desain
- Tokoh ing ngisor iki nuduhake ndhuwur-tingkat pin-metu diagram saka DDR Read.
Port Input lan Output
Tabel ing ngisor iki nampilake port input lan output saka DDR Read IP ing Native Interface.
Tabel 1-1. Port Input lan Output saka DDR Read ing Native Interface.
| Jeneng Port | Jinis | Jembar | Katrangan |
| reset_i | Input | — | Aktif Low sinyal reset bedo kanggo desain |
| piksel_clk_i | Input | — | Jam piksel |
| ddr_clk_i | Input | — | jam DDR saka controller memori |
| frame_end_i | Input | — | Pungkasan sinyal pigura |
| maca_en_i | Input | — | Waca ngaktifake sinyal kanggo maca |
| line_gap_i | Input | 16 bit | Line longkangan antarane rong baris |
| horz_resl_i | Input | 16 bit | Resolusi horisontal |
| Jeneng Port | Jinis | Jembar | Katrangan |
| h_pan_i | Input | 12 bit | Offset horisontal kanggo saben baris video kanggo panning horisontal |
| v_pan_i | Input | 12 bit | Offset vertikal saka alamat wiwitan pigura kanggo panning vertikal |
| maca_ackn_i | Input | — | Ngakoni kanggo panjalukan maca saka video arbiter |
| maca_rampung_i | Input | — | Maca input completion saka arbiter video |
| ddr_data_valid_i | Input | — | Waca data sing bener saka Arbiter |
| frame_start_addr | Input | 8 bit | Alamat wiwitan pigura video |
| wdata_i | Input | Jembar Data Input | Maca data saka Arbiter |
| maca_req_o | Output | — | Maca panyuwunan menyang arbiter |
| maca_wiwitan_addr_o | Output | 32 bit | alamat DDR saka ngendi maca kudu diwiwiti |
| burst_size_o | Output | 8 bit | Maca ukuran burst |
| data_valid_o | Output | — | Data Valid |
| data_o | Output | Jembar Data Output | Data kanggo Video Pipelining |
Tabel ing ngisor iki nampilake port input lan output saka DDR Read IP ing bis Interface Arbiter.
Tabel 1-2. Port Input lan Output saka DDR Read ing Arbiter Interface Bus.
| Jeneng Port | Jinis | Jembar | Katrangan |
| RDATA_I | Input | Jembar Data Input | Maca data saka Arbiter |
| RVALID_I | Input | — | Waca data sing bener saka Arbiter |
| ARREADY_I | Input | — | Arbiter ngakoni saka panjalukan diwaca |
| BUSER_I | Input | — | Wacan rampung |
| ARADDR_O | Output | 32 bit | alamat DDR saka ngendi maca kudu diwiwiti |
| ARVALID_O | Output | — | Maca panyuwunan menyang arbiter |
| ARSIZE_O | Output | 8 bit | Maca ukuran burst |
Tabel ing ngisor iki nampilake port input lan output saka DDR Read IP ing AXI4 Stream Interface.
Tabel 1-3. Port Input lan Output saka DDR Read ing AXI4 Stream Interface.
| Jeneng Port | Jinis | Jembar | Katrangan |
| JAM_I | Input | — | Jam piksel |
| RESET_n_I | Input | — | Aktif Low sinyal reset bedo kanggo desain |
| TDATA_O | Output | Jembar Data Output | Output Video Data |
| TSTRB_O | Output | [Jembaré Data Output/8 – 1: 0] | Output Video Data strobo |
| TKEEP_O | Output | [Jembaré Data Output/8 – 1: 0] | Output Video Data Simpen |
| TVALID_O | Output | — | Data Output Video bener |
| TUSER_O | Output | 4 bit | Output data pangguna 0bit = VSYNC
3 bit = Frame mburi |
| Jeneng Port | Jinis | Jembar | Katrangan |
| TLAST_O | Output | — | Output Video Pungkasan Frame |
Parameter Konfigurasi
Tabel ing ngisor iki nampilake paramèter konfigurasi sing digunakake ing implementasi hardware DDR Read IP. Iki minangka paramèter umum lan bisa mawarni-warni adhedhasar syarat aplikasi.
Tabel 1-4. Parameter Konfigurasi
| Jeneng Parameter | Katrangan |
| Resolusi Horizontal | Nemtokake resolusi horisontal |
| Jembar Data Input | Nemtokake jembar data input (128, 256, lan 512 bit) |
| Jembar Data Output | Nemtokake jembar data output (8, 16, 24, 32, lan 64 bit) |
| Antarmuka Arbiter | Pilihan kanggo milih Antarmuka Arbiter saka menu gulung mudhun minangka Native utawa Antarmuka Bus |
| Antarmuka Data | Pilihan kanggo milih Antarmuka Data saka menu gulung mudhun minangka Native lan AXI4 Stream Interface |
Panggunaan sumber daya
Tabel ing ngisor iki nampilake panggunaan sumber daya kanggo DDR Read IP ing Native Interface kanthi jembar data input = 256 lan jembar data output = 8.
DDR Read pemblokiran dipun ginakaken ing piranti PolarFire FPGA, paket MPF300TS_ES-1FCG1152E.
Tabel 1-5. DDR Read IP ing Native Interface
| sumber daya | Panganggone |
| DFFs | 502 |
| 4 input LUT | 513 |
| MACC | 0 |
| LSRAM 18K | 14 |
| SRAM | 0 |
Tabel ing ngisor iki nampilake panggunaan sumber daya kanggo DDR Read IP ing Antarmuka Bus lan stream AXI4 kanthi jembar data input = 256 lan jembar data output = 8.
Tabel 1-6. DDR Read IP in Bus Interface lan AXI4 Stream
| sumber daya | Panganggone |
| DFFs | 512 |
| 4 input LUT | 514 |
| MACC | 0 |
| LSRAM 18K | 14 |
| SRAM | 0 |
Riwayat Revisi
Riwayat revisi nggambarake owah-owahan sing ditindakake ing dokumen kasebut. Owah-owahan kasebut didhaptar kanthi revisi, diwiwiti saka publikasi paling anyar.
| Revisi | Tanggal | Katrangan |
| 1.0 | 03/2022 | Revisi Awal. |
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Dokumen / Sumber Daya
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MICROCHIP DDR Waca IP [pdf] Pandhuan pangguna DDR Waca IP, DDR, Waca IP, IP |
