MICROCHIP DDR Verenga IP
Zvinotsanangurwa
- Zita reChigadzirwa: DDR Verenga IP v2.0
- Inoenderana neVhidhiyo Arbiter IP
- Inoshandiswa kuverenga kuputika kwe data inoenderera kubva kuDDR memory
- Inowanzo shandiswa mumavhidhiyo maapplication kuverenga yega yega yakachinjika mutsara wevhidhiyo furemu yakachengetwa muDDR memory
Iyo DDR Read IP ine zvakare yekupinza uye yekubuda madoko muArbiter
Interface bhazi uye AXI4 Stream Interface, yakanyorwa mubhuku remushandisi.
FAQ
- Chii chinangwa cheDDR Read IP?
- Chii chinodiwa kuenderana kweDDR Read IP?
- Ndeapi maapplication ari DDR Read IP anowanzo shandiswa?
Nhanganyaya
DDR Verenga IP inoverenga zvakawanda zvinoramba zvichiitika kubva kuDDR memory. Iyo DDR Read IP inofanirwa kushandiswa neVhidhiyo Arbiter IP inoshandura zvikumbiro zvekuverenga kuita AXI4 transaction. Iyo DDR Read IP inowanzo shandiswa mumavhidhiyo maapplication kuverenga yega yega yakachinjika mutsara wevhidhiyo furemu yakachengetwa muDDR memory.
Mufananidzo 1. SmartDesign Arbiter Interface
Key Features
- Kazhinji inoshandiswa kuverenga Vhidhiyo Frame Lines
- Inotsigira Output Vhidhiyo Pixel Width ye8, 16, uye 32 bits
- Inotsigira Vhidhiyo Arbiter Interface ye128, 256, uye 512 bits
- Inotsigira AXI4 Stream Interface
Hardware Implementation
Iyo IP inogadzira masiginecha ekutonga kuVhidhiyo arbiter IP zvichibva pane zvakaiswa mushandisi yeiyo yakachinjika resolution fremu yekutanga kero. Macheto ari kusimukira e read_en_i anotanga kuverenga. Iyo data kubva kumupire wevhidhiyo inochengetwa muCDC FIFO inoshandura data kubva kuDDR wachi domain kuenda kune pixel wachi domain. Iyo data inoverengwa kubva kuFIFO kumucheto kwe read_en_i uye isina kurongedzerwa kugadzira pixel data. Iyo read_en_i inofanirwa kunge yakakwira kwenguva yakakwana yekupedzisa DDR kuverenga transaction uye nguva yakakurudzirwa ndeyewachi akati wandei akaenzana neyakachinjika kugadzirisa. Mutsetse wekutanga unoverengwa kubva kukero inotsanangurwa neframe_start_addr_i, uye mushure mekuverenga kwega kwega kutengeserana, kero inowedzerwa nemutsara_gap_i. Kero yekuverenga inoiswa patsva kune furemu_start_addr_i pane yega furemu_end_i chiratidzo. Iyo data inobuda yakakwira kune yakachinjika kugadzirisa nhamba yewachi.
Dhizaini Dhizaini
- Nhamba inotevera inoratidza iyo yepamusoro-pini-kunze dhayagiramu yeDDR Read.
Input uye Output Ports
Iyi tafura inotevera inonyora ekuisa uye kubuda madoko eDDR Verenga IP muNative Interface.
Tafura 1-1. Kupinza uye Kubuda Ports yeDDR Kuverenga muNative Interface.
| Port Name | Type | Upamhi | Tsanangudzo |
| reset_i | Input | — | Active Low asynchronous reset chiratidzo chekugadzira |
| pixel_clk_i | Input | — | Pixel wachi |
| ddr_clk_i | Input | — | DDR wachi kubva kundangariro controller |
| furemu_kuguma_i | Input | — | Kupera kwechiratidzo chechimiro |
| verenga_en_i | Input | — | Verenga inogonesa chiratidzo chekuverenga |
| mutsetse_mukana_i | Input | 16 zvishoma | Mutsetse mukaha pakati pemitsetse miviri |
| horz_resl_i | Input | 16 zvishoma | Horizontal resolution |
| Port Name | Type | Upamhi | Tsanangudzo |
| h_pan_i | Input | 12 zvishoma | Horizontal offset kune yega yega vhidhiyo mutsara wekuchinjika panning |
| v_pan_i | Input | 12 zvishoma | Vertical offset kubva pafremu yekutanga kero ye vertical panning |
| verenga_akn_i | Input | — | Mvumo yekuverenga chikumbiro kubva kune vhidhiyo arbiter |
| verenga_ndaita_i | Input | — | Verenga kupedzisa kupinza kubva kune vhidhiyo arbiter |
| ddr_data_valid_i | Input | — | Verenga data inoshanda kubva kuArbiter |
| frame_start_add | Input | 8 zvishoma | Vhidhiyo furemu yekutanga kero |
| wdata_i | Input | Input Data Width | Verenga data kubva kuArbiter |
| verenga_req_o | Output | — | Verenga chikumbiro kune mutongi gava |
| verenga_tanga_addr_o | Output | 32 zvishoma | DDR kero kubva panofanira kutangirwa kuverenga |
| burst_size_o | Output | 8 zvishoma | Verenga kuputika saizi |
| data_valid_o | Output | — | Data Inoshanda |
| data_o | Output | Output Data Width | Data yeVhidhiyo Pipelining |
Iyi tafura inotevera inoronga zvekupinza uye zvinobuda zviteshi zveDDR Verenga IP mubhazi reArbiter Interface.
Tafura 1-2. Zvekupinda uye Zvekubuda Ports zveDDR Verenga muArbiter Interface Bhazi.
| Port Name | Type | Upamhi | Tsanangudzo |
| RDATA_I | Input | Input Data Width | Verenga data kubva kuArbiter |
| RVALID_I | Input | — | Verenga data inoshanda kubva kuArbiter |
| ARREADY_I | Input | — | Arbiter kubvuma kubva pakuverenga chikumbiro |
| BUSER_I | Input | — | Verenga kupedza |
| ARADDR_O | Output | 32 zvishoma | DDR kero kubva panofanira kutangirwa kuverenga |
| ARVALID_O | Output | — | Verenga chikumbiro kune mutongi gava |
| ARSIZE_O | Output | 8 zvishoma | Verenga kuputika saizi |
Iyi tafura inotevera inonyora ekuisa uye kubuda madoko eDDR Verenga IP muAXI4 Stream Interface.
Tafura 1-3. Input and Output Ports yeDDR Verenga muAXI4 Stream Interface.
| Port Name | Type | Upamhi | Tsanangudzo |
| CLOCK_I | Input | — | Pixel wachi |
| RESET_n_I | Input | — | Active Low asynchronous reset chiratidzo chekugadzira |
| TDATA_O | Output | Output Data Width | Output Vhidhiyo Data |
| TSTRB_O | Output | [Output Data Width/8 – 1: 0] | Output Vhidhiyo Data strobe |
| TKEEP_O | Output | [Output Data Width/8 – 1: 0] | Output Vhidhiyo Data Chengetedza |
| TVALID_O | Output | — | Yakabuda Vhidhiyo data inoshanda |
| TUSER_O | Output | 4 zvishoma | Yakabuda mushandisi data 0bit= VSYNC
3bit =Frame kupera |
| Port Name | Type | Upamhi | Tsanangudzo |
| TLAST_O | Output | — | Kubuda Vhidhiyo Kupera kweFremu |
Configuration Parameters
Tafura inotevera inoronga zvigadziriso zvimiro zvinoshandiswa muDDR Verenga IP hardware kuita. Aya ma generic paramita uye anogona kusiana zvichienderana nezvinodiwa zvekushandisa.
Tafura 1-4. Configuration Parameters
| Parameter Zita | Tsanangudzo |
| Horizontal Resolution | Inotsanangura horizontal resolution |
| Input Data Width | Inotsanangura hupamhi hwedata rekuisa (128, 256, uye 512 bits) |
| Output Data Width | Inotsanangura iyo yakabuda data upamhi (8, 16, 24, 32, uye 64 bits) |
| Arbiter Interface | Sarudzo dzekusarudza iyo Arbiter Interface kubva pane yekudonha-pasi menyu seNative kana Bhazi Interface |
| Data Interface | Sarudzo dzekusarudza iyo Data Interface kubva pane yekudonha-pasi menyu seNative uye AXI4 Stream Interface |
Resource Utilization
Tafura inotevera inoronga mashandisirwo ezviwanikwa zveDDR Verenga IP muNative Interface ine yekupinda data wide = 256 uye inobuda data wide = 8.
DDR Read block inoshandiswa paPolarFire FPGA mudziyo, MPF300TS_ES-1FCG1152E package.
Tafura 1-5. DDR Verenga IP muNative Interface
| Resource | Usage |
| DFFs | 502 |
| 4 kuisa LUTs | 513 |
| MACC | 0 |
| LSRAM 18K | 14 |
| SRAM | 0 |
Tafura inotevera inoronga mashandisirwo ezviwanikwa zveDDR Verenga IP muBus Interface uye AXI4 rwizi ine yekupinda data hupamhi = 256 uye inobuda data upamhi = 8.
Tafura 1-6. DDR Verenga IP muBus Interface uye AXI4 Stream
| Resource | Usage |
| DFFs | 512 |
| 4 kuisa LUTs | 514 |
| MACC | 0 |
| LSRAM 18K | 14 |
| SRAM | 0 |
Revision History
Nhoroondo yekudzokorora inotsanangura shanduko dzakaitwa mugwaro. Kuchinja kwacho kunorongwa nekudzokorora, kutanga nebhuku razvino uno.
| Kudzokorora | Date | Tsanangudzo |
| 1.0 | 03/2022 | Ongororo Yokutanga. |
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Zvinyorwa / Zvishandiso
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MICROCHIP DDR Verenga IP [pdf] Bhuku reMushandisi DDR Verenga IP, DDR, Verenga IP, IP |
