MICROCHIP DDR Faitau IP
Fa'amatalaga
- Igoa oloa: DDR Faitau IP v2.0
- E fetaui ma le Video Arbiter IP
- Fa'aaogaina mo le faitauina o fa'amatalaga fa'aauau mai le DDR memory
- E masani ona fa'aoga i ata vitio e faitau laina ta'itasi o le ata vitio o lo'o teuina i le DDR memory
O le DDR Read IP o loʻo i ai foʻi pusa faʻapipiʻi ma faʻaogaina i le Arbiter
Interface pasi ma AXI4 Stream Interface, o loʻo lisiina i totonu o le tusi faʻaoga.
FAQ
- O le a le faʻamoemoe o le DDR Read IP?
- O le a le mea e manaʻomia mo le DDR Read IP?
- O fea talosaga e masani ona fa'aoga ai le DDR Read IP?
Folasaga
DDR Read IP e faitau le pa'u o fa'amatalaga fa'aauau mai le DDR memory. O le DDR Read IP e tatau ona faʻaaogaina ma le Video Arbiter IP e faʻaliliuina talosaga faitau i fefaʻatauaiga AXI4. O le DDR Read IP e masani ona fa'aoga i ata vitio e faitau laina ta'itasi o le ata vitio o lo'o teuina i le DDR memory.
Ata 1. SmartDesign Arbiter Interface
Vaega Autu
- E masani ona fa'aoga e Faitau Laina Vitio Fua
- Lagolagoina Output Video Pixel Width o le 8, 16, ma le 32 bits
- Lagolagoina Vitio Arbiter Interface o 128, 256, ma 512 bits
- Lagolago AXI4 Stream Interface
Fa'atinoga o Meafaigaluega
O le IP e fa'atupuina fa'ailo fa'atonutonu i le Vitio arbiter IP fa'avae i luga o mea e fa'aoga ai le fa'aoga o le fa'ava'a fa'ava'a fa'ai'uga amata tuatusi. O le pito i luga ole read_en_i e amata ai se fefaʻatauaiga faitau. O faʻamaumauga mai le faʻatonu vitio o loʻo teuina i totonu o le CDC FIFO e faʻaliliuina faʻamaumauga mai le DDR clock domain i le pixel clock domain. O fa'amaumauga e faitau mai le FIFO i le pito pa'u o le read_en_i ma tatala e fa'atupu fa'amatalaga pika. O le read_en_i e tatau ona maualuga mo le umi o le umi e faʻamaeʻa ai le fefaʻatauaʻiga DDR faitau ma o le umi fautuaina e mo le tele o uati e tutusa ma le faʻataʻitaʻiga. O le laina muamua e faitau mai le tuatusi o loʻo faʻamatalaina e le frame_start_addr_i, ma a maeʻa faʻatauga faitau taʻitasi, o le tuatusi e faʻaopoopo i le line_gap_i. O le tuatusi faitau e toe setiina i le frame_start_addr_i i fa'ailoga frame_end_i uma. E maualuga fa'amaumauga o galuega mo se numera fa'alava o uati.
Mamanu Faamatalaga
- O le ata o loʻo i lalo o loʻo faʻaalia ai le pito i luga o le pito i luga o le ata o le DDR Read.
Taulaga Ulufale ma Ulufale
O le laulau o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufale o le DDR Read IP i le Native Interface.
Laulau 1-1. Ulufale ma Taulaga o le DDR Faitau ile Native Interface.
| Igoa o le Taulaga | Ituaiga | Lautele | Fa'amatalaga |
| reset_i | Ulufale | — | Active Low asynchronous toe setiina faailoilo e mamanu |
| pixel_clk_i | Ulufale | — | Uati Pixel |
| ddr_clk_i | Ulufale | — | DDR uati mai le pule manatua |
| faavaa_mutu_i | Ulufale | — | Fa'ai'uga o fa'ailoga fa'avaa |
| faitau_en_i | Ulufale | — | Faitau fa'aagaaga fa'ailoga mo le faitau |
| laina_gap_i | Ulufale | 16 pito | Laina va i le va o laina e lua |
| horz_resl_i | Ulufale | 16 pito | Fuafuaga faalava |
| Igoa o le Taulaga | Ituaiga | Lautele | Fa'amatalaga |
| h_pan_i | Ulufale | 12 pito | Fa'asa'o fa'asaga mo laina vitio ta'itasi mo le fa'alava fa'alava |
| v_pan_i | Ulufale | 12 pito | Fa'asaga tu'usa'o mai le tuatusi amata fa'avaa mo le fa'apa sa'o |
| faitau_ackn_i | Ulufale | — | Fa'afetai mo talosaga faitau mai le video arbiter |
| faitau_fai_i | Ulufale | — | Faitau fa'amatalaga fa'amae'aina mai le fa'atonu vitiō |
| ddr_data_valid_i | Ulufale | — | Faitau faʻamatalaga faʻamaonia mai le Arbiter |
| frame_start_addr | Ulufale | 8 pito | Tulaga amata fa'avaa vitiō |
| wdata_i | Ulufale | Ulufale Fa'amatalaga Lautele | Faitau faʻamatalaga mai le Arbiter |
| faitau_req_o | Tuuina atu | — | Faitau le talosaga i le faamasino |
| faitau_amata_addr_o | Tuuina atu | 32 pito | tuatusi DDR mai le mea e tatau ona amata ai le faitau |
| male_size_o | Tuuina atu | 8 pito | Faitau le tele o le pa |
| data_valid_o | Tuuina atu | — | Fa'amatalaga Fa'amaonia |
| data_o | Tuuina atu | Lautele o Fa'amatalaga Fa'amatalaga | Fa'amatalaga mo Vitio Pipelining |
O le laulau o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufale o le DDR Read IP i totonu o le pasi Arbiter Interface.
Laulau 1-2. Ulufale ma Taulaga o le DDR Faitau ile Arbiter Interface Bus.
| Igoa o le Taulaga | Ituaiga | Lautele | Fa'amatalaga |
| RDATA_I | Ulufale | Ulufale Fa'amatalaga Lautele | Faitau faʻamatalaga mai le Arbiter |
| RVALID_I | Ulufale | — | Faitau faʻamatalaga faʻamaonia mai le Arbiter |
| UA READY_I | Ulufale | — | Fa'ailoa a le au fa'atonu mai le talosaga faitau |
| BUSER_I | Ulufale | — | Faitau mae'a |
| ARADDR_O | Tuuina atu | 32 pito | tuatusi DDR mai le mea e tatau ona amata ai le faitau |
| ARVALID_O | Tuuina atu | — | Faitau le talosaga i le faamasino |
| ARSIZE_O | Tuuina atu | 8 pito | Faitau le tele o le pa |
O le laulau o lo'o i lalo o lo'o lisiina ai ports o lo'o i totonu ma fa'aulufale o le DDR Read IP i le AXI4 Stream Interface.
Laulau 1-3. Ulufale ma Taulaga o le DDR Faitau ile AXI4 Stream Interface.
| Igoa o le Taulaga | Ituaiga | Lautele | Fa'amatalaga |
| CLOCK_I | Ulufale | — | Uati Pixel |
| RESET_n_I | Ulufale | — | Active Low asynchronous toe setiina faailoilo e mamanu |
| TDATA_O | Tuuina atu | Lautele o Fa'amatalaga Fa'amatalaga | Fa'amatalaga Vitio |
| TSTRB_O | Tuuina atu | [Aotele o Faamatalaga o Galuega/8 – 1 : 0] | Fa'amatalaga Vitio Fa'amatalaga strobe |
| TKEEP_O | Tuuina atu | [Aotele o Faamatalaga o Galuega/8 – 1 : 0] | Fa'amauina Fa'amaumauga Vitio |
| TVALID_O | Tuuina atu | — | Fa'amatalaga Fa'amatalaga Vitio aoga |
| TUSER_O | Tuuina atu | 4 pito | Fa'amatalaga tagata fa'aoga 0bit= VSYNC
3bit = Fa'ai'uga pito |
| Igoa o le Taulaga | Ituaiga | Lautele | Fa'amatalaga |
| TLAST_O | Tuuina atu | — | Tu'u Vitio Fa'ai'uga o le Fa'avaa |
Fa'atutuga Parata
O le laulau o loʻo i lalo o loʻo lisiina ai le faʻatulagaina o faʻaoga o loʻo faʻaaogaina i le DDR Read IP hardware. O ta'otoga lautele ia ma e mafai ona fesuia'i fa'atatau ile mana'oga.
Laulau 1-4. Fa'atutuga Parata
| Igoa Parameter | Fa'amatalaga |
| I'uga Fa'asaga | Fa'amatala fofo fa'ata'atia |
| Ulufale Fa'amatalaga Lautele | Fa'amatala le lautele o fa'amatalaga (128, 256, ma le 512 bits) |
| Lautele o Fa'amatalaga Fa'amatalaga | Fa'amatala le lautele o fa'amaumauga (8, 16, 24, 32, ma le 64 bits) |
| Arbiter Interface | Filifiliga e filifili ai le Arbiter Interface mai le fa'alalo-lalo lisi o Native po'o Bus Interface |
| Fa'amatalaga Fa'amatalaga | Filifiliga e filifili ai le Fa'amatalaga Fa'amatalaga mai le lisi fa'alalo e pei o le Native ma le AXI4 Stream Interface |
Fa'aaogaina o Punaoa
O le laulau o lo'o i lalo o lo'o lisiina ai le fa'aogaina o puna'oa mo le DDR Read IP i le Native Interface fa'atasi ai ma le lautele o fa'amaumauga tu'ufa'atasi = 256 ma le lautele o fa'amatalaga fa'amatalaga = 8.
DDR Read poloka o loʻo faʻatinoina i le PolarFire FPGA masini, MPF300TS_ES-1FCG1152E afifi.
Laulau 1-5. DDR Faitau le IP i le Native Interface
| Punaoa | Fa'aoga |
| DFFs | 502 |
| 4 fa'aoga LUTs | 513 |
| MACC | 0 |
| LSRAM 18K | 14 |
| SRAM | 0 |
O le laulau o lo'o i lalo o lo'o lisiina ai le fa'aogaina o puna'oa mo le DDR Read IP i le Bus Interface ma le AXI4 stream fa'atasi ai ma fa'amatalaga fa'amatalaga lautele = 256 ma fa'amatalaga fa'amatalaga lautele = 8.
Laulau 1-6. DDR Faitau le IP i le Bus Interface ma le AXI4 Stream
| Punaoa | Fa'aoga |
| DFFs | 512 |
| 4 fa'aoga LUTs | 514 |
| MACC | 0 |
| LSRAM 18K | 14 |
| SRAM | 0 |
Toe Iloilo Tala'aga
O le tala fa'asolopito o lo'o fa'amatalaina suiga na fa'atinoina i le pepa. O suiga o lo'o lisiina e ala i toe iloiloga, amata i le lomiga aupito lata mai.
| Toe Iloiloga | Aso | Fa'amatalaga |
| 1.0 | 03/2022 | Toe Iloiloga Muamua. |
Microchip FPGA Lagolago
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Fa'ailoga Puipuiga o Fa'ailoga Fa'atonu a Microchip
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Faiga Fa'atonuga
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Telefoni: 91-80-3090-4444 Initia – New Delhi Telefoni: 91-11-4160-8631 Initia - Pune Telefoni: 91-20-4121-0141 Iapani - Osaka Telefoni: 81-6-6152-7160 Iapani - Tokyo Telefoni: 81-3-6880-3770 Korea – Daegu Telefoni: 82-53-744-4301 Korea – Seoul Telefoni: 82-2-554-7200 Meleisia – Kuala Lumpur Telefoni: 60-3-7651-7906 Meleisia – Penang Telefoni: 60-4-227-8870 Filipaina – Manila Telefoni: 63-2-634-9065 Singapore Telefoni: 65-6334-8870 Taiuani – Hsin Chu Telefoni: 886-3-577-8366 Taiuani – Kaohsiung Telefoni: 886-7-213-7830 Taiuani – Taipei Telefoni: 886-2-2508-8600 Taialani – Bangkok Telefoni: 66-2-694-1351 Vietnam – Ho Chi Minh Telefoni: 84-28-5448-2100 |
Ausetalia – Uelese
Telefoni: 43-7242-2244-39 Fax: 43-7242-2244-393 Tenimaka – Copenhagen Telefoni: 45-4485-5910 Fax: 45-4485-2829 Finelani – Espoo Telefoni: 358-9-4520-820 Farani – Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Siamani – Garching Telefoni: 49-8931-9700 Siamani – Haan Telefoni: 49-2129-3766400 Siamani – Heilbronn Telefoni: 49-7131-72400 Siamani – Karlsruhe Telefoni: 49-721-625370 Siamani – Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Siamani – Rosenheim Telefoni: 49-8031-354-560 Isaraelu – Ra’anana Telefoni: 972-9-744-7705 Italia – Milan Telefoni: 39-0331-742611 Fax: 39-0331-466781 Italia – Padova Telefoni: 39-049-7625286 Netherlands – Drunen Telefoni: 31-416-690399 Fax: 31-416-690340 Nouei – Trondheim Telefoni: 47-72884388 Polani – Warsaw Telefoni: 48-22-3325737 Romania – Bucharest Tel: 40-21-407-87-50 Sepania - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Suetena – Gothenburg Tel: 46-31-704-60-40 Suetena - Stockholm Telefoni: 46-8-5090-4654 Peretania - Wokingham Telefoni: 44-118-921-5800 Fax: 44-118-921-5820 |
Pepa / Punaoa
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MICROCHIP DDR Faitau IP [pdf] Taiala mo Tagata Fa'aoga DDR Faitau IP, DDR, Faitau IP, IP |
