MICROCHIP Costas Loop Management User Guide
Mawu Oyamba
Potumiza opanda zingwe, Transmitter (Tx) ndi Receiver (Rx) zimasiyanitsidwa ndi mtunda komanso kudzipatula kwamagetsi. Ngakhale kuti Tx ndi Rx zonse zimayendetsedwa kufupipafupi, pali kusiyana kwafupipafupi pakati pa maulendo onyamulira chifukwa cha kusiyana kwa ppm pakati pa oscillator omwe amagwiritsidwa ntchito mu Tx ndi Rx. Ma frequency offset amalipidwa pogwiritsa ntchito njira zothandizira kapena zosagwiritsa ntchito deta (akhungu) kulunzanitsa.
A Costas Loop ndi njira yosagwiritsa ntchito data ya PLL yolipirira ma frequency onyamula. Kugwiritsa ntchito koyambirira kwa malupu a Costas kuli pazolandila opanda zingwe. Pogwiritsa ntchito izi, kusinthasintha kwafupipafupi pakati pa Tx ndi Rx kumalipidwa popanda kuthandizidwa ndi ma toni oyendetsa ndege kapena zizindikiro. The Costas Loop ikugwiritsidwa ntchito pakusintha kwa BPSK ndi QPSK ndikusintha kwa block calculation block. Kugwiritsa ntchito Costas Loop pagawo kapena kulunzanitsa pafupipafupi kungayambitse kusamveka bwino, komwe kuyenera kuwongoleredwa kudzera munjira monga ma encoding osiyana.
Chidule
Gome lotsatirali likupereka chidule cha mawonekedwe a Costas Loop.
Table 1. Makhalidwe a Costas Loop
| Core Version | Chikalatachi chikugwira ntchito ku Costas Loop v1.0. |
| Mabanja a Chipangizo Chothandizira |
|
| Zothandizidwa Chida Yendani | Imafunikira Libero® SoC v12.0 kapena kutulutsidwa pambuyo pake. |
| Kupereka chilolezo | Costas Loop IP clear RTL ndi laisensi yotsekedwa ndipo RTL yosungidwa imapezeka kwaulere ndi chilolezo cha Libero. RTL Yosungidwa: Khodi yathunthu ya RTL yosungidwa imaperekedwa pachimake, kupangitsa kuti pakatikati pakhazikitsidwe ndi Smart Design. Simulation, Synthesis, ndi Layout zitha kuchitidwa ndi pulogalamu ya Libero. Chotsani RTL: Nambala yathunthu ya RTL imaperekedwa pamabenchi oyambira ndi mayeso. |
Mawonekedwe
Costas Loop ili ndi izi:
- Imathandizira kusintha kwa BPSK ndi QPSK
- Tunable loop magawo osiyanasiyana pafupipafupi
Kukhazikitsidwa kwa IP Core mu Libero® Design Suite
IP core iyenera kukhazikitsidwa ku IP Catalog ya pulogalamu ya Libero SoC. Izi zimayikidwa zokha kudzera pa IP
Ntchito yosinthira khathalogi mu pulogalamu ya Libero SoC, kapena IP core imatsitsidwa pamanja kuchokera pamndandanda. Kamodzi
IP core imayikidwa mu Libero SoC software IP Catalog, pachimake chimakonzedwa, kupangidwa, ndikukhazikitsidwa mkati mwa chida cha Smart Design kuti chiphatikizidwe pamndandanda wa projekiti ya Libero.
Kugwiritsa Ntchito Chipangizo ndi Kuchita
Matebulo otsatirawa akuwonetsa zomwe zidagwiritsidwa ntchito ku Costas Loop.
Table 2. Costas Loop Utilization for QPSK
| Tsatanetsatane wa Chipangizo | Zida | Kuchita (MHz) | ma RAM | Masewera a Math | Chip Globals | |||
| Banja | Chipangizo | LUTs | DFF | LSRAM | μSRAM | |||
| PolarFire® SoC | Chithunzi cha MPFS250T | 1256 | 197 | 200 | 0 | 0 | 6 | 0 |
| PolarFire | Mtengo wa MPF300T | 1256 | 197 | 200 | 0 | 0 | 6 | 0 |
Table 3. Costas Loop Utilization kwa BPSK
| Tsatanetsatane wa Chipangizo | Zida | Kuchita (MHz) | ma RAM | Masewera a Math | Chip Globals | |||
| Banja | Chipangizo | LUTs | DFF | LSRAM | μSRAM | |||
| PolarFire® SoC | Chithunzi cha MPFS250T | 1202 | 160 | 200 | 0 | 0 | 7 | 0 |
| Moto wa Polar | Mtengo wa MPF300T | 1202 | 160 | 200 | 0 | 0 | 7 | 0 |
Zofunika:
- Zomwe zili mu tebulo ili zimajambulidwa pogwiritsa ntchito kaphatikizidwe ndi masinthidwe anthawi zonse. Gwero la wotchi ya CDR idakhazikitsidwa kuti Yodzipatulira ndi makonzedwe ena osasinthika.
- Wotchi imakakamizidwa ku 200 MHz pomwe ikuyesa kusanthula nthawi kuti mukwaniritse ziwerengero zantchito.
Kufotokozera Kwantchito
Gawoli likufotokoza tsatanetsatane wa kukhazikitsidwa kwa Costas Loop.
Chithunzi chotsatira chikuwonetsa chojambula chamtundu wa Costas Loop.
Chithunzi 1-1. Chithunzi cha Block-Level cha Costas Loop
The latency pakati pa kulowetsa ndi kutulutsa kwa Costas pamwamba ndi 11 wotchi yozungulira. TheTA_OUT latency ndi 10 koloko
mikombero. Kp (proportionality constant), Ki (integral constant), Theta factor, ndi LIMIT factor ziyenera kukhazikitsidwa molingana ndi malo aphokoso komanso ma frequency omwe akuyambitsidwa. The Costas Loop imatenga nthawi kutseka, monga momwe amachitira PLL. Mapaketi ena atha kutayika panthawi yotseka koyambirira kwa Costas Loop.
Zomangamanga
Kukhazikitsa kwa Costas Loop kumafuna midadada inayi:
- Zosefera za Loop (PI Controller pakukhazikitsa uku)
- Theta jenereta
- Kuwerengera Zolakwika
- Kuzungulira kwa Vector
Chithunzi 1-2. Chithunzi cha Costas Loop Block
Cholakwika cha dongosolo linalake losinthira chimawerengedwa potengera ma I ndi Q mozungulira ma values pogwiritsa ntchito Vector Rotation Module. Woyang'anira PI amawerengera pafupipafupi kutengera cholakwika, kupindula kofananira ndi Kp, ndi phindu lofunikira Ki. Kuchuluka kwa ma frequency offset kumayikidwa ngati malire a PI controller's frequency output. Theta Generator module imapanga ngodya mwa kuphatikiza. Kulowetsa kwa theta factor kumatsimikizira kutsetsereka kwa kuphatikiza ndikutengera.
ku sampkoloko. Mbali yopangidwa kuchokera ku Theta Generator imagwiritsidwa ntchito pozungulira I ndi Q zolowetsa. Cholakwikacho ndi cha mtundu wa modulation. Pamene chowongolera cha PI chimakhazikitsidwa mumtundu wokhazikika, kukweza kumapangidwa pazotsatira zofananira komanso zofunikira za wowongolera PI.
Momwemonso, makulitsidwe akugwiritsidwa ntchito pakuphatikiza theta.
IP Core Parameters ndi Interface Signals
Gawoli likukambirana za magawo mu Costas Loop GUI configurator ndi zizindikiro za I / O.
Zokonda Zosintha
Gome lotsatirali likuwonetsa kufotokozera kwa magawo omwe amagwiritsidwa ntchito pokhazikitsa zida za Costas Loop. Izi ndi ma generic ma parameters amasiyanasiyana malinga ndi kufunikira kwa ntchito.
Gulu 2-1. Configuration Parameter
| Dzina la Signal | Kufotokozera |
| Mtundu Wosinthira | BPSK kapena QPSK |
Zolowetsa ndi Zotulutsa Zizindikiro
Gome lotsatirali likuwonetsa madoko olowera ndi kutulutsa a Costas Loop.
Gulu 2-2. Zolowetsa ndi Zotulutsa
| Dzina la Signal | Mayendedwe | Mtundu wa Signal | M'lifupi | Kufotokozera |
| CLK_I | Zolowetsa | — | 1 | Chizindikiro Clock |
| ARST_N_IN | Zolowetsa | — | 1 | Chizindikiro chokhazikika chokhazikika chokhazikika |
| I_DATA_IN | Zolowetsa | Sayinidwa | 16 | Mu gawo / Kuyika kwa data yeniyeni |
| Q_DATA_IN | Zolowetsa | Sayinidwa | 16 | Kuyika kwa Quadrature / Imaginary Data Input |
| KP_IN | Zolowetsa | Sayinidwa | 18 | Proportionality yosasintha ya PI controller |
| KI_IN | Zolowetsa | Sayinidwa | 18 | Integral constant ya PI controller |
| LIMIT_IN | Zolowetsa | Sayinidwa | 18 | Malire a PI controller |
| THETA_FACTOR_IN | Zolowetsa | Sayinidwa | 18 | Theta factor for theta integration. |
| I_DATA_OUT | Zotulutsa | Sayinidwa | 16 | Mu gawo / Real Data Output |
| Q_DATA_OUT | Zotulutsa | Sayinidwa | 16 | Kutulutsa kwa Quadrature / Imaginary Data |
| THETA_OUT | Zotulutsa | Sayinidwa | 10 | Chiwerengero cha Theta index (0-1023) kuti chitsimikizidwe |
| PI_OUT | Zotulutsa | Sayinidwa | 18 | PI zotsatira |
Zithunzi za Nthawi
Gawoli likukambirana za nthawi ya Costas Loop.
Chithunzi chotsatira chikuwonetsa chithunzi cha nthawi ya Costas Loop.
Chithunzi 3-1. Chithunzi cha Costas Loop Timing Time
Testbench
Testbench yogwirizana imagwiritsidwa ntchito kutsimikizira ndi kuyesa Costas Loop yotchedwa benchi yoyesera. Benchi yoyesera imaperekedwa kuti muwone momwe Costas Loop IP imagwirira ntchito.
Mizere Yoyeserera
Kuti muyesere pachimake pogwiritsa ntchito testbench, chitani izi:
- Tsegulani pulogalamu ya Libero SoC, dinani Catalog tabu, kulitsani Solutions-Wireless, dinani kawiri COSTAS LOOP, kenako dinani OK. Zolemba zogwirizana ndi IP zalembedwa pansi pa Documentations.
Zofunika: Ngati simukuwona tabu ya Catalog, pitani ku View > menyu ya Windows ndikudina Catalog kuti iwonekere.
Chithunzi 4-1. Costas Loop IP Core mu Libero SoC Catalog
- Konzani IP malinga ndi zomwe mukufuna.
Chithunzi 4-2. Configurator GUI
Limbikitsani zizindikiro zonse kuti zikhale zapamwamba ndikupanga mapangidwe - Pa tabu ya Stimulus Hierarchy, dinani Build Hierarchy.
Chithunzi 4-3. Mangani Hierarchy
- Pa Stimulus Hierarchy tabu, dinani kumanja testbench (Costas loop bevy), lozani kuti Mutsatire Mapangidwe Apano, kenako dinani Open Interactively.
Chithunzi 4-4. Kutengera Mapangidwe a Pre-Synthesis
ModelSim imatsegula ndi testbench file, monga momwe zasonyezedwera m’chithunzi chotsatirachi.
Chithunzi 4-5. Window yoyeserera ya ModelSim
Zofunika: Ngati kuyerekezera kusokonezedwa chifukwa cha malire a nthawi yothamanga omwe atchulidwa mu .do file, gwiritsani ntchito run -all command kuti mumalize kuyerekezera
Mbiri Yobwereza
Mbiri yokonzanso ikufotokoza zosintha zomwe zidakhazikitsidwa muzolemba. Zosinthazo zandandalikidwa ndi kubwereza, kuyambira ndi zofalitsa zamakono.
Gulu 5-1. Mbiri Yobwereza
| Kubwereza | Tsiku | Kufotokozera |
| A | 03/2023 | Kutulutsidwa koyamba |
Thandizo la Microchip FPGA
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Nambala ya gawo, sankhani gulu loyenera, ndikuyika mapangidwe files popanga chithandizo chaukadaulo.
Lumikizanani ndi Makasitomala kuti mupeze chithandizo chosagwiritsa ntchito mwaukadaulo, monga mitengo yazinthu, kukweza kwazinthu, zosintha
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Kuti mulembetse, pitani ku www.microchip.com/pcn ndikutsatira malangizo olembetsa.
Thandizo la Makasitomala
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- Ma Microchip amawakonda ndikuteteza mwamphamvu ufulu wake wazinthu zamaluso. Kuyesa kuphwanya malamulo otetezedwa ndi zinthu za Microchip ndikoletsedwa ndipo zitha kuphwanya Digital Millennium Copyright Act.
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Chidziwitso chazamalamulo
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Zolemba / Zothandizira
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MICROCHIP Costas Loop Management [pdf] Buku Logwiritsa Ntchito Costas Loop Management, Loop Management, Management |