Nā memo hoʻokuʻu IP ʻo Intel® FPGA i ka pahu leta
Nā memo hoʻokuʻu IP ʻo Intel® FPGA i ka pahu leta
Nā mana lako polokalamu Intel® Prime Design Suite a hiki i ka v19.1. E hoʻomaka ana ma Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP he polokalamu hoʻololi hou.
Hoʻohālikelike nā mana IP FPGA me ka Intel Quartus®
Hiki ke loli ka helu Intel FPGA IP (XYZ) me kēlā me kēia polokalamu polokalamu Intel Quartus Prime. He hoʻololi i:
- Hōʻike ʻo X i kahi hoʻoponopono nui o ka IP. Inā hōʻano hou ʻoe i ka polokalamu Intel Quartus Prime, pono ʻoe e hana hou i ka IP.
- Hōʻike ʻo Y i ka IP me nā hiʻohiʻona hou. E hana hou i kāu IP e hoʻokomo i kēia mau hiʻohiʻona hou.
- Hōʻike ʻo Z i ka IP me nā loli liʻiliʻi. E hana hou i kāu IP e hoʻokomo i kēia mau hoʻololi.
ʻIke pili
- Nā memo hoʻokuʻu hou ʻana o Intel Quartus Prime Design Suite
- Hoʻolauna i nā Intel FPGA IP Cores
- Pahu Leta Client Intel FPGA IP alakaʻi hoʻohana
- Errata no nā cores IP ʻē aʻe ma ka waihona ʻike
1.1. Mea kūʻai aku i ka pahu leta Intel FPGA IP v20.2.0
Papa 1. v20.2.0 2022.09.26
| Intel Quartus Puhi Puhi |
wehewehe | Ka hopena |
| 22.3 | Hoʻohui ʻia ke kākoʻo LibRSU me ka kaʻina hana Nios® V e hoʻohana me ka manakia mea paʻa (SDM). | — |
1.2. Mea kūʻai aku i ka pahu leta Intel FPGA IP v20.1.2
Papa 2. v20.1.2 2022.03.28
| Intel Quartus Puhi Puhi |
wehewehe | Ka hopena |
| 22. | Pane hou ʻia no ke kauoha CONFIG_STATUS e hoʻokomo i ka ʻike ma ke kumu o ka uaki hoʻonohonoho. | ʻAe ʻia ka hoʻonohonoho ʻana o FPGA me ka loaʻa ʻole o kahi tile refclk i ka manawa o ka hoʻonohonoho. |
| Hoʻonui i ka hoʻopaʻa inoa interrupt status (ISR) a me ka interrupt enable register (IER) e hoʻohui i ka pale no ke kauoha/pane a heluhelu/kākau i nā FIF0. | ||
| Wehe ʻia ke kauoha REBOOT_HPS no ka loaʻa ʻole o kēia kauoha no kēia IP. |
Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i ke kuleana a i ʻole ke kuleana e puka mai ana ma waho o ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe.
* Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
1.3. Mea kūʻai aku i ka pahu leta Intel FPGA IP v20.1.1
Papa 3. v20.1.1 2021.12.13
| Intel Quartus Puhi Puhi |
wehewehe | Ka hopena |
| 21.4 | • Hōʻano hou ʻia ka inoa hoʻohālikelike crypto service-specific mai HAS_OFFLOAD e ho'ā i ka lawelawe Crypto • Hoʻololi i ka hoʻokō safeclib memcpy me ka generic memcpy i ka mea hoʻokele HAL. |
— |
1.4. Mea kūʻai aku i ka pahu leta Intel FPGA IP v20.1.0
Papa 4. v20.1.0 2021.10.04
| Intel Quartus Puhi Puhi |
wehewehe | Ka hopena |
| 21.3 | Hoʻohui ʻia ka ʻāpana HAS_OFFLOAD e kākoʻo i ka cryptographic hoʻouka ʻana. Loaʻa kēia hiʻohiʻona no nā polokalamu Intel Agilex™ wale nō. |
Ke hoʻonohonoho ʻia, hiki i ka IP ke hiki i ka crypto AXI initiator interface. |
| Ua hoʻololi i ka helu ʻāpana memo mai RN-1201 a i RN-1259. |
— |
1.5. Mea kūʻai aku i ka pahu leta Intel FPGA IP v20.0.2
Papa 5. v20.0.2 2021.03.29
| ʻO Intel Quartus Prime Version | wehewehe | Ka hopena |
| 21. | Hoʻohui i ke kākoʻo e hoʻihoʻi hou i ka Timer 1 a me ka Timer 2 hoʻopaʻa inoa i ka wā o ka pahu leka uila Intel FPGA IP reset assertion. | ʻAʻohe hopena ma Timer 1 a me Timer 2 e hoʻopaʻa inoa i ka hoʻohana ʻana i ka polokalamu polokalamu Intel Quartus Prime mai 20.2 a me 20.4. Pono ʻoe e hana hou i ka Pahu Leta Client Intel FPGA IP i ka neʻe ʻana mai Intel ʻO ka polokalamu polokalamu Quartus Prime 20.4 a i ʻole ma mua i ka mana polokalamu polokalamu Intel Quartus Prime 21.1. |
| Hoʻohui ʻia ke kākoʻo e hiki ai i ka hiki ke hoʻopili ma waena o ka pahu leka uila Intel FPGA IP IRQ hōʻailona a me Nios II kaʻina hana IRQ hōʻailona. | Pono ʻoe e neʻe i ka polokalamu polokalamu Intel Quartus Prime version 21.1 a hoʻoulu hou i ka mea kūʻai aku pahu leka uila Intel FPGA IP e hiki ai i kēia hiʻohiʻona. |
1.6. Mea kūʻai aku i ka pahu leta Intel FPGA IP v20.0.0
Papa 6. v20.0.0 2020.04.13
| Intel Quartus Puhi Puhi |
wehewehe | Ka hopena |
| 20. | Hoʻohui ʻia ke kākoʻo no ka EOP_TIMEOUT interrupt e hōʻike ana ʻaʻole i hoʻokomo ʻia ke kauoha piha i ka End of Packet. | Hiki iā ʻoe ke hoʻohana i kēia mau interrupts no ka mālama ʻana i ka ʻike hewa no nā hana hoʻopau ʻole. |
| Kākoʻo hoʻohui ʻia no ka hoʻopau ʻana o BACKPRESSURE_TIMEOUT e hōʻike ana i ka hewa i loko o ka SDM. |
1.7. Mea kūʻai aku i ka pahu leta Intel FPGA IP v19.3
Papa 7. v19.3 2019.09.30
| Intel Quartus Puhi Puhi |
wehewehe | Ka hopena |
| 19. | Hoʻohui i ke kākoʻo hāmeʻa no nā polokalamu Intel Agilex. | Hiki iā ʻoe ke hoʻohana i kēia IP i nā polokalamu Intel Agilex. |
| Kākoʻo hoʻohui ʻia no kahi hoʻopau COMMAND_INVALID e hōʻike ana i ka lōʻihi o ke kauoha i kuhikuhi ʻia ʻaʻole i kūlike ke poʻo i ke kauoha maoli i hoʻouna ʻia. | Hiki iā ʻoe ke hoʻohana i kēia interrupt e ʻike i nā kauoha i kuhikuhi hewa ʻia. | |
| Ua hoʻololi i ka inoa o kēia IP mai Intel FPGA Stratix 10 Mailbox Client a i ka Mailbox Client Intel FPGA IP. | Kākoʻo kēia IP i nā polokalamu Intel Stratix® 10 a me Intel Agilex. E hoʻohana i ka inoa hou e ʻimi ai i kēia P ma ka polokalamu Intel Quartus Prime a i ʻole ma ka web. | |
| Hoʻohui hou ʻia ka ʻōnaehana mana IP. | Hiki ke loli ka helu IP mai kahi polokalamu polokalamu Intel Quartus Prime i kekahi. |
1.8. Intel FPGA Stratix 10 Mea kūʻai aku pahu leta v17.1
Papa 8. v17.1 2017.10.30
| Intel Quartus Puhi Puhi |
wehewehe | Ka hopena |
| 17. | Hoʻokuʻu mua. | — |
1.9. Pahu Leta Client Intel FPGA IP Mea Hoʻohana Alakaʻi Archives
No nā mana hou loa o kēia alakaʻi hoʻohana, e nānā i ka pahu leka uila Intel FPGA IP User Guide. Inā ʻaʻole i helu ʻia kahi IP a i ʻole ka mana lako polokalamu, pili ke alakaʻi mea hoʻohana no ka IP mua a i ʻole ka mana polokalamu.
Ua like nā mana IP me nā polokalamu polokalamu Intel Quartus Prime Design Suite a hiki i ka v19.1. Mai ka polokalamu polokalamu Intel Quartus Prime Design Suite 19.2 a i ʻole ma hope, loaʻa i nā cores IP kahi hoʻolālā hoʻololi IP hou.
Mea kūʻai aku i ka pahu leta Intel®
FPGA IP hoʻokuʻu memo
Hoʻouna Manaʻo
Palapala / Punawai
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intel pahu leta mea kūʻai Intel FPGA IP [pdf] Ke alakaʻi hoʻohana Mea kūʻai aku i ka pahu leta Intel FPGA IP, mea kūʻai aku Intel FPGA IP, Intel FPGA IP, FPGA IP, IP |