Abokin Akwatin Wasika Intel® FPGA Bayanan Sakin IP
Abokin Akwatin Wasika Intel® FPGA Bayanan Sakin IP
Sigar software na Intel® Prime Design Suite har zuwa v19.1. An fara a cikin sigar software ta Intel Quartus Prime Design Suite 19.2, Intel FPGA IP yana da sabon tsarin siga.
Siffofin IP na FPGA sun dace da Intel Quartus®
Lambar Intel FPGA IP (XYZ) na iya canzawa tare da kowace sigar software ta Intel Quartus Prime. Canji a:
- X yana nuna babban bita na IP. Idan kun sabunta Intel Quartus Prime software, dole ne ku sake haɓaka IP ɗin.
- Y yana nuna IP ɗin ya ƙunshi sabbin abubuwa. Sake haɓaka IP ɗin ku don haɗa waɗannan sabbin fasalolin.
- Z yana nuna IP ɗin ya ƙunshi ƙananan canje-canje. Sake haɓaka IP ɗin ku don haɗa waɗannan canje-canje.
Bayanai masu alaƙa
- Intel Quartus Prime Design Suite Sabunta Bayanan Bayanan Sakin
- Gabatarwa zuwa Intel FPGA IP Cores
- Abokin Akwatin Wasika na Intel FPGA IP Jagorar Mai Amfani
- Errata don sauran nau'ikan IP a cikin Tushen Ilimi
1.1. Abokin Akwatin Wasiku Intel FPGA IP v20.2.0
Table 1. v20.2.0 2022.09.26
| Intel Quartus Babban Sigar |
Bayani | Tasiri |
| 22.3 | Ƙara goyon bayan LibRSU tare da Nios® V processor don amfani tare da amintaccen manajan na'ura (SDM). | — |
1.2. Abokin Akwatin Wasiku Intel FPGA IP v20.1.2
Table 2. v20.1.2 2022.03.28
| Intel Quartus Babban Sigar |
Bayani | Tasiri |
| 22. | Amsa da aka sabunta don umarnin CONFIG_STATUS don haɗa bayanai kan tushen agogon sanyi. | Yana ba da damar daidaitawa na FPGA ba tare da refclk na tayal ba a lokacin daidaitawa. |
| Haɓaka rijistar matsayi na katse (ISR) da katse kunna rajista (IER) don ƙara kariya don umarni/amsa da karanta/ rubuta FIF0s. | ||
| An cire umarnin akwatin saƙo na REBOOT_HPS saboda babu wannan umarni ga wannan IP. |
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
1.3. Abokin Akwatin Wasiku Intel FPGA IP v20.1.1
Table 3. v20.1.1 2021.12.13
| Intel Quartus Babban Sigar |
Bayani | Tasiri |
| 21.4 | • Sunan sigar takamaiman sabis na crypto daga HAS_OFFLOAD don Kunna Sabis ɗin Crypto • Maye gurbin aiwatar da aikin memcpy na safeclib tare da gama gari memcpy in HAL direba. |
— |
1.4. Abokin Akwatin Wasiku Intel FPGA IP v20.1.0
Table 4. v20.1.0 2021.10.04
| Intel Quartus Babban Sigar |
Bayani | Tasiri |
| 21.3 | Ƙara sigar HAS_OFFLOAD don tallafawa rubutun kalmomi saukewa. Wannan fasalin yana samuwa ne kawai don na'urorin Intel Agilex™. |
Lokacin da aka saita, IP ɗin yana kunna crypto AXI initiator interface. |
| Canza lambar sashin Bayanan Bayanan Saki daga RN-1201 zuwa Saukewa: RN-1259. |
— |
1.5. Abokin Akwatin Wasiku Intel FPGA IP v20.0.2
Table 5. v20.0.2 2021.03.29
| Intel Quartus Prime Version | Bayani | Tasiri |
| 21. | Ƙara goyon baya don sake saita Mai ƙidayar lokaci 1 da Mai ƙidayar lokaci 2 yin rijistar jinkiri yayin taron na abokin ciniki na Akwatin Wasiƙa na Intel FPGA IP sake saiti. | Babu wani tasiri a cikin Timer 1 da Timer 2 suna yin rijistar amfani a cikin Intel Quartus Prime sigar software daga 20.2 da 20.4. Dole ne ku sake haifar da Abokin Akwatin Wasika Intel FPGA IP lokacin motsi daga Intel Sigar software ta Quartus Prime 20.4 ko baya zuwa Intel Quartus Prime software version 21.1. |
| Ƙara goyon baya don ba da damar haɗin kai tsakanin Abokin Akwatin Wasiƙa Intel FPGA IP IRQ siginar da siginar Nios II processor IRQ. | Dole ne ku yi ƙaura zuwa Intel Quartus Prime software version 21.1 kuma ku sake haɓaka Abokin Wasiƙa na Intel FPGA IP don kunna wannan fasalin. |
1.6. Abokin Akwatin Wasiku Intel FPGA IP v20.0.0
Table 6. v20.0.0 2020.04.13
| Intel Quartus Babban Sigar |
Bayani | Tasiri |
| 20. | Ƙara tallafi don katsewar EOP_TIMEOUT wanda ke nuna cewa cikakken umarnin bai haɗa da Ƙarshen Fakitin ba. | Kuna iya amfani da waɗannan katsewar don sarrafa gano kuskure don ma'amaloli da ba su cika ba. |
| Ƙarin tallafi don katsewar BACKPRESSURE_TIMEOUT wanda ke nuna cewa an sami kuskure a cikin SDM. |
1.7. Abokin Akwatin Wasiku Intel FPGA IP v19.3
Table 7. v19.3 2019.09.30
| Intel Quartus Babban Sigar |
Bayani | Tasiri |
| 19. | Ƙara tallafin na'ura don na'urorin Intel Agilex. | Yanzu zaku iya amfani da wannan IP a cikin na'urorin Intel Agilex. |
| Ƙara tallafi don katsewar COMMAND_INVALID wanda ke nuna tsayin umarni da aka kayyade kan taken bai dace da ainihin umarnin da aka aiko ba. | Kuna iya amfani da wannan katsewa don gano takamaiman takamaiman umarni ba daidai ba. | |
| Canza sunan wannan IP daga Intel FPGA Stratix 10 Abokin Akwatin Wasika zuwa Abokin Wasika na Intel FPGA IP. | Wannan IP yanzu yana goyan bayan Intel Stratix® 10 da na'urorin Intel Agilex. Yi amfani da sabon suna don nemo wannan P a cikin Intel Quartus Prime software ko a kan web. | |
| An ƙara sabon tsarin sigar IP. | Lambar sigar IP na iya canzawa daga sigar software ta Intel Quartus Prime zuwa wani. |
1.8. Intel FPGA Stratix 10 Abokin Akwatin Wasiku 17.1
Table 8. v17.1 2017.10.30
| Intel Quartus Babban Sigar |
Bayani | Tasiri |
| 17. | Sakin farko. | — |
1.9. Abokin Akwatin Wasiƙa Intel FPGA Rukunin Jagorar Mai Amfani IP
Don sababbin sifofin wannan jagorar mai amfani da na baya da kuma na baya, koma zuwa Abokin ciniki na Akwatin Wasiƙa na Intel FPGA IP Jagorar Mai amfani. Idan ba a jera sigar IP ko software ba, jagorar mai amfani na IP ɗin da ta gabata ko sigar software ta shafi.
Sifofin IP iri ɗaya ne da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. Daga Intel Quartus Prime Design Suite software version 19.2 ko kuma daga baya, IP cores suna da sabon tsarin sigar IP.
Akwatin saƙon Abokin ciniki Intel®
Bayanan Bayanin Sakin IP na FPGA
Aika da martani
Takardu / Albarkatu
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Intel Akwatin Saƙonni Abokin ciniki Intel FPGA IP [pdf] Jagorar mai amfani Abokin Akwatin Wasika Intel FPGA IP, Abokin ciniki Intel FPGA IP, Intel FPGA IP, FPGA IP, IP |