Intel FPGA SDK ea OpenCL User Guide

FPGA SDK bakeng sa OpenCL
Bukana ea Mosebelisi

UG-OCL009
2017.05.08
E qetetse ho ntlafatsoa bakeng sa Intel® Quartus® Prime Design Suite: 17.0

Ngodisa
Romella Maikutlo

Litaba pata

1 Intel® FPGA SDK bakeng sa OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Porting Guide

2 Litokomane / Lisebelisoa

2.1 Litšupiso

3 Related Posts

Intel® FPGA SDK bakeng sa OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Porting Guide

V SoC Development Kit Reference Porting Guide e hlalosa sebopeho sa hardware le software ea Intel Cyclone V SoC Development Kit Reference Platform (c5soc) bakeng sa tšebeliso le Intel Software Development Kit (SDK) bakeng sa OpenCL The Intel ® FPGA SDK bakeng sa OpenCL ™ Intel Cyclone. ® . Pele o qala, Intel e khothaletsa ka matla hore u itloaetse litaba tsa litokomane tse latelang:

Intel FPGA SDK bakeng sa OpenCIntel Cyclone V SoC Tataiso ea ho Qala

Intel FPGA SDK bakeng sa Tataiso ea Mosebelisi ea OpenCL Custom Platform Toolkit
Cyclone V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual Ho phaella moo, bua ka Cyclone V SoC Development Kit le SoC Embedded Design Suite leqepheng la Altera. website bakeng sa tlhahisoleseding e eketsehileng. 1 2

Tlhokomeliso: Intel e nka hore o na le kutloisiso e tebileng ea Intel FPGA SDK bakeng sa Tataiso ea Mosebelisi ea OpenCL Custom Platform Toolkit. Tataiso ea Leholiotsoana la V SoC Development Kit Reference Porting ha e hlalose tšebeliso ea SDK's Custom Custom Platform Toolkit ho kenya tšebetsong Platform Custom for Cyclone V SoC Development Kit. E hlalosa feela phapang pakeng tsa tšehetso ea SDK ho Leholiotsoana la V SoC Development Kit le Intel FPGA SDK ea generic bakeng sa OpenCL Custom Platform.

Related Links

Intel FPGA SDK bakeng sa OpenCL Cyclone V SoC Tataiso ea ho Qala
Intel FPGA SDK bakeng sa Tataiso ea Mosebelisi ea OpenCL Custom Platform Toolkit

Cyclone V Device Handbook, Volume 3: Hard processor System Technical Reference Manual
Cyclone V SoC Development Kit le leqephe la SoC Embedded Design Suite ho Altera websebaka

OpenCL le logo ya OpenCL ke matshwao a kgwebo Apple Inc. a sebediswang ka tumello ya Khronos Group™.
Intel FPGA SDK bakeng sa OpenCL e ipapisitse le Tlhaloso ea Khronos e phatlalalitsoeng, 'me e fetile Ts'ebetso ea Teko ea Khronos Conformance. Boemo ba hona joale ba ho lumellana bo ka fumanoa ho www.khronos.org/conformance.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus le Stratix mantsoe le li-logo ke matšoao a khoebo a Intel Corporation kapa litšehetso tsa eona tsa US le/kapa linaheng tse ling. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

1.1.1 Liphetoho tsa Boto ea Leholiotsoana la V SoC Development Kit Reference
Intel FPGA SDK bakeng sa OpenCL Cyclone V SoC Development Kit Reference Platform e kenyelletsa mefuta e 'meli ea boto.

c5soc board
Boto ena ea kamehla e fana ka phihlello ea libanka tse peli tsa memori tsa DDR. HPS DDR e fumaneha ka bobeli ke FPGA le CPU. FPGA DDR e fumaneha feela ke FPGA.
c5soc_sharedonly board
Phapang ena ea boto e na le khokahano ea HPS DDR feela. FPGA DDR ha e fumanehe. Phapang ena ea boto e sebetsa hantle haholo hobane lisebelisoa tse nyane lia hlokahala ho ts'ehetsa banka e le 'ngoe ea memori ea DDR. Boto ea c5soc_sharedonly hape ke sethala se setle sa prototyping bakeng sa boto ea ho qetela ea tlhahiso e nang le banka e le 'ngoe ea memori ea DDR.
Ho shebisa mofuta ona oa boto ha o hlophisa kernel ea hau ea OpenCL, kenyelletsa khetho ea -board c5soc_sharedonly ho taelo ea hau ea aoc.
Ho fumana lintlha tse ling ho -board khetho ea taelo ea aoc, sheba Intel FPGA SDK bakeng sa OpenCL Programming Guide.

Related Links
Ho bokella Kernel bakeng sa Boto e Khethehileng ea FPGA (-board )
1.1.2 Likahare tsa Leholiotsoana V SoC Development Kit Reference Platform
The Cyclone V SoC Development Kit Reference Platform e na le tse latelang files le li-directory:

File kapa Directory	Tlhaloso
board_env.xml	Puo ea eXtensible Markup (XML) file e hlalosang c5soc ho Intel FPGA SDK bakeng sa OpenCL.
linux_sd_card_image.tgz	Setšoantšo sa karete ea flash ea SD e hatisitsoeng file e nang le tsohle tseo mosebelisi oa SDK a li hlokang ho sebelisa Cyclone V SoC Development Kit ka SDK.
arm32	Directory e nang le tse latelang:

1.1.3 Likarolo tse Amanang tsa Leholiotsoana V SoC Development Kit

Lethathamo le latelang le totobatsa likarolo tsa Leholiotsoana la V SoC Development Kit le likarolo tse amanang le Intel FPGA SDK bakeng sa OpenCL:

Dual-core ARM Cortex-A9 CPU e sebelisang 32-bit Linux.

Bese e tsoetseng pele ea eXtensible Interface (AXI) lipakeng tsa HPS le lesela la mantlha la FPGA.
Li-control tse peli tse thata tsa DDR, e 'ngoe le e' ngoe e hokahana le 1 gigabyte (GB) DDR3 SDRAM.
- Taolo e le 'ngoe ea DDR e fumaneha ho mantlha ea FPGA feela (ke hore, FPGA DDR).
- Taolo e 'ngoe ea DDR e fumaneha ho HPS le FPGA (ke hore, HPS DDR). Taolo ena e arolelanoang e lumella ho arolelana mohopolo oa mahala pakeng tsa CPU le FPGA ea mantlha.

CPU e ka lokisa lesela la mantlha la FPGA.

1.1.3.1 Leholiotsoana V SoC Development Kit Reference Platform Lipakane le Liqeto Intel e thehile ts'ebetsong ea Leholiotsoana la V SoC Development Kit Reference Platform mabapi le lipheo le liqeto tse 'maloa tsa moralo. Intel e khothaletsa hore u nahane ka lipheo le liqeto tsena ha u kenya Sethala sa Reference ho boto ea hau ea SoC FPGA.
Ka tlase ke lipheo tsa moralo oa c5soc:

Fana ka bophahamo bo phahameng ka ho fetesisa bo ka khonehang lipakeng tsa lithapo ho FPGA le sistimi ea memori ea DDR.
Netefatsa hore likhomphutha tse ho FPGA (ke hore, li-kernels tsa OpenCL) ha li kena-kenane le mesebetsi e meng ea CPU e ka kenyelletsang ho fana ka lisebelisoa.

Tlohela lisebelisoa tse ngata tsa FPGA kamoo ho ka khonehang bakeng sa likhomphutha tsa kernel ho fapana le likarolo tsa sebopeho.

Ka tlase ke liqeto tsa moralo oa maemo a holimo tseo e leng litlamorao tse tobileng tsa merero ea moralo oa Intel:

Reference Platform e sebelisa feela li-control tsa memori tse thata tsa DDR tse nang le tlhophiso e kholo ka ho fetesisa (256 bits).
FPGA e buisana le molaoli oa memori oa HPS DDR ka kotloloho, ntle le ho kenyelletsa bese ea AXI le switch ea L3 kahare ho HPS. Puisano e tobileng e fana ka bandwidth e ntle ka ho fetisisa ho DDR, 'me e boloka likhomphutha tsa FPGA hore li se ke tsa kena-kenana le lipuisano lipakeng tsa CPU le periphery ea eona.
Ho fihlella memori e otlolohileng ea Scatter-gather (SG-DMA) ha se karolo ea logic ea FPGA interface. Sebakeng sa ho fetisetsa lintlha tse ngata lipakeng tsa li-memory system tsa DDR, boloka data ho HPS DDR e arolelanoang. Ho fihlella ka kotloloho mohopolong oa CPU ka FPGA ho sebetsa hantle ho feta DMA. E boloka lisebelisoa tsa lisebelisoa (ke hore, sebaka sa FPGA) mme e nolofatsa mokhanni oa kernel oa Linux.
Tlhokomeliso: Phetisetso ea mohopolo lipakeng tsa sistimi e arolelanoang ea HPS DDR le sistimi ea DDR e fumanehang feela ho FPGA e lieha haholo. Haeba u khetha ho
fetisetsa memori ka tsela ena, e sebelisetse data e nyane haholo feela.
Moamoheli le sesebelisoa ba etsa phetiso ea data e seng ea DMA lipakeng tsa borokho ba HPS-to-FPGA (H2F), ba sebelisa boema-kepe bo le bong feela ba 32-bit. Lebaka ke hore, ntle le DMA, Linux kernel e ka fana ka kopo e le 'ngoe feela ea ho bala kapa ho ngola ea 32-bit, kahoo ha ho hlokahale ho ba le khokahanyo e pharaletseng.
Moamoheli o romela matšoao a taolo ho sesebelisoa ka borokho bo bobebe ba H2F (LH2F).
Hobane mats'oao a taolo ho tloha ho moamoheli ho ea sesebelisoa ke matšoao a tlase-bandwidth, borokho ba LH2F bo loketse mosebetsi.

1.2 Ho tsamaisa Sethala sa Litšupiso ho Boto ea hau ea SoC FPGA
Ho kenya Leholiotsoana la V SoC Development Kit Reference Platform ho boto ea hau ea SoC FPGA, etsa mesebetsi e latelang:

Khetha memori e le 'ngoe ea DDR kapa mefuta e 'meli ea mehopolo ea DDR ea c5soc Reference Platform e le qalo ea moralo oa hau.
Ntlafatsa libaka tsa phini ho ALTERAOCLSDKROOT/board/c5soc/ /top.qsf file, moo ALTERAOCLSDKROOT e leng tsela e eang sebakeng sa Intel FPGA SDK bakeng sa ho kenya OpenCL, le ke lebitso la directory la boto e fapaneng. Sengoloa sa c5soc_sharedonly ke sa mofuta oa boto e nang le sistimi e le 'ngoe ea memori ea DDR. Bukana ea c5soc ke ea boto e fapaneng e nang le mekhoa e 'meli ea memori ea DDR.
Ntlafatsa litlhophiso tsa DDR bakeng sa li-block tsa HPS le/kapa FPGA SDRAM ho ALTERAOCLSDKROOT/board/c5soc/ /system.qsys file.
4. Intel FPGA SDK eohle bakeng sa meralo ea boto e ratoang ea OpenCL e tlameha ho fihlela ho koaloa nako ho netefalitsoeng. Ka hona, sebaka sa moralo se tlameha ho ba se hloekileng ka nako. Ho kenya karolo ea boto ea c5soc (acl_iface_partition.qxp) ho boto ea hau ea SoC FPGA, etsa mesebetsi e latelang:
Bakeng sa litaelo tse qaqileng mabapi le ho fetola le ho boloka karohano ea boto, sheba Quartus
Kopano e Khōlō e Khōlō bakeng sa Khaolo ea Moqapi oa Hierarchical le Sehlopha sa Sehlopha sa Quartus Prime Standard Edition Handbook.
a. Tlosa acl_iface_partition.qxp ho tloha ho ALTERAOCLSDKROOT/board/c5soc/c5soc directory.
b. Numella sebaka sa acl_iface_region LogicLock™ ka ho fetola taelo ea Tcl set_global_assignment -name LL_ENABLED OFF -section_id acl_iface_region to set_global_assignment -name LL_ENABLED ON -section_id acl_iface_region
c. Bokella kernel ea OpenCL bakeng sa boto ea hau.
d. Haeba ho hlokahala, fetola boholo le sebaka sa sebaka sa LogicLock.
e. Ha u khotsofetse hore sebaka sa moralo oa hau se hloekile ka nako, romella karohano eo joalo ka acl_iface_partition.qxp Quartus Prime Exported Partition File.
Joalo ka ha ho hlalositsoe karolong ea Thestablishing Guaranteed Time Flow ea AIntel FPGA SDK bakeng sa OpenCL Custom Platform Toolkit User Guide, ka ho tlisa sena .qxp file moralong oa boemo bo holimo, o phethahatsa tlhoko ea ho fana ka moralo oa boto o nang le ts'ebetso e tiisitsoeng ea ho koala nako.
Bakeng sa lintlha tse ka amang boleng ba liphetho (QoR) tsa karohano ea hau e romelloang kantle ho naha, sheba Boleng bo Akaretsang ba Liphetho bakeng sa Karolo ea Karohano ea Boto e Ntle ho Intel FPGA SDK bakeng sa Bukana ea Mosebelisi ea OpenCL Custom Platform Toolkit.
f. Thibela sebaka sa acl_iface_region LogicLock ka ho khutlisetsa taelo ho Mohato 2 ho khutlela ho set_global_assignment -name LL_ENABLED OFF section_id acl_iface_region.
Haeba boto ea hau ea SoC FPGA e sebelisa lithakhisa le likarolo tse fapaneng tsa block ea HPS, nchafatsa preloader le mohloli oa sefate sa sesebelisoa (DTS) file. Haeba o fetola li-setting tsa "memory controller" tsa HPS DDR, nchafatsa preloader.
Theha setšoantšo sa karete ea flash ea SD.
Theha Platform ea hau ea Custom, e kenyelletsang setšoantšo sa karete ea SD flash.
Nahana ka ho theha mofuta oa nako ea ho sebetsa oa Platform ea hau ea Tloaelo hore e sebelisoe le Intel FPGA Runtime Environment (RTE) bakeng sa OpenCL. Mofuta oa RTE oa Custom Platform ha o kenyelle likhoele tsa hardware le setšoantšo sa karete ea flash ea SD. Sethala sena sa Tloaelo se jara sistimi ea SoC FPGA ho lumella lits'ebetso tsa moamoheli ho sebetsa. Ka lehlakoreng le leng, mofuta oa SDK oa Custom Platform oa hlokahala hore SDK e bokelle lithollo tsa OpenCL.
Keletso: U ka sebelisa mofuta oa SDK oa Platform ea hau e Tloaelehileng bakeng sa RTE. Ho boloka
sebaka, tlosa setšoantšo sa karete ea flash ea SD ho mofuta oa RTE oa Platform ea hau e Tloaelehileng.
Lekola Sethala sa hau sa Tloaelo.
Sheba karolo ea Teko ea Hardware Design ea Intel FPGA SDK bakeng sa Tataiso ea Mosebelisi ea OpenCL Custom Platform Toolkit bakeng sa tlhaiso-leseling e batsi.

Related Links

Ho Lekola Moqapi oa Hardware
Quartus Prime Incremental Compiment bakeng sa Moralo oa Hierarchical le oa Sehlopha

Ho Theha Phallo e Tiisitsoeng ea Nako
Kakaretso ea Boleng ba Liphetho bakeng sa Karohano ea Boto e Rekiselitsoeng

1.2.1 Ho Nchafatsa Sethala sa Litšupiso sa Ported
Phetolelong ea hajoale ea Cyclone V SoC Development Kit Reference Platform, block ea HPS e ka har'a karohano e hlalosang mabaka ohle a nonkernel. Leha ho le joalo, u ke ke ua romela HPS e le karolo ea .qxp file. Ho nchafatsa Sethala sa Tloaelo se seng se ntse se le teng seo u se lokisitseng ho tsoa mofuteng o fetileng oa c5soc, kenya ts'ebetsong mokhoa oa ho boloka QXP, ntlafatsa setšoantšo sa karete ea flash ea SD ho fumana boemo ba morao-rao ba nako ea ho sebetsa, 'me u ntlafatse board_spec.xml file ho etsa hore ho khonehe ho tsamaea.
Altera® SDK ea OpenCL mofuta oa 14.1 le ho feta e fuputsa board_spec.xml file bakeng sa tlhaiso-leseling ea boto, le ho kenya lisebelisoa tsa othomathike. Hobane u fetola
moralo ka ho kenya tšebetsong phallo ea poloko ea QXP, o tlameha ho nchafatsa board_spec.xml file ho sebopeho sa eona ho mofuta oa hajoale. Ho nchafatsa file e lumella SDK hore e khetholle lipakeng tsa Li-Platform tsa Tloaelo tse sa bolokoang le li-Platform tsa QXP tse thehiloeng hona joale. Sheba ho Custom Platform Automigration for Forward Compatibility ho Intel FPGA SDK bakeng sa OpenCL Custom Platform Toolkit User Guide bakeng sa boitsebiso bo eketsehileng.

Ho kenya ts'ebetsong phallo ea poloko ea QXP ho moralo oa Hardware oa Cyclone V SoC FPGA o nkiloeng ho tsoa mofuteng o fetileng oa c5soc, etsa mehato e latelang ho theha karoloana ho qhelela HPS ho tsoa ho .qxp file:
a. Pele o theha karohano ho potoloha mohopolo oa nonkernel, theha karohano ho potoloha HPS ho .qsf Quartus Prime Settings File.
Bakeng sa mohlalaampLe:
# Arola ka letsoho mohlala o fanang ka mohlala oa HPS-inehelo ea I/O set_instance_assignment -name PARTITION_HIERARCHY borde_18261 -ho "system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps_0:hps_0|system_psh_acl_i0|pshs_iface_0: system_acl_iface_hps_0_hps_io_border:border” -section_id “system_acl_iface_hps_XNUMX_hps_io_border:border”
# Beha karohano hore e be mofuta oa HPS_PARTITION e lokelang ho sebetsoa ka nepo ke Quartus kaofela
set_global_assignment -name PARTITION_TYPE HPS_PARTITION -section_id “system_acl_iface_hps_0_hps_io_border:border”
quartus_cdb holimo -c holimo
–incremental_compilation_export=acl_iface_partition.qxp
-incremental_compilation_export_partition_name=acl_iface_partition
–keketso_phutheho_export_post_synth=on
–keketso_phutheho_export_post_fit=on
–keketso_phutheho_export_routing=ho
–keketso_phutheho_export_flatten=theoha
Kamora hore o qhelele HPS karohanong, o ka reka kantle ho naha .qxp file 'me u hlophise moralo oa hau.
Ntlafatsa setšoantšo sa karete ea flash ea SD ka mofuta oa hajoale oa Intel FPGA RTE bakeng sa OpenCL ka ho etsa mesebetsi e latelang:
a. Thaba ea file tafole ea kabo (fat32) le ho atolosoa file tsamaiso (ext3) partitions setšoantšong se teng e le lisebelisoa tsa loop-back. Bakeng sa litaelo tse felletseng, sheba Mohato oa 2 oa ho Aha Setšoantšo sa Karete ea Flash ea SD.
b. Bukeng ea /home/root/opencl_arm32_rte, tlosa faele files ho tsoa mofuteng o fetileng oa RTE.
c. Khoasolla le ho notlolla mofuta oa hajoale oa RTE bukeng ea /home/root/opencl_arm32_rte.
d. Ho /mokhanni/version.h file Sebakeng sa hau sa Tloaelo, ntlafatsa mosebetsi oa ACL_DRIVER_VERSION ho . (mohlalaample, 16.1.x, moo 16.1 e leng verison ea SDK, 'me x ke mofuta oa mokhanni oo o o behileng).
e. Aha mokhanni bocha.
f. Hlakola foldara (li)hardware ea Platform ea hau e Tloaelehileng. Kopitsa Sethala sa Tloaelo, hammoho le mokhanni ea ntlafalitsoeng, ho /home/root/opencl_arm_rte/board directory.
g. Kopitsa Altera.icd file ho tsoa ho /home/root/opencl_arm32_rte directory ebe u e eketsa ho /etc/OpenCL/vendorrs directory.
h. Theola 'me u leke setšoantšo se secha. Bakeng sa litaelo tse felletseng, sheba Mehato ea 8 ho isa ho ea 11 ea ho Aha Setšoantšo sa Karete ea Flash ea SD.

Related Links

Ho theha setšoantšo sa SD Flash Card leqepheng la 14
U boetse u na le khetho ea ho theha setšoantšo se secha sa karete ea flash ea SD.
Phatlalatso e Ikemetseng ea Platform bakeng sa Tšebelisano Pele

1.3 Tšehetso ea Software bakeng sa Memori e Abelanoeng
Mehopolo ea 'mele e arolelanoeng lipakeng tsa FPGA le CPU ke memori e ratoang bakeng sa li-kernel tsa OpenCL tse sebetsang ho SoC FPGAs. Hobane FPGA e fihlella mohopolo o arolelanoang oa 'mele, ho fapana le mohopolo o arolelanoang, ha e na monyetla oa ho fumana litafole tsa leqephe la CPU tse bonts'ang liaterese tsa basebelisi ho liaterese tsa maqephe.
Mabapi le lisebelisoa tsa marang-rang, li-kernels tsa OpenCL li fihlella mohopolo o arolelanoang oa 'mele ka ho hokahana ka kotloloho le taolo e thata ea memori ea HPS DDR. Mabapi le software, tšehetso bakeng sa mohopolo o arolelanoang oa 'mele o kenyelletsa lintlha tse latelang:

Ts'ebetso e tloaelehileng ea software bakeng sa ho aba memori ho CPU (bakeng sa mohlalaample, malloc() function) e ke ke ea fana ka sebaka sa memori seo FPGA e ka se sebelisang.
Mehopolo eo mosebetsi oa malloc () e fanang ka eona e amana haufi le sebaka sa aterese ea memori, empa maqephe leha e le afe a ka tlas'a 'mele ha a na monyetla oa hore a kopane 'meleng. Ka hona, moamoheli o tlameha ho khona ho fana ka libaka tsa mohopolo tse amanang le 'mele. Leha ho le joalo, bokhoni bona ha bo teng lits'ebetsong tsa sebaka sa basebelisi ho Linux. Ka hona, mokhanni oa Linux kernel o tlameha ho etsa kabo.
Mokhanni oa kernel oa OpenCL SoC FPGA Linux o kenyelletsa mosebetsi oa mmap () ho abela mohopolo o arolelanoang oa 'mele le ho o beha sebakeng sa mosebelisi. Mosebetsi oa mmap() o sebelisa mohala o tloaelehileng oa Linux kernel dma_alloc_coherent() ho kopa libaka tsa mohopolo tse amanang le 'mele bakeng sa ho arolelana le sesebelisoa.
Ho kernel ea kamehla ea Linux, dma_alloc_coherent() ha e fane ka mohopolo o amanang le 'mele ho feta 0.5 megabytes (MB) ka boholo. Ho lumella dma_alloc_coherent() ho fana ka mohopolo o mongata o amanang le 'mele, etsa hore karolo ea contiguous memory allocator (CMA) ea kernel ea Linux ebe o khutlisetsa kernel ea Linux.
Bakeng sa Cyclone V SoC Development Kit Reference Platform, CMA e laola 512 MB ho tsoa ho 1 GB ea mohopolo oa 'mele. O ka eketsa kapa oa fokotsa boleng bona, ho latela boholo ba memori e arolelanoang eo sesebelisoa se e hlokang. Mohala oa dma_alloc_coherent() o kanna oa se khone ho fana ka 512 MB e felletseng ea mohopolo o amanang le 'mele; Leha ho le joalo, ka tloaelo e ka fumana memori ea 450 MB.

CPU e ka boloka memori eo dma_alloc_coherent() call e fanang ka eona. Haholo-holo, ts'ebetso ea ho ngola ho tsoa ho sesebelisoa sa moamoheli ha e bonahale ho li-kernels tsa OpenCL. Mosebetsi oa mmap() ho OpenCL SoC FPGA Linux kernel driver e boetse e na le mehala e eang ho pgprot_noncached() kapa remap_pf_range() ts'ebetso ea ho tima caching sebakeng sena sa mohopolo ka ho hlaka.
Ka mor'a hore ts'ebetso ea dma_alloc_coherent() e fane ka mohopolo o amanang le 'mele, mmap() mosebetsi o khutlisetsa aterese ea sebele qalong ea moeli, e leng sebaka sa aterese ea memori eo u e abetseng. Sesebelisoa sa moamoheli se hloka aterese ena ea sebele ho fihlella memori. Ka lehlakoreng le leng, li-kernels tsa OpenCL li hloka liaterese tsa 'mele. Mokhanni oa Linux kernel o boloka tlaleho ea 'mapa oa aterese ea sebele-to-physical. U ka etsa 'mapa oa liaterese tsa tlhaho tseo mmap() e khutlelang ho liaterese tsa sebele ka ho kenya potso ho mokhanni.
Mohala oa aocl_mmd_shared_mem_alloc() MMD application programming interface (API) o kenyelletsa lipotso tse latelang:
a. Mosebetsi oa mmap() o abelang memori le ho khutlisa aterese ea sebele.
b. Potso e 'ngoe e bonts'ang aterese ea sebele e khutlisitsoeng sebakeng sa sebaka.
The aocl_mmd_shared_mem_alloc() MMD API call ebe e khutlisa liaterese tse peli
-aterese ea sebele e khutlisitsoeng ke aterese ea sebele, 'me aterese ea sebele e ea ho device_ptr_out.
Hlokomela: Mokhanni a ka etsa 'mapa feela oa liaterese tsa sebele tseo mosebetsi oa mmap() o li khutlisetsang ho liaterese tsa sebaka. Haeba o kopa aterese ea 'mele ea pointer efe kapa efe, mokhanni o khutlisa boleng ba NULL.

Tlhokomeliso: Intel FPGA SDK bakeng sa lilaebrari tsa nako ea OpenCL e nka hore memori e arolelanoang ke memori ea pele e thathamisitsoeng ho board_spec.xml file. Ka mantsoe a mang, aterese ea 'mele eo mokhanni oa Linux kernel a e fumanang e fetoha aterese ea Avalon® eo kernel ea OpenCL e e fetisetsang ho HPS SDRAM.
Mabapi le laeborari ea nako ea ho sebetsa, sebelisa mohala oa clCreateBuffer() ho abela memori e arolelanoang joalo ka buffer ea sesebelisoa ka tsela e latelang:

Bakeng sa boto ea li-DDR tse peli tse nang le memori e arolelanoang le e sa arolelanoeng, clCreateBuffer() e fana ka mohopolo o arolelanoang haeba u hlakisa folakha ea CL_MEM_USE_HOST_PTR. Ho sebelisa lifolakha tse ling ho etsa hore clCreateBuffer() e fane ka buffer mohopolong o sa arolelanoeng.
Bakeng sa boto e le 'ngoe ea DDR e nang le mohopolo o arolelanoang feela, clCreateBuffer() e fana ka mohopolo o arolelanoang ho sa tsotelehe hore na u bolela folakha efe.
Hajoale, tšehetso ea 32-bit Linux ho ARM CPU e laola boholo ba ts'ehetso ea memori e arolelanoang lilaebraring tsa nako ea SDK. Ka mantsoe a mang, lilaebrari tsa nako ea ho sebetsa li hlophisitsoe libakeng tse ling (mohlalaample, x86_64 Linux kapa 64-bit Windows) ha li tšehetse mohopolo o arolelanoang.
C5soc ha ea ka ea sebelisa mohopolo o fapaneng ho khetholla pakeng tsa mohopolo o arolelanoang le o sa arolelanoeng ka mabaka a latelang:
1. Nalane - Tšehetso ea memori e fapaneng e ne e sa fumanehe ha tšehetso ea memori e arolelanoang e ne e theoa qalong.
2. Khokahano e tšoanang—Hobane OpenCL ke tekanyetso e bulehileng, Intel e boloka botsitso pakeng tsa barekisi ba sethala sa khomphutha ba mefuta-futa. Ka hona, sebopeho se ts'oanang le meaho e meng ea barekisi ba boto se sebelisetsoa ho aba le ho sebelisa mohopolo o arolelanoang.

1.4 FPGA Reconfiguration
Bakeng sa SoC FPGAs, CPU e ka lokisa lesela la mantlha la FPGA ntle le ho sitisa ts'ebetso ea CPU. FPGA Manager block block e tsamaisang HPS le FPGA ea mantlha e etsa tlhophiso bocha. Linux kernel e kenyelletsa mokhanni ea nolofalletsang ho fihlella habonolo ho Motsamaisi oa FPGA.

Ho view boemo ba mantlha ba FPGA, kopa taelo ea katse /sys/class/fpga/fpga0/.
Intel FPGA SDK bakeng sa ts'ebeliso ea lenaneo la OpenCL e fumanehang ka Cyclone V SoC Development Kit Reference Platform e sebelisa sebopeho sena ho hlophisa FPGA. Ha o hlophisa bocha FPGA ea mantlha ka CPU e sebetsang, sesebelisoa sa lenaneo se etsa mesebetsi eohle e latelang:
1. Pele o hlophisa bocha, tima marokho ohle a puisano lipakeng tsa FPGA le HPS, e leng marokho a H2F le LH2F.
Lumella marokho ana hape ka mor'a hore reprogramming e phethe.
Tlhokomeliso: Sistimi ea OpenCL ha e sebelise borokho ba FPGA-to-HPS (F2H). Sheba karolo ea HPS-FPGA Interfaces ho Leholiotsoana V Device Handbook, Volume 3: Hard processor System Technical Reference Manual bakeng sa boitsebiso bo eketsehileng.
2. Netefatsa hore sehokelo pakeng tsa FPGA le molaoli oa HPS DDR se koetsoe nakong ea ho hlophisa bocha.
3. Etsa bonnete ba hore litšitiso tsa FPGA ho FPGA li koaletsoe nakong ea ho hlophisa bocha.
Hape, tsebisa mokhanni ho hana litšitiso leha e le life tse tsoang ho FPGA nakong ea ho hlophisa bocha.

Sheba khoutu ea mohloli oa lisebelisoa tsa lenaneo bakeng sa lintlha tse mabapi le ts'ebetsong ea sebele.

Tlhokomeliso: Se ke oa fetola tlhophiso ea molaoli oa HPS DDR ha CPU e sebetsa.
Ho etsa joalo ho ka baka phoso e mpe ea sistimi hobane o kanna oa fetola tlhophiso ea taolo ea DDR ha ho na le litšebelisano tse ntle tsa memori tse tsoang ho CPU. Sena se bolela hore ha CPU e sebetsa, o kanna oa se ke oa hlophisa hape konokono ea FPGA ka setšoantšo se sebelisang HPS DDR ka tlhophiso e fapaneng.
Hopola hore sistimi ea OpenCL, le moralo oa litšupiso oa Golden Hardware o fumanehang ka Intel SoC FPGA Embedded Design Suite (EDS), e beha HPS DDR mokhoeng o le mong oa 256-bit.
Likarolo tsa sistimi ea CPU joalo ka mohlahlami oa lekala kapa prefetcher ea leqephe la leqephe li ka fana ka litaelo tsa DDR leha ho bonahala eka ha ho letho le sebetsang ho CPU.
Ka hona, nako ea boot ke eona feela nako e bolokehileng ea ho beha tlhophiso ea taolo ea HPS DDR.
Sena se boetse se bolela hore U-boot e tlameha ho ba le binary e tala file (.rbf) setšoantšo se tla kenngoa mohopolong. Ho seng joalo, o kanna oa nolofalletsa HPS DDR ka likou tse sa sebelisoeng ho FPGA ebe o khona ho fetola litlhophiso tsa boema-kepe kamora moo. Ka lebaka lena, mokhanni oa kernel oa OpenCL Linux ha a sa kenyelletsa mohopolo o hlokahalang ho beha tlhophiso ea taolo ea HPS DDR.
The SW3 dual in-line package (DIP) e fapohela Cylone V SoC Development Kit e laola mokhoa o lebelletsoeng oa setšoantšo sa .rbf (ke hore, hore na file e petelitsoe le/kapa e patiloe). C5soc, le Golden Hardware Reference Design e fumanehang ka SoC EDS, li kenyelletsa litšoantšo tse hatisitsoeng empa tse sa ngolisoang tsa .rbf. Litlhophiso tsa switjha tsa SW3 DIP tse hlalositsoeng ho Intel FPGA SDK bakeng sa OpenCL Leholiotsoana V SoC ea Tsela ea ho Qala e tsamaellana le tlhophiso ena ea setšoantšo sa .rbf.

Related Links

Li-interface tsa HPS-FPGA
Ho lokisa li-switch tsa SW3

1.4.1 Lintlha tsa Mehaho ea Tsamaiso ea FPGA
Tšehetso bakeng sa Leholiotsoana la V SoC Development Kit Reference Platform e thehiloe ho Stratix® V Reference Platform (s5_ref), e fumanehang ka Intel FPGA SDK bakeng sa OpenCL.
Kakaretso ea mokhatlo oa c5soc Qsys system le mokhanni oa kernel li tšoana haholo le tse ho s5_ref.
Likarolo tse latelang tsa mantlha tsa FPGA lia tšoana ho c5soc le s5_ref:

VERSION_ID thibela
Mochini oa ho phomola

Sekhetho sa banka ea memori
Cache snoop interface
Oache ea kernel

Li-block tsa phihlello ea ngoliso ea taolo (CRA).

1.5 Ho aha Setšoantšo sa Karete ea Flash ea SD
Hobane Leholiotsoana V SoC FPGA ke sistimi e felletseng ho chip, o na le boikarabello ba ho fana ka tlhaloso e felletseng ea sistimi. Intel e khothaletsa hore o e tsamaise ka mokhoa oa setšoantšo sa karete ea SD flash. Intel FPGA SDK bakeng sa mosebelisi oa OpenCL e ka ngolla setšoantšo ho karete ea flash ea SD mme boto ea SoC FPGA e se e loketse ho sebelisoa.
Ho fetola setšoantšo se teng sa SD Flash Card leqepheng la 13
Intel e khothaletsa hore o fetole feela setšoantšo se fumanehang ka Leholiotsoana la V SoC Development Kit Reference Platform. U boetse u na le khetho ea ho theha setšoantšo se secha sa karete ea flash ea SD.
Ho theha setšoantšo sa SD Flash Card leqepheng la 14
U boetse u na le khetho ea ho theha setšoantšo se secha sa karete ea flash ea SD.

1.5.1 Ho Fetola Sets'oants'o sa SD Flash Card se Teng
Intel e khothaletsa hore o fetole setšoantšo se fumanehang ka Leholiotsoana V SoC
Sethala sa Tšebeliso ea Kit ea Ntlafatso. U boetse u na le khetho ea ho theha setšoantšo se secha sa karete ea flash ea SD.
Setšoantšo sa c5soc linux_sd_card_image.tgz file e fumaneha bukeng ea ALTERAOCLSDKROOT/board/c5soc, moo ALTERAOCLSDKROOT e supang tsela ea Intel FPGA SDK bakeng sa bukana ea kopo ea OpenCL.

Tlhokomeliso: Ho fetola setšoantšo sa karete ea flash ea SD, o tlameha ho ba le litokelo tsa motso kapa sudo.

Ho theola $ALTERAOCLSDKROOT/board/c5soc/linux_sd_card_image.tgz file, tsamaisa taelo ea tar xvfzlinux_sd_card_image.tgz.
Kopanya hello_world OpenCL example moralo o sebelisa tšehetso ea hau ea Sethala sa Tloaelo. Reha lebitso bocha .rbf file hore Intel FPGA SDK bakeng sa OpenCL Offline Compiler e hlahisa e le opencl.rbf, 'me e e behe karolong ea fat32 ka har'a setšoantšo sa karete ea flash ea SD.
U ka khoasolla setšoantšo sa hello_worldample moralo ho tsoa ho OpenCL Design Examples leqepheng la Altera websebaka.

Beha .rbf file karolong ea fat32 ea setšoantšo sa karete ea flash.
Tlhokomeliso: Karohano ea fat32 e tlameha ho ba le li-zImage ka bobeli file le .rbf file. Ntle le .rbf file, phoso e bolaeang e tla etsahala ha o kenya mokhanni.
Kamora hore o thehe setšoantšo sa karete ea SD, e ngolle kareteng e nyane ea SD ka ho kopa taelo e latelang: sudo dd if=/path/to/sdcard/image.bin of=/dev/sdcard
Ho leka setšoantšo sa karete ea flash ea SD, etsa mesebetsi e latelang:
a. Kenya karete ea flash ea SD ka har'a boto ea SoC FPGA.
b. Matlafatsa boto.
c. Kopa taelo ea ts'ebeliso ea tlhahlobo ea aocl.

1.5.2 Ho theha setšoantšo sa SD Flash Card
U boetse u na le khetho ea ho theha setšoantšo se secha sa karete ea flash ea SD. Litaelo tse akaretsang mabapi le ho aha sets'oants'o se secha sa karete ea flash ea SD le ho aha sets'oants'o sa karete ea flash ea SD e teng ho GSRD v14.0.2 - Leqephe la SD Card la RocketBoards.org websebaka.
Mehato e ka tlase e hlalosa mokhoa oa ho theha setšoantšo sa linux_sd_card_image.tgz ho tsoa ho setšoantšo sa karete ea flash ea SD ea Golden System Reference Design (GSRD):
Hlokomela:
Ho theha setšoantšo ho tsoa setšoantšong sa c5soc, etsa mesebetsi eohle e sebetsang e hlalositsoeng ts'ebetsong ena.

Khoasolla le ho manolla mofuta oa 14.0 oa karete ea karete ea GSRD SD ho tsoa Rocketboards.org.
Thaba ea file tafole ea kabo (fat32) le ho atolosoa file tsamaiso (ext3) partitions setšoantšong sena e le lisebelisoa tsa loop-back. Ho kenya partition, etsa mehato e latelang:
a. Etsa qeto ea ho qala ha karohano ka har'a setšoantšo ka ho kopa /sbin/fdisk -lu image_file laela.
Bakeng sa mohlalaample, karohano ea nomoro ea 1 ea mofuta oa W95 FAT e na le "block offset" ea 2121728. Ka li-byte tse 512 ka boloko, ho fokotsa li-byte ke 512 byte x 2121728 = 1086324736 bytes.
b. Hlalosa sesebelisoa sa mahala sa loop (mohlalaample, /dev/loop0) ka ho thaepa taelo ea losetup -f.
c. Ho nka /dev/loop0 ke sesebelisoa sa mahala sa loop, fana ka setšoantšo sa karete ea hau ea flash ho sesebelisoa sa block block ka ho kopa tahlehelo /dev/loop0 image_file -0 1086324736 taelo.
d. Kenya sesebelisoa sa loop ka ho kopa mount /dev/loop0 /media/disk1 taelo.
Ka har'a setšoantšo file, /media/disk1 joale e se e le karohano ea fat32 e behiloeng.
e. Pheta mehato ea a ho d bakeng sa karohano ea ext3.

Khoasolla mofuta oa Cyclone V SoC FPGA ea Intel FPGA Runtime Environment bakeng sa sephutheloana sa OpenCL ho tsoa Setsing sa Khoasolla ho Altera. websebaka.
a. Tobetsa konopo ea Download haufi le khatiso ea software ea Quartus Prime.
b. Hlalosa mofuta oa tokollo, sistimi e sebetsang, le mokhoa oa ho jarolla.
c. Tobetsa tab ya Eketsa Software, ebe o kgetha ho jarolla Intel FPGA
Tikoloho ea Runtime bakeng sa OpenCL Linux Cyclone V SoC TGZ.
d. Ka mor'a hore u khoasolle aocl-rte- .arm32.tgz file, e phutholle ho
directory eo u nang le eona.
Beha li-aocl-rte- tse sa koaloang .arm32 directory ho /home/root/opencl_arm32_rte directory ho karolo ea ext3 ea setšoantšo file.
Hlakola foldara (li)hardware ea Platform ea hau e Tloaelehileng, ebe u beha Sethala sa Tloaelo ka har'a boto ea /home/root/ opencl_arm32_rte.

Theha faele ea init_opencl.sh file bukeng ea /hae/motso e nang le litaba tse latelang: romella kantle ho naha ALTERAOCLSDKROOT=/home/root/opencl_arm32_rte export AOCL_BOARD_PACKAGE_ROOT=$ALTERAOCLSDKROOT/board/ export PATH=$ALTERAOCLSDKROOT/bin:$PATH export LD_LIBRARY_PATH=$ALTERAOCLSDKROOT/host/arm32/lib:$LD_LIBRARY_PATH insmod $AOCL_BOARD_PACKAGE_ROOT/driver/aclsoc_drv.ko
Mosebelisi oa SDK o tsamaisa mohloli ./init_opencl.sh taelo ea ho kenya mefuta-futa ea tikoloho le mokhanni oa kernel oa OpenCL Linux.
Haeba o hloka ho ntlafatsa preloader, DTS files, kapa Linux kernel, o hloka compiler ea arm-linux-gnueabihf-gcc ho tsoa ho SoC EDS. Latela litaelo tse boletsoeng ho Intel SoC FPGA Embedded Design Suite User Guide ho fumana software, ho e bokella hape, le ho nchafatsa tse loketseng. files karolong e behiloeng fat32 partition.
Tlhokomeliso: Ho ka etsahala hore ebe o hloka ho nchafatsa preloader haeba Platform ea hau ea Tloaelo e na le ts'ebeliso e fapaneng ea phini ho feta ea c5soc.
Hopola: Haeba u khutlisetsa kernel ea Linux, khutlisetsa mokhanni oa Linux kernel ka mohloli o tšoanang oa Linux kernel. files. Haeba ho na le ho se lumellane pakeng tsa mokhanni oa kernel oa Linux le kernel ea Linux, mokhanni a ke ke a laela. Hape, o tlameha ho nolofalletsa CMA.
Sheba ho Recompiling Linux Kernel bakeng sa tlhaiso-leseling e batsi.
Kopanya hello_world OpenCL example moralo o sebelisa tšehetso ea hau ea Sethala sa Tloaelo. Reha lebitso bocha .rbf file hore Intel FPGA SDK bakeng sa OpenCL Offline Compiler e hlahisa e le opencl.rbf, 'me e e behe karolong ea fat32 ka har'a setšoantšo sa karete ea flash ea SD.
U ka khoasolla setšoantšo sa hello_worldample moralo ho tsoa ho OpenCL Design Examples leqepheng la Altera websebaka.
9. Ka mor'a hore u boloke tsohle tse hlokahalang files setšoantšong sa karete ea flash, kopa litaelo tse latelang:
a. sync
b. theola /media/disk1
c. theolela moo ke lebitso la directory leo u le sebelisang ho kenya karohano ea ext3 ho 3 leqepheng la 3 (bakeng sa mohlalaample, /media/disk2).
d. lahleheloa ke -d /dev/loop0
e. lahleheloa ke -d /dev/loop1

Tobetsa setšoantšo sa karete ea flash ea SD ka ho kopa taelo e latelang: tar cvfz .tgz linux_sd_card_image
Fana ka .tgz file ka har'a buka ea motso ea Sethala sa hau sa Tloaelo.
Ho leka setšoantšo sa karete ea flash ea SD, etsa mesebetsi e latelang:
a. Ngola sephetho sa setšoantšo se sa hatelloang ho karete ea Micro SD.
b. Kenya karete ea flash ea SD ka har'a boto ea SoC FPGA.
c. Matlafatsa boto.
d. Kopa taelo ea ts'ebeliso ea tlhahlobo ea aocl.

Related Links

Intel SoC FPGA Embedded Design Suite User Guide
OpenCL Design Examples leqepheng la Altera websebaka

Ho tsosolosa Linux Kernel leqepheng la 16
Ho nolofalletsa CMA, o tlameha ho qala ka ho bokella kernel ea Linux.
Ho botsa Lebitso la Sesebelisoa sa Boto ea hau ea FPGA (tlhahlobo)

1.6 Ho bokella Linux Kernel bakeng sa Leholiotsoana V SoC FPGA
Pele o sebelisa lits'ebetso tsa OpenCL botong ea Leholiotsoana V SoC FPGA, o tlameha ho bokella mohloli oa kernel ea Linux, 'me u hlophise le ho kenya mokhanni oa kernel oa OpenCL Linux.

Ho tsosolosa Linux Kernel leqepheng la 16
Ho nolofalletsa CMA, o tlameha ho qala ka ho bokella kernel ea Linux.
Ho Kopanya le ho Kenya OpenCL Linux Kernel Driver leqepheng la 17 Kopanya mokhanni oa kernel oa OpenCL Linux khahlano le mohloli o hlophisitsoeng oa kernel.

1.6.1 Ho tsosolosa Linux Kernel
Ho nolofalletsa CMA, o tlameha ho qala ka ho bokella kernel ea Linux.

Tobetsa GSRD v14.0 - Ho bokella sehokelo sa Linux leqepheng la Lisebelisoa tsa RocketBoards.org websebaka sa marang-rang ho fumana litaelo tsa ho khoasolla le ho aha bocha khoutu ea mohloli oa kernel ea Linux.
Bakeng sa tšebeliso le ™ Intel FPGA SDK bakeng sa OpenCL, bolela socfpga-3.13-rel14.0 e le .
Tlhokomeliso: Ts'ebetso ea moaho e theha arch/arm/configs/socfpga_defconfig file. Sena file e totobatsa litlhophiso tsa tlhophiso ea kamehla ea socfpga.
Kenya mela e latelang tlase ho arch/arm/configs/socfpga_defconfig file.
CONFIG_MEMORY_ISOLATION=y
CONFIG_CMA=y
CONFIG_DMA_CMA=y
CONFIG_CMA_DEBUG=y
CONFIG_CMA_SIZE_MBYTES=512
CONFIG_CMA_SIZE_SEL_MBYTES=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
Theko ea CONFIG_CMA_SIZE_MBYTES e beha moeli o ka holimo ho palo eohle ea memori e amanang le 'mele e fumanehang. O ka eketsa boleng bona haeba o hloka memori e eketsehileng.
Tlhokomeliso: Kakaretso ea memori ea 'mele e fumanehang ho processor ea ARM ho boto ea SoC FPGA ke 1 GB. Intel ha e khothaletse hore u behe mookameli oa CMA haufi le 1 GB.

Etsa taelo ea make mrproper ho hloekisa tlhophiso ea hajoale.
Matha etsa ARCH=arm socfpga_deconfig taelo.
ARCH=letsoho le bontša hore u batla ho lokisa meralo ea ARM.
socfpga_defconfig e bonts'a hore u batla ho sebelisa tlhophiso ea kamehla ea socfpga.
Etsa taelo ea ho romela thepa CROSS_COMPILE=arm-linux-gnueabihf- taelo.
Taelo ena e beha mofuta oa CROSS_COMPILE oa tikoloho ho hlakisa sehlomapele sa ketane ea lisebelisoa e lakatsehang.

Etsa taelo ea make ARCH=arm zImage. Setšoantšo se hlahisoang se fumaneha ho arch/arm/boot/zImage file.
Beha zImage file karolong ea fat32 ea setšoantšo sa karete ea flash. Bakeng sa litaelo tse qaqileng, sheba Buka ea Mosebelisi ea Leholiotsoana la V SoC FPGA-specific GSRD ho Rocketboards.org.
Tlhokomeliso: Ho kenya mokhanni oa kernel oa OpenCL Linux ka nepo, qala ka ho kenya SDKgenerated.rbf file ho FPGA.
Ho theha .rbf file, bokella moralo oa SDK example Leholiotsoana la V SoC Development Kit Reference Platform joalo ka Sethala sa Tloaelo se reriloeng.
9. Beha .rbf file karolong ea fat32 ea setšoantšo sa karete ea flash.
Tlhokomeliso: Karohano ea fat32 e tlameha ho ba le li-zImage ka bobeli file le .rbf file. Ntle le .rbf file, phoso e bolaeang e tla etsahala ha o kenya mokhanni.

Kenya karete ea micro SD e hlophisitsoeng, e nang le setšoantšo sa karete ea SD eo u e fetotseng kapa eo u e entseng pejana, ho Cyclone V SoC Development Kit ebe o matlafatsa boto ea SoC FPGA.
Netefatsa mofuta oa Linux kernel e kentsoeng ka ho sebelisa taelo ea uname -r.
Ho netefatsa hore o nolofalletsa CMA ka katleho kernel, ka boto ea SoC FPGA e matlafalitsoeng, tsamaisa taelo ea grep init_cma /proc/kallsyms.
CMA e ea lumelloa haeba tlhahiso e se na letho.

Ho sebelisa kernel ea Linux e hlophisitsoeng hape ka SDK, bokella le ho kenya mokhanni oa kernel oa Linux.

Related Links

Golden System Reference Design (GSRD) Libukana tsa Mosebelisi

Ho aha setšoantšo sa SD Flash Card leqepheng la 13
Hobane Leholiotsoana V SoC FPGA ke sistimi e felletseng ho chip, o na le boikarabello ba ho fana ka tlhaloso e felletseng ea sistimi.

1.6.2 Ho hlophisa le ho kenya OpenCL Linux Kernel Driver
Kopanya mokhanni oa kernel oa OpenCL Linux khahlano le mohloli o hlophisitsoeng oa kernel.

Mohloli oa mokhanni o fumaneha ho mofuta oa Cyclone V SoC FPGA ea Intel FPGA Runtime Environment bakeng sa OpenCL. Ho feta moo, etsa bonnete ba hore o kentse Intel FPGA SDK bakeng sa OpenCL-generated .rbf file ho FPGA ho thibela ho kenngoa ho fosahetseng ha mojule oa kernel oa Linux.

Khoasolla mofuta oa Cyclone V SoC FPGA ea Intel FPGA Runtime Environment bakeng sa sephutheloana sa OpenCL ho tsoa Setsing sa Khoasolla ho Altera. websebaka.
a. Tobetsa konopo ea Download haufi le khatiso ea software ea Quartus Prime.
b. Hlalosa mofuta oa tokollo, sistimi e sebetsang, le mokhoa oa ho jarolla.
c. Tobetsa tab ya Eketsa Software, ebe o kgetha ho jarolla Intel FPGA
Tikoloho ea Runtime bakeng sa OpenCL Linux Cyclone V SoC TGZ.
d. Ka mor'a hore u khoasolle aocl-rte- .arm32.tgz file, e phutholle ho
directory eo u nang le eona.
Mohloli oa mokhanni o ho aocl-rte- .arm32/board/c5soc/ directory ea mokhanni.
Ho bokella hape mokhanni oa kernel oa OpenCL Linux, beha boleng ba KDIR ho Makeup ea mokhannifile ho directory e nang le mohloli oa kernel oa Linux files.
Etsa taelo ea ho romela thepa CROSS_COMPILE=arm-linux-gnueabihf- ho bontša sehlongoapele sa ketane ea lisebelisoa tsa hau.

Matha taelo ea make clean.
Matha etsa taelo ho theha faele ea aclsoc_drv.ko file.
Fetisetsa bukana ea opencl_arm32_rte ho Boto ea Leholiotsoana V SoC FPGA.
Ho matha scp -r motso @ ipadresi ea hau: taelo e beha tikoloho ea nako ea ho sebetsa bukeng ea/home/root directory.

Sebelisa mongolo oa init_opencl.sh oo u o entseng ha u theha karete ea SD.
Kopa taelo ea ts'ebeliso ea tlhahlobo ea aocl. Sesebelisoa sa ho hlahloba se tla khutlisa sephetho se fetang ka mor'a hore u sebetse init_opencl.sh ka katleho.

1.7 Litaba Tse Tsejoang
Hajoale, ho na le meeli e itseng ts'ebelisong ea Intel FPGA SDK bakeng sa OpenCL e nang le Leholiotsoana la V SoC Development Kit Reference Platform.

U ka se tlole mabitso a barekisi le boto a tlalehiloeng ke CL_DEVICE_VENDOR le CL_DEVICE_NAME ea mohala oa clGetDeviceInfo().
Haeba moamoheli a fana ka mohopolo o sa khaotseng ho sistimi e arolelanoang ea DDR (ke hore, HPS DDR) mme e fetola mohopolo o sa feleng kamora ts'ebetso ea kernel, data e mohopolong e kanna ea felloa ke nako. Taba ena e hlaha hobane mantlha ea FPGA ha e khone ho nyenyefatsa tšebetso ea CPU-to-HPS DDR.
Ho thibela ts'ebetso e latelang ea kernel ho fihlella data ea khale, sebelisa e 'ngoe ea li-workaround tse latelang:
• Se ke oa fetola memori ea kamehla ka mor'a ho qala.
• Haeba o hloka disete tse ngata tsa __tsa data kamehla, etsa dibaka tse ngata tsa memori tse sa fetoheng.
• Ha e le teng, abela memori e sa feleng ho FPGA DDR botong ya accelerator.
Sesebelisoa sa SDK ho ARM se ts'ehetsa feela lenaneo le ho hlahloba litaelo tsa ts'ebeliso.
Litaelo tsa tšebeliso ea flash, kenya le ho hlakola ha li sebetse ho Cyclone V SoC Development Kit ka mabaka a latelang:
a. Sesebelisoa sa ho kenya se tlameha ho bokella mokhanni oa kernel ea aclsoc_drv le ho e nolofalletsa ho SoC FPGA. Mochini oa nts'etsopele o tlameha ho etsa pokello; leha ho le joalo, e se e ntse e na le mehloli ea kernel ea Linux bakeng sa SoC FPGA. Mehloli ea kernel ea Linux bakeng sa mochini oa nts'etsopele e fapane le ea SoC FPGA. Sebaka sa mehloli ea kernel ea Linux bakeng sa SoC FPGA mohlomong ha se tsejoe ke mosebelisi oa SDK. Ka mokhoa o ts'oanang, sesebelisoa sa uninstall se boetse ha se fumanehe ho Cyclone V SoC Development Kit.
Hape, ho tlisa aclsoc_drv ho boto ea SoC ho thata hobane kabo ea kamehla ea Cyclone V SoC Development Kit ha e na Linux kernel files kapa moqapi oa GNU Compiler Collection (GCC).
b. Sesebelisoa sa flash se hloka ho beha .rbf file ea moralo oa OpenCL karolong ea FAT32 ea karete ea flash SD. Hajoale, karohano ena ha e kenngoe ha mosebelisi oa SDK a phahamisa boto. Ka hona, tsela e molemohali ea ho ntlafatsa karohano ke ho sebelisa sebali sa karete ea flash le mochini oa nts'etsopele.

Ha o chencha lipakeng tsa Intel FPGA SDK bakeng sa OpenCL Offline Compiler e ka sebetsoang files (.aocx) tse tsamaellanang le mefuta e fapaneng ya boto (ke hore, c5soc le c5soc_sharedonly), o tlameha ho sebedisa lenaneo la SDK ho kenya .aocx file bakeng sa mofuta o mocha oa boto lekgetlo la pele. Haeba o sebelisa sesebelisoa sa moamoheli o sebelisa mofuta o mocha oa boto empa FPGA e na le setšoantšo sa mofuta o mong oa boto, phoso e mpe e ka hlaha.
The .qxp file ha e kenyelletse likabelo tsa karohano ea li-interface hobane software ea Quartus Prime e lula e fihlela litlhoko tsa nako tsa karohano ena.
Ha o matlafatsa boto, aterese ea eona ea taolo ea phihlello ea media (MAC) e behiloe ho nomoro e sa lebelloang. Haeba leano la hau la LAN le sa lumelle mokhoa ona, seta aterese ea MAC ka ho etsa mesebetsi e latelang:
a. Nakong ea ho matlafatsa U-Boot, tobetsa konopo efe kapa efe ho kenya molaetsa oa taelo oa U-Boot.
b. Type setenv ethaddr 00:07:ed:00:00:03 ka potlako ea taelo.
U ka khetha aterese efe kapa efe ea MAC.
c. Tlanya taelo ea saveenv.
d. Qala boto hape.

1.8 Nalane ea Phetoho ea Litokomane
Lethathamo la 1.
Nalane ea Tokomane ea Tokomane ea Intel FPGA SDK bakeng sa OpenCL Cyclone V SoC
Tataiso ea ho tsamaisa Platform ea Reference Kit ea Ntlafatso

Letsatsi	Phetolelo	Liphetoho
Mots'eanong-17	2017.05.08	• Tokollo ea tlhokomelo.
Octoboer 2016	2016.10.31	• Altera SDK e rehiloe bocha bakeng sa OpenCL ho ea ho Intel FPGA SDK bakeng sa OpenCL. •Setsi sa Altera Offline Compiler se fetoletsoe lebitso la Intel FPGA SDK bakeng sa OpenCL Offline Compiler.
Mots'eanong-16	2016.05.02	•Litaelo tse fetotsoeng mabapi le ho haha le ho fetola setšoantšo sa karete ea flash ea SD. •Litaelo tse fetotsoeng mabapi le ho khutlisa kernel ea Linux le mokhanni oa kernel oa OpenCL Linux.
Pulungoana-15	2015.11.02	•Tokollo ea tlhokomelo, le maemo a fetotsoeng a Quartus II ho ba Quartus Prime.
Mots'eanong-15	15.0.0	• Ho FPGA Reconfiguration, ho tlositsoe taelo ea ho hlophisa bocha FPGA mantlha le a. rbf setšoantšo ka ho kopa katse filelebitso>. rbf > /dev/ fpga0 taelo hobane mokhoa ona ha o khothalletsoe.
Tšitoe-14	14.1.0	•E reha tokomane bocha e le Altera Cyclone V SoC Development Kit Reference Porting Guide. • E ntlafalitse ts'ebeliso ea reprogram ho lenaneo la aoclfilelebitso>.aocx taelo ea tšebeliso. • E ntlafalitse ts'ebeliso ea tlhahlobo ho tlhahlobo ea aocl le tlhahlobo ea aocl taelo ea thuso. •E ntlafalitse mokhoa oa ho tsamaisa Sethala sa Litšupiso karolong ea Boto ea Hau ea SoC ho kenyelletsa litaelo mabapi le ho tsamaisa le ho fetola karolo ea boto ea c5soc ho theha karohano e hloekileng ea nako bakeng sa phallo e netefalitsoeng ea ho koala nako. •E kenyelelitse sehlooho Ho Nchafatsa Ported Reference Platform ho hlahisa mekhoa ea mesebetsi e latelang: 1.Kantle ho hard processor system (HPS) block ka har'a karohano ea boto 2.Ho ntlafatsa setšoantšo sa karete ea flash ea SD •E ntlafalitse karolo ea Kaho ea SD Flash Card Image. E khothalelitsoe ho sebelisoa mofuta oa 14.0 oa setšoantšo sa Golden System Reference Design (GSRD) e le sebaka sa ho qala sebakeng sa setšoantšo se fumanehang ka SoC Embedded Design Suite (EDS). •E ntlafalitse karolo ea Recompiling Linux Kernel le karolo ea OpenCL Linux Kernel Driver: 1.Taelo e ekelitsoeng ho seta phapang ea CROSS COMPILE. 2.E fetotse taelo eo o e tsamaisang ho netefatsa hore CMA e nolofalitsoe ka katleho.
Phupu-14	14.0.0	• Phatlalatso ea Pele.