intel FPGA SDK rau OpenCL User Guide

FPGA SDK rau OpenCL
Cov neeg siv phau ntawv qhia

UG-OCL009
2017.05.08
Hloov kho tshiab kawg rau Intel® Quartus® Prime Design Suite: 17.0

Sau npe
Xa lus tawm tswv yim

Cov ntsiab lus zais

1 Intel® FPGA SDK rau OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Platform Porting Guide

2 Cov ntaub ntawv / Cov ntaub ntawv

2.1 Cov ntaub ntawv

3 Related Posts

Intel® FPGA SDK rau OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Platform Porting Guide

V SoC Development Kit Reference Platform Porting Guide piav qhia txog kho vajtse thiab software tsim ntawm Intel Cyclone V SoC Development Kit Reference Platform (c5soc) rau siv nrog Intel Software Development Kit (SDK) rau OpenCL Intel ® FPGA SDK rau OpenCL ™ Intel Cyclone ® . Ua ntej koj pib, Intel xav kom koj paub koj tus kheej nrog cov ntsiab lus ntawm cov ntaub ntawv hauv qab no:

Intel FPGA SDK rau OpenCLIntel Cyclone V SoC Pib Qhia

Intel FPGA SDK rau OpenCL Custom Platform Toolkit User Guide
Cyclone V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual Ntxiv rau, xa mus rau Cyclone V SoC Development Kit thiab SoC Embedded Design Suite nplooj ntawv ntawm Altera website kom paub ntau ntxiv. 1

Nco ntsoov: Intel xav tias koj muaj kev nkag siab tob txog Intel FPGA SDK rau OpenCL Custom Platform Toolkit User Guide. Cyclone V SoC Development Kit Reference Platform Porting Guide tsis piav qhia txog kev siv SDK's Custom Platform Toolkit los siv lub Platform Custom rau Cyclone V SoC Development Kit. Nws tsuas yog piav qhia qhov sib txawv ntawm SDK kev txhawb nqa ntawm Cyclone V SoC Development Kit thiab ib qho generic Intel FPGA SDK rau OpenCL Custom Platform.

Txuas txuas

Intel FPGA SDK rau OpenCL Cyclone V SoC Tau Pib Qhia
Intel FPGA SDK rau OpenCL Custom Platform Toolkit User Guide

Cyclone V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual
Cyclone V SoC Development Kit thiab SoC Embedded Design Suite nplooj ntawv ntawm Altera webqhov chaw

OpenCL thiab OpenCL logo yog cov cim lag luam Apple Inc. siv los ntawm kev tso cai ntawm Khronos Group ™.
Intel FPGA SDK rau OpenCL yog raws li kev tshaj tawm Khronos Specification, thiab tau dhau los ntawm Khronos Conformance Testing Process. Cov xwm txheej tam sim no tuaj yeem pom ntawm www.khronos.org/conformance.

Intel Corporation. Txhua txoj cai. Intel, Intel lub logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus thiab Stratix cov lus thiab lub logo yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom tes hauv Asmeskas thiab / lossis lwm lub tebchaws. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam.
* Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

1.1.1 Cyclone V SoC Development Kit Reference Platform Board Variants
Intel FPGA SDK rau OpenCL Cyclone V SoC Development Kit Reference Platform suav nrog ob pawg thawj coj sib txawv.

c5soc ua
Lub default board no muab kev nkag mus rau ob lub tsev txhab nyiaj DDR nco. HPS DDR tuaj yeem siv tau los ntawm FPGA thiab CPU. FPGA DDR tsuas yog siv tau los ntawm FPGA.
c5soc_sharedonly lub rooj tsavxwm
Qhov kev hloov pauv no tsuas muaj HPS DDR txuas. FPGA DDR tsis siv tau. Qhov sib txawv ntawm pawg thawj coj no yog thaj chaw zoo dua vim tias cov khoom siv tsawg dua yog qhov tsim nyog los txhawb nqa ib lub txhab nyiaj DDR nco. Lub rooj tsav xwm c5soc_sharedonly kuj yog ib qho kev tsim qauv zoo rau lub rooj sib tham zaum kawg nrog ib lub txhab nyiaj DDR nco.
Txhawm rau lub hom phiaj ntawm pawg thawj coj no txawv thaum sau koj cov lus OpenCL, suav nrog -board c5soc_sharedonly kev xaiv hauv koj cov lus txib aoc.
Yog xav paub ntxiv ntawm -board kev xaiv ntawm aoc hais kom ua, xa mus rau Intel FPGA SDK rau OpenCL Programming Guide.

Txuas txuas
Sau cov Kernel rau Ib Pawg FPGA Tshwj Xeeb (–board )
1.1.2 Cov ntsiab lus ntawm Cyclone V SoC Development Kit Reference Platform
Cyclone V SoC Development Kit Reference Platform muaj cov hauv qab no files thiab directory:

File los yog Directory	Kev piav qhia
board_env.xml	eXtensible Markup Language (XML) file uas piav txog c5soc rau Intel FPGA SDK rau OpenCL.
linux_sd_card_image.tgz	Compressed SD daim npav duab file uas muaj txhua yam uas tus neeg siv SDK xav tau siv Cyclone V SoC Development Kit nrog SDK.
ua 32	Directory uas muaj cov hauv qab no:

1.1.3 Cov Nta Tseem Ceeb ntawm Cyclone V SoC Development Kit

Cov npe hauv qab no qhia txog Cyclone V SoC Kev Txhim Kho Cov Khoom Siv thiab cov yam ntxwv uas cuam tshuam rau Intel FPGA SDK rau OpenCL:

Dual-core ARM Cortex-A9 CPU khiav 32-ntsis Linux.

Advanced eXtensible Interface (AXI) tsheb npav ntawm HPS thiab FPGA core ntaub.
Ob lub hardened DDR nco controllers, txhua qhov txuas mus rau 1 gigabyte (GB) DDR3 SDRAM.
- Ib qho DDR maub los yog siv tau rau FPGA core nkaus xwb (uas yog, FPGA DDR).
- Lwm yam DDR maub los yog siv tau rau ob qho tib si HPS thiab FPGA (uas yog, HPS DDR). Qhov kev sib koom ua ke no tso cai rau kev nco pub dawb ntawm CPU thiab FPGA core.

CPU tuaj yeem hloov kho FPGA core ntaub.

1.1.3.1 Cyclone V SoC Development Kit Reference Platform Design Lub Hom Phiaj thiab Kev Txiav Txim Siab Intel ua raws li kev siv Cyclone V SoC Development Kit Reference Platform ntawm ntau lub hom phiaj tsim thiab kev txiav txim siab. Intel xav kom koj xav txog cov hom phiaj thiab cov kev txiav txim siab no thaum koj xa daim ntawv qhia no rau koj SoC FPGA pawg thawj coj saib.
Hauv qab no yog cov hom phiaj tsim c5soc:

Muab qhov siab tshaj plaws tau bandwidth ntawm kernels ntawm FPGA thiab DDR nco system(s).
Xyuas kom meej tias kev suav ntawm FPGA (uas yog, OpenCL kernels) tsis cuam tshuam nrog lwm cov haujlwm CPU uas yuav suav nrog kev pabcuam khoom siv.

Cia li FPGA cov peev txheej ntau npaum li qhov ua tau rau kev suav cov ntsiav es tsis txhob siv cov khoom sib txuas.

Hauv qab no yog cov kev txiav txim siab tsim qib siab uas yog qhov tshwm sim ncaj qha ntawm Intel lub hom phiaj tsim:

Lub Platform Reference tsuas yog siv zog DDR lub cim xeeb controllers nrog lub widestpossible configuration (256 khoom).
FPGA sib txuas lus nrog HPS DDR lub cim xeeb tswj ncaj qha, tsis muaj kev koom nrog lub tsheb npav AXI thiab L3 hloov hauv HPS. Kev sib txuas lus ncaj qha muab qhov zoo tshaj plaws bandwidth rau DDR, thiab khaws FPGA kev suav los ntawm kev cuam tshuam nrog kev sib txuas lus ntawm CPU thiab nws thaj chaw.
Scatter-sau direct memory access (SG-DMA) tsis yog ib feem ntawm FPGA interface logic. Hloov pauv cov ntaub ntawv loj ntawm DDR lub cim xeeb, khaws cov ntaub ntawv hauv HPS DDR sib koom. Kev nkag ncaj qha rau CPU nco los ntawm FPGA yog qhov ua tau zoo dua li DMA. Nws txuag cov khoom siv kho vajtse (uas yog, FPGA cheeb tsam) thiab ua kom yooj yim rau Linux kernel tsav tsheb.
Ceeb toom: Nco hloov ntawm qhov sib koom HPS DDR system thiab DDR system uas nkag tau tsuas yog rau FPGA qeeb heev. Yog koj xaiv
hloov lub cim xeeb li no, siv nws rau cov ntaub ntawv me me xwb.
Tus tswv tsev thiab cov cuab yeej ua haujlwm tsis yog-DMA cov ntaub ntawv hloov pauv ntawm ib leeg ntawm tus choj HPS-to-FPGA (H2F), siv tib qhov chaw nres nkoj 32-ntsis nkaus xwb. Yog vim li cas yog, tsis muaj DMA, Linux ntsiav tsuas tuaj yeem muab ib qho 32-ntsis nyeem lossis sau ntawv thov, yog li nws tsis tas yuav muaj kev sib txuas dav dua.
Tus tswv tsev xa cov teeb liab tswj rau lub cuab yeej ntawm lub teeb H2F (LH2F) choj.
Vim tias kev tswj cov teeb liab los ntawm tus tswv tsev mus rau lub cuab yeej yog cov teeb liab qis, LH2F choj yog qhov zoo tagnrho rau txoj haujlwm.

1.2 Xa cov ntaub ntawv xa mus rau koj SoC FPGA Board
Txhawm rau xa cov Cyclone V SoC Development Kit Reference Platform rau koj SoC FPGA pawg thawj coj saib, ua cov haujlwm hauv qab no:

Xaiv ib qho DDR nco lossis ob DDR nco version ntawm c5soc Reference Platform ua qhov pib ntawm koj tus qauv tsim.
Hloov kho tus pin qhov chaw hauv ALTERAOCLSDKROOT/board/c5soc/ /top.qsf file, qhov twg ALTERAOCLSDKROOT yog txoj hauv kev mus rau qhov chaw ntawm Intel FPGA SDK rau OpenCL installation, thiab yog lub npe ntawm lub rooj tsavxwm variant. Cov npe c5soc_sharedonly yog rau pawg thawj coj sib txawv nrog ib qho DDR nco system. Cov npe c5soc yog rau pawg thawj coj sib txawv nrog ob lub cim xeeb DDR.
Hloov kho DDR nqis rau HPS thiab/lossis FPGA SDRAM blocks hauv ALTERAOCLSDKROOT/board/c5soc/ /system.qsys file.
4. Txhua Intel FPGA SDK rau OpenCL nyiam lub rooj tsavxwm tsim yuav tsum ua tiav lub sijhawm kaw. Yog li ntawd, qhov kev tso kawm ntawm tus tsim yuav tsum yog lub sij hawm huv si. Txhawm rau chaw nres nkoj c5soc board faib (acl_iface_partition.qxp) rau koj SoC FPGA board, ua cov haujlwm hauv qab no:
Rau cov lus qhia ntxaws txog kev hloov kho thiab khaws cia ntawm pawg thawj coj saib xyuas, xa mus rau Quartus
Prime Incremental Compilation rau Hierarchical thiab Team-based Design tshooj ntawm Quartus Prime Standard Edition Phau Ntawv Qhia.
ib. Tshem tawm acl_iface_partition.qxp los ntawm ALTERAOCLSDKROOT/board/c5soc/c5soc directory.
b. Pab kom acl_iface_region LogicLock™ cheeb tsam los ntawm kev hloov Tcl hais kom ua set_global_assignment -name LL_ENABLED OFF -section_id acl_iface_region rau set_global_assignment -name LL_ENABLED ON -section_id acl_iface_region
c. Sau ib qho OpenCL kernel rau koj lub rooj tsavxwm.
d. Yog tias tsim nyog, kho qhov loj thiab qhov chaw ntawm thaj tsam LogicLock.
e. Thaum koj txaus siab tias qhov kev tso kawm ntawm koj tus qauv tsim yog lub sijhawm huv, xa tawm qhov muab faib ua acl_iface_partition.qxp Quartus Prime Exported Partition File.
Raws li tau piav qhia nyob rau hauv Kev Tsim Kho Lub Sijhawm Ncua Sijhawm Flow ntawm AIntel FPGA SDK rau OpenCL Custom Platform Toolkit User Guide, los ntawm importing qhov no .qxp file nyob rau hauv lub sab saum toj-theem tsim, koj ua tau raws li qhov yuav tsum tau ntawm muab ib tug board tsim nrog ib tug guaranteed lub sij hawm kaw txaus txaus.
Rau yam uas yuav cuam tshuam qhov zoo ntawm cov txiaj ntsig (QoR) ntawm koj qhov kev faib tawm, xa mus rau General Quality of Results Considerations for the Exported Board Partition section in Intel FPGA SDK for OpenCL Custom Platform Toolkit User Guide.
f. Disable acl_iface_region LogicLock cheeb tsam los ntawm reverting cov lus txib hauv Kauj Ruam 2 rov qab mus rau set_global_assignment -name LL_ENABLED OFF section_id acl_iface_region.
Yog tias koj lub SoC FPGA lub rooj tsavxwm siv cov pins sib txawv thiab thaj tsam ntawm HPS thaiv, rov tsim dua lub preloader thiab cov cuab yeej ntoo (DTS) file. Yog tias koj hloov HPS DDR lub cim xeeb tswj chaw, rov tsim dua lub preloader.
Tsim daim npav SD daim duab.
Tsim koj lub Platform Custom, uas suav nrog SD flash card duab.
Xav txog kev tsim lub sijhawm ua haujlwm ib puag ncig ntawm koj lub Platform Custom rau siv nrog Intel FPGA Runtime Environment (RTE) rau OpenCL. Lub RTE version ntawm koj lub Platform Custom tsis suav nrog cov ntaub ntawv kho vajtse thiab SD daim npav daim duab. Qhov Kev Cai Platform no thauj mus rau SoC FPGA system kom tso cai rau cov ntawv thov ua haujlwm. Hauv qhov sib piv, SDK version ntawm Kev Cai Platform yog qhov tsim nyog rau SDK los suav nrog OpenCL kernels.
Tswv yim: Koj tuaj yeem siv SDK version ntawm koj qhov Kev Cai Platform rau RTE. Txuag
qhov chaw, tshem tawm daim npav SD daim duab los ntawm RTE version ntawm koj lub Platform Custom.
Kuaj koj lub Platform Custom.
Xa mus rau Kev Ntsuam Xyuas Kev Tsim Kho Kho vajtse ntu ntawm Intel FPGA SDK rau OpenCL Custom Platform Toolkit User Guide rau cov lus qhia ntxiv.

Txuas txuas

Kuaj Kev Tsim Kho Kho vajtse
Quartus Prime Incremental Compilation rau Hierarchical thiab Team-based Design

Tsim kom muaj kev ruaj ntseg Timing Flow
General Quality of Results Considerations for Exported Board Partition

1.2.1 Hloov kho lub Ported Reference Platform
Nyob rau hauv tam sim no version ntawm Cyclone V SoC Development Kit Reference Platform, HPS block yog nyob rau hauv qhov kev faib tawm uas txhais tag nrho cov logic tsis yog. Txawm li cas los xij, koj tsis tuaj yeem xa tawm HPS ua ib feem ntawm .qxp file. Txhawm rau hloov kho qhov Custom Platform uas koj tau hloov kho los ntawm c5soc yav dhau los, siv QXP khaws cia ntws, hloov kho SD flash daim duab kom tau txais qhov chaw khiav haujlwm tshiab, thiab hloov kho board_spec.xml file pab kom automigration.
Lub Altera® SDK rau OpenCL version 14.1 thiab tshaj qhov kev sojntsuam board_spec.xml file rau board cov ntaub ntawv, thiab siv tsis siv neeg hloov tshiab. Vim koj hloov lub
tsim los ntawm kev siv QXP khaws cia ntws, koj yuav tsum hloov kho board_spec.xml file rau nws hom ntawv nyob rau hauv lub tam sim no version. Hloov kho cov file tso cai rau SDK kom paub qhov txawv ntawm qhov tsis tau khaws cia rau Kev Cai Platforms thiab QXP-based Custom Platforms tam sim no. Xa mus rau Kev Cai Platform Automigration rau Forward Compatibility hauv Intel FPGA SDK rau OpenCL Custom Platform Toolkit Tus Neeg Siv Qhia kom paub ntau ntxiv.

Txhawm rau ua raws li QXP khaws cia ntws hauv Cyclone V SoC FPGA kho vajtse tsim uas tau muab los ntawm ib qho dhau los ntawm c5soc, ua cov kauj ruam hauv qab no los tsim ib qho kev faib tawm kom tsis suav HPS los ntawm .qxp file:
ib. Ua ntej tsim ib qho kev faib tawm ib ncig ntawm lub logic tsis yog, tsim ib qho kev faib ib ncig ntawm HPS hauv .qsf Quartus Prime Chaw File.
Rau example:
# Manually faib cov piv txwv uas ua qauv HPS-dedicated I/O set_instance_assignment -name PARTITION_HIERARCHY borde_18261 -to “system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps_0:hps_0|system_hp_0_sface_ system_acl_iface_hps_0_hps_io_border:border" -section_id "system_acl_iface_hps_0_hps_io_border: ciam teb"
# Teem muab faib ua hom HPS_PARTITION kom ua tiav los ntawm tus so ntawm Quartus
set_global_assignment -name PARTITION_TYPE HPS_PARTITION -section_id "system_acl_iface_hps_0_hps_io_border: ciam teb"
quartus_cdb top -c sab saum toj
–incremental_compilation_export=acl_iface_partition.qxp
–incremental_compilation_export_partition_name=acl_iface_partition
-incremental_compilation_export_post_synth = rau
-incremental_compilation_export_post_fit = rau
-incremental_compilation_export_routing = rau
-incremental_compilation_export_flatten = tawm
Tom qab koj tshem tawm HPS los ntawm kev muab faib, koj tuaj yeem import .qxp file thiab sau koj tus qauv tsim.
Hloov kho daim npav SD daim npav nrog cov ntawv tam sim no ntawm Intel FPGA RTE rau OpenCL los ntawm kev ua cov haujlwm hauv qab no:
a. Mount lub file faib cov lus (fat32) thiab txuas ntxiv file system (ext3) partitions nyob rau hauv cov duab uas twb muaj lawm raws li lub voj-rov qab li. Rau cov lus qhia ntxaws, saib rau Kauj Ruam 2 hauv Kev Tsim SD Flash Card Duab.
b. Hauv /home/root/opencl_arm32_rte directory, tshem tawm cov files los ntawm yav dhau los version ntawm RTE.
c. Download tau thiab unpack tam sim no verison ntawm RTE rau hauv /home/root/opencl_arm32_rte directory.
d. Hauv /driver/version.h file ntawm koj qhov Kev Cai Platform, hloov kho ACL_DRIVER_VERSION txoj haujlwm rau . (rau example, 16.1.x, qhov twg 16.1 yog SDK verison, thiab x yog tus tsav tsheb version uas koj tau teeb tsa).
e. Rov tsim kho tus tsav tsheb.
f. Rho tawm hardware folder(s) ntawm koj Custom Platform. Luam lub Custom Platform, nrog rau tus tsav tsheb tshiab, mus rau /home/root/opencl_arm_rte/board directory.
g. Luam the Altera.icd file los ntawm /home/root/opencl_arm32_rte directory thiab ntxiv rau /etc/OpenCL/vendors directory.
h. Tshem tawm thiab sim cov duab tshiab. Rau cov lus qhia ntxaws ntxaws, saib rau Kauj Ruam 8 txog 11 hauv Kev Tsim SD Flash Card Duab.

Txuas txuas

Tsim SD Flash Card Duab nyob rau nplooj 14
Koj kuj muaj cov kev xaiv los tsim ib tug tshiab SD flash card duab.
Kev cai Platform Automigration rau Forward Compatibility

1.3 Software Support for Shared Memory
Sib koom lub cev nco ntawm FPGA thiab CPU yog lub cim xeeb nyiam rau OpenCL kernels khiav ntawm SoC FPGAs. Vim tias FPGA nkag mus rau kev sib koom lub cev nco, uas tsis yog kev sib koom ua ke lub cim xeeb, nws tsis muaj kev nkag mus rau CPU nplooj ntawv cov lus uas qhia cov neeg siv virtual chaw nyob rau nplooj ntawv chaw nyob.
Nrog rau cov khoom siv kho vajtse, OpenCL kernels tau txais kev sib koom ua ke ntawm lub cev nco los ntawm kev sib txuas ncaj qha rau HPS DDR hard memory controller. Nrog rau cov software, kev txhawb nqa rau kev sib koom ua ke ntawm lub cev nco tau suav nrog cov kev xav hauv qab no:

Cov kev siv software ib txwm siv rau faib lub cim xeeb ntawm CPU (rau example, qhov ua haujlwm malloc() tsis tuaj yeem faib thaj chaw nco uas FPGA tuaj yeem siv.
Lub cim xeeb tias malloc() muaj nuj nqi faib ua ke nyob rau hauv qhov chaw nyob hauv lub cim xeeb virtual, tab sis cov nplooj ntawv hauv qab lub cev tsis zoo li yuav sib txuas ntawm lub cev. Yog li ntawd, tus tswv tsev yuav tsum muaj peev xwm faib cov cheeb tsam ntawm lub cev sib txuas. Txawm li cas los xij, lub peev xwm no tsis muaj nyob hauv cov neeg siv-qhov chaw siv ntawm Linux. Yog li ntawd, Linux ntsiav tsav tsheb yuav tsum ua qhov kev faib.
Lub OpenCL SoC FPGA Linux kernel tsav tsheb suav nrog mmap() ua haujlwm los faib cov kev sib koom ua ke ntawm lub cev nco thiab qhia nws rau hauv qhov chaw siv. mmap() muaj nuj nqi siv tus qauv Linux ntsiav hu dma_alloc_coherent() thov kom lub cev sib txuas nrog lub cim xeeb thaj tsam sib koom nrog ib lub cuab yeej.
Nyob rau hauv lub neej ntawd Linux ntsiav, dma_alloc_coherent() tsis faib lub cev sib txuas nrog ntau dua 0.5 megabytes (MB) loj. Txhawm rau tso cai dma_alloc_coherent() txhawm rau faib nyiaj ntau ntawm lub cev sib txuas ua ke, ua kom lub cim xeeb sib txuas (CMA) feature ntawm Linux kernel thiab tom qab ntawd rov ua dua lub Linux kernel.
Rau Cyclone V SoC Development Kit Reference Platform, CMA tswj 512 MB tawm ntawm 1 GB ntawm lub cev nco. Koj tuaj yeem nce lossis txo tus nqi no, nyob ntawm seb muaj pes tsawg lub cim xeeb sib koom uas daim ntawv thov xav tau. Lub dma_alloc_coherent() hu yuav tsis tuaj yeem faib tag nrho 512 MB ntawm lub cev-kev nco; Txawm li cas los xij, nws niaj hnub tuaj yeem tau txais kwv yees li 450 MB ntawm lub cim xeeb.

CPU tuaj yeem cache nco tias dma_alloc_coherent() hu rau faib. Tshwj xeeb, sau cov haujlwm los ntawm daim ntawv thov tswv tsev tsis pom rau OpenCL kernels. Lub mmap() ua haujlwm hauv OpenCL SoC FPGA Linux kernel tsav tsheb kuj tseem muaj kev hu mus rau pgprot_noncached() lossis remap_pf_range() muaj nuj nqi los lov tes taw caching rau thaj tsam ntawm lub cim xeeb meej meej.
Tom qab dma_alloc_coherent() muaj nuj nqi faib cov cim xeeb ntawm lub cev, mmap() ua haujlwm rov qab qhov chaw nyob virtual mus rau qhov pib ntawm qhov ntau, uas yog qhov chaw nyob ntawm lub cim xeeb uas koj faib. Daim ntawv thov tswv tsev xav kom qhov chaw nyob virtual no nkag mus rau lub cim xeeb. Ntawm qhov tod tes, OpenCL kernels xav tau lub cev chaw nyob. Tus neeg tsav tsheb Linux kernel khaws cia ntawm qhov chaw nyob virtual-rau-lub cev. Koj tuaj yeem qhia qhov chaw nyob ntawm lub cev uas mmap() rov qab mus rau qhov chaw nyob ntawm lub cev los ntawm kev ntxiv cov lus nug rau tus tsav tsheb.
Lub aocl_mmd_shared_mem_alloc() MMD daim ntawv thov programming interface (API) hu suav nrog cov lus nug hauv qab no:
ib. mmap() ua haujlwm uas faib lub cim xeeb thiab xa rov qab qhov chaw nyob virtual.
b. Cov lus nug ntxiv uas qhia qhov chaw nyob virtual rov qab mus rau qhov chaw nyob hauv lub cev.
Lub aocl_mmd_shared_mem_alloc() MMD API hu ces xa ob qhov chaw nyob
-qhov chaw nyob xa rov qab yog qhov chaw nyob virtual, thiab qhov chaw nyob ntawm lub cev mus rau device_ptr_out.
Nco tseg: Tus neeg tsav tsheb tsuas tuaj yeem qhia qhov chaw nyob virtual uas mmap() ua haujlwm rov qab mus rau qhov chaw nyob hauv lub cev. Yog tias koj thov rau qhov chaw nyob ntawm lub cev ntawm lwm tus taw tes virtual, tus tsav tsheb rov qab tus nqi NULL.

Ceeb toom: Intel FPGA SDK rau OpenCL cov tsev qiv ntawv runtime xav tias qhov kev sib koom ua ke yog thawj lub cim xeeb teev nyob rau hauv board_spec.xml file. Hauv lwm lo lus, qhov chaw nyob ntawm lub cev uas tus neeg tsav tsheb Linux tau txais dhau los ua Avalon® chaw nyob uas OpenCL kernel hla mus rau HPS SDRAM.
Hais txog lub tsev qiv ntawv runtime, siv clCreateBuffer() hu los faib cov cim xeeb sib koom ua ib qho khoom siv tsis raws li hauv qab no:

Rau ob-DDR board variant nrog ob qho tib si sib koom thiab tsis sib koom nco, clCreateBuffer() faib cov cim xeeb sib koom yog tias koj teev tus chij CL_MEM_USE_HOST_PTR. Siv lwm tus chij ua rau clCreateBuffer() faib tsis nyob rau hauv lub cim xeeb tsis sib koom.
Rau ib-DDR board variant nrog tsuas yog sib koom nco, clCreateBuffer() faib cov cim xeeb sib koom tsis hais tus chij twg koj teev.
Tam sim no, 32-ntsis Linux kev txhawb nqa ntawm ARM CPU tswj hwm qhov sib koom nco kev txhawb nqa hauv SDK cov tsev qiv ntawv runtime. Hauv lwm lo lus, cov tsev qiv ntawv runtime tau muab tso ua ke rau lwm qhov chaw (example, x86_64 Linux lossis 64-ntsis Windows) tsis txhawb kev nco sib koom.
C5soc tsis tau siv ntau lub cim xeeb kom paub qhov txawv ntawm kev sib koom thiab tsis koom nrog lub cim xeeb rau cov laj thawj hauv qab no:
1. Keeb Kwm—Kev txhawb nqa kev nco tsis tau muaj nyob rau thaum pib kev txhawb nqa kev nco tau tsim.
2. Uniform interface-Vim OpenCL yog tus qauv qhib, Intel tswj kev sib xws ntawm cov neeg muag khoom siv computer sib txawv. Yog li ntawd, tib lub interface raws li lwm cov neeg muag khoom 'architectures yog siv los faib thiab siv kev sib koom ua ke.

1.4 FPGA Reconfiguration
Rau SoC FPGAs, CPU tuaj yeem hloov kho FPGA core ntaub yam tsis cuam tshuam rau CPU txoj haujlwm. FPGA Tus Thawj Tswj Kho vajtse thaiv uas hla HPS thiab cov tub ntxhais FPGA ua qhov kev teeb tsa. Lub Linux ntsiav suav nrog tus tsav tsheb uas ua kom yooj yim nkag mus rau FPGA Tus Thawj Tswj.

Rau view cov xwm txheej ntawm FPGA core, hu rau miv / sys / class / fpga / fpga0 / raws li txoj cai hais kom ua.
Intel FPGA SDK rau OpenCL qhov kev pab cuam muaj txiaj ntsig muaj nrog Cyclone V SoC Development Kit Reference Platform siv qhov kev sib txuas no los ua FPGA. Thaum reprogramming ib tug FPGA core nrog ib tug khiav CPU, qhov kev pab cuam qhov kev pab cuam ua tag nrho cov dej num hauv qab no:
1. Ua ntej reprogramming, lov tes taw txhua qhov txuas txuas ntawm FPGA thiab HPS, ob qho tib si H2F thiab LH2F txuas hniav.
Reenable cov choj no tom qab reprogramming tiav.
Ceeb toom: OpenCL system tsis siv FPGA-to-HPS (F2H) choj. Xa mus rau HPS-FPGA Interfaces seem hauv Cyclone V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual kom paub ntau ntxiv.
2. Xyuas kom meej tias qhov kev sib txuas ntawm FPGA thiab HPS DDR maub los yog neeg xiam thaum lub sijhawm rov ua dua.
3. Xyuas kom meej tias FPGA cuam tshuam ntawm FPGA yog neeg xiam oob qhab thaum lub sijhawm rov ua dua.
Tsis tas li ntawd, ceeb toom rau tus neeg tsav tsheb kom tsis lees txais kev cuam tshuam los ntawm FPGA thaum lub sijhawm rov ua dua.

Nrog rau lub hauv paus code ntawm qhov kev pab cuam siv hluav taws xob kom paub meej txog kev siv tiag tiag.

Ceeb toom: Tsis txhob hloov qhov kev teeb tsa ntawm HPS DDR maub los thaum CPU khiav.
Ua li no tuaj yeem ua rau muaj kev ua yuam kev tuag vim tias koj tuaj yeem hloov DDR tus tswj kev teeb tsa thaum muaj kev nco zoo los ntawm CPU. Qhov no txhais tau hais tias thaum CPU tab tom khiav, koj yuav tsis reprogram FPGA core nrog ib tug duab uas siv HPS DDR nyob rau hauv ib tug txawv configuration.
Nco ntsoov tias OpenCL system, thiab Golden Hardware siv tsim muaj nrog Intel SoC FPGA Embedded Design Suite (EDS), teeb tsa HPS DDR rau hauv ib qho 256-ntsis hom.
CPU system qhov chaw xws li ceg kwv yees lossis nplooj ntawv cov lus ua ntej yuav muab DDR cov lus txib txawm tias nws zoo li tsis muaj dab tsi khiav ntawm CPU.
Yog li ntawd, lub sijhawm khau raj tsuas yog lub sijhawm muaj kev nyab xeeb los teeb tsa HPS DDR maub los teeb tsa.
Qhov no kuj txhais tau hais tias U-boot yuav tsum muaj binary raw file (.rbf) duab los thauj rau hauv nco. Txwv tsis pub, koj tuaj yeem ua rau HPS DDR nrog cov chaw nres nkoj tsis siv ntawm FPGA thiab tom qab ntawd muaj peev xwm hloov qhov chaw nres nkoj teeb tsa tom qab. Vim li no, OpenCL Linux kernel tsav tsheb tsis suav nrog cov logic tsim nyog los teeb tsa HPS DDR tswj kev teeb tsa.
Lub SW3 dual nyob rau hauv-kab pob (DIP) hloov ntawm Cylone V SoC Development Kit tswj daim ntawv xav tau ntawm daim duab .rbf (uas yog, seb qhov file yog compressed thiab/los yog encrypted). C5soc, thiab Golden Hardware Reference Design muaj nrog SoC EDS, suav nrog cov duab compressed tab sis unencrypted .rbf. SW3 DIP hloov chaw tau piav qhia hauv Intel FPGA SDK rau OpenCL Cyclone V SoC Tau Txais Kev Qhia Pib phim qhov .rbf duab teeb tsa.

Txuas txuas

HPS-FPGA interfaces
Configuring SW3 Hloov

1.4.1 FPGA System Architecture Paub meej
Kev them nyiaj yug rau Cyclone V SoC Development Kit Reference Platform yog raws li Stratix® V Reference Platform (s5_ref), muaj nrog Intel FPGA SDK rau OpenCL.
Lub koom haum tag nrho ntawm c5soc Qsys system thiab cov neeg tsav tsheb kernel zoo ib yam li cov hauv s5_ref.
Cov nram qab no FPGA core Cheebtsam yog tib yam nyob rau hauv ob qho tib si c5soc thiab s5_ref:

VERSION_ID thaiv
So mechanism

Memory bank divider
Cache snoop interface
Kernel moos

Tswj kev nkag nkag (CRA) blocks

1.5 Tsim SD Flash Card Duab
Vim tias Cyclone V SoC FPGA yog tag nrho cov txheej txheem ntawm lub nti, koj yog lub luag haujlwm xa tag nrho cov ntsiab lus ntawm lub kaw lus. Intel xav kom koj xa nws hauv daim ntawv ntawm SD daim npav daim duab. Intel FPGA SDK rau OpenCL cov neeg siv tuaj yeem sau cov duab rau hauv daim npav micro SD thiab SoC FPGA pawg thawj coj tau npaj siv.
Hloov kho daim npav SD daim npav uas twb muaj lawm nyob rau nplooj 13
Intel xav kom koj tsuas hloov cov duab muaj nrog Cyclone V SoC Development Kit Reference Platform. Koj kuj muaj cov kev xaiv los tsim ib tug tshiab SD flash card duab.
Tsim SD Flash Card Duab nyob rau nplooj 14
Koj kuj muaj cov kev xaiv los tsim ib tug tshiab SD flash card duab.

1.5.1 Hloov kho daim npav SD uas twb muaj lawm
Intel xav kom koj hloov kho cov duab uas muaj nrog Cyclone V SoC
Development Kit Reference Platform. Koj kuj muaj cov kev xaiv los tsim ib tug tshiab SD flash card duab.
C5soc linux_sd_card_image.tgz duab file muaj nyob rau hauv ALTERAOCLSDKROOT/board/c5soc directory, qhov twg ALTERAOCLSDKROOT taw qhia rau txoj hauv kev ntawm Intel FPGA SDK rau OpenCL's installation directory.

Nco ntsoov: Txhawm rau hloov kho daim duab SD flash card, koj yuav tsum muaj cov cai hauv paus lossis sudo.

Txhawm rau decompress $ALTERAOCLSDKROOT/board/c5soc/linux_sd_card_image.tgz file, khiav tar xvfzlinux_sd_card_image.tgz hais kom ua.
Sau cov hello_world OpenCL example tsim siv koj qhov kev txhawb nqa Platform. Rename lub .rbf file tias Intel FPGA SDK rau OpenCL Offline Compiler generates li opencl.rbf, thiab muab tso rau ntawm fat32 muab faib rau hauv daim npav SD daim duab.
You can download the hello_world example tsim los ntawm OpenCL Design Examples nplooj ntawv ntawm Altera webqhov chaw.

Muab qhov .rbf file rau hauv fat32 muab faib ntawm daim npav flash duab.
Nco ntsoov: Lub fat32 muab faib yuav tsum muaj ob lub zImage file thiab rbf file. Tsis muaj .rbf file, qhov yuam kev tuag yuav tshwm sim thaum koj ntxig tus tsav tsheb.
Tom qab koj tsim daim npav SD daim duab, sau nws mus rau ib daim npav micro SD los ntawm kev hu rau cov lus txib hauv qab no: sudo dd yog =/path/to/sdcard/image.bin of =/dev/sdcard
Txhawm rau kuaj koj daim npav SD daim duab, ua cov haujlwm hauv qab no:
a. Ntxig lub micro SD flash card rau hauv SoC FPGA board.
b. Fais fab lub rooj tsavxwm.
c. Hu rau aocl diagnose utility command.

1.5.2 Tsim SD daim npav duab
Koj kuj muaj cov kev xaiv los tsim ib tug tshiab SD flash card duab. Cov lus qhia dav dav ntawm kev tsim daim npav SD daim npav tshiab thiab rov tsim kho daim npav SD daim npav uas twb muaj lawm muaj nyob rau ntawm GSRD v14.0.2 - SD Card nplooj ntawv ntawm RocketBoards.org webqhov chaw.
Cov kauj ruam hauv qab no piav qhia txog cov txheej txheem tsim cov duab linux_sd_card_image.tgz los ntawm Golden System Reference Design (GSRD) SD flash card duab:
Nco tseg:
Txhawm rau tsim cov duab los ntawm cov duab c5soc, ua txhua yam haujlwm uas tau teev tseg hauv cov txheej txheem no.

Rub tawm thiab nthuav tawm GSRD SD daim npav daim npav duab version 14.0 los ntawm Rocketboards.org.
Mount lub file faib cov lus (fat32) thiab txuas ntxiv file system (ext3) partitions nyob rau hauv daim duab no raws li lub voj-rov qab li. Txhawm rau txhim kho qhov muab faib, ua cov kauj ruam hauv qab no:
ib. Txiav txim siab qhov pib byte ntawm kev faib tawm hauv daim duab los ntawm kev hu rau /sbin/fdisk -lu image_file lus txib.
Rau example, muab faib tus naj npawb 1 ntawm hom W95 FAT muaj block offset ntawm 2121728. Nrog 512 bytes ib block, byte offset yog 512 bytes x 2121728 = 1086324736 bytes.
b. Txheeb xyuas lub voj voog dawb (rau example, /dev/loop0) los ntawm ntaus ntawv losetup -f hais kom ua.
c. Piv txwv tias /dev/loop0 yog lub voj voog dawb, muab koj daim npav flash duab rau lub voj thaiv lub cuab yeej los ntawm kev hu rau losetup /dev/loop0 image_file -0 1086324736 ib.
d. Mount lub voj ntaus ntawv los ntawm kev hu rau mount /dev/loop0 /media/disk1 hais kom ua.
Hauv daim duab file, /media/disk1 tam sim no yog mounted fat32 muab faib.
e. Rov ua cov kauj ruam a rau d rau ext3 muab faib.

Rub tawm Cyclone V SoC FPGA version ntawm Intel FPGA Runtime Ib puag ncig rau OpenCL pob los ntawm Download Center ntawm Altera webqhov chaw.
ib. Nyem lub Download khawm ntawm Quartus Prime software ib tsab.
b. Qhia meej qhov tso tawm version, lub operating system, thiab cov txheej txheem rub tawm.
c. Nyem qhov Ntxiv Software tab, thiab xaiv mus download tau Intel FPGA
Runtime Ib puag ncig rau OpenCL Linux Cyclone V SoC TGZ.
d. Tom qab koj rub tawm aocl-rte- .arm32.tgz file, unpack nws
ib daim ntawv teev npe uas koj muaj.
Muab lub unpacked aocl-rte- .arm32 directory rau hauv /home/root/opencl_arm32_rte directory ntawm ext3 muab faib ntawm daim duab file.
Rho tawm cov ntaub ntawv kho vajtse ntawm koj lub Platform Custom, thiab tom qab ntawd tso lub Custom Platform rau hauv pawg thawj coj saib ntawm /home/root/ opencl_arm32_rte.

Tsim cov init_opencl.sh file hauv /home/root directory nrog cov ntsiab lus hauv qab no: export ALTERAOCLSDKROOT=/home/root/opencl_arm32_rte export AOCL_BOARD_PACKAGE_ROOT=$ALTERAOCLSDKROOT/board/ export PATH=$ALTERAOCLSDKROOT/bin:$PATH export LD_LIBRARY_PATH=$ALTERAOCLSDKROOT/host/arm32/lib:$LD_LIBRARY_PATH insmod $AOCL_BOARD_PACKAGE_ROOT/driver/aclsoc_drv.ko
Tus neeg siv SDK khiav qhov chaw ./init_opencl.sh kom thauj khoom ib puag ncig hloov pauv thiab OpenCL Linux kernel tsav.
Yog tias koj xav tau hloov kho lub preloader, DTS files, lossis Linux ntsiav, koj xav tau arm-linux-gnueabihf-gcc compiler los ntawm SoC EDS. Ua raws li cov lus qhia tau teev tseg hauv Intel SoC FPGA Embedded Design Suite User Guide kom tau txais cov software, rov ua dua, thiab hloov kho qhov cuam tshuam. files ntawm mounted fat32 muab faib.
Nco ntsoov: Nws yog qhov zoo tshaj plaws uas koj yuav tsum tau hloov kho lub preloader yog tias koj lub Platform Kev Cai muaj kev siv tus pin sib txawv dua li cov hauv c5soc.
Nco ntsoov: Yog tias koj rov ua dua lub Linux kernel, rov ua dua lub Linux kernel tsav nrog tib lub Linux kernel qhov chaw files. Yog tias muaj qhov tsis sib haum xeeb ntawm Linux kernel tsav tsheb thiab Linux ntsiav, tus tsav tsheb yuav tsis thauj khoom. Tsis tas li, koj yuav tsum ua kom CMA.
Xa mus rau Recompiling Linux Kernel kom paub ntau ntxiv.
Sau cov hello_world OpenCL example tsim siv koj qhov kev txhawb nqa Platform. Rename lub .rbf file tias Intel FPGA SDK rau OpenCL Offline Compiler generates li opencl.rbf, thiab muab tso rau ntawm fat32 muab faib rau hauv daim npav SD daim duab.
You can download the hello_world example tsim los ntawm OpenCL Design Examples nplooj ntawv ntawm Altera webqhov chaw.
9. Tom qab koj khaws tag nrho cov tsim nyog files rau ntawm daim npav flash duab, thov cov lus txib hauv qab no:
ib. synchronization
b. unmount /media/disk1
c. tshem tawm qhov twg yog lub npe directory koj siv rau mounting ext3 muab faib nyob rau hauv 3 ntawm nplooj 3 (rau ext2ample, /media/disk2).
d. losetup -d /dev/loop0
e. losetup -d /dev/loop1

Compress SD flash card duab los ntawm invoking cov lus txib hauv qab no: tar cvfz .tgz linux_sd_card_image
Xa lub .tgz file nyob rau hauv lub hauv paus directory ntawm koj Custom Platform.
Txhawm rau kuaj koj daim npav SD daim duab, ua cov haujlwm hauv qab no:
ib. Sau cov duab uas tsis tau muab tso rau hauv daim npav micro SD.
b. Ntxig lub micro SD flash card rau hauv SoC FPGA board.
c. Fais fab lub rooj tsavxwm.
d. Hu rau aocl diagnose utility command.

Txuas txuas

Intel SoC FPGA Embedded Design Suite User Guide
OpenCL Design Examples nplooj ntawv ntawm Altera webqhov chaw

Recompiling Linux Kernel ntawm nplooj 16
Txhawm rau pab CMA, koj yuav tsum xub rov ua dua lub Linux ntsiav.
Nug Lub Npe Lub Npe ntawm Koj Lub Rooj Tswjhwm Saib Xyuas FPGA (kev kuaj mob)

1.6 Compiling Linux Kernel rau Cyclone V SoC FPGA
Ua ntej khiav OpenCL daim ntawv thov ntawm Cyclone V SoC FPGA board, koj yuav tsum muab tso ua ke ntawm Linux ntsiav qhov chaw, thiab muab tso ua ke thiab nruab OpenCL Linux kernel tsav.

Recompiling Linux Kernel ntawm nplooj 16
Txhawm rau pab CMA, koj yuav tsum xub rov ua dua lub Linux ntsiav.
Muab tso ua ke thiab txhim kho OpenCL Linux Kernel Tsav Tsheb ntawm nplooj ntawv 17 Sau cov OpenCL Linux ntsiav tsav tawm tsam cov ntsiab lus sau.

1.6.1 Recompiling Linux Kernel
Txhawm rau pab CMA, koj yuav tsum xub rov ua dua lub Linux ntsiav.

Nyem rau GSRD v14.0 - Sib sau Linux txuas ntawm nplooj ntawv Resources ntawm RocketBoards.org website kom nkag mus rau cov lus qhia ntawm rub tawm thiab rov tsim kho Linux kernel qhov chaws.
Rau siv nrog ™ Intel FPGA SDK rau OpenCL, qhia meej socfpga-3.13-rel14.0 raws li .
Nco tseg: Lub tsev txheej txheem tsim cov arch/arm/configs/socfpga_defconfig file. Qhov no file qhia qhov chaw rau socfpga default configuration.
Ntxiv cov kab hauv qab no rau hauv qab ntawm arch/arm/configs/socfpga_defconfig file.
CONFIG_MEMORY_ISOLATION=y
CONFIG_CMA = y
CONFIG_DMA_CMA = y
CONFIG_CMA_DEBUG=y
CONFIG_CMA_SIZE_MBYTES=512
CONFIG_CMA_SIZE_SEL_MBYTES=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
CONFIG_CMA_SIZE_MBYTES tus nqi teeb tsa teeb tsa lub siab tshaj plaws ntawm tag nrho cov cim ntawm lub cev sib txuas muaj. Koj tuaj yeem nce tus nqi no yog tias koj xav tau ntau lub cim xeeb.
Nco ntsoov: Tag nrho cov nqi ntawm lub cev nco muaj rau ARM processor ntawm SoC FPGA board yog 1 GB. Intel tsis pom zoo kom koj teem CMA tus thawj tswj ze rau 1 GB.

Khiav lub make mrproper hais kom ntxuav cov configuration tam sim no.
Khiav qhov ua ARCH=arm socfpga_deconfig hais kom ua.
ARCH = caj npab qhia tias koj xav teeb tsa ARM architecture.
socfpga_defconfig qhia tias koj xav siv lub default socfpga configuration.
Khiav cov export CROSS_COMPILE=arm-linux-gnueabihf- hais kom ua.
Cov lus txib no tau teeb tsa CROSS_COMPILE ib puag ncig hloov pauv kom qhia meej cov lus ua ntej ntawm cov cuab yeej xav tau.

Khiav qhov ua ARCH = caj npab zImage hais kom ua. Cov duab tau tshwm sim muaj nyob rau hauv arch/arm/boot/zImage file.
Tso lub zImage file rau hauv fat32 muab faib ntawm daim npav flash duab. Rau cov lus qhia ntxaws, saib rau Cyclone V SoC FPGA-specific GSRD User Manual ntawm Rocketboards.org.
Nco tseg: Txhawm rau kom raug ntxig rau OpenCL Linux ntsiav tsav tsheb, ua ntej thauj khoom SDKgenerated.rbf file mus rau FPGA.
Tsim cov .rbf file, compile ib SDK tsim example nrog Cyclone V SoC Development Kit Reference Platform raws li lub hom phiaj Custom Platform.
9. Muab qhov .rbf file rau hauv fat32 muab faib ntawm daim npav flash duab.
Ceeb Toom: Lub fat32 muab faib yuav tsum muaj ob lub zImage file thiab rbf file. Tsis muaj .rbf file, qhov yuam kev tuag yuav tshwm sim thaum koj ntxig tus tsav tsheb.

Ntxig lub programmed micro SD daim npav, uas muaj daim npav SD daim duab uas koj tau hloov kho lossis tsim ua ntej, rau hauv Cyclone V SoC Development Kit thiab tom qab ntawd muab lub zog rau SoC FPGA board.
Txheeb xyuas qhov version ntawm lub Linux ntsiav tau nruab los ntawm kev khiav lub uname -r hais kom ua.
Txhawm rau txheeb xyuas tias koj ua kom CMA ua tiav hauv cov ntsiav, nrog SoC FPGA pawg thawj coj saib xyuas, khiav cov lus txib grep init_cma / proc/kallsyms.
CMA yog enabled yog tias cov zis tsis yog khoob.

Txhawm rau siv lub Linux kernel rov qab nrog SDK, suav thiab nruab Linux ntsiav tsav.

Txuas txuas

Golden System Reference Design (GSRD) Cov Neeg Siv Phau Ntawv Qhia

Tsim SD Flash Card Duab nyob rau nplooj 13
Vim tias Cyclone V SoC FPGA yog tag nrho cov txheej txheem ntawm lub nti, koj yog lub luag haujlwm xa tag nrho cov ntsiab lus ntawm lub kaw lus.

1.6.2 Sau thiab txhim kho OpenCL Linux Kernel Driver
Sau cov OpenCL Linux kernel tsav tawm tsam cov ntaub ntawv sau ua ke.

Tus tsav tsheb qhov chaw muaj nyob rau hauv Cyclone V SoC FPGA version ntawm Intel FPGA Runtime Ib puag ncig rau OpenCL. Tsis tas li ntawd, xyuas kom meej tias koj tau thauj khoom Intel FPGA SDK rau OpenCL-generated .rbf file rau hauv FPGA los tiv thaiv kev teeb tsa tsis raug ntawm Linux ntsiav module.

Rub tawm Cyclone V SoC FPGA version ntawm Intel FPGA Runtime Ib puag ncig rau OpenCL pob los ntawm Download Center ntawm Altera webqhov chaw.
ib. Nyem lub Download khawm ntawm Quartus Prime software ib tsab.
b. Qhia meej qhov tso tawm version, lub operating system, thiab cov txheej txheem rub tawm.
c. Nyem qhov Ntxiv Software tab, thiab xaiv mus download tau Intel FPGA
Runtime Ib puag ncig rau OpenCL Linux Cyclone V SoC TGZ.
d. Tom qab koj rub tawm aocl-rte- .arm32.tgz file, unpack nws
ib daim ntawv teev npe uas koj muaj.
Qhov chaw tsav tsheb yog nyob rau hauv aocl-rte- .arm32/board/c5soc/ tsav tsheb directory.
Txhawm rau rov ua dua OpenCL Linux kernel tsav tsheb, teeb tsa tus nqi KDIR hauv tus tsav tsheb uafile mus rau cov ntawv teev npe uas muaj Linux kernel qhov chaw files.
Khiav qhov kev xa tawm CROSS_COMPILE=arm-linux-gnueabihf- hais kom ua los qhia cov npe ntawm koj cov cuab yeej cuab tam.

Khiav cov lus txib kom huv.
Khiav cov lus txib kom tsim cov aclsoc_drv.ko file.
Hloov cov npe opencl_arm32_rte mus rau Cyclone V SoC FPGA pawg thawj coj saib.
Ua haujlwm scp -r root@koj-ipaddress: cov lus txib tso lub sijhawm ua haujlwm ib puag ncig hauv / tsev / hauv paus directory.

Khiav cov ntawv init_opencl.sh uas koj tsim thaum koj tsim SD cardimage.
Hu rau aocl diagnose utility command. Cov cuab yeej kuaj mob yuav rov qab tau qhov tshwm sim dhau tom qab koj khiav init_opencl.sh ua tiav.

1.7 Paub Qhov Teeb Meem
Tam sim no, muaj qee qhov kev txwv ntawm kev siv Intel FPGA SDK rau OpenCL nrog Cyclone V SoC Development Kit Reference Platform.

Koj tsis tuaj yeem hla tus neeg muag khoom thiab cov npe pawg thawj coj qhia los ntawm CL_DEVICE_VENDOR thiab CL_DEVICE_NAME cov hlua ntawm clGetDeviceInfo() hu.
Yog tias tus tswv tsev faib lub cim xeeb tas li hauv kev sib koom DDR (uas yog, HPS DDR) thiab nws hloov kho lub cim xeeb tas li tom qab ua tiav cov ntsiav, cov ntaub ntawv hauv lub cim xeeb yuav dhau los. Qhov teeb meem no tshwm sim vim FPGA tub ntxhais tsis tuaj yeem snoop ntawm CPU-rau-HPS DDR kev lag luam.
Txhawm rau tiv thaiv cov kernel tom ntej los ntawm kev nkag mus rau cov ntaub ntawv dhau los, siv ib qho ntawm cov haujlwm hauv qab no:
• Tsis txhob hloov lub cim xeeb tas li tom qab nws pib.
• Yog tias koj xav tau ntau yam __ cov ntaub ntawv tsis tu ncua, tsim ntau lub cim xeeb tsis tu ncua.
• Yog tias muaj, faib lub cim xeeb tas li hauv FPGA DDR ntawm koj lub rooj tsav xwm nrawm.
SDK cov nqi hluav taws xob ntawm ARM tsuas yog txhawb nqa qhov kev pab cuam thiab kuaj xyuas cov khoom siv hluav taws xob.
Lub flash, nruab thiab tshem tawm cov lus txib siv hluav taws xob tsis siv rau Cyclone V SoC Development Kit rau cov laj thawj hauv qab no:
ib. Kev teeb tsa hluav taws xob yuav tsum suav nrog aclsoc_drv Linux kernel tsav thiab pab nws ntawm SoC FPGA. Lub tshuab kev txhim kho yuav tsum tau ua qhov muab tso ua ke; Txawm li cas los xij, nws twb muaj Linux kernel qhov chaw rau SoC FPGA. Linux kernel qhov chaw rau lub tshuab kev loj hlob txawv ntawm cov rau SoC FPGA. Qhov chaw ntawm Linux kernel qhov chaw rau SoC FPGA zoo li tsis paub rau tus neeg siv SDK. Ib yam li ntawd, qhov kev tshem tawm siv hluav taws xob kuj tseem tsis muaj rau Cyclone V SoC Development Kit.
Tsis tas li ntawd, xa aclsoc_drv rau SoC pawg thawj coj saib yog qhov nyuaj vim tias qhov kev faib tawm ntawm Cyclone V SoC Development Kit tsis muaj Linux ntsiav suav nrog files los yog GNU Compiler Collection (GCC) compiler.
b. Lub flash utility yuav tsum tso ib .rbf file ntawm OpenCL tsim mus rau FAT32 muab faib ntawm micro SD daim npav. Tam sim no, qhov kev faib tawm no tsis tau teeb tsa thaum tus neeg siv SDK txhawb nqa lub rooj tsavxwm. Yog li, txoj hauv kev zoo tshaj plaws los hloov kho qhov muab faib yog siv lub flash card nyeem ntawv thiab lub tshuab txhim kho.

Thaum hloov ntawm Intel FPGA SDK rau OpenCL Offline Compiler executable files (.aocx) uas sib haum rau cov sib txawv pawg thawj coj sib txawv (uas yog, c5soc thiab c5soc_sharedonly), koj yuav tsum siv SDK qhov kev pab cuam hluav taws xob los thauj cov .aocx file rau lub rooj tsavxwm tshiab variant thawj zaug. Yog tias koj tsuas yog khiav daim ntawv thov tswv tsev siv lub rooj tsav xwm tshiab tab sis FPGA muaj cov duab los ntawm lwm lub rooj tsav xwm sib txawv, qhov yuam kev tuag yuav tshwm sim.
ua .qxp file tsis suav nrog cov haujlwm sib faib ua haujlwm vim tias Quartus Prime software tsis tu ncua raws sijhawm raws sijhawm ntawm qhov kev faib tawm no.
Thaum koj lub hwj chim rau lub rooj tsavxwm, nws qhov chaw nyob hauv media access control (MAC) yog teem rau tus lej random. Yog tias koj txoj cai LAN tsis tso cai rau tus cwj pwm no, teeb tsa MAC chaw nyob los ntawm kev ua cov haujlwm hauv qab no:
ib. Thaum U-Boot power-up, nias txhua tus yuam sij kom nkag mus rau U-Boot hais kom ua.
b. Ntaus setenv ethaddr 00:07:ed:00:00:03 ntawm qhov hais kom ua.
Koj tuaj yeem xaiv qhov chaw nyob MAC.
c. Ntaus cov lus txib saveenv.
d. Reboot lub rooj tsavxwm.

1.8 Cov ntaub ntawv kho dua tshiab
Table 1.
Cov Ntaub Ntawv Hloov Kho Keeb Kwm ntawm Intel FPGA SDK rau OpenCL Cyclone V SoC
Development Kit Reference Platform Porting Guide

Hnub tim	Version	Hloov
Maj - 17	2017.05.08	• Kho qhov tso tawm.
Lub Kaum Hli 2016	2016.10.31	•Rebranded Altera SDK rau OpenCL rau Intel FPGA SDK rau OpenCL. •Rebranded Altera Offline Compiler rau Intel FPGA SDK rau OpenCL Offline Compiler.
Maj - 16	2016.05.02	• Hloov cov lus qhia ntawm lub tsev thiab hloov kho daim duab SD flash card. • Hloov cov lus qhia txog kev rov ua dua Linux ntsiav thiab OpenCL Linux kernel tsav.
Kaum Ib Hlis-15	2015.11.02	• Kev tso tawm tu, thiab hloov pauv ntawm Quartus II mus rau Quartus Prime.
Maj - 15	15.0.0	•Nyob rau hauv FPGA Reconfiguration, tshem tawm cov lus qhia kom reprogram FPGA core nrog ib. rbf duab los ntawm kev hu tus miv filenpe>. rbf ua > /dev/ fpga0 hais kom ua vim qhov no tsis pom zoo.
Hlis ntuj nqeg-14	14.1.0	•Renamed cov ntaub ntawv raws li Altera Cyclone V SoC Development Kit Reference Platform Porting Guide. • Hloov kho cov khoom siv hluav taws xob reprogram rau qhov kev pab cuam aoclfilenpe> .aocx utility command. •Hloov kho cov cuab yeej kuaj mob rau kev kuaj mob aocl thiab aocl kuaj mob utility command. •Hloov kho cov txheej txheem nyob rau hauv Porting the Reference Platform to Your SoC Board seem kom suav nrog cov lus qhia ntawm kev thauj mus los thiab hloov kho c5soc pawg thawj coj saib kom tsim tau lub sijhawm-huv muab faib rau lub sijhawm lav kev kaw. •Inserted lub ncauj lus Hloov Kho Ported Reference Platform los piav qhia cov txheej txheem rau cov dej num hauv qab no: 1.Tsis suav nrog cov txheej txheem nyuaj (HPS) thaiv hauv pawg thawj coj saib 2.Hloov kho cov duab SD flash card •Hloov kho lub tsev ib daim SD Flash Card Duab seem. Pom zoo siv version 14.0 ntawm Golden System Reference Design (GSRD) duab raws li qhov pib taw tes es tsis txhob cov duab muaj nrog SoC Embedded Design Suite (EDS). •Hloov kho qhov Recompiling Linux Kernel thiab OpenCL Linux Kernel Driver seem: 1.Ntxiv cov lus qhia los teeb tsa CROSS COMPILE sib txawv. 2.Hloov cov lus txib uas koj khiav los xyuas kom meej tias CMA tau ua tiav.
Lub Xya Hli - 14	14.0.0	• Pib Tso Tawm.