intel FPGA SDK don Jagorar Mai amfani na OpenCL

FPGA SDK don OpenCL
Jagorar Mai Amfani

Farashin UG-OCL009
2017.05.08
An sabunta ta ƙarshe don Intel® Quartus® Prime Design Suite: 17.0

Yi rijista
Aika da martani

Abubuwan da ke ciki boye

1 Intel® FPGA SDK don OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Platform Porting Guide

2 Takardu / Albarkatu

2.1 Magana

3 Labarai masu alaka

Intel® FPGA SDK don OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Platform Porting Guide

V SoC Development Kit Reference Platform Guide Guide ya bayyana kayan aikin hardware da software na Intel Cyclone V SoC Development Kit Reference Platform (c5soc) don amfani tare da Intel Software Development Kit (SDK) don OpenCL Intel ® FPGA SDK don OpenCL ™ Intel Cyclone ® . Kafin ka fara, Intel yana ba da shawarar sosai cewa ka saba da abubuwan da ke cikin waɗannan takaddun:

Intel FPGA SDK don Buɗe Cyclone V SoC Jagoran Farawa

Intel FPGA SDK don Jagorar Mai Amfani da Kayan Aikin Kayan Aikin Kaya na Musamman na Buɗe
Littafin Jagorar Cyclone V na Na'ura, Juzu'i na 3: Jagorar Fasahar Tsarin Tsarin Hard Processor Bugu da kari, koma zuwa Cyclone V SoC Development Kit da SoC Embedded Design Suite shafi na Altera webshafin don ƙarin bayani. 1 2

Hankali: Intel yana ɗauka cewa kuna da zurfin fahimtar Intel FPGA SDK don Jagorar Mai amfani da Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Gida Jagorar Rarraba Kayayyakin Ci gaban Cyclone V SoC bai bayyana amfanin SDK's Custom Platform Toolkit don aiwatar da Platform na Musamman na Cyclone V SoC Development Kit. Yana bayyana kawai bambance-bambance tsakanin goyon bayan SDK akan Cyclone V SoC Development Kit da kuma ingantacciyar Intel FPGA SDK don OpenCL Custom Platform.

Hanyoyin haɗi

Intel FPGA SDK don OpenCL Cyclone V SoC Jagoran Farawa
Intel FPGA SDK don Jagorar Mai Amfani da Kayan Aikin Kayan Aikin Kaya na Musamman na Buɗe

Littafin Jagorar Cyclone V na Na'ura, juzu'i na 3: Littafin Bayanin Fasaha na Tsarin Hard Processor
Cyclone V SoC Development Kit da SoC Embedded Design Suite shafi akan Altera website

OpenCL da tambarin OpenCL alamun kasuwanci ne Apple Inc. da ake amfani da shi ta izinin Khronos Group™.
Intel FPGA SDK na OpenCL ya dogara ne akan ƙayyadaddun ƙayyadaddun Khronos da aka buga, kuma ya wuce Tsarin Gwajin Ƙarfafawa na Khronos. Ana iya samun matsayin yarda na yanzu a www.khronos.org/conformance.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus da Stratix kalmomi da tambura alamun kasuwanci ne na Intel Corporation ko rassan sa a Amurka da/ko wasu ƙasashe. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

1.1.1 Cyclone V SoC Development Kit Reference Platform Variants
Intel FPGA SDK na OpenCL Cyclone V SoC Development Kit Platform ya haɗa da bambance-bambancen allo guda biyu.

c5 soc
Wannan tsohon allo yana ba da dama ga bankunan ƙwaƙwalwar ajiya na DDR guda biyu. HPS DDR yana samun damar duka FPGA da CPU. FPGA DDR yana samun damar FPGA kawai.
c5soc_sharedonly jirgin
Wannan bambance-bambancen allon ya ƙunshi haɗin HPS DDR kawai. FPGA DDR ba ya samuwa. Wannan bambance-bambancen allo ya fi dacewa da yanki saboda ƙarancin kayan aikin da ake buƙata don tallafawa bankin ƙwaƙwalwar ajiya na DDR ɗaya. Kwamitin c5soc_sharedonly shima kyakkyawan dandamali ne na samfuri don hukumar samarwa ta ƙarshe tare da bankin ƙwaƙwalwar ajiyar DDR guda ɗaya.
Don ƙaddamar da wannan bambance-bambancen allon lokacin tattara kernel na OpenCL, haɗa da zaɓin -board c5soc_sharedonly a cikin umarnin aoc ɗin ku.
Don ƙarin bayani akan allo zaɓi na umarnin aoc, koma zuwa Intel FPGA SDK don Jagorar Shirye-shiryen OpenCL.

Hanyoyin haɗi
Haɗa Kernel don takamaiman Hukumar FPGA (- allo )
1.1.2 Abun ciki na Cyclone V SoC Development Kit Platform
Cyclone V SoC Development Reference Platform ya ƙunshi abubuwa masu zuwa files da kundayen adireshi:

File ko Directory	Bayani
allon_env.xml	Harshen Alamar Haɗi (XML) file wanda ke bayyana c5soc zuwa Intel FPGA SDK don OpenCL.
linux_sd_card_image.tgz	Hoton katin flash ɗin da aka matse file wanda ya ƙunshi duk abin da mai amfani da SDK ke buƙata don amfani da Cyclone V SoC Development Kit tare da SDK.
Farashin 32	Littafin da ya ƙunshi mai zuwa:

1.1.3 Abubuwan da suka dace na Cyclone V SoC Development Kit

Lissafin da ke gaba yana haskaka abubuwan haɗin Cyclone V SoC Development Kit da fasali waɗanda suka dace da Intel FPGA SDK don OpenCL:

Dual-core ARM Cortex-A9 CPU yana gudana Linux 32-bit.

Babban bas ɗin eXtensible Interface (AXI) tsakanin HPS da masana'anta na FPGA.
Masu sarrafa ƙwaƙwalwar ajiya na DDR guda biyu masu taurara, kowanne yana haɗi zuwa 1 gigabyte (GB) DDR3 SDRAM.
- Mai sarrafa DDR ɗaya yana samun dama ga ainihin FPGA kawai (wato FPGA DDR).
- Sauran mai sarrafa DDR yana samun dama ga HPS da FPGA (wato, HPS DDR). Wannan mai sarrafa da aka raba yana ba da damar raba ƙwaƙwalwar ajiya kyauta tsakanin CPU da ainihin FPGA.

CPU na iya sake saita masana'anta na FPGA.

1.1.3.1 Cyclone V SoC Development Kit Reference Platform Manufofin ƙira da Yanke shawara Intel tushen aiwatar da Cyclone V SoC Development Kit Platform akan manufofin ƙira da yanke shawara da yawa. Intel yana ba da shawarar ku yi la'akari da waɗannan manufofin da yanke shawara lokacin da kuke jigilar wannan Platform na Magana zuwa hukumar SoC FPGA ku.
A ƙasa akwai manufofin ƙira c5soc:

Bayar da mafi girman yiwuwar bandwidth tsakanin kwaya akan FPGA da tsarin ƙwaƙwalwar ajiya na DDR.
Tabbatar cewa ƙididdigewa akan FPGA (wato, OpenCL kernels) baya tsoma baki tare da wasu ayyukan CPU waɗanda zasu iya haɗawa da kayan aikin sabis.

Bar yawancin albarkatun FPGA gwargwadon yuwuwa don ƙididdige kwaya maimakon abubuwan haɗin keɓancewa.

A ƙasa akwai yanke shawarar ƙira masu girma waɗanda ke haifar da kai tsaye sakamakon ƙirar ƙirar Intel:

Platform Reference kawai yana amfani da masu sarrafa ƙwaƙwalwar ajiya na DDR mai ƙarfi tare da daidaitawa mai yuwuwa (bit 256).
FPGA yana sadarwa tare da mai sarrafa ƙwaƙwalwar ajiya na HPS DDR kai tsaye, ba tare da haɗa bas ɗin AXI da maɓallan L3 a cikin HPS ba. Sadarwar kai tsaye tana ba da mafi kyawun bandwidth mai yuwuwa zuwa DDR, kuma tana kiyaye ƙididdigar FPGA daga tsoma baki tare da sadarwa tsakanin CPU da kewayenta.
Scatter-gather kai tsaye damar žwažwalwar ajiya (SG-DMA) baya cikin mahangar FPGA. Maimakon canja wurin bayanai masu yawa tsakanin tsarin ƙwaƙwalwar DDR, adana bayanan a cikin HPS DDR da aka raba. Samun kai tsaye zuwa ƙwaƙwalwar ajiyar CPU ta FPGA ya fi DMA inganci. Yana adana albarkatun kayan masarufi (wato, yankin FPGA) kuma yana sauƙaƙe direban kernel na Linux.
Gargadi: Canja wurin ƙwaƙwalwar ajiya tsakanin tsarin HPS DDR da aka raba da kuma tsarin DDR wanda ke da isa ga FPGA kawai yana jinkirin gaske. Idan ka zaba
canja wurin ƙwaƙwalwar ajiya ta wannan hanya, yi amfani da shi don ƙananan adadin bayanai kawai.
Mai watsa shiri da na'urar suna yin canja wurin bayanai mara-DMA tsakanin juna ta gadar HPS-zuwa-FPGA (H2F), ta amfani da tashar jiragen ruwa 32-bit guda ɗaya kawai. Dalilin shine, ba tare da DMA ba, Linux kernel zai iya ba da buƙatun karantawa ko rubuta 32-bit guda ɗaya kawai, don haka ba lallai ba ne a sami haɗin kai mai faɗi.
Mai watsa shiri yana aika siginar sarrafawa zuwa na'urar ta hanyar gada H2F (LH2F) mara nauyi.
Saboda siginar sarrafawa daga mai watsa shiri zuwa na'urar ƙananan sigina ne na bandwidth, gada LH2F ya dace da aikin.

1.2 Koyar da Dandalin Magana zuwa Hukumar SoC FPGA
Don aika da Platform Reference Kit na Cyclone V SoC zuwa hukumar SoC FPGA, yi ayyuka masu zuwa:

Zaɓi ƙwaƙwalwar DDR ɗaya ko nau'in ƙwaƙwalwar DDR guda biyu na c5soc Reference Platform azaman farkon ƙirar ku.
Sabunta wuraren fil a cikin ALTERAOCLSDKROOT/board/c5soc/ /top.qsf file, Inda ALTERAOCLSDKROOT shine hanyar zuwa wurin da Intel FPGA SDK yake don shigarwa na OpenCL, kuma shine sunan directory na bambance-bambancen hukumar. Littafin c5soc_sharedonly yana don bambance-bambancen allon tare da tsarin ƙwaƙwalwar DDR guda ɗaya. Jagorar c5soc don bambance-bambancen allon ne tare da tsarin ƙwaƙwalwar DDR guda biyu.
Sabunta saitunan DDR don HPS da/ko FPGA SDRAM tubalan a cikin ALTERAOCLSDKROOT/board/c5soc/ /system.qsys file.
4. Duk Intel FPGA SDK don ƙirar allon da aka fi so na OpenCL dole ne su sami tabbacin rufewar lokaci. Kamar yadda irin wannan, jeri na zane dole ne ya kasance mai tsabta lokaci. Don aika ɓangaren allon c5soc (acl_iface_partition.qxp) zuwa hukumar SoC FPGA, yi ayyuka masu zuwa:
Don cikakkun bayanai kan gyarawa da adana ɓangaren allo, koma zuwa Quartus
Ƙirƙirar Ƙarfafa Ƙarfafa don Tsari da Tsarin Ƙungiya na Ƙirar Ƙirar Ƙarfafa Ƙwararrun Ƙwararrun Ƙwararrun Ƙwararrun Ƙwararru.
a. Cire acl_iface_partition.qxp daga ALTERAOCLSDKROOT/board/c5soc/c5soc directory.
b. Kunna yankin acl_iface_region LogicLock™ ta hanyar canza umarnin Tcl set_global_assignment -name LL_ENABLED KASHE -section_id acl_iface_region zuwa saita_global_assignment -name LL_ENABLED ON -section_id acl_iface_region
c. Haɗa kernel na OpenCL don allon allo.
d. Idan ya cancanta, daidaita girman da wurin LogicLock yankin.
e. Lokacin da kuka gamsu cewa sanya tsarin ƙirar ku yana tsaftar lokaci, fitar da wancan ɓangaren azaman ɓangaren acl_iface_partition.qxp Quartus Prime Exported Partition. File.
Kamar yadda aka bayyana a sashin Ƙaddamar da Garanti na Gudun Gudun Lokaci na AIntel FPGA SDK don Jagorar Mai amfani da Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayanka ta Wannan .qxp file a cikin babban matakin ƙira, kuna cika buƙatun samar da ƙirar allo tare da tabbacin lokacin rufewa.
Don abubuwan da za su iya yin tasiri ga ingancin sakamako (QoR) na ɓangaren da aka fitar, koma zuwa Gabaɗaya Ingancin Sakamakon La'akari don sashin Rarraba Hukumar Fitarwa a cikin Intel FPGA SDK don Jagorar Mai amfani da Kayan Kayan Kayan Kayan Kayan Kaya na Musamman na OpenCL.
f. Kashe yankin acl_iface_region LogicLock ta hanyar mayar da umarni a Mataki na 2 zuwa saitin_global_assignment -name LL_ENABLED KASHE sashe_id acl_iface_region.
Idan allon SoC FPGA ɗinku yana amfani da fil daban-daban da abubuwan da ke cikin toshewar HPS, sake haɓaka mai ɗaukar hoto da tushen itacen na'urar (DTS) file. Idan kun canza saitunan mai sarrafa ƙwaƙwalwar ajiya na HPS DDR, sake haɓaka mai ɗaukar hoto.
Ƙirƙiri hoton katin SD na filasha.
Ƙirƙiri Platform ɗinku na Musamman, wanda ya haɗa da hoton katin SD.
Yi la'akari da ƙirƙirar nau'in yanayi na lokaci-lokaci na Platform ɗinku na Custom don amfani tare da Intel FPGA Runtime Environment (RTE) don OpenCL. Sigar RTE na Platform ɗinku na al'ada baya haɗa da kundayen adireshi na hardware da hoton katin SD. Wannan Platform na Musamman yana lodi akan tsarin SoC FPGA don ba da damar aikace-aikacen runduna suyi aiki. Sabanin haka, sigar SDK na Platform na Al'ada ya zama dole don SDK don tattara kernels na OpenCL.
Tukwici: Kuna iya amfani da sigar SDK na Platform ɗinku na Musamman don RTE. Don ajiyewa
sarari, cire hoton katin SD daga sigar RTE na Platform ɗinku na Musamman.
Gwada Platform ɗinku na Musamman.
Koma zuwa sashin Gwajin Ƙirar Hardware na Intel FPGA SDK don Jagorar Mai amfani da Kayan Kayan Kayan Kayan Kayan Kayan Kaya na Musamman don ƙarin bayani.

Hanyoyin haɗi

Gwajin Zane-zanen Hardware
Tarin Ƙarfafa Ƙarfafa Ƙwararru na Quartus don Tsare-tsare da Ƙirar Ƙungiya

Ƙaddamar da Garantin Gudun Hijira
Gabaɗaya Ingantattun Sakamakon La'akari don Bangaren Hukumar Fitarwa

1.2.1 Ana ɗaukaka Platform Reference Ported
A cikin sigar yanzu na Cyclone V SoC Development Kit Reference Platform, toshe HPS yana cikin ɓangaren da ke bayyana duk dabarun da ba na kernel ba. Koyaya, ba za ku iya fitar da HPS azaman ɓangare na .qxp ba file. Don sabunta Platform na Musamman wanda kuka canza daga sigar c5soc ta baya, aiwatar da kwararar adana QXP, sabunta hoton katin SD don samun sabon yanayin lokacin aiki, kuma sabunta allon_spec.xml file don kunna automigration.
Altera® SDK don sigar OpenCL 14.1 da bayan binciken allon_spec.xml file don bayanin allo, kuma yana aiwatar da sabuntawa ta atomatik. Domin kun gyara
ƙira ta aiwatar da kwararar kiyayewar QXP, dole ne ku sabunta board_spec.xml file zuwa tsarin sa a cikin sigar yanzu. Ana sabunta ta file yana ba SDK damar bambanta tsakanin Platforms Custom Platform da ba a kiyaye su ba da kuma tushen QXP na yanzu. Koma zuwa Ƙaƙƙarfan Dandali na Al'ada don Ci gaban Gabatarwa a cikin Intel FPGA SDK don Jagorar Mai Amfani da Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kasa na Ƙasa ta Ƙarya don ƙarin bayani.

Don aiwatar da kwararar kiyayewar QXP a cikin ƙirar kayan masarufi na Cyclone V SoC FPGA wanda aka zazzage daga sigar c5soc ta baya, yi matakan da suka biyo baya don ƙirƙirar juzu'i don ware HPS daga .qxp. file:
a. Kafin ƙirƙirar bangare a kusa da dabaru na ba kwaya, ƙirƙiri bangare kewaye da HPS a cikin .qsf Quartus Prime Settings File.
Don misaliampda:
# Rarraba da hannu misalin misalin da aka sadaukar da I/O set_intance_assignment -name PARTITION_HIERARCHY borde_18261 - zuwa “tsarin: tsarin system_acl_iface_hps_0_hps_io_border: iyaka" -section_id "system_acl_iface_hps_0_hps_io_border: iyaka"
# Sanya bangare ya zama nau'in HPS_PARTITION don sarrafa shi daidai da sauran Quartus
saitin_assignment_global_name PARTITION_TYPE HPS_PARTITION -section_id "tsarin_acl_iface_hps_0_hps_io_border: iyaka"
quartus_cdb saman -c saman
-incremental_compilation_export=acl_iface_partition.qxp
-incremental_compilation_export_partition_name=acl_iface_partition
-incremental_compilation_export_post_synth=on
-incremental_compilation_export_post_fit=on
-incremental_compilation_export_routing=on
-incremental_compilation_export_flatten=kashe
Bayan ka ware HPS daga bangaren, za ka iya shigo da .qxp file kuma ku tattara zanenku.
Sabunta hoton katin SD ɗin tare da nau'in Intel FPGA RTE na yanzu don OpenCL ta aiwatar da ayyuka masu zuwa:
a. Dutsen da file tebur kasafi (fat32) da kuma mika file ɓangarorin tsarin (ext3) a cikin hoton da ke akwai azaman na'urorin madauki na baya. Don cikakkun bayanai na umarni, koma zuwa Mataki na 2 a Gina Hoton Katin Filasha na SD.
b. A cikin /home/tushen/opencl_arm32_rte directory, cire files daga sigar da ta gabata ta RTE.
c. Zazzage kuma cire kayan aikin RTE na yanzu cikin /home/root/opencl_arm32_rte directory.
d. A cikin /driver/version.h file na Platform ɗinku na Musamman, sabunta aikin ACL_DRIVER_VERSION zuwa . (na example, 16.1.x, inda 16.1 shine sigar SDK, kuma x shine sigar direban da kuka saita).
e. Sake gina direban.
f. Share babban fayil (s) na kayan aikin Platform ɗin ku. Kwafi Platform Custom, tare da sabunta direba, zuwa /home/root/opencl_arm_rte/ directory.
g. Kwafi Altera.icd file daga / gida/tushen/opencl_arm32_rte directory kuma ƙara shi zuwa /etc/OpenCL/ directory directory.
h. Cire da gwada sabon hoton. Don cikakkun bayanai na umarni, koma zuwa Matakai 8 zuwa 11 a Gina Hoton Katin Filasha na SD.

Hanyoyin haɗi

Ƙirƙirar Hoton Katin Flash na SD akan shafi na 14
Hakanan kuna da zaɓi don ƙirƙirar sabon hoton katin SD flash.
Platform na Musamman don Ƙarfafawa na Gaba

1.3 Tallafin Software don Ƙwaƙwalwar Rarraba
Ƙwaƙwalwar ƙwaƙwalwa ta jiki tsakanin FPGA da CPU shine mafi kyawun ƙwaƙwalwar ajiya don kernels na OpenCL da ke gudana akan SoC FPGAs. Saboda FPGA yana samun damar ƙwaƙwalwar ajiyar da aka raba ta jiki, sabanin ƙwalƙwalwar ajiya da aka raba, ba ta da damar zuwa teburin shafukan CPU waɗanda ke taswirar adireshin kama-da-wane na mai amfani zuwa adiresoshin shafi na zahiri.
Game da kayan aikin, OpenCL kernels suna samun damar ƙwararrun ƙwaƙwalwar ajiyar jiki ta hanyar haɗin kai tsaye zuwa mai sarrafa ƙwaƙwalwar ajiyar ƙwaƙwalwar ajiya na HPS DDR. Game da software, goyan bayan ƙwaƙwalwar ajiyar jiki da aka raba ya ƙunshi la'akari masu zuwa:

Abubuwan aiwatar da software na yau da kullun don rarraba ƙwaƙwalwar ajiya akan CPU (misaliample, aikin malloc() ba zai iya ware yankin ƙwaƙwalwar ajiya wanda FPGA za ta iya amfani da shi ba.
Ƙwaƙwalwar ƙwaƙwalwar da aikin malloc() ke keɓancewa yana ci gaba a cikin sararin adireshi na ƙwaƙwalwar ajiya, amma duk wani shafi na zahiri ba zai yuwu ya zama mai jujjuyawar jiki ba. Don haka, mai watsa shiri dole ne ya iya rarraba yankuna masu jujjuyawa ta jiki. Koyaya, wannan ikon ba ya wanzu a aikace-aikacen sarari mai amfani akan Linux. Don haka, dole ne direban kernel na Linux ya yi rabon.
Direban kernel Linux na OpenCL SoC FPGA ya haɗa da aikin mmap() don rarraba ƙwaƙwalwar ajiyar jiki da aka raba da taswira a cikin sararin mai amfani. Aikin mmap() yana amfani da daidaitaccen kiran kernel Linux dma_alloc_coherent() don buƙatar yankunan ƙwaƙwalwar ajiya masu jujjuya jiki don rabawa tare da na'ura.
A cikin tsohowar kernel na Linux, dma_alloc_coherent() baya keɓance ƙwaƙwalwar ajiya mai jujjuyawa ta jiki fiye da megabyte 0.5 (MB) a girman. Don ba da damar dma_alloc_coherent() don keɓance ɗimbin ƙwaƙwalwar ajiya mai jujjuyawa ta jiki, ba da damar fasalin ƙwaƙwalwar ajiyar ƙwaƙwalwar ajiya (CMA) na Linux kernel sannan a sake tattara kernel na Linux.
Don Cyclone V SoC Development Kit Reference Platform, CMA tana sarrafa 512 MB daga 1 GB na ƙwaƙwalwar jiki. Kuna iya ƙarawa ko rage wannan ƙimar, dangane da adadin ƙwaƙwalwar ajiyar da aikace-aikacen ke buƙata. Kiran dma_alloc_coherent() na iya kasa kasafta cikakken 512 MB na ƙwaƙwalwar da ke haɗa jiki; duk da haka, yana iya samun kusan 450 MB na ƙwaƙwalwar ajiya akai-akai.

CPU na iya cache memorin da dma_alloc_coherent() kira ya keɓe. Musamman, rubuta ayyukan daga aikace-aikacen mai watsa shiri ba a bayyane ga kernels na OpenCL. Ayyukan mmap() a cikin OpenCL SoC FPGA Linux kernel driver shima ya ƙunshi kira zuwa aikin pgrot_noncached() ko remap_pf_range() don kashe caching na wannan yanki na ƙwaƙwalwar ajiya a sarari.
Bayan aikin dma_alloc_coherent() yana keɓance ƙwaƙwalwar ajiyar jiki-mai haɗawa, aikin mmap() yana mayar da adireshi mai kama-da-wane zuwa farkon kewayon, wanda shine tazarar adireshin memorin da kuka ware. Aikace-aikacen rundunar yana buƙatar wannan adireshin kama-da-wane don samun damar ƙwaƙwalwar ajiya. A gefe guda, kernels na OpenCL suna buƙatar adiresoshin jiki. Direban kernel na Linux yana kiyaye taswirar adireshi mai kama-da-wane. Kuna iya taswirar adiresoshin jiki waɗanda mmap() ke dawowa zuwa ainihin adiresoshin jiki ta ƙara tambaya ga direba.
Kiran aocl_mmd_shared_mem_alloc() MMD aikace-aikacen shirye-shirye (API) ya ƙunshi tambayoyi masu zuwa:
a. Aikin mmap() wanda ke keɓance ƙwaƙwalwar ajiya da dawo da adireshi mai kama-da-wane.
b. Ƙarin tambayar da ke tsara adireshin kama-da-wane da aka mayar zuwa adireshin jiki.
Kiran aocl_mmd_shared_mem_alloc() MMD API sannan ya dawo da adireshi biyu
-ainihin adireshin da aka dawo dashi shine adireshin kama-da-wane, kuma adireshin jiki yana zuwa device_ptr_out.
Lura: Direba na iya taswirar adiresoshin kama-da-wane kawai wanda aikin mmap() ke komawa zuwa adiresoshin jiki. Idan ka nemi adireshin zahiri na kowane mai nuna alama, direban ya dawo da ƙimar NULL.

Gargadi: Intel FPGA SDK don ɗakunan karatu na lokaci-lokaci na OpenCL suna ɗauka cewa ƙwaƙwalwar ajiyar da aka raba ita ce ƙwaƙwalwar farko da aka jera a cikin board_spec.xml file. A wasu kalmomi, adireshin jiki wanda direban kwaya na Linux ke samu ya zama adireshin Avalon® wanda kernel OpenCL ke wucewa zuwa HPS SDRAM.
Game da ɗakin karatu na lokacin aiki, yi amfani da kiran clCreateBuffer() don ware ƙwaƙwalwar ajiyar da aka raba azaman ma'ajin na'ura ta hanya mai zuwa:

Don bambance-bambancen allo-DDR guda biyu tare da haɗin gwiwa da ƙwaƙwalwar ajiya, clCreateBuffer() yana keɓance ma'amalar ƙwaƙwalwar ajiya idan kun saka tutar CL_MEM_USE_HOST_PTR. Amfani da wasu tutoci yana haifar da createBuffer() don keɓance buffer a cikin ƙwaƙwalwar da ba a raba ba.
Don bambance-bambancen allo-DDR guda ɗaya tare da žwažwalwar ajiya guda ɗaya kawai, clCreateBuffer() yana keɓance raba ƙwaƙwalwar ajiya ba tare da la'akari da wace tutar da kuka ƙayyade ba.
A halin yanzu, tallafin Linux na 32-bit akan ARM CPU yana sarrafa girman tallafin ƙwaƙwalwar ajiya a cikin ɗakunan karatu na lokacin aiki na SDK. A wasu kalmomi, ɗakunan karatu na lokacin aiki da aka haɗa zuwa wasu wurare (misaliample, x86_64 Linux ko 64-bit Windows) basa goyan bayan ƙwaƙwalwar ajiya.
C5soc bai aiwatar da ƙwaƙwalwar ajiya daban-daban ba don bambanta tsakanin ƙwaƙwalwar ajiya da maras rabawa saboda dalilai masu zuwa:
1. Tarihi-Ba a samun tallafin ƙwaƙwalwar ajiya daban-daban lokacin da aka ƙirƙiri tallafin ƙwaƙwalwar ajiya na asali.
2. Uniform interface-Saboda OpenCL mizanin buɗaɗɗe ne, Intel yana kiyaye daidaito tsakanin masu siyar da dandamali iri-iri. Don haka, ana amfani da keɓance iri ɗaya kamar sauran gine-ginen masu siyar da allon don keɓancewa da amfani da ƙwaƙwalwar ajiya.

1.4 Sake saita FPGA
Don SoC FPGAs, CPU na iya sake saita masana'anta na FPGA ba tare da katse aikin CPU ba. Katange kayan aikin FPGA Manager wanda ke matse HPS kuma ainihin FPGA yana aiwatar da sake fasalin. Kernel na Linux ya haɗa da direba wanda ke ba da damar shiga cikin sauƙi zuwa Manajan FPGA.

Zuwa view Matsayin ainihin FPGA, kira cat /sys/class/fpga/fpga0/ umurnin matsayi.
Intel FPGA SDK don amfanin shirin OpenCL da ke akwai tare da Cyclone V SoC Development Kit Reference Platform yana amfani da wannan keɓancewa don tsara FPGA. Lokacin sake tsara ainihin FPGA tare da CPU mai gudana, kayan aikin shirin yana yin duk ayyuka masu zuwa:
1. Kafin sake tsarawa, musaki duk hanyoyin sadarwa tsakanin FPGA da HPS, duka gadoji H2F da LH2F.
Sake kunna waɗannan gadoji bayan an kammala sake tsarawa.
Hankali: Tsarin OpenCL baya amfani da gadar FPGA-zuwa-HPS (F2H). Koma zuwa sashin mu'amalar HPS-FPGA a cikin Littafin Jagorar Cyclone V na Na'ura, juzu'i na 3: Jagorar Fasahar Fasaha ta Tsare-tsaren Hard Processor don ƙarin bayani.
2. Tabbatar cewa an kashe hanyar haɗin FPGA da mai kula da HPS DDR yayin sake tsarawa.
3. Tabbatar cewa FPGA ta katse akan FPGA an kashe su yayin sake tsarawa.
Hakanan, sanar da direba don ƙin duk wani katsewa daga FPGA yayin sake tsarawa.

Tuntuɓi lambar tushe na kayan aikin shirin don cikakkun bayanai kan ainihin aiwatarwa.

Gargadi: Kar a canza saitin mai sarrafa HPS DDR lokacin da CPU ke gudana.
Yin hakan na iya haifar da kuskuren tsarin kisa saboda kuna iya canza tsarin mai sarrafa DDR lokacin da fitattun ma'amalar ƙwaƙwalwar ajiya daga CPU. Wannan yana nufin cewa lokacin da CPU ke gudana, ƙila ba za ku sake tsara ainihin FPGA tare da hoton da ke amfani da HPS DDR a cikin wani tsari na daban ba.
Ka tuna cewa tsarin OpenCL, da ƙirar kayan aikin Golden Hardware da ke akwai tare da Intel SoC FPGA Embedded Design Suite (EDS), yana saita HPS DDR zuwa yanayin 256-bit guda ɗaya.
Sassan tsarin CPU kamar mai hasashen reshe ko prefetcher na shafi na iya ba da umarnin DDR koda ya bayyana cewa babu wani abu da ke gudana akan CPU.
Don haka, lokacin taya shine kawai amintaccen lokacin don saita saitin mai sarrafa HPS DDR.
Wannan kuma yana nuna cewa U-boot dole ne ya sami ɗanyen binary file (.rbf) hoto don loda cikin ƙwaƙwalwar ajiya. In ba haka ba, kuna iya kunna HPS DDR tare da tashoshin jiragen ruwa marasa amfani akan FPGA sannan kuma kuna iya canza saitin tashar jiragen ruwa daga baya. Don wannan dalili, direban kernel na OpenCL Linux baya haɗa da dabaru masu mahimmanci don saita saitin mai sarrafa HPS DDR.
Kunshin in-line SW3 dual in-line (DIP) yana canzawa akan Cylone V SoC Development Kit yana sarrafa nau'in da ake tsammani na hoton .rbf (wato, ko file an matsa da/ko rufaffen). C5soc, da Zane-zanen Magana na Hardware na Zinariya da ke tare da SoC EDS, sun haɗa da matsi amma ba a ɓoye hotunan rbf ba. Saitunan sauyawa na SW3 DIP da aka kwatanta a cikin Intel FPGA SDK don OpenCL Cyclone V SoC Jagoran Farawa yayi daidai da wannan tsarin hoton .rbf.

Hanyoyin haɗi

HPS-FPGA Interfaces
Ana saita SW3 Sauyawa

1.4.1 Bayanin Gine-gine na Tsarin FPGA
Taimako ga Cyclone V SoC Development Kit Reference Platform ya dogara ne akan Stratix® V Reference Platform (s5_ref), samuwa tare da Intel FPGA SDK don OpenCL.
Gaba ɗaya ƙungiyar c5soc Qsys tsarin da direban kernel sunyi kama da waɗanda ke cikin s5_ref.
Abubuwan abubuwan FPGA masu zuwa iri ɗaya ne a duka c5soc da s5_ref:

Katange VERSION_ID
Tsarin hutawa

Mai raba bankin ƙwaƙwalwar ajiya
Cache snoop interface
Agogon kwaya

Katange damar yin rajista (CRA).

1.5 Gina Hoton Katin Flash na SD
Saboda Cyclone V SoC FPGA cikakken tsari ne akan guntu, kuna da alhakin isar da cikakken ma'anar tsarin. Intel yana ba da shawarar cewa ka isar da shi ta hanyar hoton katin SD. Intel FPGA SDK don mai amfani da OpenCL na iya rubuta hoton kawai zuwa katin filashin micro SD kuma hukumar SoC FPGA tana shirye don amfani.
Gyara Hoton Katin Filasha na SD da ke wanzu a shafi na 13
Intel yana ba da shawarar cewa kawai ku canza hoton da ke akwai tare da Cyclone V SoC Development Kit Reference Platform. Hakanan kuna da zaɓi don ƙirƙirar sabon hoton katin SD flash.
Ƙirƙirar Hoton Katin Flash na SD akan shafi na 14
Hakanan kuna da zaɓi don ƙirƙirar sabon hoton katin SD flash.

1.5.1 Gyara Hoton Katin Filasha na SD da ke wanzu
Intel yana ba da shawarar cewa kawai ku canza hoton da ke akwai tare da Cyclone V SoC
Platform Reference Kit. Hakanan kuna da zaɓi don ƙirƙirar sabon hoton katin SD flash.
Hoton c5soc linux_sd_card_image.tgz file yana samuwa a cikin ALTERAOCLSDKROOT/board/c5soc directory, inda ALTERAOCLSDKROOT ke nuna hanyar Intel FPGA SDK don kundin shigarwa na OpenCL.

Hankali: Don canza hoton katin SD, dole ne ku sami tushen gata ko sudo.

Don ƙaddamar da $ALTERAOCLSDKROOT/board/c5soc/linux_sd_card_image.tgz file, gudanar da umurnin xvfzlinux_sd_card_image.tgz.
Haɗa hello_world OpenCL exampzana ta amfani da goyan bayan Platform ɗinku na Musamman. Sake suna .rbf file cewa Intel FPGA SDK na OpenCL Offline Compiler yana haifar da shi azaman opencl.rbf, kuma sanya shi akan ɓangaren fat32 a cikin hoton katin SD.
Kuna iya sauke hello_world example zane daga OpenCL Design Examples page akan Altera website.

Sanya rbf file a cikin ɓangaren fat32 na hoton katin filashi.
Hankali: Dole ne ɓangaren fat32 ya ƙunshi duka zImage file kuma rbf file. Ba tare da .rbf file, kuskuren mutuwa zai faru lokacin da kuka saka direban.
Bayan ka ƙirƙiri hoton katin SD, rubuta shi zuwa katin micro SD ta hanyar kiran umarni mai zuwa: sudo dd if =/path/to/sdcard/image.bin of=/dev/sdcard
Don gwada hoton katin SD ɗinku, yi ayyuka masu zuwa:
a. Saka katin filashin micro SD a cikin allon SoC FPGA.
b. Ƙaddamar da allon.
c. Kira umarnin mai amfani bincikar aocl.

1.5.2 Ƙirƙirar Hoton Katin Flash na SD
Hakanan kuna da zaɓi don ƙirƙirar sabon hoton katin SD flash. Umurni na gama gari akan gina sabon hoton katin SD da sake gina hoton katin SD na yanzu ana samunsu akan GSRD v14.0.2 - Shafin Katin SD na RocketBoards.org website.
Matakan da ke ƙasa suna bayyana hanyar ƙirƙirar hoton linux_sd_card_image.tgz daga Hoton Katin Katin Filasha na Tsarin Zinare (GSRD):
Lura:
Don ƙirƙirar hoton daga hoton c5soc, yi duk ayyukan da suka dace waɗanda aka zayyana a cikin wannan hanya.

Zazzagewa kuma buɗe sigar hoton katin GSRD SD filashin 14.0 daga Rocketboards.org.
Dutsen da file tebur kasafi (fat32) da kuma mika file sassan tsarin (ext3) a cikin wannan hoton azaman na'urorin madauki. Don hawa partition, yi matakai masu zuwa:
a. Ƙayyade farawar byte na ɓangaren hoto ta hanyar kiran /sbin/fdisk -lu image_file umarni.
Don misaliample, partition number 1 na nau'in W95 FAT yana da 2121728 toshe diyya.
b. Gano na'urar madauki kyauta (misaliample, /dev/loop0) ta hanyar buga umurnin Lostup -f.
c. Zaton /dev/loop0 shine na'urar madauki na kyauta, sanya hoton katin filasha zuwa na'urar toshe madauki ta hanyar kiran hasarar / dev/loop0 image_file -0 1086324736 umarni.
d. Hana na'urar madauki ta hanyar kiran mount /dev/loop0 /media/disk1 umurnin.
A cikin hoton file, /media/disk1 yanzu shine bangare na fat32 da aka saka.
e. Maimaita matakan a zuwa d don ɓangaren ext3.

Zazzage sigar Cyclone V SoC FPGA na Intel FPGA Runtime Environment don fakitin OpenCL daga Cibiyar Zazzagewa akan Altera website.
a. Danna maɓallin Zazzagewa kusa da bugu na software na Quartus Prime.
b. Ƙayyade sigar saki, tsarin aiki, da hanyar zazzagewa.
c. Danna Ƙarin Software shafin, kuma zaɓi don zazzage Intel FPGA
Mahalli na lokacin aiki don OpenCL Linux Cyclone V SoC TGZ.
d. Bayan kun sauke aocl-rte- .hannu32.tgz file, buše shi zuwa
kundin adireshin da ka mallaka.
Sanya aocl-rte- .arm32 directory a cikin /gida/tushen/opencl_arm32_rte directory akan ext3 bangare na hoton file.
Share babban fayil (s) na kayan aikin Platform ɗinku, sannan sanya Platform na Custom a cikin ƙaramin shugabanci na /home/root/ opencl_arm32_rte.

Ƙirƙiri init_opencl.sh file a cikin / gida / tushen directory tare da abun ciki mai zuwa: fitarwa ALTERAOCLSDKROOT = / gida / tushen / opencl_arm32_rte fitarwa AOCL_BOARD_PACKAGE_ROOT = $ ALTERAOCLSDKROOT / jirgi / fitarwa PATH=$ALTERAOCLSDKROOT/bin:$PATH fitarwa LD_LIBRARY_PATH=$ALTERAOCLSDKROOT/host/arm32/lib:$LD_LIBRARY_PATH insmod $AOCL_BOARD_PACKAGE_ROOT/driver/aclsoc_drv.ko
Mai amfani da SDK yana gudanar da tushen ./init_opencl.sh umarnin don loda masu canjin yanayi da direban kernel na OpenCL Linux.
Idan kana buƙatar sabunta mai ɗaukar hoto, DTS files, ko Linux kernel, kuna buƙatar haɗin-linux-gnueabihf-gcc mai tarawa daga SoC EDS. Bi umarnin da aka zayyana a cikin Intel SoC FPGA Embedded Design Suite User Guide don siyan software, sake haɗa su, da sabunta abubuwan da suka dace. files a kan ɗorawa fat32 partition.
Hankali: Da alama kuna buƙatar sabunta mai ɗaukar hoto idan Platform ɗinku na Custom yana da nau'ikan fil daban-daban fiye da waɗanda ke cikin c5soc.
Tuna: Idan kun sake tattara kernel na Linux, sake tattara direban kernel na Linux tare da tushen kernel iri ɗaya na Linux. files. Idan akwai rashin daidaituwa tsakanin direban kernel na Linux da kernel na Linux, direban ba zai yi lodi ba. Hakanan, dole ne ku kunna CMA.
Koma zuwa Sabunta Linux Kernel don ƙarin bayani.
Haɗa hello_world OpenCL exampzana ta amfani da goyan bayan Platform ɗinku na Musamman. Sake suna .rbf file cewa Intel FPGA SDK na OpenCL Offline Compiler yana haifar da shi azaman opencl.rbf, kuma sanya shi akan ɓangaren fat32 a cikin hoton katin SD.
Kuna iya sauke hello_world example zane daga OpenCL Design Examples page akan Altera website.
9. Bayan ka adana duk abin da ake bukata files kan hoton katin walƙiya, kira waɗannan umarni masu zuwa:
a. daidaitawa
b. sauke /media/disk1
c. sauke ina shine sunan directory da kuke amfani dashi don hawan ext3 partition a 3 a shafi na 3 (na misaliample, /media/disk2).
d. rasa-d /dev/loop0
e. rasatup -d /dev/loop1

Matsa hoton katin SD ta hanyar kiran umarni mai zuwa: tar cvfz .tgz linux_sd_katin_image
Isar da .tgz file a cikin tushen kundin tsarin dandalin ku na Custom.
Don gwada hoton katin SD ɗinku, yi ayyuka masu zuwa:
a. Rubuta sakamakon da ba a matsa hoton ba akan katin filashin micro SD.
b. Saka katin filashin micro SD a cikin allon SoC FPGA.
c. Ƙaddamar da allon.
d. Kira umarnin mai amfani bincikar aocl.

Hanyoyin haɗi

Intel SoC FPGA Embedded Design Suite Jagorar mai amfani
OpenCL Design Examples page akan Altera website

Ana sake tattara Kernel na Linux akan shafi na 16
Don kunna CMA, dole ne ka fara tattara kwaya ta Linux.
Neman Sunan Na'urar Hukumar FPGA ɗinku (ganowa)

1.6 Haɗa Linux Kernel don Cyclone V SoC FPGA
Kafin gudanar da aikace-aikacen OpenCL akan hukumar Cyclone V SoC FPGA, dole ne ku tattara tushen kernel na Linux, sannan ku tattara kuma shigar da direban kernel na OpenCL Linux.

Ana sake tattara Kernel na Linux akan shafi na 16
Don kunna CMA, dole ne ka fara tattara kwaya ta Linux.
Haɗawa da Sanya Direban Kernel na OpenCL Linux akan shafi na 17 Haɗa direban kernel na OpenCL Linux akan tushen kernel da aka haɗa.

1.6.1 Maimaita Linux Kernel
Don kunna CMA, dole ne ka fara tattara kwaya ta Linux.

Danna GSRD v14.0 - Haɗa haɗin Linux akan shafin albarkatun RocketBoards.org webshafin don samun damar umarni kan zazzagewa da sake gina lambar tushen Linux kernel.
Don amfani da ™ Intel FPGA SDK don OpenCL, saka socfpga-3.13-rel14.0 azaman .
Lura: Tsarin ginin yana ƙirƙirar baka/arm/configs/socfpga_defconfig file. Wannan file Yana ƙayyadad da saitunan don daidaitawar tsoho na socfpga.
Ƙara layin masu zuwa zuwa kasan arch/arm/configs/socfpga_defconfig file.
CONFIG_MEMORY_ISOLATION=y
CONFIG_CMA=y
CONFIG_DMA_CMA=y
CONFIG_CMA_DEBUG=y
CONFIG_CMA_SIZE_MBYTES=512
CONFIG_CMA_SIZE_SEL_MBYTES=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
Ƙimar daidaitawa ta CONFIG_CMA_SIZE_MBYTES tana saita iyaka mafi girma akan jimillar adadin ƙwaƙwalwar ajiyar jiki da ke da alaƙa. Kuna iya ƙara wannan ƙimar idan kuna buƙatar ƙarin ƙwaƙwalwar ajiya.
Hankali: Jimlar adadin ƙwaƙwalwar ajiyar jiki da ke akwai ga mai sarrafa ARM akan allon SoC FPGA shine 1 GB. Intel baya ba da shawarar ka saita manajan CMA kusa da 1 GB.

Guda umarnin make mrproper don tsaftace tsarin na yanzu.
Gudanar da yin ARCH=arm socfpga_deconfig umurnin.
ARCH=hannu yana nuna cewa kana son saita gine-ginen ARM.
socfpga_defconfig yana nuna cewa kuna son amfani da tsayayyen socfpga.
Gudanar da fitarwa CROSS_COMPILE=arm-linux-gnueabihf- umarni.
Wannan umarnin yana saita canjin yanayi na CROSS_COMPILE don ƙididdige prefix na sarkar kayan aiki da ake so.

Gudanar da yin ARCH=arm zImage umurnin. Hoton da aka samu yana samuwa a cikin baka/hannu/boot/zImage file.
Sanya zImage file a cikin ɓangaren fat32 na hoton katin filashi. Don cikakkun bayanai na umarni, koma zuwa Cyclone V SoC FPGA-takamaiman Manual mai amfani na GSRD akan Rocketboards.org.
Lura: Don shigar da direban kernel na OpenCL Linux daidai, fara loda SDKgenerated.rbf file ku FPGA.
Don ƙirƙirar .rbf file, tattara ƙirar SDK examptare da Cyclone V SoC Development Kit Platform a matsayin Platform Custom da aka yi niyya.
9. Sanya .rbf file a cikin ɓangaren fat32 na hoton katin filashi.
Hankali: Dole ne ɓangaren fat32 ya ƙunshi duka zImage file kuma rbf file. Ba tare da .rbf file, kuskuren mutuwa zai faru lokacin da kuka saka direban.

Saka katin micro SD da aka tsara, wanda ya ƙunshi hoton katin SD da kuka gyara ko ƙirƙira a baya, cikin Cyclone V SoC Development Kit sannan kuma kunna allon SoC FPGA.
Tabbatar da sigar kernel Linux da aka shigar ta hanyar gudanar da umarnin uname -r.
Don tabbatar da cewa kun ba da damar CMA cikin nasara a cikin kernel, tare da ƙarfin hukumar SoC FPGA, gudanar da umarnin grep init_cma /proc/kallsyms.
Ana kunna CMA idan fitarwar ba ta da komai.

Don amfani da kernel Linux da aka sake tarawa tare da SDK, haɗa kuma shigar da direban kernel na Linux.

Hanyoyin haɗi

Tsarin Magana na Tsarin Zinare (GSRD) Littattafan Mai Amfani

Gina Hoton Katin Filashin SD akan shafi na 13
Saboda Cyclone V SoC FPGA cikakken tsari ne akan guntu, kuna da alhakin isar da cikakken ma'anar tsarin.

1.6.2 Haɗawa da Sanya Direban Kernel na OpenCL Linux
Haɗa direban kwaya na OpenCL Linux akan tushen kernel da aka haɗa.

Ana samun tushen direba a cikin nau'in Cyclone V SoC FPGA na Intel FPGA Runtime Environment don OpenCL. Bugu da kari, tabbatar da cewa kun loda Intel FPGA SDK don OpenCL-generated .rbf file cikin FPGA don hana shigar da kuskuren ƙirar kernel na Linux.

Zazzage sigar Cyclone V SoC FPGA na Intel FPGA Runtime Environment don fakitin OpenCL daga Cibiyar Zazzagewa akan Altera website.
a. Danna maɓallin Zazzagewa kusa da bugu na software na Quartus Prime.
b. Ƙayyade sigar saki, tsarin aiki, da hanyar zazzagewa.
c. Danna Ƙarin Software shafin, kuma zaɓi don zazzage Intel FPGA
Mahalli na lokacin aiki don OpenCL Linux Cyclone V SoC TGZ.
d. Bayan kun sauke aocl-rte- .hannu32.tgz file, buše shi zuwa
kundin adireshin da ka mallaka.
Tushen direban yana cikin aocl-rte- .arm32/board/c5soc/ directory directory.
Don sake haɗa direban kernel na OpenCL Linux, saita ƙimar KDIR a cikin Maƙerin direbafile zuwa kundin adireshi mai ɗauke da tushen kernel Linux files.
Gudanar da fitarwar CROSS_COMPILE=arm-linux-gnueabihf- umarni don nuna prefix na sarkar kayan aikin ku.

Gudanar da tsaftataccen umarni.
Gudanar da umarnin yin don ƙirƙirar aclsoc_drv.ko file.
Canja wurin directory opencl_arm32_rte zuwa hukumar Cyclone V SoC FPGA.
Gudun scp -r tushen @your-ipaddress: umarnin yana sanya yanayin lokacin aiki a cikin/gida/tushen directory.

Guda rubutun init_opencl.sh wanda kuka ƙirƙira lokacin da kuka gina katin SD.
Kira umarnin mai amfani bincikar aocl. Mai amfani da bincike zai dawo da sakamako mai wucewa bayan kun gudanar da init_opencl.sh cikin nasara.

1.7 Abubuwan da aka sani
A halin yanzu, akwai wasu iyakoki akan amfani da Intel FPGA SDK don OpenCL tare da Cyclone V SoC Development Kit Reference Platform.

Ba za ku iya soke sunan mai siyarwa da allon allo da CL_DEVICE_VENDOR da CL_DEVICE_NAME igiyoyin clGetDeviceInfo() suka ruwaito.
Idan mai watsa shiri ya keɓance ƙwaƙwalwar ajiya akai-akai a cikin tsarin DDR da aka raba (wato, HPS DDR) kuma yana canza ƙwaƙwalwar ajiya akai-akai bayan aiwatar da kernel, bayanan da ke cikin ƙwaƙwalwar ajiya na iya zama tsoho. Wannan batu ya taso ne saboda FPGA core ba zai iya snoop akan ma'amalar CPU-to-HPS DDR.
Don hana aiwatar da kisa na kwaya daga samun damar bayanan da suka gabata, aiwatar da ɗayan hanyoyin da za a bi:
Kar a canza ƙwaƙwalwar ajiya akai-akai bayan farawa.
• Idan kana buƙatar saitin bayanai masu yawa __constant, ƙirƙiri maɓallan ƙwaƙwalwar ajiya akai-akai.
• Idan akwai, ware ƙwaƙwalwar ajiya akai-akai a cikin FPGA DDR akan allon ƙararrawar ku.
SDK mai amfani akan ARM yana goyan bayan shirin ne kawai kuma yana tantance umarnin mai amfani.
Filasha, shigarwa da cire umarnin mai amfani ba su da amfani ga Cyclone V SoC Development Kit saboda dalilai masu zuwa:
a. Mai amfani da shigarwa dole ne ya tattara direban kwaya na aclsoc_drv Linux kuma ya kunna shi akan SoC FPGA. Na'urar haɓakawa dole ne ta aiwatar da haɗawa; duk da haka, ya riga ya ƙunshi tushen kernel Linux don SoC FPGA. Tushen kernel na Linux don injin haɓaka sun bambanta da na SoC FPGA. Wurin tushen tushen kwaya na Linux don SoC FPGA mai yiwuwa ba a san mai amfani da SDK ba. Hakazalika, kayan aikin cirewa shima baya samuwa ga Cyclone V SoC Development Kit.
Hakanan, isar da aclsoc_drv zuwa hukumar SoC yana da ƙalubale saboda tsohowar rarrabawar Cyclone V SoC Development Kit bai ƙunshi kernel Linux sun haɗa da. files ko GNU Compiler Collection (GCC) mai tarawa.
b. Mai amfani da walƙiya yana buƙatar sanya .rbf file na ƙirar OpenCL akan ɓangaren FAT32 na katin filashin micro SD. A halin yanzu, wannan ɓangaren ba a hawa lokacin da mai amfani da SDK ya kunna allon allo. Don haka, hanya mafi kyau don sabunta partition shine amfani da na'urar karanta katin flash da na'urar haɓakawa.

Lokacin canzawa tsakanin Intel FPGA SDK don Buɗewar Ƙirar Layi na OpenCL mai aiwatarwa files (.aocx) wanda ya dace da bambance-bambancen allo daban-daban (wato, c5soc da c5soc_sharedonly), dole ne ku yi amfani da kayan aikin shirin SDK don loda .aocx file don sabon bambance-bambancen hukumar a karon farko. Idan kawai kuna gudanar da aikace-aikacen mai watsa shiri ta amfani da sabon bambance-bambancen allon amma FPGA ya ƙunshi hoton daga wani bambance-bambancen allon, kuskuren mutuwa zai iya faruwa.
.qxp file baya haɗa da ayyukan ɓangarori na mu'amala saboda software na Quartus Prime koyaushe yana biyan buƙatun lokacin wannan ɓangaren.
Lokacin da ka kunna allon allo, an saita adireshin sa na samun damar mai jarida (MAC) zuwa lambar bazuwar. Idan manufar LAN ɗinku ba ta ƙyale wannan hali ba, saita adireshin MAC ta yin ayyuka masu zuwa:
a. Yayin kunnawar U-Boot, latsa kowane maɓalli don shigar da umarnin U-Boot.
b. Buga setenv ethaddr 00:07:ed:00:00:03 a umarni da sauri.
Kuna iya zaɓar kowane adireshin MAC.
c. Buga umarnin savenv.
d. Sake kunna allon.

1.8 Tarihin Bita na Takardu
Tebur 1.
Tarihin Bita na Takardu na Intel FPGA SDK don OpenCL Cyclone V SoC
Jagorar Mai Rarraba Platform Reference Kit

Kwanan wata	Sigar	Canje-canje
Mayu-17	2017.05.08	• Sakin kulawa.
Oktoba 2016	2016.10.31	• Sake suna Altera SDK don OpenCL zuwa Intel FPGA SDK don OpenCL. • Sake suna Altera Compiler Offline Compiler zuwa Intel FPGA SDK don Buɗewar Layin Layin Buɗewa.
Mayu-16	2016.05.02	• Gyaran umarni kan ginawa da gyara hoton katin SD. • gyaggyara umarni kan sake tattara kernel Linux da direban kernel na OpenCL Linux.
Nuwamba-15	2015.11.02	• Sakin kulawa, da canza yanayin Quartus II zuwa Quartus Prime.
Mayu-15	15.0.0	• A cikin sake fasalin FPGA, cire umarnin don sake tsara ainihin FPGA da a. Hoton rbf ta hanyar kiran cat filesuna>. rbf > /dev/ fpga0 umarni saboda wannan hanyar ba a ba da shawarar ba.
Disamba-14	14.1.0	• Sake wa takardar suna a matsayin Altera Cyclone V SoC Development Kit Reference Platform Porting Guide. •An sabunta kayan aikin sakewa zuwa shirin aoclfilename>.aocx utility umurnin. •An sabunta kayan aikin bincike zuwa ga ganowar aocl da kuma tantancewar aocl umarnin mai amfani. •An sabunta hanya a cikin Porting Platform Reference zuwa sashin Hukumar SoC ɗinku don haɗawa da umarni kan jigilar kaya da gyara ɓangaren kwamitin c5soc don ƙirƙirar ɓangaren tsaftataccen lokaci don tabbatar da kwararar lokacin rufewa. • Shigar da taken Ana ɗaukaka Platform Reference Ported don fayyace hanyoyin ayyuka masu zuwa: 1.Excluding da hard processor system (HPS) block in the board partition 2.Updating da SD flash katin image •An sabunta sashin Ginin Hoton Katin Flash Flash. An ba da shawarar ta amfani da sigar 14.0 na Hoton Tsarin Magana na Zinare (GSRD) azaman wurin farawa maimakon hoton da ke akwai tare da SoC Embedded Design Suite (EDS). •An sabunta Sabunta Linux Kernel da sashin Direban Kernel na OpenCL Linux: 1.Ƙara umarni don saita canjin CROSS COMPILE. 2. Canza umarnin da kuke gudanar don tabbatar da cewa an kunna CMA cikin nasara.
Yuli-14	14.0.0	•Sakin Farko.