intel FPGA SDK yeOpenCL User Guide

FPGA SDK yeOpenCL
User Guide

UG-OCL009
2017.05.08
Yakagadziridzwa yekupedzisira yeIntel® Quartus® Prime Design Suite: 17.0

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1 Intel® FPGA SDK ye OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Platform Porting Guide

2 Zvinyorwa / Zvishandiso

2.1 References

3 Related Posts

Intel® FPGA SDK ye OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Platform Porting Guide

V SoC Development Kit Reference Platform Porting Guide inotsanangura hardware uye software dhizaini yeIntel Cyclone V SoC Development Kit Reference Platform (c5soc) yekushandisa neIntel Software Development Kit (SDK) yeOpenCL Iyo Intel® FPGA SDK yeOpenCL ™ Intel Cyclone. ® . Usati watanga, Intel inokurudzira zvakasimba kuti uzvizive nezviri mumagwaro anotevera:

Intel FPGA SDK ye OpenCIntel Cyclone V SoC Kutanga Gwaro

Intel FPGA SDK yeOpenCL Custom Platform Toolkit User Guide
Cyclone V Device Handbook, Vhoriyamu 3: Yakaoma processor System Technical Reference Manual Mukuwedzera, taura kune Cyclone V SoC Development Kit uye SoC Embedded Design Suite peji reAltera. websaiti kuti uwane rumwe ruzivo. 1 2

Chenjerera: Intel inofungidzira kuti une kudzika-kunzwisisa kweIntel FPGA SDK yeOpenCL Custom Platform Toolkit User Guide. Iyo Cyclone V SoC Development Kit Reference Platform Porting Guide haitsananguri mashandisirwo eSDK's Custom Platform Toolkit kuita Tsika Platform yeCyclone V SoC Development Kit. Inongotsanangura mutsauko uripo pakati perutsigiro rweSDK paCyclone V SoC Development Kit uye generic Intel FPGA SDK yeOpenCL Custom Platform.

Related Links

Intel FPGA SDK ye OpenCL Cyclone V SoC Kutanga Gwaro
Intel FPGA SDK yeOpenCL Custom Platform Toolkit User Guide

Cyclone V Device Handbook, Vhoriyamu 3: Hard processor System Technical Reference Manual
Cyclone V SoC Development Kit uye SoC Embedded Design Suite peji paAltera website

OpenCL nelogo yeOpenCL zviratidzo zveApple Inc. zvinoshandiswa nemvumo yeKhronos Group™.
Iyo Intel FPGA SDK yeOpenCL yakavakirwa pane yakaburitswa Khronos Specification, uye yakapfuura iyo Khronos Conformance Yekuyedza Maitiro. Ikozvino kuenderana mamiriro anogona kuwanikwa pa www.khronos.org/conformance.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus uye Stratix mazwi uye logos zviratidzo zveIntel Corporation kana masangano ayo muUS uye/kana dzimwe nyika. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
*Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

1.1.1 Cyclone V SoC Development Kit Reference Platform Board Variants
Iyo Intel FPGA SDK yeOpenCL Cyclone V SoC Development Kit Reference Platform inosanganisira maviri mabhodhi akasiyana.

c5soc bhodhi
Iri bhodhi rekutanga rinopa mukana kune maviri DDR memory mabhangi. Iyo HPS DDR inowanikwa neese FPGA neCPU. Iyo FPGA DDR inowanikwa chete neFPGA.
c5soc_sharedonly board
Iyi bhodhi musiyano ine chete HPS DDR yekubatanidza. Iyo FPGA DDR haisvikike. Iri bhodhi rakasiyana rinonyanya kushanda munzvimbo nekuti shoma Hardware inodiwa kutsigira imwe DDR memory bank. Iyo c5soc_sharedonly bhodhi zvakare yakanaka prototyping chikuva chekupedzisira kugadzira bhodhi ine imwechete DDR memory bank.
Kuti utarise iyi bhodhi musiyano paunenge uchigadzira yako OpenCL kernel, sanganisira iyo -board c5soc_sharedonly sarudzo mune yako aoc kuraira.
Kuti uwane rumwe ruzivo nezve -board sarudzo yeaoc command, tarisa kuIntel FPGA SDK yeOpenCL Programming Guide.

Related Links
Kugadzira Kernel yeChaiyo FPGA Bhodhi (-bhodhi )
1.1.2 Zviri mukati meCyclone V SoC Development Kit Reference Platform
Iyo Cyclone V SoC Yekuvandudza Kit Reference Platform ine zvinotevera files uye madhairekitori:

File kana Dhairekitori	Tsanangudzo
board_env.xml	eExtensible Markup Mutauro (XML) file iyo inotsanangura c5soc kuIntel FPGA SDK yeOpenCL.
linux_sd_card_image.tgz	Yakadzvanywa SD flash kadhi mufananidzo file iyo ine zvese zvinodiwa nemushandisi weSDK kushandisa Cyclone V SoC Development Kit ine SDK.
arm32	Dhairekitori rine zvinotevera:

1.1.3 Hunhu Hunoenderana neCyclone V SoC Development Kit

Rondedzero inotevera inosimbisa iyo Cyclone V SoC Development Kit zvikamu uye maficha anoenderana neIntel FPGA SDK yeOpenCL:

Dual-core ARM Cortex-A9 CPU inoshandisa 32-bit Linux.

Yepamberi eXtensible Interface (AXI) bhazi pakati peHPS neFPGA yepakati jira.
Maviri akaomeswa DDR memory controllers, imwe neimwe ichibatanidza kune 1 gigabyte (GB) DDR3 SDRAM.
- Imwe DDR controller inowanikwa kune iyo FPGA musimboti chete (kureva, FPGA DDR).
- Imwe DDR controller inowanikwa kune ese ari maviri HPS neFPGA (kureva, HPS DDR). Iyi yakagovaniswa controller inobvumira yemahara ndangariro kugovana pakati peCPU neiyo FPGA musimboti.

Iyo CPU inogona kugadzirisa zvakare iyo FPGA yepakati jira.

1.1.3.1 Cyclone V SoC Development Kit Reference Platform Design Goals and Decisions Intel inovamba kushandiswa kweCyclone V SoC Development Kit Reference Platform pazvinangwa zvakawanda zvekugadzira uye sarudzo. Intel inokurudzira kuti utarise zvibodzwa izvi uye sarudzo paunoisa iyi Reference Platform kune yako SoC FPGA board.
Pazasi pane c5soc dhizaini zvinangwa:

Ipa iyo yepamusoro-soro bandwidth pakati pema kernels paFPGA uye DDR memory system (s).
Ita shuwa kuti computations paFPGA (kureva, OpenCL kernels) haikanganise mamwe mabasa eCPU angangosanganisira kusevha maperipherals.

Siya yakawanda FPGA zviwanikwa sezvinobvira kune kernel computations panzvimbo ye interface zvikamu.

Pazasi pane yakakwirira-yepamusoro dhizaini sarudzo dziri mhedzisiro yakanangana neIntel's dhizaini zvinangwa:

Iyo Reference Platform inongoshandisa yakaoma DDR memory controllers ine widestpossible configuration (256 bits).
Iyo FPGA inotaurirana neHPS DDR memory controller zvakananga, pasina kubatanidza iyo AXI bhazi uye L3 switch mukati meHPS. Kukurukurirana kwakananga kunopa yakanakisa bandwidth kuDDR, uye inochengeta FPGA computations kubva mukukanganisa kutaurirana pakati peCPU nenzvimbo yayo.
Scatter-unganidza yakananga memory yekuwana (SG-DMA) haisi chikamu cheFPGA interface logic. Panzvimbo pekuendesa huwandu hukuru hwe data pakati peDDR memory system, chengetedza iyo data mune yakagovaniswa HPS DDR. Kupinda kwakananga kuCPU ndangariro neFPGA inoshanda zvakanyanya kupfuura DMA. Iyo inochengetedza zviwanikwa zvehardware (kureva, FPGA nharaunda) uye inorerutsa iyo Linux kernel mutyairi.
Yambiro: Kuchinjisa ndangariro pakati peiyo yakagovaniswa HPS DDR system uye iyo DDR system inowanikwa chete kuFPGA inononoka. Kana ukasarudza
kutamisa ndangariro nenzira iyi, ishandise kune mashoma mashoma e data chete.
Iyo saiti uye mudziyo anoita isiri-DMA data yekufambisa pakati peumwe neumwe kuburikidza neHPS-to-FPGA (H2F) zambuko, vachishandisa chete 32-bit chiteshi. Chikonzero ndechekuti, pasina DMA, iyo Linux kernel inogona kungoburitsa imwechete 32-bit yekuverenga kana kunyora chikumbiro, saka hazvifanirwe kuve nekubatana kwakakura.
Iyo saiti inotumira masaini ekudzora kune mudziyo kuburikidza neakareruka H2F (LH2F) zambuko.
Nekuti kudzora masaini kubva kumugadziri kuenda kune yakaderera-bandwidth masaini, LH2F zambuko rakanakira basa racho.

1.2 Kuendesa Reference Platform kune Yako SoC FPGA Board
Kuisa iyo Cyclone V SoC Development Kit Reference Platform kune yako SoC FPGA bhodhi, ita anotevera mabasa:

Sarudza iyo DDR ndangariro kana maviri DDR ndangariro vhezheni ye c5soc Reference Platform senzvimbo yekutanga dhizaini yako.
Gadziridza nzvimbo dzepini muALTERAOCLSDKROOT/bhodhi/c5soc/ /top.qsf file, uko ALTERAOCLSDKROOT ndiyo nzira inoenda kunzvimbo yeIntel FPGA SDK yekuisirwa OpenCL, uye ndiro zita redhairekitori remusiyano webhodhi. Iyo c5soc_sharedonly dhairekitori ndeyeiyo bhodhi mutsauko ine imwe DDR memory system. Iyo c5soc dhairekitori ndeyeiyo bhodhi musiyano ine maviri DDR memory masystem.
Gadziridza marongero eDDR eHPS uye/kana FPGA SDRAM mabhuroka muALTERAOCLSDKROOT/board/c5soc/ /system.qsys file.
4. Yese Intel FPGA SDK yeOpenCL yakasarudzika madhizaini ebhodhi anofanira kuwana yakavimbiswa kuvharwa kwenguva. Saka nekudaro, kuiswa kwedhizaini kunofanirwa kuve kwakachena nguva. Kuisa c5soc board partition (acl_iface_partition.qxp) kune yako SoC FPGA bhodhi, ita anotevera mabasa:
Kuti uwane mirairo yakadzama pamusoro pekugadzirisa uye kuchengetedza chikamu chebhodhi, tarisa kuQuartus
Prime Incremental Compilation yeHierarchical uye Team-Yakavakirwa Dhizaini chitsauko cheQuartus Prime Standard Edition Handbook.
a. Bvisa acl_iface_partition.qxp kubva kune ALTERAOCLSDKROOT/board/c5soc/c5soc directory.
b. Gonesa iyo acl_iface_region LogicLock™ dunhu nekushandura Tcl command set_global_assignment -name LL_ENABLED OFF -section_id acl_iface_region to set_global_assignment -zita LL_ENABLED ON -section_id acl_iface_region
c. Nyora OpenCL kernel yebhodhi rako.
d. Kana zvichidikanwa, gadzirisa saizi uye nzvimbo yeLogicLock dunhu.
e. Kana wagutsikana kuti kuiswa kwedhizaini yako kuri kuita nguva yakachena, tumira kunze chikamu ichocho se acl_iface_partition.qxp Quartus Prime Exported Partition File.
Sekutsanangurwa kwazvinoitwa muchikamu cheKugadzira Yakavimbiswa Nguva Yekuyerera kweAIntel FPGA SDK yeOpenCL Custom Platform Toolkit User Guide, nekupinza iyi .qxp file mukugadzirwa kwepamusoro-soro, iwe unozadzisa chinodikanwa chekupa dhizaini yebhodhi ine yakavimbiswa yekuvhara nguva yekuyerera.
Kune zvinhu zvinogona kukanganisa kunaka kwemhedzisiro (QoR) yechikamu chako chinotengeswa kunze kwenyika, tarisa kune General Hunhu hweMibairo Yekutarisisa yeExported Board Partition chikamu muIntel FPGA SDK yeOpenCL Custom Platform Toolkit User Guide.
f. Dzima iyo acl_iface_region LogicLock dunhu nekudzoreredza murairo muChikamu 2 kudzokera kuset_global_assignment -zita LL_ENABLED OFF chikamu_id acl_iface_region.
Kana yako SoC FPGA bhodhi ichishandisa mapini akasiyana uye maperipheries eHPS block, gadzirazve preloader uye mudziyo muti sosi (DTS) file. Kana iwe ukashandura iyo HPS DDR memory controller marongero, ita patsva iyo preloader.
Gadzira iyo SD flash kadhi mufananidzo.
Gadzira yako Yetsika Platform, iyo inosanganisira iyo SD flash kadhi mufananidzo.
Funga kugadzira vhezheni yenguva yekumhanya yeCustom Platform yako yekushandisa neIntel FPGA Runtime Environment (RTE) yeOpenCL. Iyo RTE vhezheni yeCustom Platform yako haisanganisi hardware madhairekitori uye SD flash kadhi kadhi mufananidzo. Iyi Yetsika Platform inoremedza paSoC FPGA system yekubvumira maapplication ekugamuchira kuti ashande. Mukupesana, iyo SDK vhezheni yeCustom Platform inodiwa kuti SDK iunganidze OpenCL kernels.
Zano: Unogona kushandisa SDK vhezheni yeCustom yako Platform yeRTE. Kuchengeta
nzvimbo, bvisa iyo SD flash kadhi mufananidzo kubva kuRTE vhezheni yeCustom Platform yako.
Edza yako Custom Platform.
Tarisa kune Kuyedza iyo Hardware Dhizaini chikamu cheIntel FPGA SDK yeOpenCL Tsika Platform Toolkit Mushandisi Guide kuti uwane rumwe ruzivo.

Related Links

Kuedza iyo Hardware Dhizaini
Quartus Prime Incremental Compilation yeHierarchical uye Team-Yakavakirwa Dhizaini

Kugadzira Yakavimbiswa Nguva Yekuyerera
Hunhu Hwose Hwemibairo Yekutarisisa kune Iyo Exported Board Partition

1.2.1 Kuvandudza Ported Reference Platform
Mune yazvino vhezheni yeCyclone V SoC Development Kit Reference Platform, iyo HPS block iri mukati mechikamu chinotsanangura zvese nonkernel logic. Zvakadaro, haugone kunze kweHPS sechikamu che .qxp file. Kuti uvandudze Custom Platform iripo yawakagadziridza kubva kune yakare vhezheni ye c5soc, shandisa QXP kuchengetedza mafambiro, gadziridza SD flash kadhi mufananidzo kuti uwane ichangoburwa nharaunda yekumhanya, uye gadziridza board_spec.xml file kugonesa automigration.
Iyo Altera® SDK yeOpenCL vhezheni 14.1 uye kupfuura inoongorora iyo board_spec.xml file yeruzivo rwebhodhi, uye inoshandisa otomatiki inogadziridza. Nekuti iwe unogadzirisa iyo
dhizaini nekushandisa QXP kuchengetedza kuyerera, unofanira kugadzirisa board_spec.xml file kune chimiro chayo mune yazvino vhezheni. Updating the file inobvumira iyo SDK kusiyanisa pakati peasina kuchengetedzwa Tsika Platform uye ikozvino QXP-based Custom Platform. Tarisa kuCustom Platform Automigration yeForward Compatibility muIntel FPGA SDK yeOpenCL Custom Platform Toolkit User Guide kuti uwane rumwe ruzivo.

Kushandisa QXP kuchengetedza kuyerera muCyclone V SoC FPGA hardware dhizaini iyo inotakurwa kubva kune yakare vhezheni ye c5soc, ita zvinotevera matanho ekugadzira chidimbu kuti usasanganise HPS kubva ku.qxp file:
a. Usati wagadzira chikamu chakatenderedza nonkernel zvinonzwisisika, gadzira chikamu chakatenderedza HPS mu.qsf Quartus Prime Settings. File.
For example:
# Nemaoko patsanura muenzaniso uyo unoenzanisira HPS-yakatsaurirwa I/O set_instance_assignment -zita PARTITION_HIERARCHY borde_18261 -ku "system: the_system|system_acl_iface:acl_iface|system_acl_iface_hps_0:hps_0|system_psh_acl_i0: system_acl_iface_hps_0_hps_io_border:border" -section_id "system_acl_iface_hps_0_hps_io_border:border"
# Seta chikamu kuti ive HPS_PARTITION mhando kuti igadziriswe nemazvo neQuartus yese.
set_global_assignment -zita PARTITION_TYPE HPS_PARTITION -section_id "system_acl_iface_hps_0_hps_io_border:border"
quartus_cdb pamusoro -c pamusoro
-incremental_compilation_export=acl_iface_partition.qxp
-incremental_compilation_export_partition_name=acl_iface_partition
-incremental_compilation_export_post_synth=on
-incremental_compilation_export_post_fit=on
-incremental_compilation_export_routing=on
-incremental_compilation_export_flatten=off
Mushure mekunge wabvisa HPS kubva pachikamu, unogona kunze kwenyika .qxp file uye gadzira dhizaini yako.
Gadziridza iyo SD flash kadhi mufananidzo neiyo yazvino vhezheni yeIntel FPGA RTE yeOpenCL nekuita anotevera mabasa:
a. Mount the file tafura yekugovera (fat32) uye yakawedzerwa file system (ext3) partitions mumufananidzo uripo se loop-back zvishandiso. Kuti uwane mirairo yakadzama, tarisa Danho rechipiri muKuvaka SD Flash Card Image.
b. Mu /home/root/opencl_arm32_rte dhairekitori, bvisa iyo files kubva kune yakapfuura vhezheni yeRTE.
c. Dhawunirodha uye buritsa iyo yazvino verison yeRTE mu /home/root/opencl_arm32_rte dhairekitori.
d. Mu /mutyairi/shanduro.h file yeCustom Platform yako, gadziridza iyo ACL_DRIVER_VERSION basa kuti . (semuzample, 16.1.x, apo 16.1 iri SDK verison, uye x ndiyo vhezheni yemutyairi yawakaseta).
e. Vakazve mutyairi.
f. Dzima iyo hardware folda (s) yeCustom yako Platform. Kopa Custom Platform, pamwe nemutyairi akagadziridzwa, kune /home/root/opencl_arm_rte/board directory.
g. Kopa iyo Altera.icd file kubva ku /home/root/opencl_arm32_rte dhairekitori uye woiwedzera kune /etc/OpenCL/vendorrs directory.
h. Burutsa uye edza mufananidzo mutsva. Kuti uwane mirairo yakazara, tarisa Matanho 8 kusvika 11 muKuvaka SD Flash Card Image.

Related Links

Kugadzira mufananidzo we SD Flash Card papeji 14
Iwe zvakare une sarudzo yekugadzira nyowani SD flash kadhi mufananidzo.
Custom Platform Automigration ye Forward Compatibility

1.3 Rutsigiro rweSoftware yeYakagovaniswa Memory
Yakagovaniswa ndangariro yemuviri pakati peFPGA neCPU ndiyo yakasarudzika ndangariro yeOpenCL kernels inomhanya paSoC FPGAs. Nekuti iyo FPGA inowana yakagovaniswa ndangariro yemuviri, kupesana neyakagovaniswa ndangariro, haina mukana kune iyo CPU's peji matafura anomepu emushandisi kero kero kune echokwadi peji kero.
Nekuremekedza kune Hardware, OpenCL kernels kuwana yakagovaniswa ndangariro yemuviri kuburikidza nekubatanidza yakananga kune HPS DDR hard memory controller. Nekuremekedza software, tsigiro yekugovana ndangariro yemuviri inosanganisira zvinotevera kufunga:

Yakajairika mashandisirwo esoftware yekugovera ndangariro paCPU (yeexample, iyo malloc () basa) haigone kugovera nzvimbo yekurangarira iyo FPGA ingashandise.
Memory iyo malloc () basa rinogovera inopindirana mune chaiyo ndangariro kero nzvimbo, asi chero ari pasi pemapeji emuviri haafanire kuve akabatana panyama. Saka nekudaro, mugamuchiri anofanirwa kukwanisa kugovera matunhu-akabatana ndangariro. Nekudaro, kugona uku hakupo mumashandisi-nzvimbo maapplication paLinux. Naizvozvo, mutyairi weLinux kernel anofanira kuita kugovera.
Iyo OpenCL SoC FPGA Linux kernel mutyairi inosanganisira mmap () basa rekugovera yakagovaniswa ndangariro yemuviri uye mepu munzvimbo yemushandisi. Iyo mmap () basa rinoshandisa yakajairwa Linux kernel kufona dma_alloc_coherent () kukumbira matunhu-anobatikana endangariro nzvimbo dzekugovana nemudziyo.
Mune iyo default Linux kernel, dma_alloc_coherent () haigoveri yemuviri-inobatika ndangariro kupfuura 0.5 megabytes (MB) muhukuru. Kubvumira dma_alloc_coherent () kugovera huwandu hukuru hwemuviri-inobatika ndangariro, gonesa iyo contiguous memory allocator (CMA) chimiro cheLinux kernel uye wozodzosera iyo Linux kernel.
YeCyclone V SoC Development Kit Reference Platform, CMA inobata 512 MB kunze kwe1 GB yendangariro yemuviri. Iwe unogona kuwedzera kana kuderedza kukosha uku, zvichienderana nehuwandu hwekugovana ndangariro inodiwa neapp. Iyo dma_alloc_coherent() kufona inogona kusakwanisa kugovera iyo yakazara 512 MB yemuviri- inobatana ndangariro; zvisinei, inogona kugara ichiwana ingangoita 450 MB yendangariro.

Iyo CPU inogona cache ndangariro iyo dma_alloc_coherent () inodaidza inogovera. Kunyanya, nyora mashandiro kubva kune iyo host application haisi kuoneka kune OpenCL kernels. Iyo mmap () basa muOpenCL SoC FPGA Linux kernel mutyairi zvakare ine mafoni kune pgprot_noncached () kana remap_pf_range () basa rekudzima caching yedunhu iri rendangariro zvakajeka.
Mushure meiyo dma_alloc_coherent() basa ragovera ndangariro-inotenderedza ndangariro, mmap () basa rinodzosera iyo chaiyo kero kumavambo kwerenji, inova kero yenguva yendangariro yaunogovera. Iyo yekushandisa application inoda iyi kero chaiyo kuti uwane ndangariro. Kune rimwe divi, OpenCL kernels inoda kero dzemuviri. Iyo Linux kernel mutyairi anochengeta iyo chaiyo-kune-yemuviri kero mepu. Unogona kumepu kero dzemuviri izvo mmap() inodzokera kumakero chaiwo nekuwedzera mubvunzo kumutyairi.
Iyo aocl_mmd_shared_mem_alloc() MMD application programming interface (API) call inosanganisira inotevera mibvunzo:
a. Iyo mmap () basa rinogovera ndangariro uye rinodzosera iyo chaiyo kero.
b. Mubvunzo wekuwedzera unoburitsa kero yakadzoserwa kune chaiyo kero.
Iyo aocl_mmd_shared_mem_alloc() MMD API call yobva yadzosa kero mbiri.
-kero chaiyo yakadzoserwa ndiyo kero chaiyo, uye kero yemuviri inoenda kumudziyo_ptr_out.
Cherechedza: Mutyairi anogona chete mepu chaiyo kero iyo mmap () basa rinodzokera kumakero emuviri. Kana iwe ukakumbira kero yemuviri yeimwe chaiyo pointer, mutyairi anodzosa kukosha kweNULL.

Yambiro: Iyo Intel FPGA SDK yemaraibhurari eOpenCL runtime inofungidzira kuti ndangariro yakagovaniswa ndiyo yekutanga ndangariro yakanyorwa mubhodhi_spec.xml file. Mune mamwe mazwi, iyo kero yemuviri iyo Linux kernel mutyairi anowana inova iyo Avalon® kero iyo OpenCL kernel inopfuudza kuHPS SDRAM.
Nekuremekedza raibhurari yenguva yekumhanya, shandisa iyo clCreateBuffer () kufona kugovera iyo yakagovaniswa ndangariro sechishandiso buffer nenzira inotevera:

Kune maviri-DDR bhodhi musiyano ane ese akagovaniswa uye asina kugovaniswa ndangariro, clCreateBuffer() inogovera yakagovaniswa ndangariro kana iwe ukatsanangura CL_MEM_USE_HOST_PTR mureza. Kushandisa mamwe mireza kunokonzeresa clCreateBuffer() kugovera buffer mundangariro isina kugovaniswa.
Kune iyo imwe-DDR bhodhi musiyano ine chete yakagovaniswa ndangariro, clCreateBuffer () inogovera yakagovaniswa ndangariro zvisinei kuti ndeupi mureza waunotsanangura.
Parizvino, 32-bit Linux tsigiro paARM CPU inotonga huwandu hwekugoverana ndangariro rutsigiro mumaraibhurari eSDK ekumhanya. Mune mamwe mazwi, maraibhurari ekumhanya anounganidzwa kune mamwe nharaunda (yeexample, x86_64 Linux kana 64-bit Windows) haitsigire ndangariro dzakagovaniswa.
C5soc haina kuita heterogeneous ndangariro kusiyanisa pakati pekugovana uye kusagovaniswa ndangariro nekuda kwezvikonzero zvinotevera:
1. Nhoroondo—Heterogeneous memory support yanga isipo apo tsigiro yendangariro yakagovaniswa yakasikwa.
2. Uniform interface-Nekuti OpenCL chiyero chakavhurika, Intel inochengetedza kuenderana pakati pevashambadziri vepuratifomu yekombuta. Naizvozvo, iyo yakafanana interface semamwe mabhodhi vatengesi 'zvivakwa inoshandiswa kugovera uye kushandisa yakagovaniswa ndangariro.

1.4 FPGA Reconfiguration
Kune SoC FPGAs, iyo CPU inogona kugadzirisa zvakare FPGA musimboti jira pasina kukanganisa kushanda kweCPU. Iyo FPGA Maneja Hardware block iyo inofamba neHPS uye yakakosha FPGA inoita kugadziridza. Iyo Linux kernel inosanganisira mutyairi anogonesa kupinda nyore kune iyo FPGA Maneja.

To view mamiriro eiyo FPGA musimboti, daidza katsi /sys/class/fpga/fpga0/ status command.
Iyo Intel FPGA SDK yeOpenCL chirongwa chekushandisa chinowanikwa neCyclone V SoC Development Kit Reference Platform inoshandisa iyi interface kuronga iyo FPGA. Paunenge uchigadzirisazve FPGA musimboti ine inomhanya CPU, chirongwa chekushandisa chinoita ese anotevera mabasa:
1. Kusati kwarongwa patsva, dzima mabhiriji ese ekutaurirana pakati peFPGA neHPS, ese mabhiriji eH2F neLH2F.
Vhurazve mabhiriji aya mushure mekunge reprogramming yapera.
Chenjerera: Iyo OpenCL system haishandise iyo FPGA-to-HPS (F2H) zambuko. Tarisa kune chikamu cheHPS-FPGA Interfaces muCyclone V Device Handbook, Vhoriyamu 3: Yakaoma processor System Technical Reference Manual kuti uwane rumwe ruzivo.
2. Ita shuwa kuti chinongedzo chiri pakati peFPGA neHPS DDR controller chakavharwa panguva yekudzokorora.
3. Ita shuwa kuti iyo FPGA inovhiringidza paFPGA yakavharwa panguva yekudzokorora.
Zvakare, zivisa mutyairi kuti arambe chero kukanganisa kubva kuFPGA panguva yekugadzirisa.

Bvunza iyo source code yepurogiramu utility kuti uwane ruzivo rwekuita chaiko.

Yambiro: Usashandure kumisikidzwa kweHPS DDR controller kana CPU iri kushanda.
Kuita izvi kunogona kukonzera inouraya sisitimu kukanganisa nekuti iwe unogona kushandura iyo DDR controller kumisikidzwa kana paine yakasarudzika memory transaction kubva kuCPU. Izvi zvinoreva kuti kana CPU iri kushanda, haugone kudzokorodza iyo FPGA musimboti nemufananidzo unoshandisa HPS DDR mune imwe gadziriso.
Rangarira kuti OpenCL system, uye yeGolden Hardware referensi dhizaini inowanikwa neIntel SoC FPGA Embedded Design Suite (EDS), inoisa HPS DDR kuita imwechete 256-bit modhi.
CPU system zvikamu senge fungidziro yebazi kana tafura yepeji prefetcher inogona kuburitsa DDR mirairo kunyangwe ichiita kunge hapana chiri kushanda paCPU.
Naizvozvo, nguva yebhutsu ndiyo chete nguva yakachengeteka yekuseta iyo HPS DDR controller kumisikidza.
Izvi zvinoreva zvakare kuti U-bhutsu inofanirwa kunge ine mbishi bhinari file (.rbf) mufananidzo kuti uise mundangariro. Zvikasadaro, unogona kunge uchigonesa iyo HPS DDR nemachiteshi asina kushandiswa paFPGA uye wozokwanisa kushandura magadzirirwo echiteshi mushure. Nechikonzero ichi, iyo OpenCL Linux kernel mutyairi haachasanganisi pfungwa inodiwa kuseta iyo HPS DDR controller kumisikidzwa.
Iyo SW3 dual in-line package (DIP) inochinja Cylone V SoC Development Kit inodzora chimiro chinotarisirwa chemufananidzo we.rbf (kureva, kana file yakamanikidzwa uye/kana yakavharidzirwa). C5soc, neGolden Hardware Reference Design inowanikwa neSoC EDS, inosanganisira mifananidzo yakamanikidzwa asi isina kunyorwa .rbf. Iyo SW3 DIP chinja marongero anotsanangurwa muIntel FPGA SDK yeOpenCL Cyclone V SoC Getting Start Guide inowirirana neichi .rbf chigadziriso chemufananidzo.

Related Links

HPS-FPGA Interfaces
Kugadzirisa iyo SW3 Swichi

1.4.1 FPGA System Architecture Details
Tsigiro yeCyclone V SoC Development Kit Reference Platform yakavakirwa paStratix® V Reference Platform (s5_ref), inowanikwa neIntel FPGA SDK yeOpenCL.
Sangano rose re c5soc Qsys system uye mutyairi wekernel akafanana chaizvo neaya ari mu s5_ref.
Aya anotevera FPGA musimboti zvikamu zvakafanana mune ese c5soc uye s5_ref:

VERSION_ID block
Rest mechanism

Memory bank divider
Cache snoop interface
Kernel wachi

Kudzora rejista yekuwana (CRA) inovhara

1.5 Kuvaka mufananidzo we SD Flash Card
Nekuti iyo Cyclone V SoC FPGA izere sisitimu pane chip, iwe une basa rekuunza tsanangudzo yakazara yehurongwa. Intel inokurudzira kuti uiunze iri muchimiro chemufananidzo weSD flash kadhi. Iyo Intel FPGA SDK yeOpenCL mushandisi inogona kungonyora mufananidzo kune iyo micro SD flash kadhi uye iyo SoC FPGA bhodhi yakagadzirira kushandiswa.
Kugadzirisa Iripo SD Flash Card Mufananidzo uri papeji 13
Intel inokurudzira kuti iwe unongogadzirisa mufananidzo unowanikwa neCyclone V SoC Development Kit Reference Platform. Iwe zvakare une sarudzo yekugadzira nyowani SD flash kadhi mufananidzo.
Kugadzira mufananidzo we SD Flash Card papeji 14
Iwe zvakare une sarudzo yekugadzira nyowani SD flash kadhi mufananidzo.

1.5.1 Kugadzirisa Mufananidzo Uripo weSD Flash Card
Intel inokurudzira kuti iwe unongogadzirisa mufananidzo unowanikwa neCyclone V SoC
Development Kit Reference Platform. Iwe zvakare une sarudzo yekugadzira nyowani SD flash kadhi mufananidzo.
Iyo c5soc linux_sd_card_image.tgz mufananidzo file inowanikwa muALTERAOCLSDKROOT/bhodhi/c5soc dhairekitori, uko ALTERAOCLSDKROOT inonongedza kunzira yeIntel FPGA SDK yeOpenCL yekuisa dhairekitori.

Chenjerera: Kuti ugadzirise iyo SD flash kadhi mufananidzo, unofanirwa kuve nemidzi kana sudo ropafadzo.

Kubvisa iyo $ALTERAOCLSDKROOT/board/c5soc/linux_sd_card_image.tgz file, mhanyisa tar xvfzlinux_sd_card_image.tgz kuraira.
Tora iyo hello_world OpenCL example dhizaini uchishandisa yako Custom Platform rutsigiro. Rename the .rbf file iyo Intel FPGA SDK yeOpenCL Offline Compiler inogadzira se opencl.rbf, woiisa pafat32 partition mukati meSD flash card image.
Unogona kudhawunirodha hello_world exampdhizaini kubva kuOpenCL Dhizaini ExampLes peji paAltera website.

Isa iyo .rbf file mufat32 chikamu chemufananidzo weflash kadhi.
Chenjerera: Iyo fat32 partition inofanira kunge iine ese ari maviri ziImage file uye .rbf file. Pasina .rbf file, kukanganisa kunouraya kuchaitika paunopinza mutyairi.
Mushure mekugadzira iyo SD kadhi mufananidzo, nyora kune micro SD kadhi nekudaidza unotevera murairo: sudo dd if=/path/to/sdcard/image.bin ye=/dev/sdcard
Kuti uedze mufananidzo wako weSD flash card, ita zvinotevera mabasa:
a. Isa iyo micro SD flash kadhi muSoC FPGA bhodhi.
b. Simba kumusoro kwebhodhi.
c. Koka iyo aocl yekuongorora utility command.

1.5.2 Kugadzira mufananidzo we SD Flash Card
Iwe zvakare une sarudzo yekugadzira nyowani SD flash kadhi mufananidzo. Generic mirayiridzo yekuvaka mufananidzo mutsva weSD flash kadhi uye kuvakazve iripo SD flash kadhi mufananidzo unowanikwa pane GSRD v14.0.2 - SD Kadhi peji reRocketBoards.org website.
Matanho ari pazasi anotsanangura maitiro ekugadzira iyo linux_sd_card_image.tgz mufananidzo kubva kuGolden System Reference Dhizaini (GSRD) SD flash kadhi mufananidzo:
Cherechedza:
Kuti ugadzire mufananidzo kubva pamufananidzo we c5soc, ita mabasa ese anoshanda akatsanangurwa mune iyi maitiro.

Dhawunirodha uye buritsa iyo GSRD SD flash kadhi mufananidzo shanduro 14.0 kubva Rocketboards.org.
Mount the file tafura yekugovera (fat32) uye yakawedzerwa file system (ext3) partitions mumufananidzo uyu se loop-back zvishandiso. Kuti uise partition, ita nhanho dzinotevera:
a. Sarudza iyo byte yekutanga yekuparadzanisa mukati memufananidzo nekukokera iyo /sbin/fdisk -lu image_file command.
For example, partition number 1 yerudzi W95 FAT ine block offset ye 2121728. Ne 512 byte pa block, iyo byte offset ndeye 512 bytes x 2121728 = 1086324736 bytes.
b. Ziva mudziyo wemahara loop (yeexample, /dev/loop0) nekunyora kurasika -f kuraira.
c. Kufungidzira / dev / loop0 ndiyo yemahara loop mudziyo, govera yako flash kadhi mufananidzo kune loop block mudziyo nekudaidza iyo yekurasika / dev/loop0 mufananidzo_file -0 1086324736 command.
d. Isa iyo loop mudziyo nekudaidza gomo /dev/loop0 /media/disk1 raira.
Mukati memufananidzo file, /media/disk1 ikozvino yakasungirirwa fat32 partition.
e. Dzokorora matanho a kusvika d kune ext3 chikamu.

Dhawunirodha iyo Cyclone V SoC FPGA vhezheni yeIntel FPGA Runtime Nzvimbo yeOpenCL package kubva kuDownload Center paAltera. website.
a. Dzvanya bhatani reKurodha padivi peQuartus Prime software edition.
b. Taura vhezheni yekuburitsa, sisitimu yekushandisa, uye nzira yekurodha.
c. Dzvanya iyo Yekuwedzera Software tab, uye sarudza kurodha Intel FPGA
Runtime Nzvimbo yeOpenCL Linux Cyclone V SoC TGZ.
d. Mushure mekutora iyo aocl-rte- .im32.tgz file, buritsa ku
dhairekitori raunaro.
Isa iyo isina kurongedzerwa aocl-rte- .arm32 dhairekitori mu /home/mudzi/opencl_arm32_rte dhairekitori pane ext3 partition yemufananidzo file.
Dzima iyo hardware folda (s) yeCustom Platform yako, uye woisa iyo Yetsika Platform mubhodhi subdirectory ye /home/root/ opencl_arm32_rte.

Gadzira iyo init_opencl.sh file mune / imba/mudzi dhairekitori ine zvinotevera zvirimo: kunze ALTERAOCLSDKROOT=/imba/mudzi/opencl_arm32_rte kunze AOCL_BOARD_PACKAGE_ROOT=$ALTERAOCLSDKROOT/bhodhi/ kunze PATH=$ALTERAOCLSDKROOT/bin:$PATH kunze LD_LIBRARY_PATH=$ALTERAOCLSDKROOT/host/arm32/lib:$LD_LIBRARY_PATH insmod $AOCL_BOARD_PACKAGE_ROOT/driver/aclsoc_drv.ko
Mushandisi weSDK ndiye anomhanyisa kwainobva ./init_opencl.sh kuraira kurodha mamiriro ekunze uye mutyairi weOpenCL Linux kernel.
Kana iwe uchida kugadzirisa iyo preloader, iyo DTS files, kana iyo Linux kernel, unoda ruoko-linux-gnueabihf-gcc compiler kubva kuSoC EDS. Tevedza mirairo yakatsanangurwa muIntel SoC FPGA Embedded Design Suite Mushandisi Guide kuti utore software, uidzorere, uye nekuvandudza yakakodzera. files pane yakasimudzwa fat32 partition.
Chenjerera: Zvinonyanya kuitika kuti iwe unofanirwa kugadzirisa preloader kana yako Yetsika Platform ine mapini akasiyana mashandisirwo pane ayo ari mu c5soc.
Rangarira: Kana iwe ukadzosera iyo Linux kernel, dzokorora iyo Linux kernel mutyairi ane yakafanana Linux kernel sosi. files. Kana paine kusawirirana pakati peLinux kernel mutyairi neLinux kernel, mutyairi haatakure. Zvakare, iwe unofanirwa kugonesa iyo CMA.
Tarisa kuKudzorera iyo Linux Kernel kuti uwane rumwe ruzivo.
Tora iyo hello_world OpenCL example dhizaini uchishandisa yako Custom Platform rutsigiro. Rename the .rbf file iyo Intel FPGA SDK yeOpenCL Offline Compiler inogadzira se opencl.rbf, woiisa pafat32 partition mukati meSD flash card image.
Unogona kudhawunirodha hello_world exampdhizaini kubva kuOpenCL Dhizaini ExampLes peji paAltera website.
9. Mushure mekunge machengeta zvose zvinodiwa files pamufananidzo weflash card, daidza mirairo inotevera:
a. sync
b. bvisa /media/disk1
c. unmount kupi ndiro zita redhairekitori raunoshandisa kukwirisa ext3 partition mu3 papeji 3 (ye ex.ample, /media/disk2).
d. kurasikirwa -d /dev/loop0
e. kurasikirwa -d /dev/loop1

Dzvinya iyo SD flash kadhi mufananidzo nekukokera unotevera kuraira: tar cvfz .tgz linux_sd_card_image
Delive the .tgz file mukati memudzi wedhairekitori yeCustom yako Platform.
Kuti uedze mufananidzo wako weSD flash card, ita zvinotevera mabasa:
a. Nyora mhedzisiro isina kumisikidzwa mufananidzo pane micro SD flash kadhi.
b. Isa iyo micro SD flash kadhi muSoC FPGA bhodhi.
c. Simba kumusoro kwebhodhi.
d. Koka iyo aocl yekuongorora utility command.

Related Links

Intel SoC FPGA Yakamisikidzwa Dhizaini Suite Mushandisi Yekushandisa
OpenCL Dhizaini ExampLes peji paAltera website

Kudzokorora iyo Linux Kernel pane peji 16
Kuti ugone kugonesa CMA, unofanira kutanga wadzoreredza iyo Linux kernel.
Kubvunza Zita reChishandiso cheFPGA Bhodhi yako (kuongorora)

1.6 Kugadzira iyo Linux Kernel yeCyclone V SoC FPGA
Usati wamhanyisa OpenCL zvikumbiro paCyclone V SoC FPGA board, iwe unofanirwa kuunganidza iyo Linux kernel sosi, uye kuunganidza uye kuisa OpenCL Linux kernel mutyairi.

Kudzokorora iyo Linux Kernel pane peji 16
Kuti ugone kugonesa CMA, unofanira kutanga wadzoreredza iyo Linux kernel.
Kuunganidza uye Kuisa iyo OpenCL Linux Kernel Driver pane peji 17 Gadzira iyo OpenCL Linux kernel mutyairi uchipesana neyakaunganidzwa kernel sosi.

1.6.1 Kudzorerazve Linux Kernel
Kuti ugone kugonesa CMA, unofanira kutanga wadzoreredza iyo Linux kernel.

Dzvanya iyo GSRD v14.0 - Kunyora Linux link pane Zvishandiso peji reRocketBoards.org websaiti yekuwana mirairo yekurodha uye kuvakazve iyo Linux kernel source code.
Yekushandisa ne™ Intel FPGA SDK yeOpenCL, tsanangura socfpga-3.13-rel14.0 seyo .
Cherechedza: Maitiro ekuvaka anogadzira arch/arm/configs/socfpga_defconfig file. Izvi file inotsanangura marongero eiyo socfpga default configuration.
Wedzera mitsara inotevera kuzasi kwearch/arm/configs/socfpga_defconfig file.
CONFIG_MEMORY_ISOLATION=y
CONFIG_CMA=y
CONFIG_DMA_CMA=y
CONFIG_CMA_DEBUG=y
CONFIG_CMA_SIZE_MBYTES=512
CONFIG_CMA_SIZE_SEL_MBYTES=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
Iko CONFIG_CMA_SIZE_MBYTES yekumisikidza kukosha inoisa muganho wepamusoro pahuwandu hwese hwemuviri inobatika memory iripo. Iwe unogona kuwedzera kukosha uku kana iwe uchida imwe ndangariro.
Chenjerera: Huwandu hwese hwendangariro hwemuviri hunowanikwa kune ARM processor pane SoC FPGA board ndeye 1 GB. Intel haikurudzire kuti uise maneja weCMA padyo ne1 GB.

Mhanya iyo make mrproper command kuti uchenese ikozvino gadziriso.
Mhanyai make ARCH=arm socfpga_deconfig command.
ARCH = ruoko runoratidza kuti unoda kumisikidza iyo ARM yekuvakisa.
socfpga_defconfig inoratidza kuti unoda kushandisa iyo default socfpga kumisikidza.
Mhanya kutumira kunze CROSS_COMPILE=arm-linux-gnueabihf- command.
Uyu murairo unoseta CROSS_COMPILE nharaunda inosiyana kuti itaure prefix yeinodiwa cheni yechishandiso.

Mhanya iyo make ARCH = ruoko zImage command. Mufananidzo unoguma unowanikwa mune arch/arm/boot/zImage file.
Isa zImage file mufat32 chikamu chemufananidzo weflash kadhi. Kuti uwane mirairo yakadzama, tarisa kune Cyclone V SoC FPGA-yakananga GSRD User Manual paRocketboards.org.
Cherechedza: Kuisa nemazvo OpenCL Linux kernel driver, tanga waisa SDKgenerated.rbf file kuFPGA.
Kugadzira iyo .rbf file, gadzira SDK dhizaini example neCyclone V SoC Development Kit Reference Platform seyakanangwa Yetsika Platform.
9. Isa iyo .rbf file mufat32 chikamu chemufananidzo weflash kadhi.
Chenjerera: The fat32 partition inofanira kunge iine zvese zImage file uye .rbf file. Pasina .rbf file, kukanganisa kunouraya kuchaitika paunopinza mutyairi.

Isa iyo yakarongwa micro SD kadhi, iyo ine SD kadhi mufananidzo wawakashandura kana kugadzira kare, muCyclone V SoC Development Kit uye wobva wasimudza SoC FPGA bhodhi.
Simbisa iyo vhezheni yeLinux kernel yakaiswa nekumhanyisa uname -r command.
Kuti uone kuti unogonesa CMA zvinobudirira mu kernel, neiyo SoC FPGA bhodhi yakasimudzwa, mhanya iyo grep init_cma /proc/kallsyms command.
CMA inogoneswa kana iyo inobuda isina chinhu.

Kuti ushandise iyo yakadzokororwa Linux kernel ine SDK, unganidza uye isa iyo Linux kernel mutyairi.

Related Links

Goridhe System Reference Dhizaini (GSRD) Mushandisi Manuals

Kuvaka mufananidzo we SD Flash Card papeji 13
Nekuti iyo Cyclone V SoC FPGA izere sisitimu pane chip, iwe une basa rekuunza tsanangudzo yakazara yehurongwa.

1.6.2 Kuunganidza uye Kuisa OpenCL Linux Kernel Driver
Gadzira iyo OpenCL Linux kernel mutyairi uchipesana neyakaunganidzwa kernel sosi.

Iyo mutyairi sosi inowanikwa muCyclone V SoC FPGA vhezheni yeIntel FPGA Runtime Nzvimbo yeOpenCL. Pamusoro pezvo, iva nechokwadi chekuti watakura Intel FPGA SDK yeOpenCL-generated .rbf file muFPGA kudzivirira kuisirwa zvisirizvo kweLinux kernel module.

Dhawunirodha iyo Cyclone V SoC FPGA vhezheni yeIntel FPGA Runtime Nzvimbo yeOpenCL package kubva kuDownload Center paAltera. website.
a. Dzvanya bhatani reKurodha padivi peQuartus Prime software edition.
b. Taura vhezheni yekuburitsa, sisitimu yekushandisa, uye nzira yekurodha.
c. Dzvanya iyo Yekuwedzera Software tab, uye sarudza kurodha Intel FPGA
Runtime Nzvimbo yeOpenCL Linux Cyclone V SoC TGZ.
d. Mushure mekutora iyo aocl-rte- .im32.tgz file, buritsa ku
dhairekitori raunaro.
Mutyairi sosi iri mune aocl-rte- .arm32/board/c5soc/ driver directory.
Kuti udzokorore iyo OpenCL Linux kernel mutyairi, isa iyo KDIR kukosha mune yemutyairi Makefile kune dhairekitori rine Linux kernel source files.
Mhanya kutumira kunze CROSS_COMPILE=arm-linux-gnueabihf- kuraira kuratidza prefix yecheni yako yekushandisa.

Mhanyai make clean command.
Mhanya iyo make command kugadzira iyo aclsoc_drv.ko file.
Chinja iyo opencl_arm32_rte dhairekitori kune Cyclone V SoC FPGA bhodhi.
Kumhanya iyo scp -r mudzi@yako-ipaddress: command inoisa iyo yekumhanyisa nharaunda mu/home/root directory.

Mhanya iyo init_opencl.sh script yawakagadzira pawakavaka iyo SD cardimage.
Koka iyo aocl yekuongorora utility command. Chishandiso chekuongorora chinodzosa mhedzisiro mushure mekunge wamhanya init_opencl.sh zvakabudirira.

1.7 Nyaya Dzinozivikanwa
Parizvino, pane zvimwe zvipimo pakushandiswa kweIntel FPGA SDK yeOpenCL ine Cyclone V SoC Development Kit Reference Platform.

Haukwanise kunzvenga mutengesi nemazita ebhodhi akashumwa neCL_DEVICE_VENDOR neCL_DEVICE_NAME tambo dze clGetDeviceInfo() call.
Kana muenzi akagovera ndangariro yenguva dzose mune yakagovaniswa DDR system (kureva, HPS DDR) uye ichigadzirisa ndangariro inogara mushure mekuita kernel, iyo data mundangariro inogona kuve yechinyakare. Nyaya iyi inomuka nekuti iyo FPGA musimboti haigone kuvhurika paCPU-to-HPS DDR kutengeserana.
Kudzivirira kunotevera kernel kuuraya kubva pakuwana data rekare, ita imwe yeanotevera workarounds:
• Usashandura chiyeuchidzo chenguva dzose mushure mekutanga kwayo.
• Kana uchida akawanda __maseti edata akawanda, gadzira mabhafa endangariro akawanda.
• Kana iripo, isa chiyeuchidzo chinogara chiripo muFPGA DDR pabhodhi rako rekumhanyisa.
Iyo SDK yekushandisa paARM inongotsigira chirongwa uye kuongorora utility mirairo.
Iyo flash, yekuisa uye yekubvisa utility mirairo haishande kune Cyclone V SoC Development Kit nekuda kwezvikonzero zvinotevera:
a. Iyo yekuisa yekushandisa inofanirwa kuunganidza aclsoc_drv Linux kernel driver uye kuigonesa paSoC FPGA. Muchina wekuvandudza unofanirwa kuita kuunganidza; zvisinei, inotova neLinux kernel masosi eiyo SoC FPGA. Iyo Linux kernel masosi emuchina wekuvandudza akasiyana neayo eSoC FPGA. Nzvimbo yeLinux kernel masosi yeSoC FPGA ingangove isingazivikanwe kune SDK mushandisi. Saizvozvo, iyo uninstall utility haiwanikwewo kune Cyclone V SoC Development Kit.
Zvakare, kuendesa aclsoc_drv kuSoC bhodhi kunonetsa nekuti kugovera kwakasarudzika kweCyclone V SoC Development Kit haina Linux kernel inosanganisira. files kana iyo GNU Compiler Collection (GCC) compiler.
b. Iyo flash utility inoda kuisa .rbf file yeOpenCL dhizaini pane iyo FAT32 chikamu cheiyo micro SD flash kadhi. Parizvino, chikamu ichi hachina kuiswa kana mushandisi weSDK achisimudza bhodhi. Naizvozvo, nzira yakanakisa yekuvandudza chikamu ndeye kushandisa flash kadhi kuverenga uye muchina wekuvandudza.

Kana uchichinja pakati peIntel FPGA SDK yeOpenCL Offline Compiler inogoneka files (.aocx) inoenderana neakasiyana mabhodhi akasiyana (kureva, c5soc uye c5soc_sharedonly), unofanira kushandisa chirongwa cheSDK kurongedza .aocx file kune iyo itsva board musiyano kekutanga. Kana iwe ukangomhanyisa iyo host application uchishandisa nyowani bhodhi musiyano asi iyo FPGA ine mufananidzo kubva kune imwe bhodhi musiyano, kukanganisa kunouraya kunogona kuitika.
The .qxp file haisanganisire iyo interface yekugovera migove nekuti iyo Quartus Prime software inogara ichiita zvinodiwa nenguva zvechikamu ichi.
Paunosimudza bhodhi, kero yayo yekuwana midhiya (MAC) inoiswa kune nhamba isina kurongeka. Kana mutemo wako weLAN usingatenderi maitiro aya, isa kero yeMAC nekuita mabasa anotevera:
a. Munguva yeU-Boot simba-kumusoro, tinya chero kiyi kuti uise iyo U-Boot yekuraira kukurumidza.
b. Type setenv ethaddr 00:07:ed:00:00:03 pakuraira kwekuraira.
Unogona kusarudza chero kero yeMAC.
c. Nyora iyo saveenv command.
d. Reboot bhodhi.

1.8 Document Revision History
Tafura 1.
Gwaro Revision Nhoroondo yeIntel FPGA SDK yeOpenCL Cyclone V SoC
Development Kit Reference Platform Porting Guide

Date	Version	Kuchinja
Chivabvu-17	2017.05.08	•Maintenance release.
Gumiguru 2016	2016.10.31	• Yakadzorerwa Altera SDK yeOpenCL kuenda kuIntel FPGA SDK yeOpenCL. • Yakadzorerwa Altera Offline Compiler kuita Intel FPGA SDK yeOpenCL Offline Compiler.
Chivabvu-16	2016.05.02	• Yakagadziridzwa mirairo yekuvaka nekugadzirisa SD flash kadhi mufananidzo. •Mirairo yakagadziridzwa pakudzorerazve Linux kernel uye OpenCL Linux kernel driver.
Mbudzi-15	2015.11.02	•Maintenance release, nekuchinja kweQuartus II kuita Quartus Prime.
Chivabvu-15	15.0.0	•MuFPGA Reconfiguration, yakabviswa rairo yekurongazve iyo FPGA musimboti pamwe a. rbf mufananidzo nekukokera katsi filezita>. rbf > /dev/ fpga0 raira nekuti iyi nzira haina kukurudzirwa.
Zvita-14	14.1.0	•Yakapazve gwaro racho seAltera Cyclone V SoC Development Kit Reference Platform Porting Guide. • Yakagadziridza reprogram utility kune aocl chirongwafilezita>.aocx utility command. • Yakagadziridzwa yekuongorora kushandiswa kune aocl yekuongorora uye aocl yekuongorora utility command. • Yakagadziridza maitiro muPorting the Reference Platform kune Yako SoC Board chikamu kuti isanganise mirairo yekufambisa nekugadzirisa c5soc board partition kugadzira nguva-yakachena partition yekuvharwa nguva yakavimbiswa kuyerera. •Yakaisa musoro wenyaya Kuvandudza Ported Reference Platform kuratidza maitirwo emabasa anotevera: 1.Kusasanganisira iyo yakaoma processor system (HPS) block mubhodhi partition 2.Kuvandudza mufananidzo we SD flash card • Yakagadziridza chikamu cheKuvaka SD Flash Card Image. Inokurudzirwa uchishandisa vhezheni 14.0 yeGolden System Reference Dhizaini (GSRD) sepanotangira pane mufananidzo unowanikwa neSoC Embedded Design Suite (EDS). • Yakagadziridza Recompiling iyo Linux Kernel uye OpenCL Linux Kernel Driver chikamu: 1.Added instruction yekuisa CROSS COMPILE variable. 2.Changed murairo waunomhanya kuti uone kuti CMA inogoneswa zvinobudirira.
Chikunguru-14	14.0.0	•Kusunungurwa kwekutanga.