intel FPGA SDK maka ntuziaka onye ọrụ OpenCL

FPGA SDK maka OpenCL
Ntuziaka onye ọrụ

UG-OCL009
2017.05.08
Emelitere ikpeazụ maka Intel® Quartus® Prime Design Suite: 17.0

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1 Intel® FPGA SDK maka OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Platform Porting Guide

2 Akwụkwọ / akụrụngwa

2.1 Ntụaka

3 Ozi ndị metụtara

Intel® FPGA SDK maka OpenCL™ Intel® Cyclone®V SoC Development Kit Reference Platform Porting Guide

V SoC Development Kit Reference Platform Guide na-akọwa ngwaike na ngwanrọ nke Intel Cyclone V SoC Development Kit Reference Platform (c5soc) maka iji ya na Intel Software Development Kit (SDK) maka OpenCL Intel ® FPGA SDK maka OpenCL ™ Intel Cyclone ® . Tupu ịmalite, Intel na-akwadosi ike ka ị mara onwe gị nke ọma na ọdịnaya nke akwụkwọ ndị a:

Intel FPGA SDK maka OpenCLIntel Cyclone V SoC Ntuziaka mmalite

Intel FPGA SDK maka ntuziaka onye ọrụ ngwa ngwa Platform omenala OpenCL
Akwụkwọ ntuziaka ngwaọrụ Cyclone V, Mpịakọta 3: Akwụkwọ ntuziaka nka nka na ụzụ Sistemu Hard Processor Na mgbakwunye, rụtụ aka na Cyclone V SoC Development Kit na ibe SoC Embedded Design Suite nke Altera websaịtị maka ozi ndị ọzọ. 1

Nlebara anya: Intel na-eche na ị nwere nghọta miri emi nke Intel FPGA SDK maka ntuziaka onye ọrụ OpenCL Custom Platform Toolkit. Ntuziaka Ntugharị Ntụaka Platform Cyclone V SoC anaghị akọwa ojiji nke SDK's Custom Platform Toolkit iji mejuputa Platform omenala maka ngwa mmepe Cyclone V SoC. Ọ na-akọwa naanị ọdịiche dị n'etiti nkwado SDK na Cyclone V SoC Development Kit yana ọnyà Intel FPGA SDK maka OpenCL Custom Platform.

Njikọ ndị emetụtara

Intel FPGA SDK maka OpenCL Cyclone V SoC Ntuziaka mmalite
Intel FPGA SDK maka ntuziaka onye ọrụ ngwa ngwa Platform omenala OpenCL

Akwụkwọ ntuziaka ngwaọrụ Cyclone V, Mpịakọta 3: Akwụkwọ ntuziaka Nka na ụzụ Sistemu Hard Processor
Cyclone V SoC Development Kit na ibe SoC Embedded Design Suite na Altera websaịtị

OpenCL na akara OpenCL bụ ụghalaahịa Apple Inc. ejiri ikike nke Khronos Group™ na-eji.
Intel FPGA SDK maka OpenCL gbadoro ụkwụ na nkọwapụta Khronos ebipụtara, wee gafere Usoro Nleba anya nke Khronos. Enwere ike ịhụ ọkwa nkwenye ugbu a na www.khronos.org/conformance.

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus na Stratix okwu na akara bụ ụghalaahịa nke ụlọ ọrụ Intel ma ọ bụ ndị enyemaka ya na US na/ma ọ bụ obodo ndị ọzọ. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
* Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

1.1.1 Cyclone V SoC Development Kit Reference Platform Board Variants
Intel FPGA SDK maka OpenCL Cyclone V SoC Development Kit Reference Platform gụnyere ụdị bọọdụ abụọ.

c5soc osisi
Bọdụ ndabara a na-enye ohere ịnweta ụlọ akụ ebe nchekwa DDR abụọ. HPS DDR na-enweta ma FPGA na CPU. FPGA DDR bụ naanị FPGA na-enweta ya.
osisi c5soc_sharedonly
Ụdị bọọdụ a nwere naanị njikọta HPS DDR. FPGA DDR adịghị enweta ya. Ụdị bọọdụ a na-arụ ọrụ nke ọma karịa n'ihi na ngwaike dị obere dị mkpa iji kwado otu ụlọ akụ ebe nchekwa DDR. Bọdụ c5soc_sharedonly bụkwa ezigbo ikpo okwu prototyping maka bọọdụ mmepụta ikpeazụ nwere otu ebe nchekwa DDR.
Iji lekwasịrị anya n'ụdị bọọdụ a mgbe ị na-achịkọta kernel OpenCL gị, tinye nhọrọ -board c5soc_sharedonly na iwu aoc gị.
Maka ozi ndị ọzọ na -board nhọrọ nke iwu aoc, rụtụ aka na Intel FPGA SDK maka OpenCL Programming Guide.

Njikọ ndị emetụtara
Na-achịkọta kernel maka bọọdụ FPGA akọwapụtara (- bọọdụ )
1.1.2 Ọdịnaya nke Cyclone V SoC Development Kit Reference Platform
Ihe nrụtụ aka nke Cyclone V SoC Development Kit nwere ihe ndị a files na akwụkwọ ndekọ aha:

File ma ọ bụ ndekọ	Nkọwa
bọọdụ_env.xml	Asụsụ eXtensible Markup (XML) file nke na-akọwa c5soc na Intel FPGA SDK maka OpenCL.
linux_sd_card_image.tgz	Onyonyo kaadị flash SD emetụtara file nke nwere ihe niile onye ọrụ SDK kwesịrị iji Cyclone V SoC Development Kit na SDK.
ogwe aka 32	Akwụkwọ ndekọ nke nwere ihe ndị a:

1.1.3 Akụkụ dị mkpa nke ngwa mmepe Cyclone V SoC

Ndepụta ndị a na-akọwapụta ihe akụrụngwa mmepe Cyclone V SoC yana atụmatụ dabara na Intel FPGA SDK maka OpenCL:

Dual-core ARM Cortex-A9 CPU na-agba Linux 32-bit.

Ụgbọ ala eXtensible Interface (AXI) dị elu n'etiti HPS na akwa isi FPGA.
Ihe njikwa ebe nchekwa DDR abụọ siri ike, nke ọ bụla na-ejikọ na 1 gigabyte (GB) DDR3 SDRAM.
- Otu onye njikwa DDR nwere ike ịnweta naanị isi FPGA (ya bụ, FPGA DDR).
- Onye njikwa DDR ọzọ nwere ike ịnweta ma HPS na FPGA (ya bụ, HPS DDR). Ihe njikwa ekekọrịtara a na-enye ohere ikesa ebe nchekwa efu n'etiti CPU na isi FPGA.

CPU nwere ike ịhazigharị akwa isi FPGA.

1.1.3.1 Cyclone V SoC Development Kit Reference Platform Atụmatụ Ebumnuche na Mkpebi Intel na-adabere na mmejuputa nke Cyclone V SoC Development Kit Reference Platform na ọtụtụ ebumnuche imewe na mkpebi. Intel na-atụ aro ka ị tụlee ebumnuche na mkpebi ndị a mgbe ị na-ebufe Platform Reference a na bọọdụ SoC FPGA gị.
N'okpuru bụ ebumnuche imewe c5soc:

Nye bandwidth kacha elu enwere ike n'etiti kernels na FPGA na sistemụ ebe nchekwa DDR.
Gbaa mbọ hụ na mgbakọ na mwepụ na FPGA (ya bụ, kernel OpenCL) anaghị egbochi ọrụ CPU ndị ọzọ nwere ike ịgụnye mpaghara ọrụ.

Hapụ akụrụngwa FPGA dị ka o kwere mee maka mgbakọ kernel kama ihe mejupụtara interface.

N'okpuru bụ mkpebi nhazi ọkwa dị elu bụ nsonaazụ ozugbo nke ebumnuche imepụta Intel:

Platform Reference na-eji naanị ndị na-ahụ maka ebe nchekwa DDR siri ike nwere nhazi nwere ike ime (256 bits).
FPGA na-ekwurịta okwu na onye na-ahụ maka ebe nchekwa HPS DDR ozugbo, na-etinyeghị ụgbọ ala AXI na mgba ọkụ L3 n'ime HPS. Nzikọrịta ozi ozugbo na-enye bandwidth kachasị mma na DDR, ma na-eme ka mgbakọ FPGA ghara itinye aka na nkwukọrịta n'etiti CPU na mpụta ya.
Ịnweta ebe nchekwa ozugbo (SG-DMA) abụghị akụkụ nke mgbanaka interface FPGA. Kama ibufe nnukwu data n'etiti sistemụ ebe nchekwa DDR, chekwaa data na HPS DDR nkekọrịta. Nweta ozugbo na ebe nchekwa CPU site na FPGA na-arụ ọrụ nke ọma karịa DMA. Ọ na-echekwa akụrụngwa ngwaike (ya bụ, mpaghara FPGA) ma mee ka onye ọkwọ ụgbọ ala Linux dị mfe.
Ịdọ aka ná ntị: Nbufe ebe nchekwa n'etiti sistemu HPS DDR nkekọrịta yana sistemụ DDR nke a na-enweta naanị na FPGA na-adị nwayọ. Ọ bụrụ na ị họrọ
nyefee ebe nchekwa n'ụzọ dị otu a, jiri ya maka obere data naanị.
Onye ọbịa na ngwaọrụ ahụ na-enyefe data na-abụghị DMA n'etiti ibe ha site na akwa HPS-to-FPGA (H2F), na-eji naanị otu ọdụ ụgbọ mmiri 32-bit. Ihe kpatara ya bụ, na-enweghị DMA, Linux kernel nwere ike ịnye naanị otu 32-bit gụọ ma ọ bụ dee arịrịọ, yabụ na ọ dịghị mkpa inwe njikọ sara mbara.
Onye ọbịa na-eziga akara njikwa na ngwaọrụ site na akwa H2F (LH2F) dị fechaa.
N'ihi na akara njikwa sitere na onye ọbịa na ngwaọrụ ahụ bụ akara bandwit dị ala, akwa LH2F dị mma maka ọrụ ahụ.

1.2 Ibufe Platform ntụaka na bọọdụ SoC FPGA gị
Iji bubata Cyclone V SoC Development Kit Reference Platform na bọọdụ SoC FPGA gị, rụọ ọrụ ndị a:

Họrọ otu ebe nchekwa DDR ma ọ bụ ụdị ncheta DDR abụọ nke c5soc Reference Platform dị ka mmalite nke imewe gị.
Melite ọnọdụ ntụtụ dị na ALTERAOCLSDKROOT/board/c5soc/ /top.qsf file, ebe ALTERAOCLSDKROOT bụ ụzọ na ọnọdụ nke Intel FPGA SDK maka OpenCL nwụnye, na bụ aha ndekọ aha nke ụdị bọọdụ ahụ. Akwụkwọ ndekọ c5soc_sharedonly bụ maka ụdị bọọdụ nwere otu sistemụ ebe nchekwa DDR. Akwụkwọ ndekọ c5soc bụ maka ụdị bọọdụ nwere sistemụ ebe nchekwa DDR abụọ.
Melite ntọala DDR maka ngọngọ HPS na/ma ọ bụ FPGA SDRAM na ALTERAOCLSDKROOT/board/c5soc/ /system.qsys file.
4. Niile Intel FPGA SDK maka OpenCL chọrọ osisi aghụghọ ga-enweta n'ezie oge mmechi. Dị ka ndị dị otú ahụ, ntinye nke imewe ga-adị ọcha oge. Iji bufee akụkụ bọọdụ c5soc (acl_iface_partition.qxp) na bọọdụ SoC FPGA gị, rụọ ọrụ ndị a:
Maka nkọwa zuru ezu maka imeghari na ichekwa nkebi bọọdụ, rụtụ aka na Quartus
Mmụba Mmụba Prime maka isi akwụkwọ nhazi nke Quartus Prime Standard Edition.
a. Wepu acl_iface_partition.qxp na ndekọ ALTERAOCLSDKROOT/board/c5soc/c5soc.
b. Kwado mpaghara acl_iface_region LogicLock™ site na ịgbanwe iwu Tcl set_global_assignment -aha LL_ENABLED OFF -section_id acl_iface_region ka ịtọ_global_assignment - aha LL_ENABLED ON -section_id acl_iface_region
c. Chịkọta kernel OpenCL maka bọọdụ gị.
d. Ọ bụrụ na ọ dị mkpa, dozie nha na ọnọdụ mpaghara LogicLock.
e. Mgbe afọ juru gị na ntinye nke imewe gị bụ oge dị ọcha, bupụ akụkụ ahụ dị ka acl_iface_partition.qxp Quartus Prime Exported Partition. File.
Dị ka akọwara n'ime ngalaba na-eme ka oge eruo nke AIntel FPGA SDK maka OpenCL Custom Platform Toolkit Guide User, site na ibubata .qxp a. file n'ime imewe nke elu-larịị, ị na-emezu ihe achọrọ nke ịnye nhazi bọọdụ nwere oge mmechi na-ekwe nkwa.
Maka ihe ndị nwere ike imetụta ogo nsonaazụ (QoR) nke ngalaba mbupu gị, rụtụ aka na Ntụle Nleba Ọdịmma Nsonaazụ zuru oke maka ngalaba nkebi nke bọọdụ ebupụ na Intel FPGA SDK maka ntuziaka onye ọrụ OpenCL Custom Platform Toolkit.
f. Gbanyụọ mpaghara acl_iface_region LogicLock site na ịtụgharị iwu ahụ na Nzọụkwụ 2 azụ ka set_global_assignment -name LL_ENABLED OFF section_id acl_iface_region.
Ọ bụrụ na bọọdụ SoC FPGA gị na-eji ntụtụ dị iche iche na mpụta nke ngọngọ HPS, megharịa preloader na isi iyi osisi ngwaọrụ (DTS) file. Ọ bụrụ n’ịgbanwe ntọala ebe nchekwa HPS DDR, megharịa ihe ebubu ụzọ.
Mepụta onyonyo kaadị SD flash.
Mepụta Platform Omenala gị, nke gụnyere onyonyo kaadị flash SD.
Tụlee ịmepụta ụdị oge ịgba ọsọ nke Platform omenala gị maka iji Intel FPGA Runtime Environment (RTE) maka OpenCL. Ụdị RTE nke Platform omenala gị anaghị agụnye akwụkwọ ndekọ aha ngwaike yana onyonyo kaadị SD. Platform omenala a na-ebuba na sistemụ SoC FPGA iji kwe ka ngwa ndị ọbịa na-agba ọsọ. N'ụzọ dị iche, ụdị SDK nke Platform Custom dị mkpa maka SDK iji chịkọta kernel OpenCL.
Ndụmọdụ: Ị nwere ike iji ụdị SDK nke Platform omenala gị maka RTE. Ka ịchekwaa
oghere, wepụ ihe oyiyi kaadị SD flash na ụdị RTE nke Platform omenala gị.
Nwalee Platform omenala gị.
Rụtụ aka na Nnwale Nleba Nhazi Ngwaike nke Intel FPGA SDK maka ntuziaka onye ọrụ OpenCL Custom Platform Toolkit maka ozi ndị ọzọ.

Njikọ ndị emetụtara

Na-anwale nhazi ngwaike
Nchịkọta Quartus Prime Mgbakwunye maka nhazi nhazi yana nhazi otu dabere

Ịmepụta usoro oge a na-ekwe nkwa
Nlebanya nlebanya n'ozuzu ogo nke nsonaazụ maka nkebi bọọdụ ebupụ

1.2.1 Na-emelite Platform ntụaka Ported
N'ụdị dị ugbu a nke Cyclone V SoC Development Kit Reference Platform, ngọngọ HPS dị n'ime nkebi nke na-akọwa mgbagha niile na-abụghị kernel. Agbanyeghị, ịnweghị ike mbupụ HPS dịka akụkụ nke .qxp file. Ka imelite Platform omenala dị adị nke ị meziri site na ụdị c5soc gara aga, mejuputa usoro nchekwa QXP, melite onyonyo kaadị SD iji nweta gburugburu oge ịgba ọsọ kachasị ọhụrụ, wee melite board_spec.xml. file iji mee ka akpaaka.
Altera® SDK maka ụdị OpenCL 14.1 na gafere nyocha nke board_spec.xml file maka ozi bọọdụ, ma mejuputa mmelite akpaka. N'ihi na ị gbanwee
imewe site na mmejuputa atumatu QXP nchekwa eruba, ị ga-emelite board_spec.xml file na usoro ya na ụdị dị ugbu a. Na-emelite file na-enye SDK ohere ịmata ọdịiche dị n'etiti Platform Omenala echedoroghị ya na Platform Custom dabere na QXP ugbu a. Rụtụ aka na Automigration Platform Omenala maka ndakọrịta n'ihu na Intel FPGA SDK maka ntuziaka onye ọrụ OpenCL Custom Platform maka ozi ndị ọzọ.

Iji mejuputa usoro nchekwa QXP n'ime ngwaike Cyclone V SoC FPGA nke ewepụtara site na ụdị c5soc gara aga, mee usoro ndị a iji mepụta nkebi iji wepụ HPS na .qxp. file:
a. Tupu ịmepụta nkebi gburugburu mgbagha na-abụghị kernel, mepụta nkebi gburugburu HPS na .qsf Quartus Prime Settings File.
Maka exampLe:
# Jiri aka kee ihe atụ nke na-egosipụta ọrụ nhazi nke HPS raara onwe ya nye I/O set_intance_name PARTITION_HIERARCHY borde_18261 - na “sistemu: the_system|system_acl_iface:acl_iface|system_acl_iface_hps_0:hps_0|system_acl_iface_h:hpsi system_acl_iface_hps_0_hps_io_border: ókè-ala" -section_id "system_acl_iface_hps_0_hps_io_border: ókè"
# Tọọ akụkụ ka ọ bụrụ ụdị HPS_PARTITION nke Quartus ndị ọzọ ga-ahazi ya nke ọma.
set_global_assignment - aha PARTITION_TYPE HPS_PARTITION -section_id "system_acl_iface_hps_0_hps_io_border: ókè"
quartus_cdb n'elu -c n'elu
-incremental_compilation_export=acl_iface_partition.qxp
-incremental_compilation_export_partition_name=acl_iface_partition
-incremental_compilation_export_post_synth=na
-incremental_compilation_export_post_fit=na
-incremental_compilation_export_routing=na
-incremental_compilation_export_flatten = gbanyụọ
Mgbe i wepụrụ HPS na nkebi, ị nwere ike ibubata .qxp file ma chịkọta atụmatụ gị.
Jiri ụdị Intel FPGA RTE dị ugbu a kwalite onyonyo kaadị SD maka OpenCL site na ịrụ ọrụ ndị a:
a. Ugwu ahụ file table nkenye (fat32) ma gbasaa file Sistemu (ext3) nkebi na onyonyo dị ugbu a dị ka ngwaọrụ akaghị azụ. Maka ntụzịaka zuru ezu, rụtụ aka na Nzọụkwụ 2 na Iwuli Foto Kaadị Flash SD.
b. Na /home/root/opencl_arm32_rte ndekọ, wepụ ihe files sitere na ụdị RTE gara aga.
c. Budata ma budata ụdị RTE dị ugbu a n'ime ndekọ aha /home/root/opencl_arm32_rte.
d. N'ime / ọkwọ ụgbọ ala/version.h file nke Platform omenala gị, kwalite ọrụ ACL_DRIVER_VERSION na . (maka example, 16.1.x, ebe 16.1 bụ SDK verison, na x bụ ụdị ọkwọ ụgbọala nke ị debere).
e. wughachi onye ọkwọ ụgbọ ala.
f. Hichapụ folda (s) ngwaike nke Platform omenala gị. Detuo Platform Custom, yana onye ọkwọ ụgbọ ala emelitere, na /home/root/opencl_arm_rte/akwụkwọ ndekọ aha.
g. Detuo Altera.icd file site na / home/root/opencl_arm32_rte ndekọ ma tinye ya na /etc/OpenCL/ndị na-ere ahịa ndekọ.
h. Bupụ ma nwalee onyonyo ọhụrụ ahụ. Maka ntụzịaka zuru oke, rụtụ aka na nzọụkwụ 8 ruo 11 na iwulite onyonyo kaadị Flash SD.

Njikọ ndị emetụtara

Ịmepụta onyonyo kaadị Flash SD na ibe 14
Ị nwekwara nhọrọ ịmepụta foto kaadị SD flash ọhụrụ.
Omenala Platform Automigration maka ndakọrịta aga n'ihu

1.3 Nkwado ngwanrọ maka ebe nchekwa ekekọrịtara
Ebe nchekwa anụ ahụ ekekọrịtara n'etiti FPGA na CPU bụ ebe nchekwa kachasị amasị maka kernel OpenCL na-agba ọsọ na SoC FPGA. N'ihi na FPGA na-enweta ebe nchekwa anụ ahụ nkekọrịta, n'adịghị ka ebe nchekwa mebere nkekọrịta, ọ nweghị ohere na tebụl ibe CPU nke na-esepụta adreesị nke onye ọrụ na adreesị ibe anụ ahụ.
N'ihe gbasara ngwaike, OpenCL kernels na-enweta ebe nchekwa anụ ahụ nkekọrịta site na njikọ kpọmkwem na njikwa ebe nchekwa nchekwa HPS DDR. N'ihe gbasara sọftụwia, nkwado maka ebe nchekwa anụ ahụ nkekọrịta gụnyere ihe ndị a:

Mmejuputa ngwanrọ a na-ahụkarị maka ikenye ebe nchekwa na CPU (maka example, ọrụ malloc() enweghị ike ịnye mpaghara ebe nchekwa nke FPGA nwere ike iji.
Ebe nchekwa nke ọrụ malloc() na-ekenye na-aga n'ihu na oghere adresị ebe nchekwa, mana ibe anụ ahụ ọ bụla enweghị ike ịgafe n'anụ ahụ. Dị ka ndị dị otú a, onye ọbịa ga-enwe ike ịkenye mpaghara ebe nchekwa na-aga n'ihu. Agbanyeghị, ikike a adịghị na ngwa-ohere onye ọrụ na Linux. Ya mere, onye na-anya kernel Linux ga-arụ ọrụ ahụ.
Onye ọkwọ ụgbọ ala Linux kernel OpenCL SoC FPGA gụnyere ọrụ mmap() iji kenye ebe nchekwa anụ ahụ na-ekekọrịta wee mapụta ya na oghere onye ọrụ. Ọrụ mmap() na-eji ọkọlọtọ Linux kernel call dma_alloc_coherent() iji rịọ mpaghara ebe nchekwa na-aga n'ihu maka ịkekọrịta na ngwaọrụ.
Na Linux kernel ndabara, dma_alloc_coherent() anaghị ekenye ebe nchekwa na-aga n'ihu karịa 0.5 megabyte (MB) n'ogo. Iji kwe ka dma_alloc_coherent() kenye nnukwu ebe nchekwa na-aga n'ihu n'anụ ahụ, mee ka njirimara nchekwa ihe nchekwa (CMA) nke Linux kernel wee chịkọta kernel Linux.
Maka Cyclone V SoC Development Kit Reference Platform, CMA na-ejikwa 512 MB n'ime 1 GB nke ebe nchekwa anụ ahụ. Ị nwere ike ịbawanye ma ọ bụ wedata uru a, dabere na ọnụọgụ ebe nchekwa nke ngwa ahụ chọrọ. Oku dma_alloc_coherent() nwere ike ọ gaghị enwe ike ịnye 512 MB zuru oke nke ebe nchekwa na-aga n'ihu; Otú ọ dị, ọ nwere ike nweta ihe dịka 450 MB nke ebe nchekwa mgbe niile.

CPU nwere ike ichekwa ebe nchekwa nke dma_alloc_coherent() kpọrọ ekenye. Karịsịa, dee ọrụ sitere na ngwa nnabata anaghị ahụ kernels OpenCL. Ọrụ mmap() dị na OpenCL SoC FPGA Linux kernel ọkwọ ụgbọ ala nwekwara oku na ọrụ pgprot_noncached() ma ọ bụ remap_pf_range() iji gbanyụọ caching maka mpaghara ebe nchekwa a n'ụzọ doro anya.
Mgbe ọrụ dma_alloc_coherent () ekenyela ebe nchekwa na-aga n'ihu nke anụ ahụ, ọrụ mmap () na-eweghachi adreesị mebere na mmalite nke oke, nke bụ ogologo adreesị nke ebe nchekwa ị na-ekenye. Ngwa nnabata chọrọ adreesị mebere nke a iji nweta ebe nchekwa. N'aka nke ọzọ, kernel OpenCL chọrọ adreesị anụ ahụ. Onye na-anya kernel Linux na-edobe maapụ adreesị mebere-na-anụ ahụ. Ị nwere ike ịdepụta adreesị anụ ahụ mmap() na-alaghachi na adreesị anụ ahụ n'ezie site na ịgbakwunye ajụjụ na ọkwọ ụgbọala.
Oku aocl_mmd_shared_mem_alloc() MMD ngwa mmemme interface (API) gụnyere ajụjụ ndị a:
a. Ọrụ mmap() nke na-ekenye ebe nchekwa ma weghachi adreesị mebere.
b. Ajụjụ agbakwunyere nke na-esetịpụ adreesị ozi ọma eweghachiri na adreesị anụ ahụ.
Oku aocl_mmd_shared_mem_alloc() MMD API wee weghachi adreesị abụọ
-adreesị eweghachiri n'ezie bụ adreesị mebere, na adreesị anụ ahụ na-aga na ngwaọrụ_ptr_out.
Mara: Onye ọkwọ ụgbọ ala nwere ike ịdepụta naanị adreesị mebere nke ọrụ mmap() na-alaghachi na adreesị anụ ahụ. Ọ bụrụ na ị rịọ maka adreesị anụ ahụ nke pointer mebere ọ bụla ọzọ, onye ọkwọ ụgbọ ala ahụ ga-eweghachi uru efu.

Ịdọ aka ná ntị: The Intel FPGA SDK maka OpenCL ọbá akwụkwọ ọbá akwụkwọ na-eche na ebe nchekwa nkekọrịta bụ ebe nchekwa mbụ edepụtara na board_spec.xml file. N'ikwu ya n'ụzọ ọzọ, adreesị anụ ahụ nke onye ọkwọ ụgbọ ala Linux na-enweta na-aghọ adreesị Avalon® nke kernel OpenCL na-agafe na HPS SDRAM.
N'ihe gbasara ọba akwụkwọ oge, jiri oku clCreateBuffer() kesaa ebe nchekwa ekekọrịtara dị ka ihe nchekwa ngwaọrụ n'ụzọ ndị a:

Maka ụdị bọọdụ abụọ-DDR nwere ebe nchekwa ekekọrịtara na nke enweghị nkekọrịta, clCreateBuffer() na-ekenye ebe nchekwa nkekọrịta ma ọ bụrụ na ị kọwapụta ọkọlọtọ CL_MEM_USE_HOST_PTR. Iji ọkọlọtọ ndị ọzọ na-eme ka createBuffer() kenye ihe nchekwa na ebe nchekwa enweghị ikekọrịta.
Maka ụdị bọọdụ otu-DDR nwere naanị ebe nchekwa ekekọrịtara, clCreateBuffer() na-ekenye ebe nchekwa ekekọrịtara n'agbanyeghị ọkọlọtọ ị ezipụtara.
Ugbu a, nkwado Linux 32-bit na ARM CPU na-achịkwa oke nkwado ebe nchekwa na ọba akwụkwọ oge SDK. N'ikwu ya n'ụzọ ọzọ, ọba akwụkwọ oge agbakọtara na gburugburu ndị ọzọ (maka example, x86_64 Linux ma ọ bụ 64-bit Windows) anaghị akwado ebe nchekwa nkekọrịta.
C5soc emejuputaghị ebe nchekwa dị iche iche iji mata ọdịiche dị n'etiti ebe nchekwa na-ekekọrịtaghị na nke na-abụghị nke n'ihi ihe ndị a:
1. Akụkọ ihe mere eme-Heterogeneous ebe nchekwa nkwado adịghị mgbe ekekọrịta nkwado ebe nchekwa na mbụ kere.
2. Uniform interface-N'ihi na OpenCL bụ ọkọlọtọ mepere emepe, Intel na-edobe nkwekọ n'etiti ndị na-ere ahịa ikpo okwu dị iche iche. Ya mere, a na-eji otu interface dị ka ụlọ ndị na-ere ụlọ ndị ọzọ na-ekesa na iji ebe nchekwa nkekọrịta.

1.4 FPGA nhazigharị
Maka SoC FPGA, CPU nwere ike ịhazigharị akwa isi FPGA na-akwụsịghị ọrụ CPU. Ihe mgbochi ngwaike njikwa FPGA nke na-adakwasị HPS na isi FPGA na-eme nhazigharị ahụ. Linux kernel gụnyere ọkwọ ụgbọ ala nke na-enyere aka ịnweta njikwa FPGA dị mfe.

Iji view Ọnọdụ nke isi FPGA, kpọọ iwu cat /sys/class/fpga/fpga0/ status.
Intel FPGA SDK maka ngwa mmemme OpenCL dị na Cyclone V SoC Development Kit Reference Platform na-eji interface a iji hazie FPGA. Mgbe ị na-emegharị isi FPGA na CPU na-agba ọsọ, ngwa mmemme na-arụ ọrụ ndị a niile:
1. Tupu ịmegharịgharị, gbanyụọ àkwà mmiri nkwukọrịta niile n'etiti FPGA na HPS, ma àkwà mmiri H2F na LH2F.
Megharia àkwà mmiri ndị a ka emechara nhazigharị.
Ntị: Usoro OpenCL anaghị eji akwa mmiri FPGA-to-HPS (F2H). Rụtụ aka na akụkụ Interfaces HPS-FPGA dị na Akwụkwọ Ngwaọrụ Cyclone V, Mpịakọta 3: Akwụkwọ ntuziaka Nka na ụzụ Sistemu Hard Processor maka ozi ndị ọzọ.
2. Gbaa mbọ hụ na njikọ dị n'etiti FPGA na onye na-ahụ maka HPS DDR nwere nkwarụ n'oge mmegharị.
3. Gbaa mbọ hụ na nkwụsị FPGA na FPGA nwere nkwarụ mgbe a na-emegharịgharị ya.
Ọzọkwa, gwa onye ọkwọ ụgbọ ala ka ọ jụ nkwụsị ọ bụla sitere na FPGA n'oge nhazigharị.

Gaa na koodu isi mmalite nke mmemme mmemme maka nkọwa gbasara mmejuputa ya n'ezie.

Ịdọ aka ná ntị: Agbanwela nhazi nke onye na-ahụ maka HPS DDR mgbe CPU na-agba ọsọ.
Ime nke a nwere ike ibute njehie sistemụ na-egbu egbu n'ihi na ị nwere ike ịgbanwe nhazi njikwa DDR mgbe enwere azụmahịa ebe nchekwa pụtara ìhè sitere na CPU. Nke a pụtara na mgbe CPU na-agba ọsọ, ị nwere ike ị gaghị emegharị FPGA isi na onyonyo na-eji HPS DDR na nhazi dị iche.
Cheta na usoro OpenCL, yana ihe nrụtụ aka ọla edo dị na Intel SoC FPGA Embedded Design Suite (EDS), na-edobe HPS DDR ka ọ bụrụ otu ọnọdụ 256-bit.
Akụkụ sistemụ CPU dị ka onye amụma ngalaba ma ọ bụ prefetcher tebụl ibe nwere ike inye iwu DDR ọbụlagodi mgbe ọ dị ka ọ nweghị ihe na-agba na CPU.
Ya mere, oge buut bụ naanị oge nchekwa iji tọọ nhazi njikwa HPS DDR.
Nke a pụtakwara na U-boot ga-enwerịrị ọnụọgụ abụọ file (.rbf) onyonyo iji tinye n'ime ebe nchekwa. Ma ọ bụghị ya, ị nwere ike na-enyere HPS DDR aka na ọdụ ụgbọ mmiri ejighi ya na FPGA wee nwee ike ịgbanwe nhazi ọdụ ụgbọ mmiri ma emesịa. Maka nke a, onye ọkwọ ụgbọala kernel OpenCL Linux anaghị agụnye mgbagha dị mkpa iji tọọ nhazi njikwa HPS DDR.
Ihe ngwugwu SW3 dual in-line (DIP) na-agbanye na Cylone V SoC Development Kit na-achịkwa ụdị a na-atụ anya nke onyinyo .rbf (ya bụ, ma ọ bụ file na-akpakọ na/ma ọ bụ ezoro ezo). C5soc, na ihe nrụtụ aka nke ngwaike ọla edo dị na SoC EDS, gụnyere onyonyo .rbf ekpokọtara mana enweghị ezoro ezo. Ntọala mgba ọkụ SW3 DIP akọwara na Intel FPGA SDK maka OpenCL Cyclone V SoC mmalite mmalite dabara nhazi onyonyo .rbf a.

Njikọ ndị emetụtara

HPS-FPGA Interface
Ịhazi SW3 Switches

1.4.1 FPGA nkọwa nhazi usoro
Nkwado maka Cyclone V SoC Development Kit Reference Platform dabere na Stratix® V Reference Platform (s5_ref), dị na Intel FPGA SDK maka OpenCL.
Nhazi nke sistemu c5soc Qsys na onye ọkwọ ụgbọ ala kernel yiri nke ahụ na s5_ref.
Ihe ndị a bụ isi FPGA bụ otu na ma c5soc na s5_ref:

VERSION_ID ngọngọ
Usoro izu ike

Nkesa ụlọ akụ ebe nchekwa
Cache snoop interface
Elekere kernel

Nnweta ndebanye aha njikwa (CRA).

1.5 Ime ihe onyonyo kaadi SD
N'ihi na Cyclone V SoC FPGA bụ sistemụ zuru oke na mgbawa, ọ bụ gị na-ahụ maka ịnye nkọwa zuru oke nke sistemụ. Intel na-atụ aro ka ị na-ebuga ya n'ụdị ihe oyiyi kaadị SD. Intel FPGA SDK maka onye ọrụ OpenCL nwere ike dee onyonyo a na kaadị flash micro SD yana bọọdụ SoC FPGA dị njikere maka ojiji.
Ịgbanwe onyonyo kaadị Flash SD dị na ibe 13
Intel na-atụ aro ka ị gbanwee onyonyo dị na Cyclone V SoC Development Kit Reference Platform. Ị nwekwara nhọrọ ịmepụta foto kaadị SD flash ọhụrụ.
Ịmepụta onyonyo kaadị Flash SD na ibe 14
Ị nwekwara nhọrọ ịmepụta foto kaadị SD flash ọhụrụ.

1.5.1 Na-agbanwe onyonyo kaadị Flash SD dị adị
Intel na-atụ aro ka ị gbanwee onyonyo dị na Cyclone V SoC
Platform ntụaka ngwa mmepe. Ị nwekwara nhọrọ ịmepụta foto kaadị SD flash ọhụrụ.
Onyonyo c5soc linux_sd_card_image.tgz file dị na ALTERAOCLSDKROOT/board/c5soc ndekọ, ebe ALTERAOCLSDKROOT na-atụ aka n'ụzọ nke Intel FPGA SDK maka ndekọ nwụnye OpenCL.

Nlebara anya: Iji gbanwee onyonyo kaadị flash SD, ị ga-enwerịrị ikike mgbọrọgwụ ma ọ bụ sudo.

Iji mebie $ALTERAOCLSDKROOT/board/c5soc/linux_sd_card_image.tgz file, gbaa iwu tar xvfzlinux_sd_card_image.tgz.
Chịkọta hello_world OpenCL example chepụta site na iji gị omenala Platform nkwado. Kpọgharia aha .rbf file na Intel FPGA SDK maka OpenCL Offline Compiler na-ewepụta dị ka opencl.rbf, ma tinye ya na akụkụ fat32 n'ime foto kaadị SD.
Ị nwere ike budata ndewo_world example imewe si OpenCL Design Examples ibe na Altera websaịtị.

Debe .rbf file banye na nkebi fat32 nke foto kaadị flash.
Nlebara anya: Nkebi fat32 ga-enwerịrị ma zImage file na .rbf file. Enweghị .rbf file, njehie na-egbu egbu ga-eme mgbe ịtinye ọkwọ ụgbọala ahụ.
Mgbe ịmechara onyonyo kaadị SD, dee ya na kaadị micro SD site n'ịkpọ iwu a: sudo dd if=/path/to/sdcard/image.bin of=/dev/sdcard
Iji nwalee onyonyo kaadị SD gị, rụọ ọrụ ndị a:
a. Fanye kaadị flash micro SD n'ime bọọdụ SoC FPGA.
b. Mee ka osisi dị ike.
c. Kpọọ iwu akụrụngwa nyocha aocl.

1.5.2 Ịmepụta onyonyo kaadị Flash SD
Ị nwekwara nhọrọ ịmepụta foto kaadị SD flash ọhụrụ. Ntuziaka izugbe maka iwulite onyonyo kaadị SD ọhụrụ yana iwughachi onyonyo kaadị flash SD dị na GSRD v14.0.2 - ibe kaadị SD nke RocketBoards.org websaịtị.
Nzọụkwụ dị n'okpuru na-akọwa usoro maka ịmepụta linux_sd_card_image.tgz oyiyi si na Golden System Reference Design (GSRD) SD flash card image:
Mara:
Iji mepụta onyonyo site na onyonyo c5soc, rụọ ọrụ niile dị mkpa akọwapụtara na usoro a.

Budata ma budata GSRD SD flash mbiet oyiyi kaadị 14.0 site na Rocketboards.org.
Ugwu ahụ file table nkenye (fat32) ma gbasaa file akụkụ sistemu (ext3) dị na onyonyo a dị ka ngwaọrụ akaghị azụ. Iji bulie nkebi, mee usoro ndị a:
a. Kpebie mmalite byte nke nkebi dị n'ime onyonyo a site na ịkpọku /sbin/fdisk -lu image_file iwu.
Maka example, nọmba nkebi 1 nke ụdị W95 FAT nwere nkwụsị nkwụsị nke 2121728. Site na 512 bytes kwa ngọngọ, nkwụsị byte bụ 512 bytes x 2121728 = 1086324736 bytes.
b. Chọpụta ngwaọrụ loop efu (maka example, /dev/loop0) site na ịpị iwu losetup -f.
c. Na-eche na / dev/loop0 bụ ngwaọrụ loop efu, kenye onyonyo kaadị flash gị na ngwaọrụ mgbochi akaghị site na ịkpọ oku Lostup / dev/loop0 image_file -0 1086324736 iwu.
d. Wụnye ngwaọrụ loop site na ịkpọku iwu ugwu /dev/loop0 /media/disk1.
N'ime foto a file, /media/disk1 bụ ugbu a nkebi abụba32 etinyere.
e. Tinyegharịa usoro a ruo d maka nkebi ext3.

Budata ụdị Cyclone V SoC FPGA nke Intel FPGA Runtime Environment maka ngwugwu OpenCL site na ebe nbudata na Altera. websaịtị.
a. Pịa bọtịnụ nbudata n'akụkụ mbipụta sọftụwia Quartus Prime.
b. Ezipụta ụdị ntọhapụ, sistemụ arụmọrụ na usoro nbudata.
c. Pịa taabụ Ngwa mgbakwunye, wee họrọ ibudata Intel FPGA
Gburugburu oge ojiri maka OpenCL Linux Cyclone V SoC TGZ.
d. Mgbe ibudatara aocl-rte- .ogwe32.tgz file, bupụ ya
ndekọ nke ị nwere.
Debe aocl-rte- a na-achịkọtaghị .arm32 ndekọ n'ime /home/root/opencl_arm32_rte ndekọ na ext3 nkebi nke oyiyi file.
Hichapụ folda (s) ngwaike nke Platform omenala gị, wee tinye Platform omenala n'ime akwụkwọ ndekọ aha nke /home/root/ opencl_arm32_rte.

Mepụta init_opencl.sh file na / ụlọ / mgbọrọgwụ ndekọ nwere ọdịnaya ndị a: mbupụ ALTERAOCLSDKROOT = / ụlọ / mgbọrọgwụ / opencl_arm32_rte mbupụ AOCL_BOARD_PACKAGE_ROOT = $ALTERAOCLSDKROOT/board/ mbupụ PATH=$ALTERAOCLSDKROOT/bin:$PATH mbupụ LD_LIBRARY_PATH=$ALTERAOCLSDKROOT/host/arm32/lib:$LD_LIBRARY_PATH insmod $AOCL_BOARD_PACKAGE_ROOT/ọkwọ ụgbọala/aclsoc_drv.ko
Onye ọrụ SDK na-agba isi iyi ./init_opencl.sh iwu iji buo mgbanwe gburugburu ebe obibi yana onye ọkwọ ụgbọala kernel OpenCL Linux.
Ọ bụrụ na ịchọrọ imelite preloader, DTS files, ma ọ bụ Linux kernel, ị chọrọ ogwe aka-linux-gnueabihf-gcc compiler sitere na SoC EDS. Soro ntuziaka ndị akọwapụtara na ntuziaka onye ọrụ Intel SoC FPGA Embedded Design Suite iji nweta ngwanro, chịkọta ya, wee kwalite nke dị mkpa. files na agbakwunyere abụba32 nkebi.
Nlebara anya: O yikarịrị ka ị ga-emelite onye na-ebu ụzọ ma ọ bụrụ na Platform omenala gị nwere ntụtụ dị iche iche karịa nke dị na c5soc.
Cheta: Ọ bụrụ na ị na-achịkọta kernel Linux, jiri otu Linux kernel chịkọta onye ọkwọ ụgbọ ala Linux. files. Ọ bụrụ na enwere ndakọrịta n'etiti ọkwọ ụgbọ ala Linux na kernel Linux, ọkwọ ụgbọ ala agaghị ebu. Ọzọkwa, ị ga-emerịrị CMA.
Rụtụ aka na nchịkọtaghachi Linux Kernel maka ozi ndị ọzọ.
Chịkọta hello_world OpenCL example chepụta site na iji gị omenala Platform nkwado. Kpọgharia aha .rbf file na Intel FPGA SDK maka OpenCL Offline Compiler na-ewepụta dị ka opencl.rbf, ma tinye ya na akụkụ fat32 n'ime foto kaadị SD.
Ị nwere ike budata ndewo_world example imewe si OpenCL Design Examples ibe na Altera websaịtị.
9. Mgbe ị na-echekwa ihe niile dị mkpa files na foto kaadị flash, kpọọ iwu ndị a:
a. mekọrịta
b. unmount /media/disk1
c. tutuo ebee bụ aha ndekọ aha ị na-eji maka ịgbanye akụkụ ext3 na 3 na ibe 3 (maka ex.ample, /media/disk2).
d. losetup -d /dev/loop0
e. losetup -d /dev/loop1

Tinye ihe oyiyi kaadị SD flash site na ịkpọku iwu a: tar cvfz .tgz linux_sd_card_image
Nyefee ihe .tgz file n'ime mgbọrọgwụ ndekọ nke gị omenala Platform.
Iji nwalee onyonyo kaadị SD gị, rụọ ọrụ ndị a:
a. Dee onyonyo a na-akpakọghị aka na kaadị micro SD.
b. Fanye kaadị flash micro SD n'ime bọọdụ SoC FPGA.
c. Mee ka osisi ahụ dị ike.
d. Kpọọ iwu akụrụngwa nyocha aocl.

Njikọ ndị emetụtara

Ntuziaka onye ọrụ Intel SoC FPGA agbakwunyere Design Suite
OpenCL Design Examples ibe na Altera websaịtị

Na-achịkọta Kernel Linux na ibe 16
Iji mee ka CMA nwee ike, ị ga-ebu ụzọ chịkọta kernel Linux.
Ịjụ aha ngwaọrụ nke Board FPGA gị (nchọpụta nyocha)

1.6 Na-achịkọta Linux Kernel maka Cyclone V SoC FPGA
Tupu ịmee ngwa OpenCL na bọọdụ Cyclone V SoC FPGA, ị ga-achịkọta isi iyi Linux kernel, ma chịkọta ma wụnye ọkwọ ụgbọala kernel OpenCL Linux.

Na-achịkọta Kernel Linux na ibe 16
Iji mee ka CMA nwee ike, ị ga-ebu ụzọ chịkọta kernel Linux.
Ịchịkọta na ịwụnye OpenCL Linux Kernel Driver na ibe 17 Chịkọta ọkwọ ụgbọala kernel OpenCL Linux megide isi iyi kernel achịkọtara.

1.6.1 Na-achịkọta Linux Kernel
Iji mee ka CMA nwee ike, ị ga-ebu ụzọ chịkọta kernel Linux.

Pịa GSRD v14.0 - Nchịkọta Linux njikọ na ibe akụrụngwa nke RocketBoards.org websaịtị iji nweta ntuziaka maka nbudata na iwughachi koodu isi iyi kernel Linux.
Maka iji ya na ™ Intel FPGA SDK maka OpenCL, kọwaa socfpga-3.13-rel14.0 dị ka .
Mara: Usoro ụlọ na-emepụta arch/arm/configs/socfpga_defconfig file. Nke a file ezipụta ntọala maka nhazi ndabere socfpga.
Tinye ahịrị ndị a na ala arch/arm/configs/socfpga_defconfig file.
CONFIG_MEMORY_ISOLATION=y
CONFIG_CMA=y
CONFIG_DMA_CMA=y
CONFIG_CMA_DEBUG=y
CONFIG_CMA_SIZE_MBYTES=512
CONFIG_CMA_SIZE_SEL_MBYTES=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
Uru nhazi CONFIG_CMA_SIZE_MBYTES na-esetịpụ oke elu na mkpokọta ebe nchekwa na-aga n'ihu dị. Ị nwere ike ịbawanye uru a ma ọ bụrụ na ịchọrọ ebe nchekwa karịa.
Nlebara anya: Ọnụ ego ebe nchekwa anụ ahụ dị na ARM processor na bọọdụ SoC FPGA bụ 1 GB. Intel anaghị akwado ka ịtọọ njikwa CMA nso 1 GB.

Gbaa iwu make mrproper iji hichaa nhazi dị ugbu a.
Gbaa iwu mee ARCH=arm socfpga_deconfig.
ARCH = ogwe aka na-egosi na ịchọrọ ịhazi nhazi ụlọ ARM.
socfpga_defconfig na-egosi na ịchọrọ iji nhazi socfpga ndabara.
Gbaa mbupụ CROSS_COMPILE=arm-linux-gnueabihf-iwu.
Iwu a na-edobe mgbanwe gburugburu CROSS_COMPILE iji kọwapụta prefix nke yinye ngwaọrụ achọrọ.

Gbaa iwu mee ARCH=arm zImage. Ihe onyonyo a rụpụtara dị na arch/arm/boot/zImage file.
Tinye zImage ahụ file banye na nkebi fat32 nke foto kaadị flash. Maka ntuziaka zuru ezu, rụtụ aka na ntuziaka onye ọrụ Cyclone V SoC FPGA akọwapụtara na Rocketboards.org.
Mara: Iji tinye nke ọma OpenCL Linux kernel ọkwọ ụgbọ ala, buru ụzọ buo SDKgenerated.rbf file gaa na FPGA.
Iji mepụta .rbf file, chịkọta ihe SDK imewe exampya na Cyclone V SoC Development Kit Reference Platform dị ka Platform omenala ezubere iche.
9. Debe .rbf file banye na nkebi fat32 nke foto kaadị flash.
Ntị: Nkebi fatị32 ga-enwerịrị ma zImage file na .rbf file. Enweghị .rbf file, njehie na-egbu egbu ga-eme mgbe ịtinye ọkwọ ụgbọala ahụ.

Fanye kaadị micro SD akwadoro, nke nwere onyonyo kaadị SD ị meziri ma ọ bụ mepụta na mbụ, n'ime ngwa mmepe Cyclone V SoC wee kwalite bọọdụ SoC FPGA.
Nyochaa ụdị kernel Linux arụnyere site na iji iwu uname -r.
Iji chọpụta na ị na-enyere CMA aka nke ọma na kernel, na-eji bọọdụ SoC FPGA kwadoro, mee iwu grep init_cma /proc/kallsyms.
Agbanyere CMA ma ọ bụrụ na mmepụta abụghị ihe efu.

Iji jiri Linux kernel chịkọtara na SDK, chịkọta ma wụnye ọkwọ ụgbọala kernel Linux.

Njikọ ndị emetụtara

Akwụkwọ ntuziaka onye ọrụ Golden System Reference (GSRD).

Wulite onyogho kaadi SD na ibe 13
N'ihi na Cyclone V SoC FPGA bụ sistemụ zuru oke na mgbawa, ọ bụ gị na-ahụ maka ịnye nkọwa zuru oke nke sistemụ.

1.6.2 Ịchịkọta na wụnye OpenCL Linux Kernel Driver
Chịkọta onye ọkwọ ụgbọala kernel OpenCL Linux megide isi iyi kernel achịkọtara.

Isi iyi ọkwọ ụgbọ ala dị na ụdị Cyclone V SoC FPGA nke Intel FPGA Runtime Environment maka OpenCL. Na mgbakwunye, hụ na ị kwajuru Intel FPGA SDK maka OpenCL mepụtara .rbf file banye na FPGA iji gbochie ntinye nke modul kernel Linux na-ezighi ezi.

Budata ụdị Cyclone V SoC FPGA nke Intel FPGA Runtime Environment maka ngwugwu OpenCL site na ebe nbudata na Altera. websaịtị.
a. Pịa bọtịnụ nbudata n'akụkụ mbipụta sọftụwia Quartus Prime.
b. Ezipụta ụdị ntọhapụ, sistemụ arụmọrụ na usoro nbudata.
c. Pịa taabụ Ngwa mgbakwunye, wee họrọ ibudata Intel FPGA
Gburugburu oge ojiri maka OpenCL Linux Cyclone V SoC TGZ.
d. Mgbe ibudatara aocl-rte- .ogwe32.tgz file, bupụ ya
ndekọ nke ị nwere.
Isi iyi ọkwọ ụgbọala dị na aocl-rte- .arm32/board/c5soc/ akwụkwọ ndekọ aha ọkwọ ụgbọala.
Iji chịkọta onye ọkwọ ụgbọala kernel OpenCL Linux, tọọ uru KDIR na Mere onye ọkwọ ụgbọ alafile gaa na ndekọ nwere isi iyi kernel Linux files.
Gbaa mbupụ CROSS_COMPILE=arm-linux-gnueabihf-iwu iji gosi prefix nke yinye ngwaọrụ gị.

Gbaa iwu mee dị ọcha.
Gbaa iwu ime ka imepụta aclsoc_drv.ko file.
Nyefee akwụkwọ ndekọ opencl_arm32_rte na bọọdụ Cyclone V SoC FPGA.
Na-agba ọsọ scp -r mgbọrọgwụ @your-ipaddress: iwu na-etinye gburugburu oge ojiri gaa na ndekọ ụlọ/nkpọrọgwụ.

Gbaa init_opencl.sh script nke ị mepụtara mgbe ị rụrụ kaadị SD.
Kpọọ iwu akụrụngwa nyocha aocl. Ngwa nyocha ga-eweghachite nsonaazụ na-agafe mgbe ị gbachara init_opencl.sh nke ọma.

1.7 Okwu ama ama
Ugbu a, enwere oke ụfọdụ na ojiji nke Intel FPGA SDK maka OpenCL na Cyclone V SoC Development Kit Reference Platform.

Ị nweghị ike ịkagbu onye na-ere ahịa na aha bọọdụ nke CL_DEVICE_VENDOR na CL_DEVICE_NAME strings nke oku clGetDeviceInfo() kọrọ.
Ọ bụrụ na onye ọbịa ahụ na-ekenye ebe nchekwa oge niile na sistemụ DDR nkekọrịta (ya bụ, HPS DDR) ma ọ na-agbanwe ebe nchekwa mgbe niile mgbe ogbugbu kernel gasịrị, data dị na ebe nchekwa nwere ike ịbụ ihe ochie. Okwu a na-ebilite n'ihi na isi FPGA enweghị ike ịbanye na azụmahịa CPU-na-HPS DDR.
Iji gbochie ogbugbu kernel na-esote ịnweta data emechiela, mejuputa otu n'ime usoro ndị a:
• Agbanwela ebe nchekwa mgbe niile ka mmalite ya gasịrị.
• Ọ bụrụ na ịchọrọ ọtụtụ __constant data setịpụ, mepụta ọtụtụ nchekwa ebe nchekwa mgbe niile.
• Ọ bụrụ na ọ dị, kenye ebe nchekwa oge niile na FPGA DDR na bọọdụ osooso gị.
Ngwa SDK dị na ARM na-akwado mmemme ahụ yana chọpụta iwu ịba uru.
Iwu ọkụ, wụnye na iwepụ na iwu ịba uru adịghị adabara na ngwa mmepe Cyclone V SoC maka ihe ndị a:
a. Ngwa wụnye ga-achịkọta aclsoc_drv Linux kernel ọkwọ ụgbọ ala wee mee ya na SoC FPGA. Igwe mmepe ga-arụ ọrụ nchịkọta; Agbanyeghị, o nweelarị isi mmalite kernel Linux maka SoC FPGA. Isi mmalite kernel Linux maka igwe mmepe dị iche na nke SoC FPGA. Ebe isi mmalite kernel Linux maka SoC FPGA nwere ike bụrụ onye onye SDK amaghị. N'otu aka ahụ, ngwa iwepụ ngwa ahụ adịghịkwa na ngwa mmepe Cyclone V SoC.
Ọzọkwa, ibuga aclsoc_drv na bọọdụ SoC bụ ihe ịma aka n'ihi na nkesa ndabara nke Cyclone V SoC Development Kit enweghị Linux kernel gụnyere. files ma ọ bụ GNU Compiler Collection (GCC).
b. Ngwa ọkụ na-achọ itinye .rbf file nke imewe OpenCL na akụkụ FAT32 nke kaadi flash micro SD. Ugbu a, anaghị agbanye nkebi a mgbe onye ọrụ SDK na-ebuli bọọdụ ahụ. Ya mere, ụzọ kachasị mma isi melite nkebi bụ iji ihe na-agụ kaadị flash na igwe mmepe.

Mgbe ị na-agbanwe n'etiti Intel FPGA SDK maka OpenCL Offline Compiler executable files (.aocx) nke kwekọrọ na ụdị bọọdụ dị iche iche (ya bụ, c5soc na c5soc_sharedonly), ị ga-eji ngwa mmemme SDK buo .aocx file maka ụdị bọọdụ ọhụrụ maka oge mbụ. Ọ bụrụ na ị na-eji ụdị bọọdụ ọhụrụ na-eme ngwa nnabata mana FPGA nwere onyonyo sitere na ụdị bọọdụ ọzọ, njehie nwere ike ime.
Nke .qxp file anaghị agụnye ọrụ nkebi interface n'ihi na Quartus Prime software na-emezu oge achọrọ maka nkebi a.
Mgbe ị na-agbanye osisi ahụ, a na-edozi adreesị njikwa nnweta mgbasa ozi (MAC) ka ọ bụrụ nọmba enweghị usoro. Ọ bụrụ na amụma LAN gị anabataghị omume a, tọọ adreesị MAC site na ịrụ ọrụ ndị a:
a. N'oge nkwalite U-Boot, pịa igodo ọ bụla iji tinye ngwa ngwa U-Boot.
b. Pịnye setenv ethaddr 00:07:ed:00:00:03 na iwu ozugbo.
Ị nwere ike ịhọrọ adreesị MAC ọ bụla.
c. Pịnye iwu savenv.
d. Malitegharịa ekwentị ahụ.

1.8 Akụkọ ndegharị akwụkwọ
Tebụl 1.
Akwụkwọ akụkọ ngbanwe nke Intel FPGA SDK maka OpenCL Cyclone V SoC
Ntuziaka Ntugharị Ntụaka Ngwa Ngwa

Ụbọchị	Ụdị	Mgbanwe
Mee -17	2017.05.08	• Ntọhapụ mmezi.
Ọktoba 2016	2016.10.31	• Altera SDK ewegharịrị aha maka OpenCL gaa na Intel FPGA SDK maka OpenCL. • Ndị nchịkọta Altera na-anọghị n'ịntanetị ewegharịrị aha ya na Intel FPGA SDK maka OpenCL Compiler Offline.
Mee -16	2016.05.02	• Ntuziaka gbanwere maka iwulite na imegharị onyonyo kaadị flash SD. • Ntuziaka gbanwere maka ịchịkọta kernel Linux na onye ọkwọ ụgbọala kernel OpenCL Linux.
Nọvemba-15	2015.11.02	• Ntọhapụ mmezi, ma gbanwee ihe atụ nke Quartus II gaa na Quartus Prime.
Mee -15	15.0.0	• Na nhazigharị FPGA, ewepụrụ ntụziaka iji megharịa isi FPGA ya na a . foto rbf site n'ịkpọku pusi fileaha>. rbf > / dev/ fpga0 iwu n'ihi na akwadoghị usoro a.
Disemba-14	14.1.0	• Tinyegharịa aha akwụkwọ ahụ ka Altera Cyclone V SoC Development Kit Reference Platform Porting Guide. •Emelitere akụrụngwa reprogram na mmemme aoclfileaha> .aocx utility iwu. • emelitere akụrụngwa diagnostic na nyocha aocl na nyocha aocl iwu ịba uru. • Emelitere usoro dị na Porting the Reference Platform na ngalaba SoC gị iji tinye ntuziaka maka mbubata na imeghari nkebi bọọdụ c5soc iji mepụta nkebi dị ọcha nke oge maka oge mmechi oge ejiri n'aka. • Tinyere isiokwu na-emelite Platform ntụaka Ported iji depụta usoro maka ọrụ ndị a: 1.Excluding siri ike processor usoro (HPS) ngọngọ na osisi nkebi 2.Emelite na SD flash kaadị image • Emelitere ngalaba ihe onyonyo nke kaadị Flash Flash. Akwadoro site na iji ụdị 14.0 nke onyonyo Golden System Reference Design (GSRD) dị ka mmalite kama onyonyo dị na SoC Embedded Design Suite (EDS). • emelitere Linux Kernel na ngalaba kernel Driver OpenCL Linux: 1.gbakwunyere ntuziaka ka ịtọ mgbanwe CROSS COMPILE. 2.Changed iwu ị na-agba ọsọ iji nyochaa na CMA na-enyere ọma.
Julaị-14	14.0.0	• Mwepụta mbụ.