F-Tile DisplayPort FPGA IP Design Example
Fa'aoga Taiala

F-Tile DisplayPort FPGA IP Design Example

Fa'afou mo Intel® Quartus® Prime Design Suite: 22.2 IP Version: 21.0.1

DisplayPort Intel FPGA IP Design Example Taiala Amata vave

O le DisplayPort Intel® F-tile masini o loʻo faʻaalia ai se suʻega faʻataʻitaʻiga ma se mamanu meafaigaluega e lagolagoina le tuʻufaʻatasia ma suʻega meafaigaluega FPGA IP design ex.amptusi mo Intel Agilex™
O le DisplayPort Intel FPGA IP o loʻo ofoina atu le faʻataʻitaʻiga leaamples:

• Fa'aaligaPort SST fa'asolo fa'atasi e aunoa ma se fa'aola Pixel Clock Recovery (PCR) module
• Fa'aaligaPort SST fa'asolo fa'atasi ma le AXIS Vitio Fa'amatalaga

A e fatuina se mamanu example, e otometi lava ona fatuina e le faatonu parameter le files e manaʻomia e faʻataʻitaʻi, faʻapipiʻi, ma suʻe le mamanu i meafaigaluega.
Ata 1. Atina'e StagesFa'amatalaga Fa'atatau

• DisplayPort Intel FPGA IP Taiala Tagata Fa'aoga
• Fa'asolo ile Intel Quartus Prime Pro Edition

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
*O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
ISO 9001:2015 Resitala
1.1. Fa'atonuga Fa'atonu
Ata 2. Fa'atonuga Fa'atonu

Laulau 1. Fuafuaga Example Vaega

Folders	Files
rtl/core	dp_core.ip
	dp_rx . ip
	dp_tx . ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX poloka faufale)
	dp_rx_data_fifo . ip
	rx_top_phy . sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX poloka faufale)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Meafaigaluega ma Polokalama Manaoga
E fa'aogaina e Intel meafaigaluega ma polokalama fa'akomepiuta nei e su'e ai le mamanu exampLe:
Meafaigaluega

• Intel Agilex I-Series Development Kit
• DisplayPort Punavai GPU
• Fa'aigoa Fa'ata'oto (Monitor)
• Bitec DisplayPort FMC tama teine ​​pepa Toe Iloiloga 8C
• Uaea DisplayPort

Polokalama

• Intel Quartus® Palemia
• Synopsys* VCS Simulator

1.3. Fausiaina o le Fuafuaga
Fa'aaoga le DisplayPort Intel FPGA IP fa'atonu fa'atonu i le Intel Quartus Prime software e fa'atupu ai le fa'ata'ita'igaample.
Ata 3. Fa'atupuina o le Fa'asologa o Fuafuaga

1.  Filifili Meafaigaluega ➤ IP Catalog, ma filifili le Intel Agilex F-tile e avea ma aiga masini faʻamoemoe.
   Fa'aaliga: Le mamanu exampLe na'o le lagolagoina o masini Intel Agilex F-tile.
2. I le IP Catalog, su'e ma kiliki fa'alua DisplayPort Intel FPGA IP. Ua aliali mai le fa'amalama New IP Variation.
3. Fa'ailoa se igoa pito i luga mo lau suiga masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .ip.
4. Filifili se masini Intel Agilex F-tile i totonu o le masini masini, poʻo le faʻatumauina le faʻaogaina o masini komepiuta Intel Quartus Prime filifilia.
5. Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
6. Fa'atulaga mea e mana'omia mo TX ma RX.
7. I lalo ole Design Exampi le tab, filifili DisplayPort SST Parallel Loopback e aunoa ma le PCR.
8. Filifili Fa'ata'ita'iga e fa'atupu ai le su'ega, ma filifili Fa'atasi e fa'atupuina ai le fa'asologa o meafaigaluegaample. E tatau ona e filifilia se tasi o nei filifiliga e fa'atupu ai le fa'ata'ita'igaample files. Afai e te filifilia mea uma e lua, o le a umi atu le taimi o le gaosiga.
9. Mo le Pusa Atina'e, filifili le Intel Agilex I-Series SOC Development Kit. O le mea lea e mafua ai ona sui le masini taulaʻi i le Laasaga 4 e fetaui ma le masini i luga o le pusa atinaʻe. Mo le Intel Agilex I-Series SOC Development Kit, o le masini fa'aletonu ole AGIB027R31B1E2VR0.
10. Kiliki Fausia Example Design.

1.4. Fa'ata'ita'iina o le Fuafuaga
Le DisplayPort Intel FPGA IP design example testbench fa'ata'ita'iina se fa'asologa o le loopback mamanu mai se fa'ata'ita'iga TX i se fa'ata'ita'iga RX. O se masini fa'atupu ata vitio i totonu e fa'aosoina le DisplayPort TX fa'ata'ita'iga ma le RX fa'ata'ita'iga ata vitio e feso'ota'i i siaki CRC i le su'ega.
Ata 4. Fa'asologa Fa'ata'ita'iga Fa'asologa

1. Alu ile Synopsys simulator folder ma filifili VCS.
2. Fa'ata'ita'i fa'asologa.
   Punavai vcs_sim.sh
3. O le tusitusiga e faʻatino ai le Quartus TLG, faʻapipiʻi ma faʻatautaia le suʻega suʻega i le simulator.
4. Iloilo le taunuuga.
   O se faʻataʻitaʻiga manuia e faʻamaeʻa i le Source ma Sink SRC faʻatusatusaga.

1.5. Tu'ufa'atasia ma Fa'ata'ita'i le Fuafuaga
Ata 5. Tu'ufa'atasia ma Fa'ata'ita'i le Fa'ata'ita'igaE fa'aputu ma fa'atino se su'ega fa'ata'ita'iga ile meafaigaluega fa'aample mamanu, mulimuli i laasaga nei:

1. Ia mautinoa meafaigaluega exampua mae'a le fausiaina o mamanu.
2. Tatala le polokalama Intel Quartus Prime Pro Edition ma tatala / quartus/agi_dp_demo.qpf.
3. Kiliki Processing ➤ Amata Fa'aopoopo.
4. A mae'a le fa'aputuga manuia, e fa'atupuina e le Intel Quartus Prime Pro Edition se .sof file i lau lisi fa'apitoa.
5. Fa'afeso'ota'i le feso'ota'iga DisplayPort RX i le kata tama Bitec i se puna DisplayPort i fafo, e pei o le kata fa'ata i luga o le PC.
6. Fa'afeso'ota'i le DisplayPort TX fa'afeso'ota'i i luga o le Bitec daughter card i se masini fa'agogo DisplayPort, e pei o se su'esu'e vitiō po'o se mata'itū PC.
7.  Ia mautinoa o ki uma i luga o le laupapa atina'e o lo'o i le tulaga le lelei.
8. Fa'atulaga le masini Intel Agilex F-Tile filifilia i luga o le laupapa atinae e fa'aaoga ai le .sof file (Meafaigaluega ➤ Polokalama ).
9. O le DisplayPort sink masini e faʻaalia ai le vitio na gaosia mai le puna vitio.

Fa'amatalaga Fa'atatau
Intel Agilex I-Series FPGA Development Kit Guide Guide/
1.5.1. Toe fa'afouina ELF File
Ona o le faaletonu, o le ELF file e fa'atupuina pe a e fa'atupuina le fa'ata'ita'iga malosi fa'aample.
Ae ui i lea, i nisi tulaga, e te manaʻomia le toe faʻafouina o le ELF file pe afai e te suia le polokalama file pe toe fa'afouina le dp_core.qsys file. Toe fa'afouina le dp_core.qsys file fa'afou le .sopcinfo file, lea e manaʻomia ai oe e toe faʻafouina le ELF file.

1. Alu i le /software ma fa'asa'o le code pe a mana'omia.
2. Alu i le /script ma faʻatino le faʻasologa o le fausiaina: source build_sw.sh
   • I luga ole Windows, su'e ma tatala le Nios II Command Shell. I le Nios II Command Shell, alu i /script ma faʻatino le puna build_sw.sh.
   Fa'aaliga: Ina ia faʻatinoina le faʻasologa o tusitusiga i luga Windows 10, e manaʻomia e lau polokalama Windows Subsystems mo Linux (WSL). Mo nisi faʻamatalaga e uiga i laasaga faʻapipiʻi WSL, tagai ile Nios II Software Developer Handbook.
   • I luga o Linux, fa'alauiloa le Platform Designer, ma tatala Meafaigaluega ➤ Nios II Command Shell. I le Nios II Command Shell, alu i /script ma faʻatino le puna build_sw.sh.
3. Ia mautinoa o se .elf file ua gaosia i totonu /software/ dp_demo.
4. La'u mai le .elf ua faia file i totonu o le FPGA e aunoa ma le toe tuufaatasia o le .sof file e ala i le faʻaogaina o le faʻasologa o loʻo i lalo: nios2-download /software/dp_demo/*.elf
5. Oomi le faamau toe setiina i luga o le laupapa FPGA mo le polokalama fou e aoga.

1.6. DisplayPort Intel FPGA IP Design Example Parameter
Laulau 2. DisplayPort Intel FPGA IP Design Example QSF fa'agata mo le Intel Agilex Ftile Device

QSF Fa'agata	Fa'amatalaga
seti_global_assignment -igoa VERILOG_MACRO “__DISPLAYPORT_support__=1”	Mai le Quartus 22.2 i luma, e manaʻomia lenei faʻatapulaʻaina QSF ina ia mafai ai ona faʻagasolo le DisplayPort custom SRC (Soft Reset Controller)

Laulau 3. DisplayPort Intel FPGA IP Design Example Parameter mo le Intel Agilex F-tile Device

Parameter	Taua	Fa'amatalaga
Avanoa Design Example
Filifili Design	• Leai •DisplayPort SST Parallel Loopback e aunoa ma le PCR •DisplayPort SST Parallel Loopback ma le AXIS Video Interface	Filifili le mamanu example e gaosia. • Leai: Leai se mamanu example avanoa mo le filifiliga parakalafa o lo'o iai nei. •DisplayPort SST Parallel Loopback e aunoa ma le PCR: O le mamanu leneiampe fa'aalia le fa'asolo tutusa mai le fa'agogo o le DisplayPort i le puna DisplayPort e aunoa ma se Pixel Clock Recovery (PCR) module pe a e kiina le fa'aagaoioiga Enable Video Input Image Port. •DisplayPort SST Parallel Loopback ma le AXIS Video Interface: O lenei mamanu exampe fa'aalia le fa'alava fa'atusa mai le fa'agogo DisplayPort i le puna DisplayPort fa'atasi ai ma le AXIS Vitio atina'e pe a fa'aagaoioi le Active Video Data Protocols ua seti i le AXIS-VVP Full.
Design Example Files
Fa'ata'oto	Ua pe, ua pe	Fa'aola lenei filifiliga e fa'atupu ai mea e mana'omia files mo le su'ega fa'ata'ita'iga.
Fa'asologa	Ua pe, ua pe	Fa'aola lenei filifiliga e fa'atupu ai mea e mana'omia files mo Intel Quartus Prime tu'ufa'atasiga ma mamanu meafaigaluega.
Fausia le HDL Format
Fa'atupu File Fa'asologa	Verilog, VHDL	Filifili lau fa'atulagaga HDL e te mana'o iai mo le fa'ata'ita'iga fa'atupuample fileseti. Fa'aaliga: O lenei filifiliga e na'o le fa'atulagaina mo le fa'atupuina o le tulaga maualuga IP files. O isi uma files (egample testbenches ma le tulaga maualuga files mo meafaigaluega faʻataʻitaʻiga) o loʻo i le Verilog HDL format.
Pusa Atina'e Sini
Filifili le Komiti Faatino	•Leai se atigi pusa •Intel Agilex I-Series Pusa Atina'e	Filifili le laupapa mo le mamanu fa'atatauample.

Parameter	Taua	Fa'amatalaga
		• Leai se Pusa Atina'e: O lenei filifiliga e le aofia ai vaega uma o meafaigaluega mo le mamanu muamuaample. O le P core e setiina uma tofitofiga pine i pine mama. •Intel Agilex I-Series FPGA Development Kit: O lenei filifiliga e otometi lava ona filifilia le masini fa'atatau i le poloketi e fetaui ma le masini i lenei pusa atina'e. E mafai ona e suia le masini fa'atatau i le fa'aogaina o le Suiga o le Fa'atonu Fa'atonu pe a fai e iai se suiga ole masini e iai lau su'ega laupapa. O le IP autu e setiina uma tofitofiga pine e tusa ai ma le pusa atinaʻe. Manatua: Fuafuaga Muamua Exampe le'o fa'amaonia fa'atino i meafaigaluega i lenei fa'asalalauga Quartus. • Pusa Atina'e Fa'apitoa: O lenei filifiliga e fa'atagaina ai le mamanu fa'atusaampe fa'ata'ita'iina i se pusa atina'e lona tolu ma se Intel FPGA. Atonu e te mana'omia le setiina e oe lava o tofiga o pine.
Meafaigaluega Sini
Suia Mea Fa'atatau	Ua pe, ua pe	Fa'aola le filifiliga lea ma filifili le mea e sili ona fiafia i ai masini mo le atina'e pusa.

Fa'atusa Loopback Fa'atasiamples

Le DisplayPort Intel FPGA IP design exampfa'aalia le fa'ata'ita'iga tutusa mai le fa'ata'ita'iga DisplayPort RX i le fa'ata'ita'iga DisplayPort TX e aunoa ma se fa'aoga Pixel Clock Recovery (PCR).
Laulau 4. DisplayPort Intel FPGA IP Design Example mo le Intel Agilex F-tile Device

Design Example	Tofiga	Fua Fa'amatalaga	Faiga Ala	Ituaiga Loopback
DisplayPort SST fa'asolo fa'atasi e aunoa ma le PCR	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Fa'atasi e aunoa ma se PCR
Fa'aaligaPort SST fa'asolo fa'atasi ma le AXIS Vitio Fa'amatalaga	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Fa'atasi ma le AXIS Vitio Fa'amatalaga

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Vaega
Le SST parallel loopback design exampO lo'o fa'aalia le tu'uina atu o se ata vitio se tasi mai le fa'agogo DisplayPort i le puna DisplayPort.
Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
ISO 9001:2015 Resitala
Ata 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback e aunoa ma le PCR

• I lenei fesuiaiga, o le DisplayPort source's parameter, TX_SUPPORT_IM_ENABLE, ua ki ma faʻaoga le ata vitio faʻaoga.
• O le DisplayPort sink e maua ai le vitio ma poʻo le faʻalogo leo mai le puna vitio i fafo e pei o le GPU ma faʻavasegaina i totonu o ata vitio tutusa.
• O le DisplayPort goto vitiō e ave sa'o ai le DisplayPort source video interface ma fa'ailoga i le DisplayPort so'otaga autu a'o le'i tu'uina atu i le mata'itū.
• O le IOPLL e fa'aulu uma le fa'agogo DisplayPort ma fa'apogai uati vitio i se taimi fa'amau.
• Afai o le DisplayPort goto ma le puna MAX_LINK_RATE parakalafa ua configured i HBR3 ma PIXELS_PER_CLOCK configured i Quad, o le uati vitio e tamoe i le 300 MHz e lagolago 8Kp30 pika fua (1188/4 = 297 MHz).

Ata 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback ma le AXIS Vitio Fa'afeso'ota'i

• I lenei fesuiaiga, o le DisplayPort source ma le parakalafa sisi, filifili AXIS-VVP FULL i ENABLE ACTIVE VIDEO DATA PROTOCOLS e mafai ai le Axis Video Data Interface.
• O le DisplayPort sink e maua ai le vitio ma poʻo le faʻalogo leo mai le puna vitio i fafo e pei o le GPU ma faʻavasegaina i totonu o ata vitio tutusa.
• O le DisplayPort Sink e fa'aliliuina fa'amaumauga o fa'amatalaga vitio i fa'amatalaga vitio axis ma fa'auluina le fa'amatalaga fa'amatalaga fa'amatalaga axis puna DisplayPort e ala i le VVP Video Frame Buffer. O le DisplayPort Source e fa'aliliuina ai fa'amatalaga vitio axis i le feso'ota'iga autu o le DisplayPort a'o le'i tu'uina atu i le mata'itū.
• I lenei suiga mamanu, e tolu uati autu autu, e ta'ua rx/tx_axi4s_clk, rx_vid_clk, ma tx_vid_clk. axi4s_clk e tamo'e ile 300 MHz mo AXIS modules ile Source ma Sink. rx_vid_clk fa'atautaia le DP Sink Video pipeline i le 300 MHz (e lagolagoina so'o se iugafono e o'o atu i le 8Kp30 4PIPs), a'o tx_vid_clk e fa'atautaia le DP Source Video pipeline i le taimi tonu o le Pixel Clock (vaevaeina e PIPs).
• Ole suiga ole mamanu lea e fetuutuunai ai le tx_vid_clk frequency e ala ile polokalame I2C ile luga ole SI5391B OSC pe a iloa e le mamanu se ki i le iugafono.
• O lenei suiga mamanu e na o le faʻaalia o se numera faʻamautu o iugafono e pei ona muai faʻamalamalamaina i le DisplayPort software, e pei o:
  — 720p60, RGB
  — 1080p60, RGB
  — 4K30, RGB
  — 4K60, RGB

2.2. Fuafuaga uati
O lo'o fa'ailoa mai e le fa'ailoga uati le fa'ailoga uati i le DisplayPort Intel FPGA IP design example.
Ata 8. Intel Agilex F-tile DisplayPort Transceiver polokalame uatiLaulau 5. Fa'ailoga Fa'ailoga Fa'ailoga

Uati i le ata	Fa'amatalaga
SysPLL refclk	F-tile System PLL reference clock lea e mafai ona avea ma so'o se taimi uati e mafai ona vaevae e le System PLL mo lena fa'asologa o galuega. I lenei mamanu example, system_pll_clk_link ma rx/tx refclk_link faasoa tutusa 150 MHz SysPLL refclk.

Uati i le ata	Fa'amatalaga
	E tatau ona avea ma se uati e leai se totogi e feso'ota'i mai se pine uati fa'asinomaga fa'apitoa i le uati fa'aulu o le Fa'asinoga ma le System PLL Uati IP, a'o le'i fa'afeso'ota'i le uati fa'atatau i le DisplayPort Phy Top. Manatua: Mo lenei mamanu example, configure Pule Uati GUI Si5391A OUT6 i 150 MHz.
faiga pll clk so'oga	Ole la'ititi ole System PLL ole fa'aulufalega e lagolago uma DisplayPort fua ole 320 MHz. O lenei mamanu exampe fa'aaoga le 900 MHz (maualuga) fa'alava fa'aulu ina ia mafai ona fa'asoa le SysPLL refclk i rx/tx refclk_link o le 150 MHz.
rx_cdr_refclk_link / tx_pll_refclk_link	Rx CDR ma Tx PLL Link refclk lea na fa'amauina i le 150 MHz e lagolago uma ai fa'amatalaga fa'amatalaga DisplayPort.
rx_ls_clkout / tx_ls_clkout	DisplayPort Link Speed ​​Clock i le uati DisplayPort IP autu. Fa'atelega tutusa ma le Fa'amatalaga Fa'amatalaga vaevae i le lautele o fa'amaumauga tutusa. ExampLe: Auala = fua fa'amatalaga / lautele fa'amatalaga = 8.1G (HBR3) / 40 bits = 202.5 MHz

2.3. Simulation Testbench
O le faʻataʻitaʻiga testbench faʻataʻitaʻiina le DisplayPort TX serial loopback i le RX.
Ata 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block DiagramLaulau 6. Vaega Su'esu'e

Vaega	Fa'amatalaga
Vitio Mamanu Faia	O lenei generator e maua ai mamanu pa lanu e mafai ona e faʻatulagaina. E mafai ona e fa'avasega le taimi fa'atulagaina o le vitio.
Su'ega Pulea	O lenei poloka e pulea le faʻasologa o suʻega o le faʻataʻitaʻiga ma faʻatupuina faʻailoga faʻamalosi e manaʻomia i le TX autu. E faitau fo'i e le poloka su'esu'e le tau o le CRC mai le puna ma le goto e fai ai fa'atusatusaga.
RX Link Speed ​​​​Clock Time Checker	E fa'amaonia e le siaki lea pe o fetaui le fa'asologa o le uati o le RX transceiver ma le fua faatatau o fa'amaumauga e mana'omia.
TX So'otaga Saosaoa Uati Su'e Fa'asao	E fa'amaonia e le siaki lenei pe a fetaui le TX transceiver toe maua mai le taimi ole uati ma le fua faatatau o fa'amatalaga mana'omia.

O le simulation testbench e faia faʻamaoniga nei:
Laulau 7. Testbench Verifications

Tulaga o Su'ega	Fa'amaoniga
• Feso'ota'iga a'oa'oga ile Fa'amaumauga HBR3 • Faitau le resitara o le DPCD e siaki ai pe fa'atulaga e le Tulaga DP ma fua uma le TX ma le RX Link Speed ​​frequency.	Fa'atasi le Su'esu'ega Fa'atele e fua ai le Saosaoa So'oga fa'asolo fa'avavevave a le uati mai le TX ma le RX transceiver.
• Fa'asolo ata vitio mai le TX i le RX. • Fa'amaonia le CRC mo le puna ma le goto e siaki pe fetaui	• Fa'afeso'ota'i generator mamanu ata vitio i le DisplayPort Source e fa'atupu ai le ata vitio. • O le fa'atonuga o le Testbench e soso'o ai e faitau uma le Source ma le Sink CRC mai le DPTX ma le DPRX resitala ma fa'atusatusa ina ia mautinoa e tutusa uma tau o le CRC. Fa'aaliga: Ina ia mautinoa o lo'o fuafuaina le CRC, e tatau ona e fa'agaoioia le Su'ega CTS fa'ata'ita'iga otometi.

Fa'amatalaga Toe Iloiloga mo F-Tile DisplayPort Intel FPGA IP Design Example User Guide

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
2022.09.02	22.	20.0.1	•Suia le ulutala pepa mai le DisplayPort Intel Agilex F-Tile FPGA IP Design Example Ta'iala mo le Fa'aoga ile F-Tile DisplayPort Intel FPGA IP Design Example User Guide. • Fa'aagaoioi le AXIS Video Design Example eseesega. • Aveese le Static Rate design ma suia i le Multi Rate Design Example. • Aveese le fa'amatalaga i le DisplayPort Intel FPGA IP Design Example Quick Start Guide o loʻo faʻapea mai Intel Quartus Prime 21.4 software version e naʻo le lagolagoina o Preliminary Design Examples. • Suia le ata Fa'atonu Fa'atonu i le ata sa'o. • Fa'aopoopoina se vaega Toe fa'afouina ELF File i lalo o le Tu'ufa'atasia ma le Su'ega o le Fuafuaga. • Fa'afou le vaega o Meafaigaluega ma Polokalama Manaomia e aofia ai meafaigaluega faaopoopo manaoga.
2021.12.13	21.	20.0.0	Fa'asalalauga muamua.

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
*O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
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Faʻasinomaga Faʻainitaneti
Lauina Manatu
UG-20347
ID: 709308
Fa'aliliuga: 2022.09.02

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intel F-Tile DisplayPort FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga F-Tile DisplayPort FPGA IP Design Example, F-Tile DisplayPort, DisplayPort, FPGA IP Design Example, IP Design Example, UG-20347, 709308

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