Intel LogoAN 987: Aimi Update Apa kan
Tutorial atunto

Awọn akoonu tọju
1 Imudojuiwọn Aimi Itọnisọna Atunto Apa kan fun Intel® ™ Agilex F-Series FPGA Development Board
2 Laasigbotitusita PR Awọn aṣiṣe siseto
3 Awọn iwe aṣẹ / Awọn orisun
3.1 Awọn itọkasi

Imudojuiwọn Aimi Itọnisọna Atunto Apa kan fun Intel® ™ Agilex F-Series FPGA Development Board

Akọsilẹ ohun elo yii ṣe afihan isọdọtun apa kan imudojuiwọn aimi (SUPR) lori Igbimọ Idagbasoke FPGA ti Intel ® F-Series. Atunto apakan (PR) gba ọ laaye lati tunto apakan kan ti Intel FPGA ni agbara, lakoko ti FPGA to ku tẹsiwaju lati ṣiṣẹ. PR ṣe imuse awọn eniyan lọpọlọpọ ni agbegbe kan pato ninu apẹrẹ rẹ, laisi ipa iṣẹ ni awọn agbegbe ni ita agbegbe yii. Ilana yii pese advan atẹletages ninu awọn eto ninu eyiti awọn iṣẹ lọpọlọpọ akoko pin pin awọn orisun FPGA kanna:

  • Faye gba ṣiṣe-akoko atunto
  • Ṣe alekun iwọn apẹrẹ
  • Din akoko-isalẹ eto
  • Ṣe atilẹyin awọn iṣẹ akoko-multiplexing ti o ni agbara ninu apẹrẹ
  • Dinku idiyele ati agbara agbara nipasẹ lilo daradara ti aaye igbimọ

Kini Imudojuiwọn Aimi Apakan?

Ni PR ibile, iyipada eyikeyi si agbegbe aimi nilo atunko ti gbogbo eniyan. Sibẹsibẹ, pẹlu SUPR o le ṣalaye agbegbe amọja ti o fun laaye iyipada, laisi nilo atunko ti eniyan. Ilana yii wulo fun apakan ti apẹrẹ kan ti o le fẹ yipada fun idinku eewu, ṣugbọn iyẹn ko nilo atunto akoko asiko rara.

1.1. Tutorial ibeere
Ikẹkọ yii nilo atẹle naa:

  • Imọmọ ipilẹ pẹlu Intel Quartus® Prime Pro Edition FPGA sisan imuse ati iṣẹ akanṣe files.
  •  Fifi sori ẹrọ ti ẹya Intel Quartus Prime Pro Edition 22.3, pẹlu atilẹyin ẹrọ Intel Agilex.
  • Fun imuse FPGA, JTAG asopọ pẹlu Intel Agilex F-Series FPGA idagbasoke ọkọ lori ibujoko.
  • Ṣe igbasilẹ Apẹrẹ Itọkasi Files. Alaye ti o jọmọ
  • Itọsọna olumulo atunto apakan
  • Apa kan reconfiguration Tutorials
  • Ikẹkọ Atunto Apa kan lori Ayelujara

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO 9001: 2015 forukọsilẹ
1.2. Reference Design Loriview
Apẹrẹ itọkasi yii ni ọkan, counter 32-bit. Ni ipele igbimọ, apẹrẹ naa so aago pọ si orisun 50MHz, lẹhinna so abajade pọ si awọn LED mẹrin lori ọkọ. Yiyan abajade lati awọn iwọn counter, ni ọkọọkan kan, fa awọn LED lati seju ni igbohunsafẹfẹ kan pato. Module top_counter ni agbegbe SUPR.
olusin 1. Alapin Reference Design

Intel Logo1.3. Aimi Update Region Loriview
Nọmba ti o tẹle n ṣe afihan aworan atọka fun apẹrẹ PR ti o pẹlu agbegbe SUPR kan. Àkọsílẹ A ni Top aimi agbegbe. Block B jẹ agbegbe SUPR. Àkọsílẹ C jẹ ipin PR.
Ṣe nọmba 2. Apẹrẹ PR pẹlu agbegbe SUPR

intel Agilex F-Series FPGA Development Board - Ekun

  • A Top Static Region-ni ninu awọn kannaa oniru ti ko ni yi. Yiyipada agbegbe yii nilo atunkopọ gbogbo awọn eniyan ti o somọ. Agbegbe aimi pẹlu apakan ti apẹrẹ ti ko yipada fun eyikeyi eniyan. Agbegbe yii le pẹlu ẹba ati awọn orisun ẹrọ pataki. O gbọdọ forukọsilẹ gbogbo ibaraẹnisọrọ laarin SUPR ati awọn ipin PR ni agbegbe aimi. Ibeere yii ṣe iranlọwọ lati rii daju pipade akoko fun eyikeyi eniyan, pẹlu ọwọ si agbegbe aimi.
  • Ẹkun B SUPR-ni awọn ọgbọn-ọrọ-nikan ti o le yipada fun idinku eewu, ṣugbọn ko nilo atunto akoko asiko rara. Agbegbe SUPR ni awọn ibeere kanna ati awọn ihamọ bi ipin PR. Ipin SUPR le ni awọn orisun pataki nikan ninu. Nitorinaa, ipin SUPR gbọdọ jẹ ipin ọmọ ti ipin root ti oke-ipele ti o ni ẹba apẹrẹ ati awọn aago. Yiyipada agbegbe SUPR ṣe agbejade Nkan SRAM kan File (.sof) ti o ni ibamu pẹlu gbogbo awọn ti o wa tẹlẹ compiled Raw alakomeji File (.rbf) files fun PR ipin C.
  • C PR Partition—ni awọn ọgbọn lainidii ninu ti o le tun ṣe ni akoko asiko ṣiṣe pẹlu eyikeyi ọgbọn apẹrẹ ti o baamu ati ṣaṣeyọri pipade akoko lakoko iṣakojọpọ.

1.4. Ṣe igbasilẹ Apẹrẹ Itọkasi Files
Ikẹkọ atunto apa kan wa ni ipo atẹle: https://github.com/intel/fpga-partial-reconfig
Lati ṣe igbasilẹ ikẹkọ:

  1. Tẹ Clone tabi ṣe igbasilẹ.
  2. Tẹ Gba ZIP silẹ. Unzip fpga-partial-reconfig-master.zip file.
  3. Lilö kiri si awọn olukọni/agilex_pcie_devkit_blinking_led_supr folda lati wọle si apẹrẹ itọkasi.
    Awọn Building folda oriširiši awọn wọnyi files:
    Table 1. Reference Design Files
File Oruko Apejuwe
oke. sv Ipele oke file ti o ni awọn Building imuse ti awọn oniru. Eleyi module instantiates awọn blinking_led iha-ipin ati top_counter module.
t op_counter. sv Oke-ipele 32-bit counter ti o dari LED [1] taara. Awọn aami-ijade ti counter idari LED [0], ati ki o tun agbara LED [2] ati LED [3] nipasẹ blinking_led module.
blinking_led. sdc Ṣe alaye awọn ihamọ akoko fun iṣẹ akanṣe naa.
blinking_led. sv Ninu ikẹkọ yii, o ṣe iyipada module yii sinu ipin PR obi kan. Awọn module gba awọn aami-o wu ti top_counter module, ti o išakoso LED [2] ati LED [3].
blinking_led.qpf Intel Quartus NOMBA ise agbese file ti o ni awọn akojọ ti gbogbo awọn atunṣe ni ise agbese.
blinking_led . qs f Intel Quartus NOMBA eto file ti o ni awọn iṣẹ iyansilẹ ati eto fun ise agbese.

Akiyesi: Awọn supr folda ni awọn pipe ṣeto ti files o ṣẹda nipa lilo ohun elo yii akiyesi. Tọkasi awọn wọnyi files ni eyikeyi ojuami nigba ti Ririn.
1.5. Reference Design Ririn
Awọn igbesẹ wọnyi ṣe apejuwe imuse ti SUPR pẹlu apẹrẹ alapin:

  • Igbesẹ 1: Bibẹrẹ
  • Igbesẹ 2: Ṣẹda Awọn ipin Apẹrẹ
  • Igbesẹ 3: Pin Ibi ati Awọn agbegbe ipa ọna
  • Igbesẹ 4: Ṣe alaye Awọn eniyan
  • Igbesẹ 5: Ṣẹda Awọn Atunyẹwo
  • Igbesẹ 6: Ṣe akopọ Atunyẹwo Ipilẹ
  • Igbesẹ 7: Ṣeto Awọn atunwo imuse PR
  • Igbesẹ 8: Yi Iyipada SUPR pada
  • Igbesẹ 9: Ṣeto Igbimọ naa

olusin 3. SUPR Compilation Flow

intel Agilex F-Series FPGA Development Board - Sisan

1.5.1. Igbesẹ 1: Bibẹrẹ
Lati daakọ apẹrẹ itọkasi files si agbegbe iṣẹ rẹ ki o ṣajọ apẹrẹ alapin blinking_led:

  1. Ṣaaju ki o to bẹrẹ, Ṣe igbasilẹ Apẹrẹ Itọkasi Files loju iwe 5.
  2. Ṣẹda itọsọna agilex_pcie_devkit_blinking_led_supr ni agbegbe iṣẹ rẹ.
  3. Daakọ awọn ikẹkọ ti a gbasile/agilex_pcie_devkit_blinking_led/folda iha-ipin si agilex_pcie_devkit_blinking_led_supr liana.
  4. Ninu sọfitiwia Intel Quartus Prime Pro Edition, tẹ File ➤ Ṣii Project ati ṣii /flat/blinking_led.qpf.
  5. Lati ṣajọ apẹrẹ ipilẹ, tẹ Ṣiṣe-ṣiṣe ➤ Bẹrẹ Iṣakojọpọ. Awọn ijabọ Oluyanju akoko ṣii laifọwọyi nigbati akopọ ba ti pari. O le pa Oluyanju akoko fun ni bayi.

1.5.2. Igbesẹ 2: Ṣẹda Awọn ipin Apẹrẹ
Ṣẹda awọn ipin apẹrẹ fun agbegbe kọọkan ti o fẹ lati tunto ni apakan. O le ṣẹda nọmba eyikeyi ti awọn ipin ominira tabi awọn agbegbe PR ninu iṣẹ akanṣe rẹ. Tẹle awọn igbesẹ wọnyi lati ṣẹda awọn ipin apẹrẹ fun apẹẹrẹ u_blinking_led gẹgẹbi ipin PR, ati apẹẹrẹ u_top_counter gẹgẹbi agbegbe SUPR:

  1. Tẹ-ọtun apẹẹrẹ u_blinking_led ni Aṣawari Iṣẹ ki o tẹ Ipin Apẹrẹ
    ➤ atunto. Aami ipin apẹrẹ kan han lẹgbẹẹ apẹẹrẹ kọọkan ti o ṣeto bi ipin kan.
    olusin 4. Ṣiṣẹda Design Partitionsintel Agilex F-Series FPGA Development Board - Awọn ipin
  2. Tun igbese 1 ṣe lati ṣẹda ipin kan fun apẹẹrẹ u_top_counter.
  3. Tẹ Awọn iṣẹ iyansilẹ ➤ Ferese Awọn ipin Apẹrẹ. Ferese naa ṣafihan gbogbo awọn ipin apẹrẹ ninu iṣẹ akanṣe naa.
    olusin 5. Design Partitions Window
    intel Agilex F-Series FPGA Development Board - Window
  4. Tẹ-lẹẹmeji sẹẹli Orukọ ipin blinking_led lati fun lorukọ rẹ si pr_partition. Bakanna, tun lorukọ apakan top_counter si supr_partition.
    Ni omiiran, fifi awọn ila wọnyi kun si blinking_led.qsf ṣẹda awọn ipin wọnyi:
    set_intance_assignment -name PARTITION pr_partition \ -to u_blinking_led -entity top
    set_intance_assignment -orukọ PARTIAL_RECONFIGURATION_PARTITION LORI \ -to u_blinking_led -entity top
    set_intance_assignment -orukọ PARTITION supr_partition \ -to u_top_counter -entity oke
    set_intance_assignment -orukọ PARTIAL_RECONFIGURATION_PARTITION LORI \ -to u_top_counter -entity oke

1.5.3. Igbesẹ 3: Pin Ibi ati Awọn agbegbe ipa ọna
Fun gbogbo atunyẹwo ipilẹ ti o ṣẹda, Olupilẹṣẹ naa nlo ipinpin agbegbe ipin PR lati gbe mojuto persona ti o baamu ni agbegbe ti a fi pamọ. Tẹle awọn igbesẹ wọnyi lati wa ati yan agbegbe PR kan ninu ero ilẹ-ilẹ ẹrọ fun atunyẹwo ipilẹ rẹ:

  1. Ni awọn Project Navigator logalomomoise taabu, ọtun-tẹ awọn u_blinking_led apeere, ati ki o si tẹ Logic Lock Region ➤ Ṣẹda New Logic Lock Region. Ekun naa han ni window Logic Lock Regions.
  2. Pato agbegbe kan Iwọn ti 5 ati Giga ti 5.
  3. Pato awọn ipoidojuko agbegbe fun u_blinking_led ni iwe Oti. Ipilẹṣẹ ni ibamu si igun apa osi isalẹ ti agbegbe naa. Pato Ipilẹṣẹ bi X166_Y199. Olupilẹṣẹ ṣe iṣiro (X170 Y203) bi ipoidojuko oke-ọtun.
  4. Mu awọn aṣayan Ifipamọ ati Core-Nikan ṣiṣẹ fun agbegbe naa.
  5. Tẹ lẹẹmeji aṣayan Agbegbe ipa ọna. Apoti ibanisọrọ Awọn Eto Agbegbe Logic Lock Routing yoo han.
  6. Fun Iru Ipa ọna, yan Ti o wa titi pẹlu imugboroja. Aṣayan yii yoo ṣe ipinnu ipari Imugboroosi kan laifọwọyi.
  7. Tun awọn igbesẹ ti tẹlẹ ṣe lati pin awọn orisun wọnyi fun ipin u_top_counter:
    • Giga-5
    • Ìbú—5
    • Oti-X173_Y199
    • Agbegbe ipa ọna- Ti o wa titi pẹlu imugboroja pẹlu ipari Imugboroosi ti ọkan.
    • Ni ipamọ- Tan-an
    • Koko-Nikan-Lori
    olusin 6. Logic Lock Regions Window
    intel Agilex F-Series FPGA Development Board - Awọn agbegbe Window    Akiyesi: Ẹkun ipa-ọna gbọdọ jẹ ti o tobi ju agbegbe ti a fi sii, lati pese afikun ni irọrun fun awọn ipa-ọna Compiler's s.tage, nigbati awọn Compiler ipa ọna ti o yatọ si personas.
  8. Ekun ibi-ipo rẹ gbọdọ fi imọ-ọrọ blinking_led kun. Lati yan agbegbe ti o wa ni ipo nipa wiwa ipade ni Chip Planner, tẹ-ọtun orukọ agbegbe u_blinking_led ni window Logic Lock Region, lẹhinna tẹ Wa Node ➤ Wa ni Chip Planner.
  9.  Labẹ Awọn ijabọ ipin, tẹ lẹẹmeji Awọn ipin Apẹrẹ Ijabọ. Oluṣeto Chip ṣe afihan ati awọn koodu awọ agbegbe naa.

olusin 7. Chip Alakoso Node Location fun blinking_led
intel Agilex F-Series FPGA Development Board -blinking_ledNi omiiran, fifi awọn laini wọnyi kun si blinking_led.qsf ṣẹda awọn agbegbe wọnyi:
set_intance_assignment -name PARTITION pr_partition -to \ u_blinking_led -entity top
set_intance_assignment -orukọ PARTIAL_RECONFIGURATION_PARTITION LORI \ -to u_blinking_led -entity top
set_intance_assignment -orukọ PARTITION supr_partition -to u_top_counter \ -entity oke
set_intance_assignment -orukọ PARTIAL_RECONFIGURATION_PARTITION ON -to \ u_top_counter -entity oke
set_intance_assignment -orukọ PLACE_REGION "X166 Y199 X170 Y203" -to \ u_blinking_led
set_intance_assignment -orukọ RESERVE_PLACE_REGION ON -to u_blinking_led
ṣeto_intance_assignment -orukọ CORE_ONLY_PLACE_REGION ON -to u_blinking_led
set_intance_assignment -orukọ REGION_NAME pr_partition -to u_blinking_led
set_intance_assignment -orukọ ROUTE_REGION "X165 Y198 X171 Y204" -to \ u_blinking_led
ṣeto_intance_assignment -orukọ RESERVE_ROUTE_REGION PA -to u_blinking_led
set_intance_assignment -orukọ PLACE_REGION "X173 Y199 X177 Y203" -to \ u_top_counter
set_intance_assignment -orukọ RESERVE_PLACE_REGION LORI -to u_top_counter
set_intance_assignment -orukọ CORE_ONLY_PLACE_REGION ON -to u_top_counter
set_intance_assignment -orukọ REGION_NAME supr_partition -to u_top_counter
set_intance_assignment -orukọ ROUTE_REGION "X172 Y198 X178 Y204" -to \ u_top_counter
set_intance_assignment -orukọ RESERVE_ROUTE_REGION PA -to u_top_counter
1.5.4. Igbesẹ 4: Ṣetumo Eniyan

Apẹrẹ itọkasi yii ṣalaye awọn eniyan lọtọ mẹta fun ipin PR ẹyọkan, ati eniyan SUPR kan fun agbegbe SUPR. Tẹle awọn igbesẹ wọnyi lati ṣalaye ati ṣafikun awọn eniyan wọnyi ninu iṣẹ akanṣe rẹ. Ti o ba nlo Intel Quartus Prime Text Olootu, mu Fikun-un ṣiṣẹ file
si lọwọlọwọ ise agbese nigbati fifipamọ awọn files.

  1. Ṣẹda blinking_led_slow.sv tuntun, blinking_led_empty.sv, ati top_counter_fast.sv SystemVerilog files ninu rẹ ṣiṣẹ liana. Jẹrisi pe blinking_led.sv ti wa tẹlẹ ninu ilana iṣẹ.
  2.  Tẹ awọn akoonu wọnyi fun SystemVerilog files:
    Table 2. Reference Design Personas SystemVerilog
    File Oruko Apejuwe Koodu
    blinking_led_slow. sv Awọn LED seju losokepupo timescale 1 ps / 1 ps 'default_nettype ko si
    module blinking_led_slow // aago
    aago waya titẹ sii, atunto waya titẹ sii, okun waya titẹ sii [31:01 counter,
    // Awọn ifihan agbara iṣakoso fun okun LED ti o wu led_two_on,
    okun waya led_three_on localparam COUNTER_TAP = 27;
    reg led_meji_on_r; ẹsẹ mu_mẹta_on_r; fi led_two_on = led_two_on_r; fi led_three_on = led_three_on_r; nigbagbogbo_ff @( aago posige ) bẹrẹ led_two_on_r <= counter[COUNTER_TAP]; led_three_on_r <= counter[COUNTER_TAP]; opin endmodule
    blinking_led_ofo. sv Awọn LED duro ON timescale 1 ps / 1 ps 'default_nettype ko si module blinking_led_empty (// aago okun waya titẹ sii, atunto okun waya, okun titẹ sii [31:01 counter, // Awọn ifihan agbara iṣakoso fun LEC- okun waya led_two_on, okun waya ti o wu led_three_on
    tesiwaju…
    File Oruko Apejuwe Koodu
    // LED ti nṣiṣe lọwọ kekere assign led_two_on = l'IDO; fi led_three_on = 11b0; endmodule
    top_counter_fast.sv SUPR keji 'timescale 1 ps / 1 ps
    eniyan Thdefault_nettype kò module top_counter_fast
    // Awọn ifihan agbara iṣakoso fun awọn LEDs ti o wu led_one_on okun waya, okun waya [31:0] kika, // aago waya titẹ sii aago
    ) ; localparam COUNTER TAP = 23; rejimenti [31:0] count_d; sọtọ kika = count_d; fi led_one_on = ount_d[COUNTER_TAP]; nigbagbogbo_ff @( aago posiji ) bẹrẹ count_d <= count_d + 2; ipari
    .: module
  3.  Tẹ File ➤ Fipamọ Bi ati ṣafipamọ .sv files ninu atojọ ise agbese liana.

1.5.5. Igbesẹ 5: Ṣẹda Awọn Atunyẹwo
Ṣiṣan apẹrẹ PR nlo ẹya awọn atunyẹwo iṣẹ akanṣe ni sọfitiwia Intel Quartus Prime. Apẹrẹ akọkọ rẹ jẹ atunyẹwo ipilẹ, nibiti o ti ṣalaye awọn aala agbegbe aimi ati awọn agbegbe atunto lori FPGA. Lati atunyẹwo ipilẹ, o ṣẹda awọn atunyẹwo afikun. Awọn atunyẹwo wọnyi ni awọn imuse oriṣiriṣi fun awọn agbegbe PR. Sibẹsibẹ, gbogbo awọn atunyẹwo imuse PR lo ipo ipo-oke kanna ati awọn abajade ipa-ọna lati atunyẹwo ipilẹ. Lati ṣajọ apẹrẹ PR kan, o ṣẹda atunyẹwo imuse PR fun eniyan kọọkan. Ni afikun, o gbọdọ fi boya Iṣatunṣe Apakan – Ipilẹ tabi Atunto Apá – Persona Imuse iru atunto fun kọọkan ninu awọn atunto. Tabili ti o tẹle yii ṣe atokọ orukọ atunyẹwo ati iru atunyẹwo fun ọkọọkan awọn atunyẹwo naa. Atunyẹwo impl_blinking_led_supr_new.qsf jẹ imuse eniyan SUPR.
Table 3. Àtúnyẹwò Names ati Orisi

Orukọ Atunyẹwo Àtúnyẹwò Iru
blinking_led Atunto apakan - Ipilẹ
blinking_led_default Atunto apa kan – Persona imuse
blinking_led_slow Atunto apa kan – Persona imuse
blinking_led_ofo Atunto apa kan – Persona imuse
impl_blinking_led_supr_new Atunto apa kan – Persona imuse

1.5.5.1. Ṣiṣeto Atunyẹwo Ipilẹ
Tẹle awọn igbesẹ wọnyi lati ṣeto blinking_led bi atunyẹwo ipilẹ:

  1. Tẹ Project ➤ Awọn atunwo.
  2. Fun Iru Atunyẹwo, yan Atunto Apa kan – Ipilẹ.

intel Agilex F-Series FPGA Development Board - Awọn atunṣeIgbese yii ṣafikun atẹle naa si blinking_led.qsf:
##blinking_led.qsf ṣeto_ipinfunni_agbaye -orukọ REVISION_TYPE PR_BASE
1.5.5.2. Ṣiṣẹda Awọn atunṣe imuse
Tẹle awọn igbesẹ wọnyi lati ṣẹda awọn atunṣe imuse:

  1. Ninu apoti ibaraẹnisọrọ Awọn atunṣe, tẹ-lẹẹmeji < >.
  2. Ni orukọ Àtúnyẹwò, pato blinking_led_default ki o si yan blinking_led fun Da lori àtúnyẹwò.
  3. Fun iru Atunyẹwo, yan Atunto Apa kan – Imuṣe Persona.
  4. Mu Ṣeto naa ṣiṣẹ bi aṣayan atunyẹwo lọwọlọwọ.
  5. Tun awọn igbesẹ 2 si 5 ṣe lati ṣeto iru Atunyẹwo fun awọn atunyẹwo imuse miiran:
Orukọ Atunyẹwo Àtúnyẹwò Iru Da lori Revision
blinking_led_slow Atunto apa kan – Persona imuse blinking_led
blinking_led_ofo Atunto apa kan – Persona imuse blinking_led
impl_blinking_led_supr_new Atunto apa kan – Persona imuse blinking_led

Ṣe nọmba 8. Ṣiṣẹda Awọn atunṣe imuse

intel Agilex F-Series FPGA Development Board - Awọn atunṣe imuseKọọkan .qsf file bayi ni awọn iṣẹ iyansilẹ wọnyi:
set_global_assignment -orukọ REVISION_TYPE PR_IMPL
set_intance_assignment -name ENTITY_REBINDING place_holder -to u_top_counter
set_intance_assignment -name ENTITY_REBINDING place_holder -to u_blinking_led
1.5.6. Igbesẹ 6: Ṣe akopọ Atunyẹwo Ipilẹ
Tẹle awọn igbesẹ wọnyi lati ṣajọ atunyẹwo ipilẹ ati okeere aimi ati awọn agbegbe SUPR fun lilo nigbamii ni awọn atunyẹwo imuse fun awọn eniyan PR tuntun:

  1. Ṣeto blinking_led bi Atunyẹwo lọwọlọwọ ti ko ba ṣeto tẹlẹ.
  2. Ni Ferese Awọn ipin Apẹrẹ, tẹ (…) nitosi iwe apa ọtun ti o jinna ki o mu ki Ifiweranṣẹ Ipari Ikẹhin ṣiṣẹ File ọwọn. O tun le mu tabi yi aṣẹ ti awọn ọwọn pada.
  3. Lati ṣe okeere aworan ifaworanhan ikẹhin ti awọn ipin apẹrẹ imuse PR lẹhin ikojọpọ kọọkan, pato atẹle wọnyi fun Sitajasita Ikẹhin Ifiweranṣẹ File awọn aṣayan fun root ati SUPR ipin. Awọn .qdb files okeere si ise agbese liana nipa aiyipada.
    • root_partition — blinking_led_static.qdb
    • supr_partition — blinking_led_supr_partition_final.qdb
    olusin 9. Auto Export ni Design Partitions Windowintel Agilex F-Series FPGA Development Board - Awọn ipin WindowNi omiiran, awọn iṣẹ iyansilẹ .qsf wọnyi ṣe okeere awọn ipin ni adaaṣe lẹhin akojọpọ kọọkan:
    set_intance_assignment -orukọ EXPORT_PARTITION_SNAPSHOT_FINAL \ blinking_led_static.qdb -to | - oke nkan
    set_intance_assignment -orukọ EXPORT_PARTITION_SNAPSHOT_FINAL \ blinking_led_supr_partition_final.qdb -to u_top_counter \ -ohun oke
  4. Lati ṣajọ atunyẹwo ipilẹ blinking_led, tẹ Ṣiṣe ilana ➤ Bẹrẹ
    Iṣakojọpọ. Ni omiiran, o le lo aṣẹ atẹle lati ṣajọ atunyẹwo yii:
    quartus_sh –flow compile blinking_led -c blinking_led Lẹhin ikojọpọ aṣeyọri, atẹle naa files han ninu ilana ise agbese:
    • blinking_led.sof
    • blinking_led.pr_partition.rbf
    • blinking_led.supr_partition.rbf
    • blinking_led_static.qdb
    • blinking_led_supr_partition_final.qdb

1.5.7. Igbesẹ 7: Ṣeto Awọn atunwo imuse PR
O gbọdọ mura awọn atunyẹwo imuse PR ṣaaju ki o to le ṣe ina PR bitstream fun siseto ẹrọ. Eto yii pẹlu fifi agbegbe aimi kun .qdb file bi orisun file fun kọọkan imuse àtúnyẹwò. Ni afikun, o gbọdọ pato
nkan ti o baamu ti agbegbe PR. Tẹle awọn igbesẹ wọnyi lati ṣeto awọn atunyẹwo imuse PR:

  1.  Lati ṣeto atunyẹwo lọwọlọwọ, tẹ Project ➤ Awọn atunyẹwo, yan blinking_led_default bi orukọ Atunyẹwo, lẹhinna tẹ Ṣeto Lọwọlọwọ. Ni omiiran, o le yan atunyẹwo lọwọlọwọ lori ọpa irinṣẹ Intel Quartus Prime akọkọ.
  2. Lati jẹrisi orisun to pe fun atunyẹwo imuse yii, tẹ Project ➤ Fikun-un/Yọ kuro Files ni Project. Jẹrisi pe blinking_led.sv file han ninu file akojọ.intel Agilex F-Series FPGA Development Board - Ferese Awọn ipin 1
  3. Lati mọ daju awọn ti o tọ orisun file fun awọn atunṣe imuse, tẹ Project ➤ Fikun-un/Yọ kuro files ni Project, ki o si fi awọn wọnyi orisun files fun awọn atunṣe imuse. Ti o ba wa, yọ blinking_led.sv kuro ninu atokọ iṣẹ akanṣe files.
    Iimuse Àtúnyẹwò Name Orisun File
    blinking_led_ofo blinking_led_empty.sv
    blinking_led_slow blinking_led_slow.sv
  4. Ṣeto blinking_led_default bi Atunyẹwo lọwọlọwọ.
  5. Lati pato awọn .qdb file bi orisun fun root_partition, tẹ Awọn iṣẹ iyansilẹ ➤ Window Awọn ipin Apẹrẹ. Lẹẹmeji tẹ aaye data ipin File sẹẹli ki o si pato blinking_led_static.qdb file.
  6. Bakanna, pato blinking_led_supr_partition_final.qdb gẹgẹbi aaye data ipin File fun supr_partition.

    Olusin 10.intel Agilex F-Series FPGA Development Board - patoNi omiiran, lo awọn iṣẹ iyansilẹ .qsf wọnyi lati ṣe pato .qdb:
    set_intance_assignment -orukọ QDB_FILE_PARTITION \ blinking_led_static.qdb -to |
    set_intance_assignment -orukọ QDB_FILE_PARTITION \ blinking_led_supr_partition_final.qdb -to u_top_counter

  7. Ninu Ferese Awọn ipin Oniru, tẹ (…) nitosi iwe apa ọtun ti o jinna ki o mu iwe-itumọ Nkankan ṣiṣẹ.

  8.  Ninu sẹẹli Tun-abuda ohun elo, pato orukọ nkan tuntun fun ipin PR ti o n yipada ni atunyẹwo imuse lọwọlọwọ. Fun atunyẹwo imuse blinking_led_default, orukọ nkan naa jẹ blinking_led. Ni idi eyi, o n ṣe atunṣe apẹẹrẹ u_blinking_led lati ipilẹ atunyẹwo ipilẹ pẹlu nkan tuntun blinking_led. Fun awọn atunyẹwo imuse miiran, tọka si tabili atẹle:

    Àtúnyẹwò Nkankan Tun-abuda Iye
    blinking_led_slow blinking_led_slow
    blinking_led_ofo blinking_led_ofo

    olusin 11. Nkankan Rebindingintel Agilex F-Series FPGA Development Board - RebindingNi omiiran, o le lo awọn ila wọnyi ni .qsf atunyẹwo kọọkan lati ṣeto awọn iṣẹ iyansilẹ:
    ##blinking_led_default.qsf
    set_intance_assignment -orukọ ENTITY_REBINDING blinking_led \ -to u_blinking_led
    # # pawalara_led_slow.qsf
    set_intance_assignment -orukọ ENTITY_REBINDING blinking_led_slow \ -to u_blinking_led
    # # pawalara_led_empty.qsf
    set_intance_assignment -orukọ ENTITY_REBINDING blinking_led_empty \ -to u_blinking_led

  9. Pa ọrọ ibi_holder rẹ kuro ni sẹẹli Tun-abuda ohun elo fun supr_partition.
  10. Lati ṣajọ apẹrẹ, tẹ Ṣiṣe-ṣiṣe ➤ Bẹrẹ Iṣakojọpọ. Ni omiiran, lo aṣẹ atẹle lati ṣajọ iṣẹ akanṣe yii: quartus_sh –flow compile blinking_led –c blinking_led_default
  11. Tun awọn igbesẹ 4 si 11 ṣe lati mura ati ṣajọ awọn atunyẹwo imuse blinking_led_slow ati blinking_led_empty.

1.5.8. Igbesẹ 8: Yi Iyipada SUPR pada
Lati yi iṣẹ-ṣiṣe ti ọgbọn pada laarin ipin SUPR, o gbọdọ yi orisun ipin SUPR pada. Pari awọn igbesẹ wọnyi lati rọpo apẹẹrẹ u_top_counter ni ipin SUPR pẹlu nkan top_counter_fast.

  1. Lati ṣeto atunyẹwo imuse SUPR bi lọwọlọwọ, tẹ Project ➤ Awọn atunyẹwo ati ṣeto impl_blinking_led_supr_new bi atunyẹwo lọwọlọwọ, tabi yan
    àtúnyẹwò lori Intel Quartus Prime bọtini irinṣẹ akọkọ.
  2. Lati mọ daju awọn ti o tọ orisun file fun atunyẹwo imuse, tẹ Project ➤
    Fikun-un/Yọ kuro files ni Project, ati rii daju pe top_counter_fast.sv ni orisun fun impl_blinking_led_supr_new imuse àtúnyẹwò. Ti o ba wa, yọ top_counter.sv kuro ninu atokọ iṣẹ akanṣe files.intel Agilex F-Series FPGA Development Board - iyansilẹ
  3. Lati pato awọn .qdb file ni nkan ṣe pẹlu ipin root, tẹ Awọn iṣẹ iyansilẹ ➤ Ferese Awọn ipin Apẹrẹ, ati lẹhinna tẹ-lẹẹmeji aaye data ipin. File sẹẹli lati pato blinking_led_static.qdb.
    Ni omiiran, lo aṣẹ atẹle lati fi eyi ranṣẹ file: set_intance_assignment -orukọ QDB_FILE_PARTITION \ blinking_led_static.qdb -to |
  4. Ninu sẹẹli Tun-abuda ohun elo fun pr_partition, pato orukọ nkan ti o yẹ. Fun eyi example, pato awọn blinking_led_empty nkankan. Ni idi eyi, o n ṣe atunṣe apẹẹrẹ u_blinking_led lati ipilẹ atunyẹwo ipilẹ pẹlu nkan tuntun linking_led_empty. Laini atẹle wa bayi ni .qsf:
    ##impl_blinking_led_supr_new.qsf ṣeto_apejuwe_ipinfunni -orukọ ENTITY_REBINDING pawalara_led_ofo \ -to u_blinking_led
  5. Ninu sẹẹli Tun-abuda ohun elo fun supr_partition, pato nkan ti oke_counter_fast. top_counter_fast ni orukọ ti nkan aimi ti o rọpo u_top_counter nigbati o ba pari SUPR.intel Agilex F-Series FPGA Development Board - SUPR##impl_blinking_led_supr_new.qsf ṣeto_ipinfunni_ipinfunni -orukọ ENTITY_REBINDING top_counter_fast \ -to u_top_counter
  6. Lati ṣajọ apẹrẹ, tẹ Ṣiṣe-ṣiṣe ➤ Bẹrẹ Iṣakojọpọ. Ni omiiran, lo aṣẹ atẹle lati ṣajọ atunyẹwo iṣẹ akanṣe yii: quartus_sh –flow compile blinking_led –c \ impl_blinking_led_supr_new

1.5.9. Igbesẹ 9: Ṣeto Igbimọ naa
Tẹle awọn igbesẹ wọnyi lati sopọ ati ṣe eto igbimọ idagbasoke Intel Agilex F-Series FPGA.

  1. So ipese agbara pọ si igbimọ idagbasoke Intel Agilex F-Series FPGA.
  2. So okun USB pọ laarin ibudo USB PC rẹ ati ohun elo siseto USB lori igbimọ idagbasoke.
  3. Ṣii sọfitiwia Intel Quartus Prime, lẹhinna tẹ Awọn irinṣẹ ➤ Programmer. Tọkasi Eto Eto Igbimọ Idagbasoke.
  4. Ni awọn Programmer, tẹ Hardware Setup, ati ki o si yan USB-Blaster.
  5. Tẹ Iwari Aifọwọyi, lẹhinna yan ẹrọ AGFB014R24B.
  6.  Tẹ O DARA. Sọfitiwia Intel Quartus Prime ṣe iwari ati ṣe imudojuiwọn Oluṣeto pẹlu awọn ẹrọ FPGA mẹta lori igbimọ.
  7.  Yan ẹrọ AGFB014R24B, tẹ Yipada File, ati fifuye blinking_led_default.sof file.
  8. Mu Eto ṣiṣẹ/Ṣeto fun blinking_led_default.sof file.
  9. Tẹ Bẹrẹ ati duro fun ọpa ilọsiwaju lati de ọdọ 100%.
  10.  Kiyesi awọn LED lori ọkọ si pawalara.
  11. Lati ṣe eto agbegbe PR nikan, tẹ-ọtun blinking_led_default.sof file ninu awọn Programmer ki o si tẹ Fi PR siseto File. Yan blinking_led_slow.pr_partition.rbf file.
  12. Pa Eto/Ṣeto fun blinking_led_default.sof file.
  13.  Mu Eto ṣiṣẹ/Ṣeto fun blinking_led_slow.pr_partition.rbf file, ati ki o si tẹ Bẹrẹ. Lori igbimọ, ṣe akiyesi LED[0] ati LED[1] tẹsiwaju lati paju. Nigbati ọpa ilọsiwaju ba de 100%, LED [2] ati LED [3] n parẹ losokepupo.
  14. Lati tun eto agbegbe PR ṣe, tẹ-ọtun .rbf file ninu awọn Programmer, ati ki o si tẹ Change PR Programing File.
  15.  Yan .rbf files fun awọn miiran meji personas lati ma kiyesi ihuwasi lori awọn ọkọ. Ikojọpọ blinking_led_default.pr_partition.rbf file fa awọn LED lati seju ni atilẹba igbohunsafẹfẹ, ati ikojọpọ blinking_led_empty.pr_partition.rbf file fa awọn LED duro ON. 17. Lati yi awọn kannaa SUPR pada, tun igbese 7 loke lati yan awọn impl_blinking_led_supr_new.sof. Lẹhin iyipada eyi file, led [0:1] ni bayi n paju ni iwọn iyara ju ti iṣaaju lọ. PR .rbf miiran files tun wa ni ibamu pẹlu titun .sof.
    Akiyesi: Apejọ ṣe ipilẹṣẹ .rbf file fun agbegbe SUPR. Sibẹsibẹ, o yẹ ki o ko lo eyi file lati tun ṣe FPGA ni akoko asiko nitori pe ipin SUPR ko ṣe afara afara didi, oluṣakoso agbegbe PR, ati ọgbọn miiran ninu eto gbogbogbo. Nigbati o ba ṣe awọn ayipada si kannaa ipin SUPR, o gbọdọ tun ṣe .sof ni kikun file lati akopọ imuse imuse SUPR.

olusin 12. Siseto a Development Board
intel Agilex F-Series FPGA Development Board - Board1.5.9.1. Laasigbotitusita PR Awọn aṣiṣe siseto
Aridaju iṣeto to dara ti Intel Quartus Prime Programmer ati ohun elo ti o sopọ ṣe iranlọwọ lati yago fun awọn aṣiṣe eyikeyi lakoko siseto PR.
Ti o ba koju eyikeyi awọn aṣiṣe siseto PR, tọka si “Laasigbotitusita PR Awọn aṣiṣe siseto” ni Itọsọna olumulo Intel Quartus Prime Pro Edition: Atunto apakan fun awọn imọran laasigbotitusita-igbesẹ.
Alaye ti o jọmọ

Laasigbotitusita PR Awọn aṣiṣe siseto

1.5.10. Iyipada ipin SUPR
O le ṣe atunṣe ipin SUPR ti o wa tẹlẹ. Lẹhin iyipada ipin SUPR, o gbọdọ ṣajọ rẹ, ṣe ipilẹṣẹ .sof file, ati eto igbimọ, lai ṣe akopọ awọn eniyan miiran. Fun example, tẹle awọn igbesẹ lati yi top_counter_fast.sv module lati ka yiyara:

  1. Ṣeto impl_blinking_led_supr_new gẹgẹbi atunyẹwo lọwọlọwọ.
  2.  Ninu oke_counter_fast.sv file, rọpo count_d + 2 gbólóhùn pẹlu count_d + 4.
  3.  Ṣiṣe awọn aṣẹ wọnyi lati tun-ṣiṣẹpọ bulọọki SUPR ati ṣe ipilẹṣẹ .sof tuntun file: quartus_sh –flow compile blinking_led \ -c impl_blinking_led_supr_new
    Abajade .sof bayi ni agbegbe SUPR tuntun, o si nlo blinking_led fun aiyipada (agbara-lori) eniyan.

1.6. Iwe itan Àtúnyẹwò ti AN 987: Aimi Update Apa kan atunto Tutorial History Àtúnyẹwò

Ẹya Iwe aṣẹ Intel Quartus NOMBA Version Awọn iyipada
2022.10.24 22. Itusilẹ akọkọ ti iwe-ipamọ naa.

Imudojuiwọn fun Intel® Quartus®Prime Design Suite: 22.3

Awọn idahun si Awọn FAQ ti o ga julọ:

Fi esi ranṣẹ

Q Kini isọdọtun apa kan imudojuiwọn aimi

Imudojuiwọn Aimi Atunto apakan ni oju-iwe 3

Q Kini MO nilo fun ikẹkọ yii?

Awọn ibeere Ikẹkọ ni oju-iwe 3

Q Nibo ni MO le gba apẹrẹ itọkasi?

A Download Reference Design Files loju iwe 5

Q Bawo ni MO ṣe ṣẹda apẹrẹ SUPR kan?

Ririn Apẹrẹ Itọkasi ni oju-iwe 6

Q Kini eniyan PR kan?

Ṣe alaye Awọn eniyan ni oju-iwe 10

Q Bawo ni MO ṣe yi ọgbọn SUPR pada? Yipada Ilana SUPR ni oju-iwe 16

Yipada Ilana SUPR ni oju-iwe 16

Q Bawo ni MO ṣe ṣe eto igbimọ naa?

Eto Igbimọ ni oju-iwe 18

Q Kini awọn ọran ti a mọ PR ati awọn idiwọn?

A Intel FPGA Support Forums: PR

intel Agilex F-Series FPGA Development Board - Aami Idajọ Ayelujara
intel Agilex F-Series FPGA Development Board - Aami 154 Fi esi ranṣẹ

ID: 749443
AN-987
Ẹya: 2022.10.24

Awọn iwe aṣẹ / Awọn orisun

intel Agilex F-Series FPGA Development Board [pdf] Itọsọna olumulo
Agilex F-Series, Agilex F-Series FPGA Development Board, FPGA Development Board, Igbimọ Idagbasoke, Igbimọ

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