AN 987: Sashe na Sabuntawa A tsaye
Koyarwar sake tsarawa

Koyarwar Sake Tsara Sabunta Tsayi don Intel® ™ Agilex F-Series FPGA Board Development

Wannan bayanin kula na aikace-aikacen yana nuna daidaitaccen sabuntawa na sake daidaitawa (SUPR) akan Intel ® F-Series FPGA Development Board. Sake fasalin ɓarna (PR) yana ba ku damar sake saita wani yanki na Intel FPGA a hankali, yayin da sauran FPGA ke ci gaba da aiki. PR yana aiwatar da mutane da yawa a cikin wani yanki a cikin ƙirar ku, ba tare da tasirin aiki a yankunan da ke wajen wannan yanki ba. Wannan hanya tana ba da advan mai zuwatages a cikin tsarin da ayyuka masu yawa lokaci-raba albarkatun FPGA iri ɗaya:

• Yana ba da damar sake saita lokacin gudu
• Yana ƙara ƙira scalability
• Yana rage lokacin ƙarancin tsarin
• Yana goyan bayan ayyukan haɓaka lokaci mai ƙarfi a cikin ƙira
• Yana rage farashi da amfani da wutar lantarki ta hanyar ingantaccen amfani da sararin allo

Menene Sake daidaita Sashe na Sabuntawa Static?

A cikin PR na al'ada, kowane canji zuwa yanki na tsaye yana buƙatar sake tattarawa na kowane mutum. Koyaya, tare da SUPR zaku iya ayyana yanki na musamman wanda ke ba da damar canji, ba tare da buƙatar sake tattara mutane ba. Wannan dabarar tana da amfani ga wani yanki na ƙirar da ƙila za ku so ku canza don rage haɗarin, amma hakan baya buƙatar sake saita lokacin aiki.

1.1. Bukatun Koyarwa
Wannan koyawa tana buƙatar abubuwa masu zuwa:

• Sanin asali tare da kwararar aiwatarwa da aikin Intel Quartus® Prime Pro FPGA files.
•  Shigar da Intel Quartus Prime Pro Edition 22.3, tare da tallafin na'urar Intel Agilex.
• Don aiwatar da FPGA, a JTAG haɗi tare da kwamitin haɓakawa na Intel Agilex F-Series FPGA akan benci.
• Zazzage Tsarin Magana Files. Bayanai masu alaƙa
• Jagoran Mai Amfani na Sake Tsari Sashe
• Koyawawan Sake Tsara Jumla
• Horon Sake Tsara Sashe na Kan layi

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
ISO 9001: 2015 Rajista
1.2. Reference Design Overview
Wannan ƙirar ƙira ta ƙunshi ƙira ɗaya, 32-bit. A matakin hukumar, ƙirar tana haɗa agogo zuwa tushen 50MHz, sannan ta haɗa fitarwa zuwa LEDs huɗu akan allon. Zaɓin abin da ake fitarwa daga maƙallan ƙididdiga, a cikin takamaiman jeri, yana sa LEDs su yi kiftawa a takamaiman mitar. Samfurin saman_counter shine yankin SUPR.
Hoto 1. Zane-zanen Magana

1.3. Yankin Sabuntawa A tsayeview
Hoto na gaba yana nuna zanen toshe don ƙirar PR wanda ya haɗa da yankin SUPR. Block A shine babban yanki mai tsayi. Block B shine yankin SUPR. Block C shine ɓangaren PR.
Hoto 2. Tsarin PR tare da yankin SUPR

• Babban Yanki na Tsaya—ya ƙunshi dabaru na ƙira wanda baya canzawa. Canza wannan yanki yana buƙatar sake tattara duk waɗanda ke da alaƙa. Yankin a tsaye ya haɗa da ɓangaren ƙirar da baya canzawa ga kowane mutum. Wannan yanki na iya haɗawa da keɓaɓɓun kayan aikin na'ura. Dole ne ku yi rajistar duk hanyar sadarwa tsakanin sassan SUPR da PR a cikin yanki na tsaye. Wannan buƙatun yana taimakawa don tabbatar da lokacin rufewa ga kowane mutum, dangane da yanki na tsaye.
• Yankin B SUPR — ya ƙunshi ainihin dabaru-kawai waɗanda ƙila za su iya canzawa don rage haɗarin, amma baya buƙatar sake saita lokacin aiki. Yankin SUPR yana da buƙatu iri ɗaya da ƙuntatawa kamar ɓangaren PR. Bangaren SUPR zai iya ƙunsar ainihin albarkatu kawai. Don haka, sashin SUPR dole ne ya zama ɓangaren yara na babban matakin tushen ɓangaren wanda ya ƙunshi ƙirar ƙira da agogo. Canza yankin SUPR yana samar da Abun SRAM File (.sof) wanda ya dace da duk abin da aka haɗa Raw Binary File (rbf) files don PR partition C.
• C PR Partition — ya ƙunshi dabaru na sabani wanda zaku iya sake tsarawa a lokacin aiki tare da kowane dabarar ƙira wacce ta dace kuma ta cimma lokacin rufewa yayin haɗawa.

1.4. Zazzage Tsarin Magana Files
Ana samun koyawa na sake fasalin fasalin a wuri mai zuwa: https://github.com/intel/fpga-partial-reconfig
Don sauke koyawa:

1. Danna Clone ko zazzagewa.
2. Danna Zazzage ZIP. Cire fpga-partial-reconfig-master.zip file.
3. Kewaya zuwa koyawa /agilex_pcie_devkit_blinking_led_supr babban fayil don samun damar ƙirar ƙira.
   Babban fayil ɗin lebur ya ƙunshi abubuwa masu zuwa files:
   Tebur 1. Tsarin Magana Files

File Suna	Bayani
saman. sv	Babban matakin file dauke da lebur aiwatar da zane. Wannan ƙirar tana ɗaukar ɓangaren ɓoyayyiyar blinking_led da top_counter module.
t op_counter . sv	Babban matakin 32-bit counter wanda ke sarrafa LED [1] kai tsaye. Fitarwa mai rijista na counter yana sarrafa LED [0], kuma yana ba da ikon LED [2] da LED [3] ta hanyar ƙirar haske_led.
kyaftawar ido. sdc	Yana bayyana ƙayyadaddun ƙayyadaddun lokaci don aikin.
kyaftawar ido. sv	A cikin wannan koyawa, kun canza wannan ƙirar zuwa ɓangaren PR na iyaye. Module ɗin yana karɓar fitarwa mai rijista na top_counter module, wanda ke sarrafa LED [2] da LED [3].
kyaftawa_led.qpf	Intel Quartus Prime aikin file dauke da jerin duk bita-da-kulli a cikin aikin.
kyaftawar ido. qs f	Intel Quartus Prime saituna file dauke da ayyuka da saituna don aikin.

Lura: Babban fayil ɗin supr ya ƙunshi cikakken saitin files ka ƙirƙiri ta amfani da wannan aikace-aikacen bayanin kula. Duba waɗannan files a kowane lokaci yayin tafiya.
1.5. Tafiyar Tsara Nasiha
Matakan da ke biyowa suna bayyana aiwatar da SUPR tare da ƙirar lebur:

• Mataki 1: Farawa
• Mataki 2: Ƙirƙiri Ƙirƙirar Ƙira
• Mataki na 3: Rarraba Wuraren Wuta da Yankuna
• Mataki na 4: ayyana Mutane
• Mataki 5: Ƙirƙiri Bita
• Mataki 6: Haɗa Tushen Bita
• Mataki 7: Saita Bita Bita na Ayyukan PR
• Mataki 8: Canja dabarar SUPR
• Mataki 9: Shirya Hukumar

Hoto 3. Gudun Rubutun SUPR

1.5.1. Mataki 1: Farawa
Don kwafi ƙirar tunani files zuwa yanayin aikin ku kuma ku haɗa ƙirar lebur ɗin blinking_led:

1. Kafin ka fara, zazzage Tsarin Magana Files a shafi na 5.
2. Ƙirƙiri littafin adireshi agilex_pcie_devkit_blinking_led_supr a cikin mahallin aikin ku.
3. Kwafi koyawa da aka sauke/agilex_pcie_devkit_blinking_led/lebur babban fayil zuwa agilex_pcie_devkit_blinking_led_supr directory.
4. A cikin Intel Quartus Prime Pro Edition software, danna File ➤ Buɗe Project kuma buɗe /flat/blinking_led.qpf.
5. Don haɗa ƙirar tushe, danna Sarrafa ➤ Fara Tari. Rahoton Analyzer na lokaci yana buɗewa ta atomatik lokacin da aka gama haɗawa. Kuna iya rufe Analyzer na lokaci a yanzu.

1.5.2. Mataki 2: Ƙirƙiri Ƙirƙirar Ƙira
Ƙirƙiri ɓangarori na ƙira don kowane yanki da kuke son sake fasalin wani yanki. Kuna iya ƙirƙirar kowane adadin ɓangarori masu zaman kansu ko yankuna na PR a cikin aikin ku. Bi waɗannan matakan don ƙirƙirar sassan ƙira don misalin u_blinking_led azaman ɓangaren PR, da misalin u_top_counter azaman yankin SUPR:

1. Danna dama-dan misali u_blinking_led a cikin Project Navigator kuma danna Partition Design
   ➤ Reconfigurable. Alamar ɓangaren ƙira yana bayyana kusa da kowane misali wanda aka saita azaman bangare.
   Hoto 4. Ƙirƙirar Ƙungiyoyin Ƙira
2. Maimaita mataki na 1 don ƙirƙirar bangare don misalin u_top_counter.
3. Danna Ayyuka ➤ Tagan Rarraba Tsara. Tagar tana nuna duk ɓangarorin ƙira a cikin aikin.
   Hoto 5. Tagar Rarraba Tsara
   
4. Danna tantanin halitta sunan bangare na blinking_led sau biyu don sake suna zuwa pr_partition. Hakazalika, sake suna ɓangaren saman_counter zuwa supr_partition.
   A madadin, ƙara waɗannan layukan zuwa blinking_led.qsf yana ƙirƙirar waɗannan ɓangarori:
   saitin_intance_assignment -name PARTITION pr_partition \ -to u_blinking_led -entity top
   saitin_intance_assignment -suna PARTIAL_RECONFIGURATION_PARTITION ON \ -zuwa babban abun ciki_blinking_leed
   saitin_intance_assignment -suna PARTITION supr_partition \ -to u_top_counter - saman mahallin
   saitin_intance_assignment -suna PARTIAL_RECONFIGURATION_PARTITION ON \ -zuwa babban_counter - saman mahaɗan

1.5.3. Mataki na 3: Rarraba Wuraren Wuta da Yankuna
Ga kowane bita na tushe da kuka ƙirƙira, Mai tarawa yana amfani da rabon yanki na PR don sanya ainihin ainihin mutum a cikin yankin da aka keɓe. Bi waɗannan matakan don ganowa da sanya yankin PR a cikin tsarin bene na na'urar don sake fasalin tushe:

1. A cikin shafin Maɓallin Maɓalli na Project, danna-dama misali u_blinking_led, sannan danna Logic Lock Region ➤ Ƙirƙiri Sabon Logic Lock Region. Yankin yana bayyana a cikin taga Logic Lock Regions.
2. Ƙayyade Faɗin yanki na 5 da Tsawo na 5.
3. Ƙayyade daidaitawar yankin jeri don u_blinking_led a cikin ginshiƙi na asali. Asalin ya yi daidai da ƙananan kusurwar hagu na yankin. Ƙayyade Asalin azaman X166_Y199. Mai tarawa yana ƙididdige (X170 Y203) azaman haɗin kai na sama-dama.
4. Kunna keɓancewa da zaɓuɓɓukan Mahimmanci-kawai don yankin.
5. Danna Zaɓin Yankin Hanyar Sau biyu. Akwatin maganganu na Logic Lock Routing Region ya bayyana.
6. Don Nau'in Roting, zaɓi Kafaffen tare da faɗaɗawa. Wannan zaɓin yana sanya tsayin Faɗawa ta atomatik.
7. Maimaita matakan da suka gabata don rarraba albarkatun masu zuwa don ɓangaren u_top_counter:
   • Tsawo—5
   • Nisa—5
   • Asalin—X173_Y199
   • Yanki na Rarraba- Kafaffen tare da faɗaɗa tare da Tsawon Fadada ɗaya.
   • Ajiye- Kunnawa
   • Mabuɗin-Kawai-A kunne
   Hoto 6. Tagar Yankunan Logic Logic
   Lura: Dole ne yankin da ake tuƙi ya zama ya fi yankin da aka sanyawa girma, don samar da ƙarin sassauci ga s ɗin na'urar tattara bayanai.tage, lokacin da Compiler ya bi hanyoyi daban-daban.
8. Dole ne yankin da aka sanya ku ya ƙunshi ma'anar blinking_led. Don zaɓar yankin sanyawa ta hanyar gano kumburi a cikin Chip Planner, danna dama-danna sunan yankin u_blinking_led a cikin taga Logic Lock Regions, sannan danna Nemo Node ➤ Gano wuri a cikin Tsarin Chip.
9.  Ƙarƙashin Rahoton Rarraba, danna Rahoto Ƙirar Ƙira sau biyu. Chip Planner yana ba da haske da lambobi a yankin.

Hoto 7. Wurin Node Mai Tsara Chip don blinking_led
A madadin, ƙara waɗannan layukan zuwa blinking_led.qsf yana haifar da waɗannan yankuna:
saita_intance_assignment -name PARTITION pr_partition -zuwa \ u_blinking_led - saman mahallin
saitin_intance_assignment -suna PARTIAL_RECONFIGURATION_PARTITION ON \ -zuwa babban abun ciki_blinking_leed
saita_intance_assignment -suna PARTITION supr_partition -zuwa u_top_counter - saman mahallin
saitin_intance_assignment -suna PARTIAL_RECONFIGURATION_PARTITION ON -zuwa sama_ saman_counter
saitin_intance_assignment -name PLACE_REGION "X166 Y199 X170 Y203" -to \ u_blinking_led
saitin_misali -suna RESERVE_PLACE_REGION ON -zuwa ja-gora
saitin_misali -suna CORE_ONLY_PLACE_REGION ON -zuwa_blinking_led
saita_intance_assignment -name REGION_NAME pr_partition -zuwa u_blinking_led
set_intance_assignment -name ROUTE_REGION "X165 Y198 X171 Y204" -zuwa \ u_blinking_led
saitin_intance_assignment -name RESERVE_ROUTE_REGION KASHE -to u_blinking_led
saitin_intance_assignment -suna PLACE_REGION "X173 Y199 X177 Y203" -to \ u_top_counter
saitin_misali -suna RESERVE_PLACE_REGION ON -zuwa sama_counter
saitin_misali -suna CORE_ONLY_PLACE_REGION ON -zuwa babban_counter
saita_intance_assignment -name REGION_NAME supr_partition -zuwa u_top_counter
set_intance_assignment -name ROUTE_REGION "X172 Y198 X178 Y204" -zuwa \ u_top_counter
saitin_intance_assignment -suna RESERVE_ROUTE_REGION KASHE -zuwa sama_counter
1.5.4. Mataki na 4: ayyana Mutane

Wannan ƙirar ƙira tana ayyana mutane daban-daban guda uku don ɓangaren PR guda ɗaya, da mutum ɗaya SUPR don yankin SUPR. Bi waɗannan matakan don ayyana kuma haɗa waɗannan mutane a cikin aikin ku. Idan amfani da Intel Quartus Prime Text Editan, musaki Ƙara file
zuwa aikin na yanzu lokacin adanawa files.

1. Ƙirƙiri sabon blinking_led_slow.sv, blinking_led_empty.sv, da top_counter_fast.sv SystemVerilog files a cikin kundin aiki. Tabbatar da cewa blinking_led.sv ya riga ya kasance a cikin kundin aiki.
2.  Shigar da abubuwan ciki masu zuwa don SystemVerilog files:
   Table 2. Reference Design Personas SystemVerilog
   

   File Suna	Bayani	Lambar
   kyaftawa_led_slow. sv	LEDs suna kyaftawa a hankali	timescale 1 ps / 1 ps 'default_nettype babu module blinking_led_slow // agogo agogon shigarwar waya, sake saitin waya na shigar, waya shigar [31:01 counter, // Alamun sarrafawa don LEDs fitarwa waya led_two_on, waya fitarwa led_three_on localparam COUNTER_TAP = 27; reg led_biyu_on_r; kafa ya jagoranci_uku_on_r; sanya led_biyu_on = led_biyu_on_r; sanya led_uku_on = jagoranci_uku_on_r; ko da yaushe_ff @ (agogon da aka tsara) fara led_two_on_r <= counter[COUNTER_TAP]; led_three_on_r <= counter[COUNTER_TAP]; karshen endmodule
   kyaftawa_led_ba komai. sv	LEDs suna tsayawa ON	timescale 1 ps / 1 ps 'default_nettype babu wani module blinking_led_empty (// agogon shigarwar agogo, sake saitin waya, wayar shigarwa [31: 01 counter, // Sigina na sarrafawa na LEC- fitarwa led_two_on, waya fitarwa led_three_on
   ci gaba…

   File Suna	Bayani	Lambar
   		// LED yana aiki low assign led_two_on = l'IDO; sanya led_uku_on = 11b0; endmodule
   babban_counter_fast.sv	SUPR ta biyu	'Lokaci 1 ps / 1 ps
   	mutum	Thdefault_nettype babu wani module top_counter_fast
   		// Alamun sarrafawa don LEDs fitarwa wayoyi led_one_on, waya fitarwa [31:0] ƙidaya, // agogon shigar da agogo
   		) ; localparam COUNTER TAP = 23; misali [31:0] kirga_d; sanya ƙidayar = ƙidaya_d; sanya led_one_on = ount_d [COUNTER_TAP]; ko da yaushe_ff @ (agogon saƙo) fara count_d <= count_d + 2; karshen
   		.:module

3.  Danna File ➤ Ajiye As kuma ajiye .sv files a cikin kundin tsarin aiki na yanzu.

1.5.5. Mataki 5: Ƙirƙiri Bita
Gudun ƙira na PR yana amfani da fasalin fasalin aikin a cikin Intel Quartus Prime software. Ƙirar ku ta farko ita ce bita ta tushe, inda kuka ayyana iyakoki na yanki a tsaye da yankunan da za a sake daidaita su akan FPGA. Daga bita na tushe, kuna ƙirƙirar ƙarin bita. Waɗannan sake dubawa sun ƙunshi aiwatarwa daban-daban don yankunan PR. Koyaya, duk bita na aiwatar da PR suna amfani da jeri na sama-sama da sakamako iri ɗaya daga bita na tushe. Don haɗa ƙirar PR, kuna ƙirƙiri bita na aiwatar da PR ga kowane mutum. Bugu da kari, dole ne ka sanya ko dai Tsarin Sake Tsari - Tushe ko Sake Tsari na Sashe - Nau'in Bita na Aiwatar da Persona na kowane bita. Tebur mai zuwa yana lissafin sunan bita da nau'in bita ga kowane bita. Bita na impl_blinking_led_supr_new.qsf shine aiwatar da mutum na SUPR.
Tebur 3. Sunaye da Nau'ukan Gyarawa

Sunan Bita	Nau'in Bita
kyaftawar ido	Sake fasalin ɓangarori - Tushe
blinking_led_default	Sake fasalin wani ɓangare - Aiwatar da Mutum
kyaftawa_led_slow	Sake fasalin wani ɓangare - Aiwatar da Mutum
kyaftawa_led_ba komai	Sake fasalin wani ɓangare - Aiwatar da Mutum
impl_blinking_led_supr_new	Sake fasalin wani ɓangare - Aiwatar da Mutum

1.5.5.1. Kafa Tushen Bita
Bi waɗannan matakan don saita blinking_led azaman tushen bita:

1. Danna Project ➤ Bita.
2. Don Nau'in Bita, zaɓi Sake saitin Sashe - Tushe.

Wannan matakin yana ƙara waɗannan abubuwan zuwa blinking_led.qsf:
##blinking_led.qsf saita_aikin_duniya -suna REVISION_TYPE PR_BASE
1.5.5.2. Ƙirƙirar Bita Bita
Bi waɗannan matakan don ƙirƙirar gyare-gyaren aiwatarwa:

1. A cikin akwatin tattaunawa na Revisions, danna sau biyu < >.
2. A cikin sunan bita, saka blinking_led_default kuma zaɓi blinking_led don Bisa bita.
3. Don nau'in Bita, zaɓi Sake fasalin Sashe - Aiwatar da Mutum.
4. Kashe Saitin azaman zaɓi na bita na yanzu.
5. Maimaita matakai na 2 zuwa 5 don saita nau'in Bita don sauran bitar aiwatarwa:

Sunan Bita	Nau'in Bita	Dangane da Revision
kyaftawa_led_slow	Sake fasalin wani ɓangare - Aiwatar da Mutum	kyaftawar ido
kyaftawa_led_ba komai	Sake fasalin wani ɓangare - Aiwatar da Mutum	kyaftawar ido
impl_blinking_led_supr_new	Sake fasalin wani ɓangare - Aiwatar da Mutum	kyaftawar ido

Hoto 8. Ƙirƙirar Bita Bita

Kowane .qsf file yanzu ya ƙunshi aiki mai zuwa:
saitin_aikin_duniya -suna REVISION_TYPE PR_IMPL
saitin_intance_assignment -suna ENTITY_REBINDING mai riƙe_wuri -zuwa u_top_counter
saitin_intance_assignment -suna ENTITY_REBINDING mai riƙe wuri_zuwa u_blinking_led
1.5.6. Mataki 6: Haɗa Tushen Bita
Bi waɗannan matakan don tattara tushen bita da fitar da a tsaye da SUPR yankuna don amfani daga baya wajen aiwatar da bita ga sabbin mutanen PR:

1. Saita blinking_led a matsayin Bita na Yanzu idan ba a riga an saita shi ba.
2. A cikin Tagar Ƙirar Ƙira, danna (...) kusa da ginshiƙi mafi nisa kuma kunna Fitar da Ƙarshe na Ƙarshe. File shafi. Hakanan zaka iya kashe ko canza tsarin ginshiƙai.
3. Don fitarwa ta atomatik hoto na ƙarshe na ɓangarori na aiwatar da PR bayan kowane haɗawa, ƙididdige masu zuwa don Fitar da Ƙarshe File zažužžukan ga tushen da SUPR partitions. Da .qdb files fitarwa zuwa kundin aikin ta tsohuwa.
   • tushen_partition — blinking_led_static.qdb
   • supr_partition — blinking_led_supr_partition_final.qdb
   Hoto 9. Fitarwa ta atomatik a Tagar Rarraba ƘiraA madadin, ayyuka na .qsf masu zuwa suna fitar da ɓangarori ta atomatik bayan kowace haɗawa:
   saitin_intance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \ blinking_led_static.qdb -to | - saman mahallin
   set_intance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \ blinking_led_supr_partition_final.qdb -to u_top_counter \ -entity top
4. Don haɗa bita na tushe mai ƙyalli, danna Sarrafa ➤ Fara
   Tari A madadin, zaku iya amfani da umarni mai zuwa don haɗa wannan bita:
   quartus_sh –flow compile blinking_led -c blinking_led Bayan an yi nasarar haɗawa, mai zuwa files bayyana a cikin kundin tsarin aiki:
   • kyaftawa_led.sof
   • blinking_led.pr_partition.rbf
   • blinking_led.supr_partition.rbf
   • blinking_led_static.qdb
   • blinking_led_supr_partition_final.qdb

1.5.7. Mataki na 7: Saita Bita Bita na Ayyukan PR
Dole ne ku shirya bita na aiwatar da PR kafin ku iya samar da PR bitstream don shirye-shiryen na'ura. Wannan saitin ya haɗa da ƙara yanki na tsaye .qdb file a matsayin tushe file ga kowane aiwatar da bita. Bugu da kari, dole ne ka saka
madaidaicin mahallin yankin PR. Bi waɗannan matakan don saita sake fasalin aiwatar da PR:

1.  Don saita bita na yanzu, danna Project ➤ Bita, zaɓi blinking_led_default azaman sunan Revision, sannan danna Saita Yanzu. A madadin, zaku iya zaɓar bita na yanzu akan babban kayan aikin Intel Quartus Prime.
2. Don tabbatar da madaidaicin tushen wannan bita na aiwatarwa, danna Project ➤ Ƙara/cire Files in Project. Tabbatar da cewa blinking_led.sv file ya bayyana a cikin file jeri.
3. Don tabbatar da madaidaicin tushe file don sake fasalin aiwatarwa, danna Project ➤ Ƙara/cire files a cikin Project, kuma ƙara tushen mai zuwa files don aiwatar da bita. Idan akwai, cire blinking_led.sv daga lissafin aikin files.
   

   Iaiwatar da Sunan Bita	Source File
   kyaftawa_led_ba komai	blinking_led_empty.sv
   kyaftawa_led_slow	blinking_led_slow.sv

4. Saita blinking_led_default azaman Bita na Yanzu.
5. Don tantance .qdb file a matsayin tushen tushen_partition, danna Ayyuka ➤ Zane Partition Window. Danna Rukunin Database sau biyu File cell kuma saka blinking_led_static.qdb file.
6. Hakazalika, saka blinking_led_supr_partition_final.qdb a matsayin Database File domin supr_partition.

   Hoto na 10.A madadin, yi amfani da ayyukan .qsf masu zuwa don tantance .qdb:
   saitin_intance_assignment -suna QDB_FILE_PARTITION \ blinking_led_static.qdb -zuwa |
   saitin_intance_assignment -suna QDB_FILE_PARTITION \ blinking_led_supr_partition_final.qdb -to u_top_counter
7. A cikin Tagar Ƙirar Ƙira, danna (...) kusa da ginshiƙin dama mafi nisa kuma kunna ginshiƙin Sake ɗaure mahallin.

8.  A cikin tantanin halitta Sake ɗaurewa, saka sabon sunan mahaɗan don ɓangaren PR da kuke canzawa a cikin bita na aiwatarwa na yanzu. Don bitar aiwatar da blinking_led_default, sunan mahallin yana blinking_led. A wannan yanayin, kuna sake rubuta misalin u_blinking_led daga tushen bita da kullin tare da sabon mahallin blinking_led. Don wasu bita na aiwatarwa, koma zuwa tebirin mai zuwa:

   Bita	Ƙimar Sake ɗaure mahalli
   kyaftawa_led_slow	kyaftawa_led_slow
   kyaftawa_led_ba komai	kyaftawa_led_ba komai

   Hoto 11. Maimaita mahallinA madadin, zaku iya amfani da layin masu zuwa a kowane .qsf na bita don saita ayyukan:
   ##blinking_led_default.qsf
   saitin_intance_assignment -suna ENTITY_REBINDING kyaftawa_led -zuwa_blinking_led
   ## kyaftawar_ya jagoranci_slow.qsf
   saitin_intance_assignment -suna ENTITY_REBINDING_l_slow_blinking_led_slow \ -zuwa u_blinking_led
   ## kyaftawa_ya jagoranci_ba komai.qsf
   saitin_intance_assignment -name ENTITY_REBINDING_led_empty_blaking_led_led_to u_blinking_led

9. Share rubutun mai riƙe da wuri daga Tantanin halitta Sake ɗaure don supr_partition.
10. Don haɗa ƙirar, danna Sarrafa ➤ Fara Tari. A madadin, yi amfani da umarni mai zuwa don haɗa wannan aikin: quartus_sh –flow compile blinking_led –c blinking_led_default
11. Maimaita matakai na 4 zuwa 11 don shirya da tattara bitar aiwatar da blinking_led_slow da blinking_led_empty.

1.5.8. Mataki 8: Canja dabarar SUPR
Don canza aikin dabaru a cikin sashin SUPR, dole ne ku canza tushen ɓangaren SUPR. Cika waɗannan matakai don maye gurbin misalin u_top_counter a cikin sashin SUPR tare da mahallin top_counter_fast.

1. Don saita bita na aiwatar da SUPR a matsayin na yanzu, danna Project ➤ Bita kuma saita impl_blinking_led_supr_new azaman bita na yanzu, ko zaɓi
   bita akan babban kayan aikin Intel Quartus Prime.
2. Don tabbatar da madaidaicin tushe file don bitar aiwatarwa, danna Project ➤
   Ƙara/cire files a cikin Project, kuma tabbatar da cewa top_counter_fast.sv shine tushen fasalin impl_blinking_led_supr_new aiwatarwa. Idan akwai, cire top_counter.sv daga lissafin aikin files.
3. Don tantance .qdb file hade da tushen partition, danna Assignments ➤ Design Partitions Window, sa'an nan sau biyu danna Partition Database. File cell don tantance blinking_led_static.qdb.
   A madadin, yi amfani da umarni mai zuwa don sanya wannan file: saita_intance_assignment -suna QDB_FILE_PARTITION \ blinking_led_static.qdb -zuwa |
4. A cikin tantanin halitta Sake ɗaure don pr_partition, saka sunan mahaɗan da ya dace. Domin wannan example, ƙayyade mahallin blinking_led_empty. A wannan yanayin, kuna sake rubuta misalin u_blinking_led daga tushen bita da kullin tare da sabon mahaɗan linking_led_empty. Layi mai zuwa yanzu yana cikin .qsf:
   ##impl_blinking_led_supr_new.qsf saita_misali assignment -sunan ENTITY_REBINDING_kyakkyawa_ jagoranci_ba komai \ -zuwa_guda_gudu
5. A cikin tantanin halitta Re-daure don supr_partition, saka saman_counter_fast mahallin. top_counter_fast shine sunan daidaitaccen mahaɗan da ke maye gurbin u_top_counter lokacin da kuka kammala SUPR.##impl_blinking_led_supr_new.qsf saita_misali assignment -sunan ENTITY_KARAWA babban_counter_sauri \ -zuwa_top_counter
6. Don haɗa ƙirar, danna Sarrafa ➤ Fara Tari. A madadin, yi amfani da umarni mai zuwa don haɗa wannan bita na aikin: quartus_sh -flow compile blinking_led -c \ impl_blinking_led_supr_new

1.5.9. Mataki 9: Shirya Hukumar
Bi waɗannan matakan don haɗawa da tsara kwamitin haɓakawa na Intel Agilex F-Series FPGA.

1. Haɗa wutar lantarki zuwa kwamitin haɓakawa na Intel Agilex F-Series FPGA.
2. Haɗa kebul na USB tsakanin tashar USB na PC ɗinku da na'urar shirye-shiryen USB akan allon haɓakawa.
3. Bude Intel Quartus Prime software, sa'an nan kuma danna Tools ➤ Programmer. Koma zuwa Shirye-shiryen Hukumar Haɓakawa.
4. A cikin Programmer, danna Saitin Hardware, sannan zaɓi USB-Blaster.
5. Danna Gane Auto, sannan zaɓi na'urar AGFB014R24B.
6.  Danna Ok. Software na Intel Quartus Prime yana ganowa kuma yana sabunta Programmer tare da na'urorin FPGA guda uku a kan allo.
7.  Zaɓi na'urar AGFB014R24B, danna Canja File, kuma loda blinking_led_default.sof file.
8. Kunna Shirin/Sanya don blinking_led_default.sof file.
9. Danna Fara kuma jira sandar ci gaba don isa 100%.
10.  Lura da LEDs a kan allo suna kyalkyali.
11. Don tsara yankin PR kawai, danna dama da blinking_led_default.sof file a cikin Programmer kuma danna Add PR Programming File. Zaɓi blinking_led_slow.pr_partition.rbf file.
12. Kashe Shirin/Sanya don blinking_led_default.sof file.
13.  Kunna Shirin/Sanya don blinking_led_slow.pr_partition.rbf file, sa'an nan kuma danna Fara. A kan allo, lura da LED[0] da LED[1] suna ci gaba da kiftawa. Lokacin da sandar ci gaba ta kai 100%, LED[2] da LED[3] suna kyaftawa a hankali.
14. Don sake tsara yankin PR, danna-dama .rbf file a cikin Programmer, sannan danna Change PR Programing File.
15.  Zaɓi .rbf files ga sauran mutane biyu su lura da halin da ake ciki a kan allo. Ana loda blinking_led_default.pr_partition.rbf file yana sa LEDs suyi ƙiftawa a mitar asali, kuma suna loda blinking_led_empty.pr_partition.rbf file yana sa LEDs su tsaya ON. 17. Don canza tunanin SUPR, maimaita mataki na 7 a sama don zaɓar impl_blinking_led_supr_new.sof. Bayan canza wannan file, led [0:1] yanzu yana kiftawa da sauri fiye da da. Sauran PR .rbf files kuma sun dace da sabon .sof.
    Lura: Mai Taruwa yana haifar da .rbf file ga yankin SUPR. Koyaya, bai kamata ku yi amfani da wannan ba file don sake tsara FPGA a lokacin aiki saboda rabon SUPR baya saurin daskare gada, mai kula da yankin PR, da sauran dabaru a cikin tsarin gaba ɗaya. Lokacin da kuka yi canje-canje ga ma'anar ɓangaren SUPR, dole ne ku sake tsara cikakken .sof file daga tsarin aiwatar da SUPR.

Hoto 12. Shirye-shiryen Hukumar Ci Gaba
1.5.9.1. Shirya matsala Kurakurai na Shirye-shiryen PR
Tabbatar da saitin da ya dace na Intel Quartus Prime Programmer da kayan haɗin da aka haɗa yana taimakawa wajen guje wa kowane kurakurai yayin shirye-shiryen PR.
Idan kun fuskanci kowane kurakurai na shirye-shiryen PR, koma zuwa "Masu matsala PR Kurakurai na Shirye-shiryen" a cikin Intel Quartus Prime Pro Edition Jagorar Mai amfani: Sake daidaitawa don matakai na warware matsalar mataki-mataki.
Bayanai masu alaƙa

Shirya matsala Kurakurai na Shirye-shiryen PR

1.5.10. Gyara ɓangarorin SUPR
Kuna iya canza sashin SUPR da ke akwai. Bayan gyaggyara ɓangaren SUPR, dole ne ku haɗa shi, samar da .sof file, da kuma tsara allon, ba tare da tattara sauran mutane ba. Domin misaliampko, bi waɗannan matakan don canza tsarin top_counter_fast.sv don ƙidaya sauri:

1. Saita impl_blinking_led_supr_new azaman bita na yanzu.
2.  A cikin babban_counter_fast.sv file, maye gurbin lissafin count_d + 2 da count_d + 4.
3.  Gudun waɗannan umarni don sake haɗawa da toshe SUPR kuma ƙirƙirar sabon .sof file: quartus_sh -flow compile blinking_led \ -c impl_blinking_led_supr_new
   Sakamakon .sof yanzu ya ƙunshi sabon yankin SUPR, kuma yana amfani da blinking_led don tsoho (power-on) mutum.

1.6. Tarihin Bita na Takardu na AN 987: Tsayayyen Sabunta Sashe na Sake Tsare-tsaren Koyarwa Tarihin Bita

Sigar Takardu	Intel Quartus Prime Version	Canje-canje
2022.10.24	22.	Sakin farko na takaddar.

An sabunta don Intel® Quartus®Prime Design Suite: 22.3

Amsoshi ga Manyan FAQs:

Aika da martani

Q Menene sabuntawa a tsaye

Sake fasalin Sake Tsayawa Tsaye akan shafi na 3

Tambaya Me nake buƙata don wannan koyawa?

Bukatun Koyarwa a shafi na 3

Q A ina zan iya samun ƙirar tunani?

Zane-zanen Magana Files shafi na 5

Q Ta yaya zan ƙirƙira ƙirar SUPR?

Tafiyar Tsara Nasiha a shafi na 6

Q Menene PR persona?

Bayyana Mutane a shafi na 10

Q Ta yaya zan canza tunanin SUPR? Canja dabarar SUPR akan shafi na 16

Canja dabarar SUPR akan shafi na 16

Ta yaya zan tsara allon?

Shirin Hukumar a shafi na 18

Q Menene sanannun al'amurran da suka shafi PR da iyakoki?

Dandalin Taimakon Intel FPGA: PR

Online Version
Aika da martani

Saukewa: 749443
AN-987
Shafin: 2022.10.24

Takardu / Albarkatu

intel Agilex F-Series FPGA Development Board [pdf] Jagorar mai amfani Agilex F-Series, Agilex F-Series FPGA Development Board, FPGA Development Board, Board Development Board, Board

Magana

• Manual mai amfani