ALTERA Cyclone VE FPGA Development Board

ọja Alaye

Awọn pato

• Awoṣe FPGA: Cyclone VE FPGA (5CEFA7F31I7N)
• Package FPGA: 896-pin FineLine BGA (FBGA)
• Adarí: Flash fast palolo parallel (FPP) iṣeto ni
• Awoṣe CPLD: MAX II CPLD (EPM240M100I5N)
• Package CPLD: 100-pin FBGA
• Olupilẹṣẹ aago ti eto fun titẹ sii aago itọkasi FPGA
• 50-MHz oscillator ti o pari ẹyọkan fun titẹ sii aago FPGA ati MAX V CPLD
• 100-MHz nikan-opin oscillator fun MAX V CPLD iṣeto ni aago igbewọle
• Iṣagbewọle SMA (LVDS)
• Iranti:
  • Meji 256-Mbyte (MB) DDR3 SDRAM awọn ẹrọ pẹlu a 16-bit data akero
  • Ọkan 18-Mbit (Mb) SSRAM
  • Ọkan 512-Mb amuṣiṣẹpọ filasi
  • LPDDR512 SDRAM 2-MB kan pẹlu ọkọ akero data 32-bit (ọkọ akero data 16-bit nikan ni a lo lori igbimọ yii)
  • Ọkan ni tẹlentẹle 64-Kb I2C PROM ti itanna nu (EEPROM)
• Ẹ̀rọ: 6.5 x 4.5 ọkọ iwọn

Awọn ilana Lilo ọja

Chapter 1: Opinview

Gbogbogbo Apejuwe

Cyclone VE FPGA Development Board jẹ apẹrẹ lati pese awọn agbara apẹrẹ ilọsiwaju pẹlu awọn ẹya bii atunto apakan. O funni ni iṣẹ yiyara, agbara kekere, ati akoko yiyara si ọja ni akawe si awọn idile FPGA ti tẹlẹ.

Wulo Links

Fun alaye diẹ sii lori awọn koko-ọrọ wọnyi, tọka si awọn iwe aṣẹ ti o yẹ:

• Idile ẹrọ Cyclone V: Cyclone V Device Handbook
• Ipilẹṣẹ HSMC: Ga iyara Mezzanine Kaadi (HSMC) Specification

Chapter 2: Board irinše

Awọn bulọọki paati Board

Igbimọ idagbasoke naa ṣe ẹya awọn bulọọki paati pataki wọnyi:

• Cyclone kan VE FPGA (5CEFA7F31I7N) ninu 896-pin FineLine BGA (FBGA)
• Adarí: Flash fast palolo parallel (FPP) iṣeto ni
• MAX II CPLD (EPM240M100I5N) ninu akojọpọ FBGA-pin 100 kan
• Olupilẹṣẹ aago ti eto fun titẹ sii aago itọkasi FPGA
• 50-MHz oscillator ti o pari ẹyọkan fun titẹ sii aago FPGA ati MAX V CPLD
• 100-MHz nikan-opin oscillator fun MAX V CPLD iṣeto ni aago igbewọle
• Iṣagbewọle SMA (LVDS)
• Iranti:
  • Meji 256-Mbyte (MB) DDR3 SDRAM awọn ẹrọ pẹlu a 16-bit data akero
  • Ọkan 18-Mbit (Mb) SSRAM
  • Ọkan 512-Mb amuṣiṣẹpọ filasi
  • LPDDR512 SDRAM 2-MB kan pẹlu ọkọ akero data 32-bit (ọkọ akero data 16-bit nikan ni a lo lori igbimọ yii)
  • Ọkan ni tẹlentẹle 64-Kb I2C PROM ti itanna nu (EEPROM)

Ẹ̀rọ

Igbimọ idagbasoke naa ni iwọn ti 6.5 x 4.5 inches.

Chapter 3: Board irinše Reference

Yi apakan pese alaye alaye nipa kọọkan ọkọ paati ati awọn oniwe-iṣẹ. Jọwọ tọkasi Iwe Itọkasi Igbimọ Idagbasoke Cyclone VE FPGA fun alaye diẹ sii.

FAQs

Q: Nibo ni MO le rii awọn HSMC tuntun ti o wa?

A: Lati wo atokọ ti awọn HSMC tuntun ti o wa tabi lati ṣe igbasilẹ ẹda kan ti sipesifikesonu HSMC, tọka si oju-iwe Awọn kaadi DaughterCard Development Board ti Altera webojula.

Q: Kini ilọsiwaju naatages ti Cyclone VE FPGA Development Board?

A: Igbimọ Idagbasoke Cyclone VE FPGA nfunni ni awọn ilọsiwaju apẹrẹ ati awọn imotuntun, gẹgẹbi atunto apa kan, eyiti o rii daju iṣẹ yiyara, agbara kekere, ati akoko yiyara si ọja ni akawe si awọn idile FPGA iṣaaju.

Q: Nibo ni MO le wa alaye diẹ sii nipa idile ẹrọ Cyclone V?

A: Fun alaye diẹ ẹ sii nipa ẹbi ẹrọ Cyclone V, tọka si Iwe amudani ẹrọ Cyclone V.

Q: Kini iwọn ti igbimọ idagbasoke?

A: Igbimọ idagbasoke naa ni iwọn ti 6.5 x 4.5 inches.

101 Innovation wakọ
San Jose, CA 95134
www.altera.com
MNL-01075-1.4

© 2017 Altera Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS ati STRATIX ọrọ ati awọn apejuwe jẹ aami-išowo ti Altera Corporation ati forukọsilẹ ni US Patent ati Trademark Office ati ni awọn orilẹ-ede miiran. Gbogbo awọn ọrọ miiran ati awọn aami idanimọ bi aami-išowo tabi awọn ami iṣẹ jẹ ohun-ini awọn oniwun wọn gẹgẹbi a ti ṣalaye ni www.altera.com/common/legal.html. Altera ṣe atilẹyin iṣẹ ti awọn ọja semikondokito rẹ si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Altera, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Altera ko gba ojuse tabi layabiliti ti o waye lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Altera. A gba awọn alabara Altera nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
August 2017 Altera Corporation Cyclone VE FPGA Development Board
Ilana itọkasi

Iwe yii ṣe apejuwe awọn ẹya ohun elo ti igbimọ idagbasoke Cyclone® VE FPGA, pẹlu pin-jade alaye ati alaye itọkasi paati ti o nilo lati ṣẹda awọn aṣa FPGA aṣa ti o ni wiwo pẹlu gbogbo awọn paati ti igbimọ naa.

Pariview

Gbogbogbo Apejuwe

Igbimọ idagbasoke Cyclone VE FPGA n pese iru ẹrọ ohun elo kan fun idagbasoke ati ṣiṣe adaṣe agbara kekere, iṣẹ ṣiṣe giga, ati awọn apẹrẹ ti o lekoko nipa lilo Altera's Cyclone VE FPGA. Igbimọ naa pese ọpọlọpọ awọn agbeegbe ati awọn atọkun iranti lati dẹrọ idagbasoke ti awọn apẹrẹ Cyclone VE FPGA. Asopọmọra kaadi mezzanine iyara giga kan (HSMC) wa lati ṣafikun iṣẹ ṣiṣe afikun nipasẹ ọpọlọpọ awọn HSMC ti o wa lati Altera® ati awọn alabaṣiṣẹpọ lọpọlọpọ.

• Lati wo atokọ ti awọn HSMC tuntun ti o wa tabi lati ṣe igbasilẹ ẹda kan ti sipesifikesonu HSMC, tọka si oju-iwe Awọn kaadi Daughterboard Development Board ti Altera webojula.
  Awọn ilọsiwaju apẹrẹ ati awọn imotuntun, gẹgẹbi atunto apakan, rii daju pe awọn apẹrẹ ti a ṣe imuse ni Cyclone VE FPGAs ṣiṣẹ ni iyara, pẹlu agbara kekere, ati ni akoko yiyara si ọja ju awọn idile FPGA iṣaaju lọ.
• Fun alaye diẹ sii lori awọn koko-ọrọ wọnyi, tọka si awọn iwe aṣẹ ti o yẹ:
  • Idile ẹrọ Cyclone V, tọka si Iwe amudani ẹrọ Cyclone V.
  • Sipesifikesonu HSMC, tọka si Kaadi Mezzanine Iyara giga (HSMC) Specification.

Awọn bulọọki paati Board

Igbimọ idagbasoke naa ṣe ẹya awọn bulọọki paati pataki wọnyi:

• Cyclone kan VE FPGA (5CEFA7F31I7N) ninu akojọpọ 896-pin FineLine BGA (FBGA) kan
  • 149,500 LES
  • 56,480 awọn modulu kannaa aṣamubadọgba (ALMs)
  • 6,860 Kbit (Kb) M10K ati 836 Kb MLAB iranti
  • Awọn yipu titiipa ipele ida meje (PLS)
  • 312 18× 18-bit multipliers
  • 480 igbewọle/ijade idi gbogbogbo (GPIO)
  • 1.1-V mojuto voltage
• FPGA iṣeto ni circuitry
  • Tẹlentẹle ti nṣiṣe lọwọ (AS) x1 tabi iṣeto AS x4 (EPCQ256SI16N)
  • MAX® V CPLD (5M2210ZF256I5N) ninu apo FBGA-pin 256 kan gẹgẹbi Alakoso Eto
  • Flash fast palolo parallel (FPP) iṣeto ni
  • MAX II CPLD (EPM240M100I5N) ni 100-pin FBGA package gẹgẹ bi ara USB-BlasterTM II ifibọ fun lilo pẹlu Quartus® II Programmer
• clocking circuitry
  • Olupilẹṣẹ aago ti eto fun titẹ sii aago itọkasi FPGA
  • 50-MHz oscillator ti o pari ẹyọkan fun titẹ sii aago FPGA ati MAX V CPLD
  • 100-MHz nikan-opin oscillator fun MAX V CPLD iṣeto ni aago igbewọle
  • Iṣagbewọle SMA (LVDS)
• Iranti
  • Meji 256-Mbyte (MB) DDR3 SDRAM awọn ẹrọ pẹlu a 16-bit data akero
  • Ọkan 18-Mbit (Mb) SSRAM
  • Ọkan 512-Mb amuṣiṣẹpọ filasi
  • LPDDR512 SDRAM 2-MB kan pẹlu ọkọ akero data 32-bit (ọkọ akero data 16-bit nikan ni a lo lori igbimọ yii)
  • Ọkan ni tẹlentẹle 64-Kb I2C PROM ti itanna nu (EEPROM)
• Gbogbogbo olumulo input / o wu
  • Awọn LED ati awọn ifihan
  • Awọn LED olumulo mẹrin
  • Ọkan fifuye iṣeto ni LED
  • Ọkan iṣeto ni ṣe LED
  • Ọkan aṣiṣe LED
  • Meta iṣeto ni yan LED
  • Awọn LED ipo USB-Blaster II mẹrin ti a fi sinu
  • Awọn LED wiwo HSMC mẹta
  • Mẹwa àjọlò LED
  • Meji UART data atagba ati gba awọn LED
  • Meji USB-UART ni wiwo TX / RX LED
  • Ọkan agbara lori LED
  • Ọkan meji-ila kikọ LCD àpapọ
• Awọn bọtini titari
  • Ọkan Sipiyu tun bọtini titari
  • Ọkan MAX V tun titari bọtini
  • Eto kan yan bọtini titari
  • Ọkan bọtini titari iṣeto ni eto
  • Awọn bọtini titari olumulo gbogbogbo mẹrin
• Awọn iyipada DIP
  • Mẹrin MAX V CPLD System Adarí awọn yipada
  • Meji JTAG pq Iṣakoso DIP yipada
  • Ọkan àìpẹ iṣakoso DIP yipada
  • Mẹrin gbogboogbo olumulo DIP yipada
• Ibi ti ina elekitiriki ti nwa
  14-20-V (laptop) DC igbewọle
• Ẹ̀rọ
  6.5 ″ x 4.5 ″ igbimọ iwọn

Development Board Àkọsílẹ aworan atọka

Nọmba 1–1 fihan aworan atọka ti igbimọ idagbasoke Cyclone VE FPGA.

Mimu Board

Nigbati o ba n ṣakoso igbimọ, o ṣe pataki lati ṣe akiyesi iṣọra itusilẹ aimi atẹle wọnyi:

ṣọra
Laisi to dara egboogi-aimi mu, awọn ọkọ le bajẹ. Nitorinaa, lo awọn iṣọra mimu aiṣedeede nigbati o ba fọwọkan igbimọ naa.

Awọn paati Igbimọ

Ipin yii ṣafihan awọn paati pataki lori igbimọ idagbasoke Cyclone VE FPGA. Nọmba 2-1 ṣe apejuwe awọn ipo paati ati Table 2-1 pese apejuwe kukuru ti gbogbo awọn ẹya paati ti igbimọ.

Eto pipe ti awọn sikematiki, aaye data ipilẹ ti ara, ati GERBER files fun igbimọ idagbasoke n gbe inu iwe ilana ohun elo idagbasoke Cyclone VE FPGA.

Fun alaye nipa fifi agbara soke igbimọ ati fifi sọfitiwia ifihan sori ẹrọ, tọka si Itọsọna olumulo Apo Idagbasoke Cyclone VE FPGA.

Abala yii ni awọn apakan wọnyi:

• "Paader Overview”
• “Ẹrọ Afihan: Cyclone VE FPGA” ni oju-iwe 2–4
• "MAX V CPLD 5M2210 System Adarí" loju iwe 2-5
• “Iṣeto FPGA” ni oju-iwe 2–10
• “Aago Circuit” loju iwe 2–18
•  “Igbewọle/Igbejade Olumulo Gbogbogbo” ni oju-iwe 2–20
• "Awọn ẹya ara ẹrọ ati Awọn Itumọ" ni oju-iwe 2-24
• “Ìrántí” ní ojú ìwé 2–32
• “Ipese Agbara” ni oju-iwe 2–41

Board Overview

Yi apakan pese ohun loriview ti igbimọ idagbasoke Cyclone VE FPGA, pẹlu aworan igbimọ asọye ati awọn apejuwe paati. Nọmba 2-1 fihan ohun ti o pariview ti awọn ẹya ara ẹrọ ọkọ.

Tabili 2-1 ṣe apejuwe awọn paati ati ṣe atokọ awọn itọkasi igbimọ ti o baamu.

Tabili 2–1. Awọn irinše igbimọ (Apá 1 ti 3)

Ọkọ Itọkasi	Iru	Apejuwe
Afihan Awọn ẹrọ
U1	FPGA	Cyclone VE FPGA, 5CEFA7F31I7N, 896-pin FBGA.
U13	CPLD	MAX V CPLD, 5M2210ZF256I5N, 256-pin FBGA.
Iṣeto, Ipo, ati Eto Awọn eroja
J4	JTAG pq akọsori	Pese wiwọle si JTAG pq ati ki o mu awọn ifibọ USB-Blaster II nigba lilo ohun ita USB-Blaster USB.
SW2	JTAG pq Iṣakoso DIP yipada	Yọọ kuro tabi ṣafikun awọn ẹrọ inu JTAG pq.
J10	USB iru-B asopo	Ni wiwo USB fun siseto FPGA ati n ṣatunṣe aṣiṣe nipasẹ USB-Blaster II JTAG nipasẹ okun USB iru-B.

Tabili 2–1. Awọn irinše igbimọ (Apá 2 ti 3)

Ọkọ Itọkasi	Iru	Apejuwe
SW3	Board eto DIP yipada	Ṣakoso awọn iṣẹ oluṣakoso eto MAX V CPLD 5M2210 gẹgẹbi aago ṣiṣẹ, iṣakoso titẹ sii aago SMA, ati aworan wo lati gbe lati iranti filasi ni agbara-soke.
SW1	MSEL DIP yipada	Išakoso awọn iṣeto ni eni lori awọn ọkọ. Awọn pinni MSEL 0, 1, 2 ati 4 sopọ si iyipada DIP lakoko ti MSEL pin 3 sopọ si ilẹ.
S2	Eto yan bọtini titari	Yipada eto yan Awọn LED, eyiti o yan aworan eto ti o gbejade lati iranti filasi si FPGA.
S1	Bọtini titari iṣeto ni eto	Fifuye aworan lati iranti filasi si FGPA ti o da lori awọn eto ti eto naa yan Awọn LED.
D19	Iṣeto ni ṣe LED	Tan imọlẹ nigbati FPGA ti wa ni tunto.
D18	Fifuye LED	Itanna nigbati MAX V CPLD 5M2210 System Adarí ti wa ni actively atunto FPGA.
D17	LED aṣiṣe	Ṣe itanna nigbati iṣeto FPGA lati iranti filasi kuna.
D35	LED Agbara	Ṣe itanna nigbati agbara 5.0-V wa.
D25 ~ D27	Eto yan awọn LED	Itanna lati fi LED ọkọọkan ti o ipinnu eyi ti filasi iranti image fifuye si FPGA nigbati o ba tẹ awọn eto yan titari bọtini. Tọkasi Tabili 2-6 fun awọn eto LED.
D1 ~ D10	Awọn LED àjọlò	Ṣe itanna lati ṣe afihan iyara asopọ daradara bi gbigbe tabi gba iṣẹ ṣiṣe.
D20, D21	Awọn LED ibudo HSMC	O le tunto awọn LED wọnyi lati tọka atagba tabi gba iṣẹ ṣiṣe.
D22	HSMC ibudo bayi LED	Itanna nigbati a ọmọbinrin kaadi ti wa ni edidi sinu HSMC ibudo.
D15, D16	Awọn LED USB-UART	Ṣe itanna nigbati atagba USB-UART ati olugba wa ni lilo.
D23, D24	Tẹlentẹle UART LED	Ṣe itanna nigbati atagba UART ati olugba wa ni lilo.
Aago Ayika
X1	Oscillator eto	Oscillator ti siseto pẹlu awọn igbohunsafẹfẹ aiyipada ti 125 MHz. Igbohunsafẹfẹ jẹ siseto nipa lilo GUI iṣakoso aago ti nṣiṣẹ lori MAX V CPLD 5M2210 System Adarí.
U4	50-MHz oscillator	50.000-MHz gara oscillator fun gbogboogbo idi kannaa.
X3	100-MHz oscillator	100.000-MHz gara oscillator fun MAX V CPLD 5M2210 System Adarí.
J2, J3	Awọn asopọ SMA titẹ sii aago	Wakọ awọn igbewọle aago ibaramu LVDS sinu ifipamọ multiplexer aago.
J4	Aago o wu SMA asopo	Wakọ jade 2.5-V CMOS aago o wu lati FPGA.
Gbogboogbo Olumulo Input/Ojade
D28 ~ D31	Awọn LED olumulo	Awọn LED olumulo mẹrin. Itanna nigba ti ìṣó kekere.
SW3	Olumulo DIP yipada	Quad olumulo DIP yipada. Nigbati iyipada ba wa ni ON, a yan ọgbọn kan 0.
S4	Sipiyu tun titari bọtini	Tun FPGA kannaa.
S3	MAX V tun titari bọtini	Tun MAX V CPLD 5M2210 System Adarí.
S5 ~ S8	Awọn bọtini titari olumulo gbogbogbo	Awọn bọtini titari olumulo mẹrin. Wakọ kekere nigbati o ba tẹ.
Iranti Awọn ẹrọ
U7, U8	DDR3 x32 iranti	Meji 256-MB DDR3 SDRAM pẹlu 16-bit data akero.
U9	LPDDR2 x 16 iranti	512-MB LPDDR 2 SDRAM pẹlu 32-bit akero, nikan 16-bit akero lo lori yi ọkọ.

Tabili 2–1. Awọn irinše igbimọ (Apá 3 ti 3)

Ọkọ Itọkasi	Iru	Apejuwe
U10	Flash x16 iranti	512-Mb amuṣiṣẹpọ flash awọn ẹrọ pẹlu a 16-bit data akero fun ti kii-iyipada iranti.
U11	SSRAM x16 iranti	18-Mb boṣewa amuṣiṣẹpọ Ramu pẹlu a 12-bit data akero ati 4-bit parity.
U12	EEPROM	64-Mb I2C ni tẹlentẹle EEPROM.
Ibaraẹnisọrọ Awọn ibudo
J1	HSMC ibudo	Pese 84 CMOS tabi awọn ikanni LVDS 17 fun sipesifikesonu HSMC.
J11	Gigabit àjọlò ibudo	RJ-45 asopo ohun ti o pese a 10/100/1000 àjọlò asopọ nipasẹ a Marvell 88E1111 PHY ati awọn FPGA-orisun Altera Triple Speed ​​àjọlò MegaCore iṣẹ ni RGMII mode.
J12	Tẹlentẹle UART ibudo	DSUB 9-pin asopo pẹlu RS-232 transceiver lati se RS-232 ni tẹlentẹle UART ikanni.
J13	USB-UART ibudo	USB asopo pẹlu USB-to-UART Afara fun ni tẹlentẹle UART ni wiwo.
J15, J16	Ṣatunkọ awọn akọle	Awọn akọle 2 × 8 meji fun awọn idi yokokoro.
Fidio ati Ifihan Awọn ibudo
J14	LCD ohun kikọ	Asopọ ti o ni atọkun si a pese 16 kikọ × 2 ila LCD module pẹlu meji standoffs.
Agbara Ipese
J17	Jack igbewọle DC	Gba ipese agbara 14–20-V DC.
SW5	Yipada agbara	Yipada si agbara tan tabi pa igbimọ nigbati a ba pese agbara lati inu Jack input DC.

Ẹrọ ifihan: Cyclone VE FPGA

Igbimọ idagbasoke Cyclone VE FPGA ṣe ẹya ẹrọ Cyclone VE FPGA 5CEFA7F31I7N (U1) ninu package FBGA-896-pin kan.

Fun alaye diẹ sii nipa idile ẹrọ Cyclone V, tọka si Iwe-ifọwọsi ẹrọ Cyclone V.
Tabili 2-2 ṣe apejuwe awọn ẹya ti ẹrọ Cyclone VE FPGA 5CEFA7F31I7N.

Tabili 2-2. Cyclone VE FPGA Awọn ẹya ara ẹrọ

Awọn ALMs	Dédéédé Les	M10K Àgbo Ohun amorindun	Lapapọ Ramu (Kbits)	18-bit × 18-bit Multipliers	PLLs	Package Iru
56,480	149,500	6,860	836	312	7	896-pin FBGA

I/O Resources
Ẹrọ Cyclone VE FPGA 5CEFA7F31I7N ni apapọ I/O olumulo 480. Tabili 2–3 ṣe atokọ ti Cyclone VE FPGA I/O pin ka ati lilo nipasẹ iṣẹ lori igbimọ.

Tabili 2–3. Cyclone VE FPGA I/O Pin ka

Išẹ	I/O Standard	I/O Ka	Pataki Awọn pinni
DDR3	1.5-V SSTL	71	Ọkan iyatọ x4 DQS pin
LPDDR2	1.2-V HSUL	37	Ọkan iyatọ x2 DQS pin
Filaṣi, SSRAM, EEPROM, ati MAX V FSM akero	2.5-V CMOS, 3.3-V LVCMOS	69	—
HSMC ibudo	2.5-V CMOS + LVDS	79	17 LVDS, I2C
Gigabit àjọlò ibudo	2.5-V CMOS	42	—
Ifibọ USB-Blaster II	2.5-V CMOS	20	—
Akọsori yokokoro	1.5-V, 2.5-V	20	—
UART	3.3-V LVTTL	4	—
USB-UART	2.5-V CMOS	12	—
Awọn bọtini titari	2.5-V CMOS	5	Ọkan DEV_CLRn pinni
Awọn iyipada DIP	2.5-V CMOS	4	—
LCD ohun kikọ	2.5-V CMOS	11	—
Awọn LED	2.5-V CMOS	9	—
Aago tabi Oscillators	2.5-V CMOS + LVDS	12	Aago kan jade pin
Lapapọ I/O Lo:		395

MAX V CPLD 5M2210 System Adarí
Igbimọ naa nlo Alakoso Eto 5M2210, Altera MAX V CPLD kan, fun awọn idi wọnyi:

• FPGA iṣeto ni lati filasi
• Iwọn agbara
• Iṣakoso ati awọn iforukọsilẹ ipo fun imudojuiwọn eto latọna jijin

Nọmba 2–2 ṣe afihan iṣẹ-ṣiṣe Adarí Eto MAX V CPLD 5M2210 ati awọn asopọ iyika ita bi aworan atọka.

Olusin 2–2. MAX V CPLD 5M2210 System Adarí Àkọsílẹ aworan atọka

Tabili 2–4 ṣe atokọ awọn ami I/O ti o wa lori MAX V CPLD 5M2210 Alakoso Eto. Awọn orukọ ifihan agbara ati awọn iṣẹ jẹ ibatan si ẹrọ MAX V.

O le gba lati ayelujara ohun example ṣe apẹrẹ pẹlu awọn ipo pin ati awọn iṣẹ iyansilẹ ti o pari ni ibamu si tabili atẹle lati Ile itaja Apẹrẹ Altera. Ninu Apo Idagbasoke Cyclone VE FPGA, labẹ Apẹrẹ Examples, tẹ Cyclone VE FPGA Development Kit Ipilẹ Pinout.

Tabili 2–4. MAX V CPLD 5M2210 Ẹrọ Alakoso Eto Eto Pin-Jade (Apá 1 ti 5)

Ọkọ Itọkasi (U13)	Sisọmu Ifihan agbara Oruko	I/O Standard	Apejuwe
N4	5M2210_JTAG_TMS	3.3-V	MAX VJTAG TMS
E9	CLK50_EN	2.5-V	50 MHz oscillator jeki
H12	CLK_CONFIG	2.5-V	100 MHz iṣeto ni aago input
A15	CLK_GBANI	2.5-V	DIP yipada fun aago oscillator jeki
A13	CLK_SEL	2.5-V	DIP yipada fun aago yan-SMA tabi oscillator
J12	CLKIN_50_MAXV	2.5-V	50 MHz aago input
D9	CLOCK_SCL	2.5-V	Ti siseto oscillator I2C aago
C9	CLOCK_SDA	2.5-V	Oscillator I2C data siseto
D10	CPU_RESETN	2.5-V	FPGA tun bọtini titari
P12	EXTRA_SIG0	2.5-V	Ifibọ USB-Blaster II ni wiwo. Ni ipamọ fun ojo iwaju lilo
T13	EXTRA_SIG1	2.5-V	Ifibọ USB-Blaster II ni wiwo. Ni ipamọ fun ojo iwaju lilo
T15	EXTRA_SIG2	2.5-V	Ifibọ USB-Blaster II ni wiwo. Ni ipamọ fun ojo iwaju lilo
A2	FACTORY_LOAD	2.5-V	DIP yipada si fifuye ile-iṣẹ tabi apẹrẹ olumulo ni agbara-soke

Tabili 2–4. MAX V CPLD 5M2210 Ẹrọ Alakoso Eto Eto Pin-Jade (Apá 2 ti 5)

Ọkọ Itọkasi (U13)	Sisọmu Ifihan agbara Oruko	I/O Standard	Apejuwe
R14	FACTORY_REQUEST	2.5-V	Ifibọ USB-Blaster II ìbéèrè lati fi aṣẹ FACTORY
N12	Ipò FACTORY	2.5-V	Ifibọ USB-Blaster II FACTORY ipo pipaṣẹ
C8	FAN_FORCE_ON	2.5-V	DIP yipada si tan tabi pa afẹfẹ naa
N7	FLASH_ADVN	2.5-V	FSM akero filasi iranti adirẹsi wulo
R5	FLASH_CEN	2.5-V	FSM akero filasi iranti ni ërún jeki
R6	FLASH_CLK	2.5-V	FSM akero filasi iranti aago
M6	FLASH_OEN	2.5-V	FSM akero filasi iranti o wu jeki
T5	FLASH_RDYBSYN	2.5-V	FSM akero filasi iranti setan
P7	FLASH_RESETN	2.5-V	FSM akero filasi iranti atunto
N6	FLASH_WEN	2.5-V	FSM akero filasi iranti Kọ jeki
K1	FPGA_CONF_DONE	3.3-V	FPGA iṣeto ni ṣe LED
D3	FPGA_CONFIG_D0	3.3-V	FPGA iṣeto ni data
C2	FPGA_CONFIG_D1	3.3-V	FPGA iṣeto ni data
C3	FPGA_CONFIG_D2	3.3-V	FPGA iṣeto ni data
E3	FPGA_CONFIG_D3	3.3-V	FPGA iṣeto ni data
D2	FPGA_CONFIG_D4	3.3-V	FPGA iṣeto ni data
E4	FPGA_CONFIG_D5	3.3-V	FPGA iṣeto ni data
D1	FPGA_CONFIG_D6	3.3-V	FPGA iṣeto ni data
E5	FPGA_CONFIG_D7	3.3-V	FPGA iṣeto ni data
F3	FPGA_CONFIG_D8	3.3-V	FPGA iṣeto ni data
E1	FPGA_CONFIG_D9	3.3-V	FPGA iṣeto ni data
F4	FPGA_CONFIG_D10	3.3-V	FPGA iṣeto ni data
F2	FPGA_CONFIG_D11	3.3-V	FPGA iṣeto ni data
F1	FPGA_CONFIG_D12	3.3-V	FPGA iṣeto ni data
F6	FPGA_CONFIG_D13	3.3-V	FPGA iṣeto ni data
G2	FPGA_CONFIG_D14	3.3-V	FPGA iṣeto ni data
G3	FPGA_CONFIG_D15	3.3-V	FPGA iṣeto ni data
K4	FPGA_MAX_DCLK	3.3-V	FPGA iṣeto ni aago
J3	FPGA_DCLK	3.3-V	FPGA iṣeto ni aago
N1	FPGA_NCONFIG	3.3-V	FPGA iṣeto ni lọwọ
J4	FPGA_NSTATUS	3.3-V	FPGA iṣeto ni setan
H1	FPGA_PR_DONE	3.3-V	FPGA apa kan atunto ṣe
P2	FPGA_PR_ERROR	3.3-V	Aṣiṣe atunto apa kan FPGA
E2	FPGA_PR_READY	3.3-V	FPGA apa kan atunto setan
F5	FPGA_PR_REQUEST	3.3-V	Ibere ​​atunto apa kan FPGA
L5	FPGA_MAX_NCS	3.3-V	FPGA iṣeto ni ërún yan
E14	FSM_A1	2.5-V	FSM adirẹsi akero
C14	FSM_A2	2.5-V	FSM adirẹsi akero

Tabili 2–4. MAX V CPLD 5M2210 Ẹrọ Alakoso Eto Eto Pin-Jade (Apá 3 ti 5)

Ọkọ Itọkasi (U13)	Sisọmu Ifihan agbara Oruko	I/O Standard	Apejuwe
C15	FSM_A3	2.5-V	FSM adirẹsi akero
E13	FSM_A4	2.5-V	FSM adirẹsi akero
E12	FSM_A5	2.5-V	FSM adirẹsi akero
D15	FSM_A6	2.5-V	FSM adirẹsi akero
F14	FSM_A7	2.5-V	FSM adirẹsi akero
D16	FSM_A8	2.5-V	FSM adirẹsi akero
F13	FSM_A9	2.5-V	FSM adirẹsi akero
E15	FSM_A10	2.5-V	FSM adirẹsi akero
E16	FSM_A11	2.5-V	FSM adirẹsi akero
F15	FSM_A12	2.5-V	FSM adirẹsi akero
G14	FSM_A13	2.5-V	FSM adirẹsi akero
F16	FSM_A14	2.5-V	FSM adirẹsi akero
G13	FSM_A15	2.5-V	FSM adirẹsi akero
G15	FSM_A16	2.5-V	FSM adirẹsi akero
G12	FSM_A17	2.5-V	FSM adirẹsi akero
G16	FSM_A18	2.5-V	FSM adirẹsi akero
H14	FSM_A19	2.5-V	FSM adirẹsi akero
H20	FSM_A20	2.5-V	FSM adirẹsi akero
H13	FSM_A21	2.5-V	FSM adirẹsi akero
H16	FSM_A22	2.5-V	FSM adirẹsi akero
J13	FSM_A23	2.5-V	FSM adirẹsi akero
J16	FSM_A24	2.5-V	FSM adirẹsi akero
T2	FSM_A25	2.5-V	FSM adirẹsi akero
P5	FSM_A26	2.5-V	FSM adirẹsi akero
J14	FSM_D0	2.5-V	FSM data akero
J15	FSM_D1	2.5-V	FSM data akero
K16	FSM_D2	2.5-V	FSM data akero
K13	FSM_D3	2.5-V	FSM data akero
K15	FSM_D4	2.5-V	FSM data akero
K14	FSM_D5	2.5-V	FSM data akero
L16	FSM_D6	2.5-V	FSM data akero
L11	FSM_D7	2.5-V	FSM data akero
L15	FSM_D8	2.5-V	FSM data akero
L12	FSM_D9	2.5-V	FSM data akero
M16	FSM_D10	2.5-V	FSM data akero
L13	FSM_D11	2.5-V	FSM data akero
M15	FSM_D12	2.5-V	FSM data akero
L14	FSM_D13	2.5-V	FSM data akero
N16	FSM_D14	2.5-V	FSM data akero

Tabili 2–4. MAX V CPLD 5M2210 Ẹrọ Alakoso Eto Eto Pin-Jade (Apá 4 ti 5)

Ọkọ Itọkasi (U13)	Sisọmu Ifihan agbara Oruko	I/O Standard	Apejuwe
M13	FSM_D15	2.5-V	FSM data akero
B8	HSMA_PRSNTN	2.5-V	HSMC ibudo bayi
L6	JTAG_5M2210_TDI	3.3-V	MAX V CPLD JTAG pq data ni
M5	JTAG_5M2210_TDO	3.3-V	MAX V CPLD JTAG pq data jade
P3	JTAG_TCK	3.3-V	JTAG aago pq
P11	M570_Aago	2.5-V	25-MHz aago to ifibọ USB-Blaster II fun a firanṣẹ FACTORY pipaṣẹ
M1	M570_JTAG_EN	3.3-V	Ifihan agbara kekere lati mu ifibọ USB-Blaster II ṣiṣẹ
P10	MAX5_BEN0	2.5-V	FSM akero MAX V baiti jeki 0
R11	MAX5_BEN1	2.5-V	FSM akero MAX V baiti jeki 1
T12	MAX5_BEN2	2.5-V	FSM akero MAX V baiti jeki 2
N11	MAX5_BEN3	2.5-V	FSM akero MAX V baiti jeki 3
T11	MAX5_CLK	2.5-V	FSM akero MAX V aago
R10	MAX5_CSN	2.5-V	FSM akero MAX V ërún yan
M10	MAX5_OEN	2.5-V	FSM akero MAX V o wu jeki
N10	MAX5_WEN	2.5-V	FSM akero MAX V kikọ jeki
E11	MAX_CONF_DON	2.5-V	Ifibọ USB-Blaster II iṣeto ni ṣe LED
A4	MAX_ERROR	2.5-V	FPGA iṣeto ni aṣiṣe LED
A6	MAX_LOAD	2.5-V	FPGA iṣeto ni LED ti nṣiṣe lọwọ
M9	MAX_RESETN	2.5-V	MAX V tun titari bọtini
B7	OVERTEMP	2.5-V	Igba otutu atẹle àìpẹ jeki
D12	PGM_CONFIG	2.5-V	Gbe aworan iranti filasi ti a damọ nipasẹ awọn LED PGM
B14	PGM_LED0	2.5-V	Filaṣi iranti PGM yan atọka 0
C13	PGM_LED1	2.5-V	Filaṣi iranti PGM yan atọka 1
B16	PGM_LED2	2.5-V	Filaṣi iranti PGM yan atọka 2
B13	PGM_SEL	2.5-V	Yipada PGM_LED [2: 0] LED ọkọọkan
H4	PSAS_CSn	3.3-V	AS iṣeto ni ërún yan
G1	PSAS_DCLK	3.3-V	AS aago iṣeto ni
G4	PSAS_CONF_DONE	3.3-V	AS iṣeto ni ṣe
H2	PSAS_CONFIGn	3.3-V	AS iṣeto ni lọwọ
G5	PSAS_DATA1	3.3-V	AS iṣeto ni data
H3	PSAS_DATA0_ASD0	3.3-V	AS iṣeto ni data
J1	PSAS_CEn	3.3-V	AS iṣeto ni ërún jeki
R12	SECURITY_MODE	2.5-V	Yipada DIP fun USB-Blaster II ti a fi sii lati firanṣẹ aṣẹ FACTORY ni agbara soke
E7	SENSE_CS0N	2.5-V	Chip atẹle agbara yan
A5	SENSE_SCK	2.5-V	Agbara atẹle aago SPI
D7	SENSE_SDI	2.5-V	Agbara atẹle data SPI ni
B6	SENSE_SDO	2.5-V	Agbara atẹle SPI data jade

Tabili 2–4. MAX V CPLD 5M2210 Ẹrọ Alakoso Eto Eto Pin-Jade (Apá 5 ti 5)

Ọkọ Itọkasi (U13)	Sisọmu Ifihan agbara Oruko	I/O Standard	Apejuwe
M13	FSM_D15	2.5-V	FSM data akero
B8	HSMA_PRSNTN	2.5-V	HSMC ibudo bayi
L6	JTAG_5M2210_TDI	3.3-V	MAX V CPLD JTAG pq data ni
M5	JTAG_5M2210_TDO	3.3-V	MAX V CPLD JTAG pq data jade
P3	JTAG_TCK	3.3-V	JTAG aago pq
P11	M570_Aago	2.5-V	25-MHz aago to ifibọ USB-Blaster II fun a firanṣẹ FACTORY pipaṣẹ
M1	M570_JTAG_EN	3.3-V	Ifihan agbara kekere lati mu ifibọ USB-Blaster II ṣiṣẹ
P10	MAX5_BEN0	2.5-V	FSM akero MAX V baiti jeki 0
R11	MAX5_BEN1	2.5-V	FSM akero MAX V baiti jeki 1
T12	MAX5_BEN2	2.5-V	FSM akero MAX V baiti jeki 2
N11	MAX5_BEN3	2.5-V	FSM akero MAX V baiti jeki 3
T11	MAX5_CLK	2.5-V	FSM akero MAX V aago
R10	MAX5_CSN	2.5-V	FSM akero MAX V ërún yan
M10	MAX5_OEN	2.5-V	FSM akero MAX V o wu jeki
N10	MAX5_WEN	2.5-V	FSM akero MAX V kikọ jeki
E11	MAX_CONF_DON	2.5-V	Ifibọ USB-Blaster II iṣeto ni ṣe LED
A4	MAX_ERROR	2.5-V	FPGA iṣeto ni aṣiṣe LED
A6	MAX_LOAD	2.5-V	FPGA iṣeto ni LED ti nṣiṣe lọwọ
M9	MAX_RESETN	2.5-V	MAX V tun titari bọtini
B7	OVERTEMP	2.5-V	Igba otutu atẹle àìpẹ jeki
D12	PGM_CONFIG	2.5-V	Gbe aworan iranti filasi ti a damọ nipasẹ awọn LED PGM
B14	PGM_LED0	2.5-V	Filaṣi iranti PGM yan atọka 0
C13	PGM_LED1	2.5-V	Filaṣi iranti PGM yan atọka 1
B16	PGM_LED2	2.5-V	Filaṣi iranti PGM yan atọka 2
B13	PGM_SEL	2.5-V	Yipada PGM_LED [2: 0] LED ọkọọkan
H4	PSAS_CSn	3.3-V	AS iṣeto ni ërún yan
G1	PSAS_DCLK	3.3-V	AS aago iṣeto ni
G4	PSAS_CONF_DONE	3.3-V	AS iṣeto ni ṣe
H2	PSAS_CONFIGn	3.3-V	AS iṣeto ni lọwọ
G5	PSAS_DATA1	3.3-V	AS iṣeto ni data
H3	PSAS_DATA0_ASD0	3.3-V	AS iṣeto ni data
J1	PSAS_CEn	3.3-V	AS iṣeto ni ërún jeki
R12	SECURITY_MODE	2.5-V	Yipada DIP fun USB-Blaster II ti a fi sii lati firanṣẹ aṣẹ FACTORY ni agbara soke
E7	SENSE_CS0N	2.5-V	Chip atẹle agbara yan
A5	SENSE_SCK	2.5-V	Agbara atẹle aago SPI
D7	SENSE_SDI	2.5-V	Agbara atẹle data SPI ni
B6	SENSE_SDO	2.5-V	Agbara atẹle SPI data jade

FPGA iṣeto ni

Abala yii ṣapejuwe FPGA, iranti filasi, ati MAX V CPLD 5M2210 System Controller ẹrọ awọn ọna siseto atilẹyin nipasẹ igbimọ idagbasoke Cyclone VE FPGA.

Igbimọ idagbasoke Cyclone VE FPGA ṣe atilẹyin awọn ọna atunto wọnyi:

• USB-Blaster II ti a fi sinu jẹ ọna aiyipada fun atunto FPGA ni lilo Quartus II Programmer ni JTAG ipo pẹlu okun USB ti a pese.
•  Flash iranti download fun atunto FPGA lilo awọn aworan ti o ti fipamọ lati filasi iranti lori boya agbara-soke tabi titẹ awọn eto iṣeto ni titari bọtini (S1).
• USB-Blaster ita fun atunto FPGA ni lilo USB-Blaster ita ti o sopọ si JTAG pq akọsori (J4).
• EPCQ ẹrọ fun ni tẹlentẹle tabi quad-serial FPGA iṣeto ni ti o ṣe atilẹyin AS x1 tabi AS x4 eto iṣeto ni.

FPGA siseto lori ifibọ USB-Blaster II
Ọna iṣeto yii n ṣe imuse asopọ iru-B (J10), ẹrọ USB 2.0 PHY (U18), ati Altera MAX II CPLD EPM570GF100I5N (U16) lati gba iṣeto FPGA laaye nipa lilo okun USB kan. Okun USB yii so taara laarin asopọ iru-B USB lori ọkọ ati ibudo USB kan ti PC ti nṣiṣẹ sọfitiwia Quartus II.
USB-Blaster II ti a fi sii ninu MAX II CPLD EPM570GF100I5N ni deede ni oluwa JTAG pq.

Nọmba 2–3 ṣe apejuwe JTAG pq.

Awọn JTAG pq Iṣakoso DIP yipada (SW2) išakoso awọn jumpers han ni Figure 2-3.
Lati so ẹrọ kan tabi ni wiwo ninu pq, wọn ti o baamu yipada gbọdọ wa ni PA ipo. Gbe gbogbo awọn iyipada si ipo ON lati ni FPGA nikan ni pq.

Alakoso Eto MAX V CPLD 5M2210 gbọdọ wa ni JTAG pq lati lo diẹ ninu awọn ti GUI atọkun.

Tabili 2–5 ṣe atokọ awọn orukọ ifihan sikematiki USB 2.0 PHY ati awọn nọmba pin Cyclone VE FPGA ti o baamu.

Tabili 2–5. USB 2.0 PHY Awọn orukọ ifihan agbara Sikematiki ati Awọn iṣẹ (Apá 1 ti 2)

Board Reference (U18)	Sisọmu Ifihan agbara Oruko	Cyclone VE Nọmba PIN FPGA	I/O Standard	Apejuwe
C1	24M_XTALIN	—	3.3-V	Crystal oscillator igbewọle
C2	24M_XTALOUT	—	3.3-V	Crystal oscillator o wu
E1	FX2_D_N	—	3.3-V	USB 2.0 PHY data
E2	FX2_D_P	—	3.3-V	USB 2.0 PHY data
H7	FX2_FLAGA	—	3.3-V	Ẹrú FIFO o wu ipo

Tabili 2–5. USB 2.0 PHY Awọn orukọ ifihan agbara Sikematiki ati Awọn iṣẹ (Apá 2 ti 2)

Board Reference (U18)	Sisọmu Ifihan agbara Oruko	Cyclone VE Nọmba PIN FPGA	I/O Standard	Apejuwe
G7	FX2_FLAG	—	3.3-V	Ẹrú FIFO o wu ipo
H8	FX2_FLAGC	—	3.3-V	Ẹrú FIFO o wu ipo
G6	FX2_PA1	—	3.3-V	USB 2.0 PHY ibudo A ni wiwo
F8	FX2_PA2	—	3.3-V	USB 2.0 PHY ibudo A ni wiwo
F7	FX2_PA3	—	3.3-V	USB 2.0 PHY ibudo A ni wiwo
F6	FX2_PA4	—	3.3-V	USB 2.0 PHY ibudo A ni wiwo
C8	FX2_PA5	—	3.3-V	USB 2.0 PHY ibudo A ni wiwo
C7	FX2_PA6	—	3.3-V	USB 2.0 PHY ibudo A ni wiwo
C6	FX2_PA7	—	3.3-V	USB 2.0 PHY ibudo A ni wiwo
H3	FX2_PB0	—	3.3-V	USB 2.0 PHY ibudo B ni wiwo
F4	FX2_PB1	—	3.3-V	USB 2.0 PHY ibudo B ni wiwo
H4	FX2_PB2	—	3.3-V	USB 2.0 PHY ibudo B ni wiwo
G4	FX2_PB3	—	3.3-V	USB 2.0 PHY ibudo B ni wiwo
H5	FX2_PB4	—	3.3-V	USB 2.0 PHY ibudo B ni wiwo
G5	FX2_PB5	—	3.3-V	USB 2.0 PHY ibudo B ni wiwo
F5	FX2_PB6	—	3.3-V	USB 2.0 PHY ibudo B ni wiwo
H6	FX2_PB7	—	3.3-V	USB 2.0 PHY ibudo B ni wiwo
A8	FX2_PD0	—	3.3-V	USB 2.0 PHY ibudo D ni wiwo
A7	FX2_PD1	—	3.3-V	USB 2.0 PHY ibudo D ni wiwo
B6	FX2_PD2	—	3.3-V	USB 2.0 PHY ibudo D ni wiwo
A6	FX2_PD3	—	3.3-V	USB 2.0 PHY ibudo D ni wiwo
B3	FX2_PD4	—	3.3-V	USB 2.0 PHY ibudo D ni wiwo
A3	FX2_PD5	—	3.3-V	USB 2.0 PHY ibudo D ni wiwo
C3	FX2_PD6	—	3.3-V	USB 2.0 PHY ibudo D ni wiwo
A2	FX2_PD7	—	3.3-V	USB 2.0 PHY ibudo D ni wiwo
B8	FX2_RESETN	V21	3.3-V	Atunto lile USB-Blaster ti a fi sinu
F3	FX2_SCL	—	3.3-V	USB 2.0 PHY ni tẹlentẹle aago
G3	FX2_SDA	—	3.3-V	USB 2.0 PHY data ni tẹlentẹle
A1	FX2_SLRDN	—	3.3-V	Ka strobe fun ẹrú FIFO
B1	FX2_SLWRN	—	3.3-V	Kọ strobe fun ẹrú FIFO
B7	FX2_WAKEUP	—	3.3-V	USB 2.0 PHY ji ifihan agbara
G2	USB_CLK	AA23	3.3-V	USB 2.0 PHY 48-MHz ni wiwo aago

FPGA siseto lati Flash Memory

Filaṣi iranti siseto ṣee ṣe nipasẹ awọn ọna oriṣiriṣi. Ọna aiyipada ni lati lo apẹrẹ ile-iṣẹ — Portal Update Board. Yi oniru jẹ ẹya ifibọ webolupin, ti o Sin Board Update Portal web oju-iwe. Awọn web oju-iwe gba ọ laaye lati yan awọn aṣa FPGA tuntun pẹlu ohun elo, sọfitiwia, tabi mejeeji ni S-Record boṣewa ile-iṣẹ File (.flash) ki o si kọ apẹrẹ si oju-iwe ohun elo olumulo (oju-iwe 1) ti iranti filasi lori nẹtiwọki.

Ọna keji ni lati lo apẹrẹ agberu filasi parallel parallel (PFL) ti a ti kọ tẹlẹ ti o wa ninu ohun elo idagbasoke. Igbimọ idagbasoke n ṣe iṣẹ megafunction Altera PFL fun siseto iranti filasi. PFL megafunction jẹ bulọọki ti oye ti o ti ṣe eto sinu ohun elo kannaa ti eto Altera (FPGA tabi CPLD). PFL n ṣiṣẹ bi ohun elo fun kikọ si ẹrọ iranti filasi ibaramu. Apẹrẹ ti a ti kọ tẹlẹ ni megafunction PFL ti o fun ọ laaye lati kọ boya oju-iwe 0, oju-iwe 1, tabi awọn agbegbe miiran ti iranti filasi lori wiwo USB nipa lilo sọfitiwia Quartus II. Ọna yii ni a lo lati mu pada igbimọ idagbasoke si awọn eto aiyipada ile-iṣẹ rẹ.

Awọn ọna miiran lati ṣe eto iranti filasi le ṣee lo pẹlu, pẹlu ero isise Nios® II.

Fun alaye diẹ sii lori ero isise Nios II, tọka si oju-iwe Processor Nios II ti Altera webojula.
Lori boya agbara-soke tabi nipa titẹ bọtini titari iṣeto ni eto, PGM_CONFIG (S1), MAX V CPLD 5M2210 System Controller's PFL tunto FPGA lati iranti filasi. Megafunction PFL n ka data 16-bit lati iranti filasi ati yi pada si ọna kika palolo iyara (FPP). Awọn data 16-bit yii lẹhinna kọ si awọn pinni iṣeto ni igbẹhin ni FPGA lakoko iṣeto.
Titẹ bọtini titari PGM_CONFIG (S1) n gbe FPGA pẹlu oju-iwe ohun elo kan ti o da lori eyiti PGM_LED [2: 0] (D25, D26, D27) n tan imọlẹ. Tabili 2–6 ṣe atokọ apẹrẹ ti o gbe nigbati o ba tẹ bọtini titari PGM_CONFIG.

Tabili 2–6. Eto PGM_LED (1)

PGM_LED0 (D25)	PGM_LED1 (D26)	PGM_LED2 (D27)	Apẹrẹ
ON	PAA	PAA	Factory hardware
PAA	ON	PAA	Ohun elo olumulo 1
PAA	PAA	ON	Ohun elo olumulo 2

Nọmba 2-4 fihan iṣeto PFL.

Fun alaye diẹ sii lori awọn koko-ọrọ wọnyi, tọka si awọn iwe aṣẹ ti o yẹ:

• Portal Update Board, apẹrẹ PFL, ati ibi ipamọ maapu iranti filasi, tọka si Itọsọna olumulo Apo Idagbasoke Cyclone VE FPGA.
• PFL megafunction, tọka si Parallel Flash Loader Megafunction User Itọsọna.

Eto FPGA lori Ita USB-Blaster
Awọn JTAG akọsori pq n pese ọna miiran fun atunto FPGA nipa lilo ẹrọ USB-Blaster ita pẹlu Quartus II Programmer ti nṣiṣẹ lori PC kan. Lati yago fun ariyanjiyan laarin JTAG awọn oluwa, USB-Blaster ti a fi sinu jẹ alaabo laifọwọyi nigbati o ba so USB-Blaster ita si JTAG pq nipasẹ JTAG pq akọsori.

Eto FPGA nipa lilo EPCQ
Ẹrọ ECPQ ti o ni iye owo kekere pẹlu iranti ti kii ṣe iyipada ṣe ẹya wiwo-pin mẹfa ti o rọrun ati ifosiwewe fọọmu kekere kan. ECPQ ṣe atilẹyin awọn ipo AS x1 ati x4. Nipa aiyipada, igbimọ yii ni eto eto iṣeto FPP kan. Lati le ṣeto ero atunto si ipo AS, atunṣe resistor nilo lati ṣee. Ṣe atunto eto MSEL nipa lilo MSEL DIP yipada (SW1) lati yi ero iṣeto naa pada.

Nọmba 2-5 fihan asopọ laarin EPCQ ati Cyclone VE FPGA.

Olusin 2–5. EPCQ iṣeto ni

Awọn eroja ipo
Igbimọ idagbasoke pẹlu awọn LED ipo. Yi apakan apejuwe awọn eroja ipo.

Tabili 2–7 ṣe atokọ awọn itọkasi igbimọ LED, awọn orukọ, ati awọn apejuwe iṣẹ.

Tabili 2–7. Awọn LED-pato Igbimọ (Apakan 1 ti 2)

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	I/O Standard	Apejuwe
D35	Agbara	5.0-V	LED bulu. Ṣe itanna nigbati agbara 5.0 V n ṣiṣẹ.
D19	MAX_CONF_DONE	2.5-V	LED alawọ ewe. Ṣe itanna nigbati FPGA ti ni atunto ni ifijišẹ. Iwakọ nipasẹ MAX V CPLD 5M2210 System Adarí.
D17	MAX_ERROR	2.5-V	LED pupa. Imọlẹ nigbati MAX V CPLD 5M2210 System Adarí kuna lati tunto FPGA. Iwakọ nipasẹ MAX V CPLD 5M2210 System Adarí.
D18	MAX_LOAD	2.5-V	LED alawọ ewe. Itanna nigbati MAX V CPLD 5M2210 System Adarí ti wa ni actively atunto FPGA. Iwakọ nipasẹ MAX V CPLD 5M2210 System Adarí.
D25 D26 D27	PGM_LED[0] PGM_LED[1] PGM_LED[2]	2.5-V	Awọn LED alawọ ewe. Ṣe itanna lati tọka iru oju-iwe ohun elo ti n gbe lati iranti filasi nigbati o tẹ bọtini titari PGM_SEL.

Tabili 2–7. Awọn LED-pato Igbimọ (Apakan 2 ti 2)

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	I/O Standard	Apejuwe
D11, D12 D13, D14	JTAG_RX, JTAG_TX SC_RX, SC_TX	2.5-V	Awọn LED alawọ ewe. Ṣe itanna lati tọka USB-Blaster II gbigba ati atagba awọn iṣẹ ṣiṣe.
D1	ENETA_LED_TX	2.5-V	LED alawọ ewe. Ṣe itanna lati tọka iṣẹ ṣiṣe atagba Ethernet PHY. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D2	ENETA_LED_RX	2.5-V	LED alawọ ewe. Ṣe itanna lati tọka iṣẹ ṣiṣe gbigba Ethernet PHY. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D5	ENETA_LED_LINK10	2.5-V	LED alawọ ewe. Imọlẹ lati tọkasi Ethernet ti sopọ ni iyara asopọ 10 Mbps. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D4	ENETA_LED_LINK100	2.5-V	LED alawọ ewe. Imọlẹ lati tọkasi Ethernet ti sopọ ni iyara asopọ 100 Mbps. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D3	ENETA_LED_LINK1000	2.5-V	LED alawọ ewe. Imọlẹ lati tọkasi Ethernet ti sopọ ni iyara asopọ 1000 Mbps. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D19	ENETB_LED_TX	2.5-V	LED alawọ ewe. Ṣe itanna lati tọka iṣẹ ṣiṣe atagba Ethernet PHY B. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D22	ENETB_LED_RX	2.5-V	LED alawọ ewe. Ṣe itanna lati tọka iṣẹ ṣiṣe gbigba Ethernet PHY B. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D24	NETB_LED_LINK10	2.5-V	LED alawọ ewe. Imọlẹ lati tọkasi Ethernet B ti o sopọ ni iyara asopọ 10 Mbps. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D20	NETB_LED_LINK100	2.5-V	LED alawọ ewe. Imọlẹ lati tọkasi Ethernet B ti o sopọ ni iyara asopọ 100 Mbps. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D21	NETB_LED_LINK1000	2.5-V	LED alawọ ewe. Imọlẹ lati tọkasi Ethernet B ti o sopọ ni iyara asopọ 1000 Mbps. Ìṣó nipasẹ awọn Marvell 88E1111 PHY.
D15, D16	USB_UART_TX_TOGGLE, USB_UART_RX_TOGGLE	2.5-V	LED alawọ ewe. Awọn itanna lati tọka USB_UART gbigba ati atagba awọn iṣẹ ṣiṣe.
D23, D24	UART_RXD_LED, UART_TXD_LED	2.5-V	LED alawọ ewe. Itanna lati tọka UART gba ati atagba akitiyan.
D3	HSMA_PRSNTn	3.3-V	LED alawọ ewe. Imọlẹ nigbati HSMC ibudo ni a ọkọ tabi USB edidi-ni iru awọn ti pin 160 di ilẹ. Ìṣó nipasẹ awọn fi-ni kaadi.

Eto Awọn eroja
Igbimọ idagbasoke pẹlu ọpọlọpọ awọn oriṣi awọn eroja iṣeto. Abala yii ṣe apejuwe awọn eroja iṣeto wọnyi:

• Board eto DIP yipada
• JTAG eto DIP yipada
• Sipiyu tun titari bọtini
• MAX V tun titari bọtini
• Bọtini titari iṣeto ni eto
• Eto yan bọtini titari

Fun alaye diẹ sii nipa awọn eto aiyipada ti awọn iyipada DIP, tọka si Itọsọna olumulo Apo Idagbasoke Cyclone VE FPGA.

Board Eto DIP Yipada
Awọn eto igbimọ DIP yipada (SW4) n ṣakoso ọpọlọpọ awọn ẹya ni pato si igbimọ ati MAX V CPLD 5M2210 System Adarí kannaa oniru. Tabili 2-8 ṣe atokọ awọn iṣakoso iyipada ati awọn apejuwe.

Tabili 2–8. Board Eto DIP Yipada idari

Yipada	Sisọmu Ifihan agbara Oruko	Apejuwe
1	CLK_SEL	ON : Yan aago oscillator eto PA: Yan aago titẹ sii SMA
2	CLK_GBANI	ON : Muu on-board oscillator PA: Mu on-board oscillator ṣiṣẹ
3	FACTORY_LOAD	ON : Fifuye apẹrẹ olumulo lati filasi ni agbara soke PA: Fifuye apẹrẹ ile-iṣẹ lati filasi ni agbara soke
4	SECURITY_MODE	ON : USB-Blaster II ti a fi sinu firanṣẹ aṣẹ FACTORY ni agbara soke. PAA: USB-Blaster II ti a fi sinu ko fi aṣẹ FACTORY ranṣẹ ni agbara soke.

JTAG Pq Iṣakoso DIP Yipada
Awọn JTAG DIP iṣakoso pq yipada (SW2) boya yọ kuro tabi pẹlu awọn ẹrọ inu J ti nṣiṣe lọwọTAG pq. Cyclone VE FPGA nigbagbogbo wa ninu JTAG pq. Tabili 2-9 ṣe atokọ awọn iṣakoso iyipada ati awọn apejuwe rẹ.

Tabili 2–9. JTAG Pq Iṣakoso DIP Yipada

Yipada	Sisọmu Ifihan agbara Oruko	Apejuwe
1	5M2210_JTAG_EN	ON: Fori MAX V CPLD 5M2210 System Adarí PA: MAX V CPLD 5M2210 System Adarí in-pq
2	HSMC_JTAG_EN	ON : Fori HSMC ibudo PA: HSMC ibudo ni-pq
3	FAN_FORCE_ON	ON : Jeki àìpẹ PA : Pa àìpẹ
4	NI ipamọ	Ni ipamọ

Sipiyu Tun Titari Button
Bọtini titari atunto Sipiyu, CPU_RESETn (S4), jẹ titẹ sii si pin Cyclone VE FPGA DEV_CLRn ati pe o jẹ I/O ṣiṣi silẹ lati ọdọ MAX V CPLD Eto Adarí. Bọtini titari yii jẹ atunto aiyipada fun mejeeji FPGA ati ọgbọn CPLD. Alakoso Eto MAX V CPLD 5M2210 tun wakọ bọtini titari yii lakoko atunto-agbara (POR).

MAX V Tun Titari Bọtini
Bọtini titari atunto MAX V, MAX_RESETn (S3), jẹ titẹ sii si MAX V CPLD 5M2210 Eto Adarí. Bọtini titari yii jẹ atunto aiyipada fun ọgbọn CPLD.

Bọtini Titari Iṣeto Eto
Bọtini titari iṣeto ni eto, PGM_CONFIG (S1), jẹ titẹ sii si MAX V CPLD 5M2210 System Adarí. Eleyi input fi agbara mu a FPGA atunto lati filasi iranti. Ipo ti o wa ninu iranti filasi da lori awọn eto ti PGM_LED[2:0], eyiti o jẹ iṣakoso nipasẹ eto yan bọtini titari, PGM_SEL. Awọn eto to wulo pẹlu PGM_LED0, PGM_LED1, tabi PGM_LED2 lori awọn oju-iwe mẹta ni iranti filaṣi ti a fi pamọ fun awọn apẹrẹ FPGA.

Eto Yan Bọtini Titari
Awọn eto yan titari bọtini, PGM_SEL (S2), jẹ ẹya input to MAX V CPLD 5M2210 System Adarí. Bọtini titari yii yi ọna PGM_LED [2: 0] pada ti o yan ipo wo ni iranti filasi ti a lo lati tunto FPGA. Tọkasi Tabili 2–6 fun PGM_LED[2:0] awọn itumọ ti ọkọọkan.

Aago Circuit
Abala yii ṣe apejuwe awọn igbewọle aago ati awọn igbejade igbimọ.

Lori-ọkọ Oscillators
Igbimọ idagbasoke naa pẹlu awọn oscillators pẹlu igbohunsafẹfẹ ti 50-MHz, 100-MHz, ati oscillator eto kan.

Nọmba 2-6 fihan awọn igbohunsafẹfẹ aiyipada ti gbogbo awọn aago ita ti n lọ si igbimọ idagbasoke Cyclone VE FPGA.

Olusin 2–6. Cyclone VE FPGA Development Board Agogo

Tabili 2–10 ṣe atokọ awọn oscillators, boṣewa I/O rẹ, ati voltages beere fun idagbasoke ọkọ.

Tabili 2-10. Lori-ọkọ Oscillators

Orisun	Sisọmu Ifihan agbara Oruko	Igbohunsafẹfẹ	I/O Standard	Cyclone VE Nọmba PIN FPGA	Ohun elo
U4	CLKIN_50_FPGA_TOP	50.000 MHz	Nikan-Opin	L14	Oke ati eti ọtun
	CLKIN_50_FPGA_RIGHT			P22
X3	CLK_CONFIG	100.000 MHz	2.5V CMOS	—	Fast FPGA iṣeto ni
X1 ati U3 (fifipamọ)	DIFF_CLKIN_TOP_125_P	125.000 MHz	LVDS	L15	Oke ati isalẹ eti
	DIFF_CLKIN_TOP_125_N			K15
	DIFF_CLKIN_BOT_125_P			AB17
	DIFF_CLKIN_BOT_125_N			AB18

Pa-Board Aago Input/O wu
Igbimọ idagbasoke naa ni titẹ sii ati awọn aago iṣejade eyiti o le wakọ sori igbimọ naa. Awọn aago iṣejade le ṣe eto si awọn ipele oriṣiriṣi ati awọn iṣedede I/O ni ibamu si sipesifikesonu ẹrọ FPGA.

Tabili 2–11 ṣe atokọ awọn igbewọle aago fun igbimọ idagbasoke.

Tabili 2-11. Awọn igbewọle Aago Paa-Board

Orisun	Ifihan agbara sikematiki Oruko	I/O Standard	Afẹfẹ V E Pin FPGA Nọmba	Apejuwe
SMA	CLKIN_SMA_P	LVDS	—	Iṣagbewọle si olufẹ-jade LVDS.
	CLKIN_SMA_N	LVDS	—
Samtec HSMC	HSMA_CLK_IN0	2.5-V	AB16	Iṣagbewọle ọkan-opin lati okun HSMC ti a fi sii tabi igbimọ.
Samtec HSMC	HSMA_CLK_IN_P1	LVDS / 2.5-V	AB14	Iṣagbewọle LVDS lati inu okun HSMC ti a fi sii tabi igbimọ. Tun le ṣe atilẹyin awọn igbewọle 2x LVTTL.
	HSMA_CLK_IN_N1	LVDS/LVTTL	AC14
Samtec HSMC	HSMA_CLK_IN_P2	LVDS/LVTTL	Y15	Iṣagbewọle LVDS lati inu okun HSMC ti a fi sii tabi igbimọ. Tun le ṣe atilẹyin awọn igbewọle 2x LVTTL.
	HSMA_CLK_IN_N2	LVDS/LVTTL	AA15

Tabili 2–12 ṣe atokọ awọn abajade aago fun igbimọ idagbasoke.

Tabili 2-12. Pa-Board Awọn abajade

Orisun	Ifihan agbara sikematiki Oruko	I/O Standard	Afẹfẹ V E Pin FPGA Nọmba	Apejuwe
Samtec HSMC	HSMA_CLK_OUT0	2.5V CMOS	AJ14	Ijade FPGA CMOS (tabi GPIO)
Samtec HSMC	HSMA_CLK_OUT_P1	LVDS / 2.5V CMOS	AE22	Ijade LVDS. Tun le ṣe atilẹyin awọn abajade CMOS 2x.
	HSMA_CLK_OUT_N1	LVDS / 2.5V CMOS	AF23
Samtec HSMC	HSMA_CLK_OUT_P2	LVDS / 2.5V CMOS	AG23	Ijade LVDS. Tun le ṣe atilẹyin awọn abajade CMOS 2x.
	HSMA_CLK_OUT_N2	LVDS / 2.5V CMOS	AH22
SMA	CLKOUT_SMA	2.5V CMOS	F9	Ijade FPGA CMOS (tabi GPIO)

Gbogbogbo User Input / o wu
Abala yii ṣe apejuwe wiwo olumulo I/O si FPGA, pẹlu awọn bọtini titari, awọn iyipada DIP, Awọn LED, ati LCD ihuwasi.

Awọn bọtini Titari Olumulo
Igbimọ idagbasoke pẹlu awọn bọtini titari asọye olumulo mẹta. Fun alaye lori eto ati awọn bọtini titari atunto ailewu, tọka si “Awọn ohun elo Eto” ni oju-iwe 2–16. Awọn itọkasi igbimọ S5, S6, S7, ati S8 jẹ awọn bọtini titari fun ṣiṣakoso awọn aṣa FPGA ti o gbe sinu ẹrọ Cyclone VE FPGA. Nigbati o ba tẹ ki o si mu mọlẹ awọn yipada, awọn ẹrọ PIN ti ṣeto si kannaa 0; nigbati o ba tu awọn yipada, awọn ẹrọ pin pin si kannaa 1. Ko si ọkọ-kan pato awọn iṣẹ fun awọn wọnyi gbogboogbo olumulo titari bọtini.

Tabili 2–13 ṣe atokọ awọn orukọ ifihan agbara sikematiki bọtini titari ti olumulo ati awọn nọmba pin Cyclone VE FPGA ti o baamu.

Tabili 2-13. Bọtini Titari-itumọ olumulo Awọn orukọ ifihan agbara ifihan ati awọn iṣẹ

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Pin Nọmba	I/O Standard
S5	USER_PB0	AB12	2.5-V
S6	USER_PB1	AB13	2.5-V
S7	USER_PB2	AF13	2.5-V
S8	USER_PB3	AG12	2.5-V

Olumulo-telẹ DIP Yipada
Board itọkasi SW3 ni a mẹrin-pin DIP yipada. Yi yipada jẹ asọye olumulo ati pese afikun iṣakoso igbewọle FPGA. Nigbati iyipada ba wa ni ipo PA, a yan ọgbọn kan 1. Nigbati iyipada ba wa ni ipo ON, a yan ọgbọn kan 0. Ko si awọn iṣẹ igbimọ-pato fun iyipada yii.

Tabili 2–14 ṣe atokọ ti olumulo-telẹ DIP yipada awọn ami ifihan sikematiki ati awọn nọmba pin Cyclone VE FPGA ti o baamu wọn.

Tabili 2-14. Olumulo-itumọ DIP Yipada Sikematiki Awọn orukọ ifihan agbara ati Awọn iṣẹ

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Pin Nọmba	I/O Standard
S5	USER_PB0	AB12	2.5-V
S6	USER_PB1	AB13	2.5-V
S7	USER_PB2	AF13	2.5-V
S8	USER_PB3	AG12	2.5-V

Olumulo-telẹ LED
Igbimọ idagbasoke pẹlu gbogbogbo ati awọn LED asọye olumulo HSMC. Yi apakan apejuwe gbogbo olumulo-telẹ LED. Fun alaye lori ọkọ ni pato tabi awọn LED ipo, tọka si “Awọn eroja Ipo” ni oju-iwe 2–15.

Awọn LED gbogbogbo
Awọn itọkasi igbimọ D28 nipasẹ D31 jẹ awọn LED asọye olumulo mẹrin. Ipo ati awọn ifihan agbara n ṣatunṣe aṣiṣe ni a gbe lọ si awọn LED lati awọn apẹrẹ ti a kojọpọ sinu Cyclone VE FPGA. Wiwakọ ọgbọn kan 0 lori ibudo I/O titan LED lakoko wiwakọ ọgbọn kan 1 pa LED naa. Ko si awọn iṣẹ igbimọ-pato fun awọn LED wọnyi.

Tabili 2–15 ṣe atokọ awọn orukọ ifihan agbara sikematiki LED gbogbogbo ati awọn nọmba pin Cyclone VE FPGA ti o baamu.

Tabili 2-15. Awọn orukọ ifihan agbara Sikematiki LED Gbogbogbo ati Awọn iṣẹ

Ọkọ Itọkasi	Sisọmu Orukọ ifihan agbara	Cyclone VE FPGA Nọmba PIN	I/O Standard
D28	USER_LED0	AK3	2.5-V
D29	USER_LED1	AJ4	2.5-V
D30	USER_LED2	AJ5	2.5-V
D31	USER_LED3	AK6	2.5-V

Awọn LED HSMC
Awọn itọkasi igbimọ D20 ati D21 jẹ awọn LED fun ibudo HSMC. Ko si awọn iṣẹ igbimọ kan fun awọn LED HSMC. Awọn LED jẹ aami TX ati RX, ati pe wọn pinnu lati ṣafihan sisan data si ati lati awọn kaadi ọmọbinrin ti o sopọ. Awọn LED ti wa ni idari nipasẹ ẹrọ Cyclone VE FPGA.

Tabili 2–16 ṣe atokọ awọn orukọ ifihan agbara sikematiki LED HSMC ati awọn nọmba pin Cyclone VE FPGA ti o baamu wọn.

Tabili 2-16. Awọn orukọ ifihan agbara Sikematiki LED HSMC ati Awọn iṣẹ

Ọkọ Itọkasi	Sisọmu Orukọ ifihan agbara	Cyclone VE FPGA Pin Nọmba	I/O Standard
D1	HSMC_RX_LED	AH12	2.5-V
D2	HSMC_TX_LED	AH11	2.5-V

LCD ohun kikọ
Igbimọ idagbasoke naa pẹlu ọkan 14-pin 0.1 ″ ipolowo akọsori ila-meji ti o ni atọkun si laini 2 × 16 ohun kikọ Lumex LCD. LCD ohun kikọ ni o ni a 14-pin receptacle ti o gbeko taara si awọn ọkọ ká 14-pin akọsori, ki o le wa ni awọn iṣọrọ kuro fun wiwọle si irinše labẹ awọn ifihan. O tun le lo akọsori fun n ṣatunṣe aṣiṣe tabi awọn idi miiran.

Tabili 2-17 ṣe akopọ awọn iṣẹ iyansilẹ pin LCD ohun kikọ. Awọn orukọ ifihan agbara ati awọn itọnisọna jẹ ibatan si ẹrọ Cyclone VE FPGA.

Tabili 2-17. Awọn iṣẹ iyansilẹ Pin LCD ohun kikọ, Awọn orukọ ifihan agbara Sikematiki, ati Awọn iṣẹ

Ọkọ Itọkasi (J14)	Orukọ ifihan agbara sikematiki	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
7	LCD_DATA0	AJ7	2.5-V	LCD data akero
8	LCD_DATA1	AK7	2.5-V	LCD data akero
9	LCD_DATA2	AJ8	2.5-V	LCD data akero
10	LCD_DATA3	AK8	2.5-V	LCD data akero
11	LCD_DATA4	AF9	2.5-V	LCD data akero
12	LCD_DATA5	AG9	2.5-V	LCD data akero
13	LCD_DATA6	AH9	2.5-V	LCD data akero
14	LCD_DATA7	AJ9	2.5-V	LCD data akero

Tabili 2-17. Awọn iṣẹ iyansilẹ Pin LCD ohun kikọ, Awọn orukọ ifihan agbara Sikematiki, ati Awọn iṣẹ

Ọkọ Itọkasi (J14)	Orukọ ifihan agbara sikematiki	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
4	LCD_D_Cn	AK11	2.5-V	LCD data tabi pipaṣẹ yan
5	LCD_WEn	AK10	2.5-V	LCD kikọ jeki
6	LCD_CSn	AJ12	2.5-V	LCD ërún yan

Tabili 2–18 ṣe atokọ awọn asọye pin LCD, ati pe o jẹ yiyan lati iwe data Lumex.

Tabili 2-18. LCD Pin Awọn itumọ ati Awọn iṣẹ

Pin Nọmba	Aami	Ipele	Išẹ
1	VDD	—	Ibi ti ina elekitiriki ti nwa	5 V
2	VSS	—		GND (0V)
3	V0	—		Fun LCD wakọ
4	RS	H/L	Forukọsilẹ yan ifihan agbara H: Data input L: Iṣagbewọle itọnisọna
5	R/W	H/L	H: Data kika (modulu si MPU) L: Kọ data (MPU si module)
6	E	H, H si L	Mu ṣiṣẹ
7–14	DB0–DB7	H/L	Data akero-software yiyan 4-bit tabi 8-bit mode

Fun alaye diẹ sii gẹgẹbi akoko, maapu ohun kikọ, awọn itọnisọna wiwo, ati awọn iwe miiran ti o jọmọ, ṣabẹwo www.lumex.com.

Akọsori yokokoro
Igbimọ idagbasoke yii pẹlu awọn akọle yokokoro 2 × 8 meji fun awọn idi yokokoro. Ona FPGA I/O taara si akọsori fun idanwo apẹrẹ, n ṣatunṣe aṣiṣe, tabi ijẹrisi iyara.

Tabili 2–19 ṣe akopọ awọn iṣẹ iyansilẹ PIN akọsori yokokoro, awọn orukọ ifihan agbara, ati awọn iṣẹ.

Tabili 2–19. Awọn iṣẹ iyansilẹ Pin akọsori yokokoro, Awọn orukọ ifihan agbara Sikematiki, ati Awọn iṣẹ (Apá 1 ti 2)

Ọkọ Itọkasi	Ifihan agbara sikematiki Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
Ṣatunkọ Akọsori (J15)
1	HEADER_D0	H21	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan
5	HEADER_D1	G21	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan
9	HEADER_D2	G22	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan
13	HEADER_D3	E26	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan
4	HEADER_D4	E25	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan
8	HEADER_D5	C27	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan
12	HEADER_D6	C26	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan

Tabili 2–19. Awọn iṣẹ iyansilẹ Pin akọsori yokokoro, Awọn orukọ ifihan agbara Sikematiki, ati Awọn iṣẹ (Apá 2 ti 2)

Ọkọ Itọkasi	Ifihan agbara sikematiki Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
16	HEADER_D7	B27	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan
Ṣatunkọ Akọsori (J16)
1 ati 2	HEADER_P0 ati HEADER_N0	H25 ati H26	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
3 ati 4	HEADER_P1 ati HEADER_N1	P20 ati N20	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
7 ati 8	HEADER_P2 ati HEADER_N2	J22 ati J23	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
9 ati 10	HEADER_P3 ati HEADER_N3	D28 ati D29	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
13 ati 14	HEADER_P4 ati HEADER_N4	E27 ati D27	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
15 ati 16	HEADER_P5 ati HEADER_N5	H24 ati J25	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan

Irinše ati awọn atọkun
Abala yii ṣe apejuwe awọn ibudo ibaraẹnisọrọ ti igbimọ idagbasoke ati awọn kaadi wiwo ojulumo si ẹrọ Cyclone VE FPGA. Igbimọ idagbasoke n ṣe atilẹyin awọn ebute ibaraẹnisọrọ atẹle wọnyi:

• RS-232 Serial UART
• 10/100/1000 àjọlò
• HSMC
• USB UART

10/100/1000 àjọlò
Igbimọ idagbasoke naa ṣe atilẹyin meji 10/100/1000 mimọ-T Ethernet nipa lilo Marvell 88E1111 PHY ita meji ati iṣẹ Altera Triple-Speed ​​Ethernet MegaCore MAC. Awọn atọkun PHY-si-MAC gba wiwo RGMII. Iṣẹ MAC gbọdọ wa ni ipese ni FPGA fun awọn ohun elo netiwọki aṣoju. Marvell 88E1111 PHY nlo awọn afowodimu agbara 2.5-V ati 1.0-V ati pe o nilo aago itọkasi 25-MHz ti o wa lati oscillator igbẹhin kan. Awọn atọkun PHY si awoṣe RJ45 pẹlu awọn oofa inu ti o le ṣee lo fun wiwakọ awọn laini idẹ pẹlu ijabọ Ethernet.

Nọmba 2-7 fihan wiwo RGMII laarin FPGA (MAC) ati Marvell 88E1111 PHY.

Olusin 2–7. Atọka RGMII laarin FPGA (MAC) ati Marvell 88E1111 PHY

Tabili 2–20 ṣe atokọ awọn iṣẹ iyansilẹ ni wiwo Ethernet PHY

Tabili 2-20. Awọn iṣẹ Pinpin Ethernet PHY, Awọn orukọ ifihan agbara ati Awọn iṣẹ (Apá 1 ti 3)

Ọkọ Itọkasi	Ifihan agbara sikematiki Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
16	HEADER_D7	B27	1.5-V	Ifihan agbara-opin fun awọn idi yokokoro nikan
Ṣatunkọ Akọsori (J16)
1 ati 2	HEADER_P0 ati HEADER_N0	H25 ati H26	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
3 ati 4	HEADER_P1 ati HEADER_N1	P20 ati N20	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
7 ati 8	HEADER_P2 ati HEADER_N2	J22 ati J23	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
9 ati 10	HEADER_P3 ati HEADER_N3	D28 ati D29	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
13 ati 14	HEADER_P4 ati HEADER_N4	E27 ati D27	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan
15 ati 16	HEADER_P5 ati HEADER_N5	H24 ati J25	2.5-V	Awọn ifihan agbara afarape fun awọn idi yokokoro nikan

Tabili 2-20. Awọn iṣẹ Pinpin Ethernet PHY, Awọn orukọ ifihan agbara ati Awọn iṣẹ (Apá 2 ti 3)

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
33	ENETA_MDI_P1	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
34	ENETA_MDI_N1	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
39	ENETA_MDI_P2	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
41	ENETA_MDI_N2	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
42	ENETA_MDI_P3	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
43	ENETA_MDI_N3	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
Àjọlò PHY B (U11)
8	ENETB_GTX_CLK	E28	2.5-V CMOS	125-MHz RGMII atagba aago
23	ENETB_INTN	K22	2.5-V CMOS	Idaduro akero isakoso
60	ENETB_LED_DUPLEX	—	2.5-V CMOS	Ile oloke meji tabi ijamba LED. Ko lo
70	ENETB_LED_DUPLEX	—	2.5-V CMOS	Ile oloke meji tabi ijamba LED. Ko lo
76	NETB_LED_LINK10	—	2.5-V CMOS	10-Mb ọna asopọ LED
74	NETB_LED_LINK100	—	2.5-V CMOS	100-Mb ọna asopọ LED
73	NETB_LED_LINK1000	—	2.5-V CMOS	1000-Mb ọna asopọ LED
58	ENETB_LED_RX	—	2.5-V CMOS	RX data ti nṣiṣe lọwọ LED
69	ENETB_LED_RX	—	2.5-V CMOS	RX data ti nṣiṣe lọwọ LED
68	ENETB_LED_TX	—	2.5-V CMOS	TX data ti nṣiṣe lọwọ LED
25	ENETB_MDC	A29	2.5-V CMOS	Aago data akero isakoso
24	ENETB_MDIO	L23	2.5-V CMOS	Data akero isakoso
28	ENETB_RESETN	M21	2.5-V CMOS	Atunto ẹrọ
2	ENETB_RX_CLK	R23	2.5-V CMOS	RGMII gbigba aago
95	ENETB_RX_D0	F25	2.5-V CMOS	RGMII gba data akero
92	ENETB_RX_D1	F26	2.5-V CMOS	RGMII gba data akero
93	ENETB_RX_D2	R20	2.5-V CMOS	RGMII gba data akero
91	ENETB_RX_D3	T21	2.5-V CMOS	RGMII gba data akero
94	ENETB_RX_DV	L24	2.5-V CMOS	RGMII gba data wulo
11	ENETB_TX_D0	F29	2.5-V CMOS	RGMII atagba data akero
12	ENETB_TX_D1	D30	2.5-V CMOS	RGMII atagba data akero
14	ENETB_TX_D2	C30	2.5-V CMOS	RGMII atagba data akero
16	ENETB_TX_D3	F28	2.5-V CMOS	RGMII atagba data akero
9	ENETB_TX_EN	B29	2.5-V CMOS	RGMII atagba sise
55	ENETB_XTAL_25MHZ	—	2.5-V CMOS	25-MHz RGMII atagba aago
29	ENETB_MDI_P0	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
31	ENETB_MDI_N0	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
33	ENETB_MDI_P1	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
34	ENETB_MDI_N1	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
39	ENETB_MDI_P2	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
41	ENETB_MDI_N2	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo

Tabili 2-20. Awọn iṣẹ Pinpin Ethernet PHY, Awọn orukọ ifihan agbara ati Awọn iṣẹ (Apá 3 ti 3)

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
42	ENETB_MDI_P3	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo
43	ENETB_MDI_N3	—	2.5-V CMOS	Media ti o gbẹkẹle ni wiwo

HSMC

• Igbimọ idagbasoke ṣe atilẹyin wiwo HSMC kan. Ni wiwo HSMC ṣe atilẹyin wiwo SPI4.2 ni kikun (awọn ikanni LVDS 17), titẹ sii mẹta ati awọn aago iṣejade, bakanna bi J.TAG ati awọn ifihan agbara SMB. Awọn ikanni LVDS le ṣee lo fun ifihan CMOS tabi LVDS.
• HSMC jẹ sipesifikesonu ṣiṣi ti Altera, eyiti o fun ọ laaye lati faagun iṣẹ ṣiṣe ti igbimọ idagbasoke nipasẹ afikun ti awọn kaadi ọmọbinrin (HSMCs).
• Fun alaye diẹ ẹ sii nipa sipesifikesonu HSMC gẹgẹbi awọn iṣedede ifihan, iduroṣinṣin ifihan, awọn asopọ ibaramu, ati alaye ẹrọ, tọka si Kaadi Iyara Mezzanine giga (HSMC) Itọnisọna pato.
• Asopọmọra HSMC ni apapọ awọn pinni 172, pẹlu awọn pinni ifihan agbara 120, awọn pinni agbara 39, ati awọn pinni ilẹ 13. Awọn pinni ilẹ wa laarin awọn ori ila meji ti ifihan agbara ati awọn pinni agbara, ṣiṣe mejeeji bi apata ati itọkasi kan. Asopọ agbalejo HSMC da lori 0.5 mm-pitch QSH/QTH idile ti iyara-giga, awọn asopọ igbimọ-si-ọkọ lati Samtec. Awọn ile-ifowopamọ mẹta wa ni asopọ yii. Bank 1 ni gbogbo pinni kẹta kuro bi a ti ṣe ni jara QSH-DP/QTH-DP. Bank 2 ati banki 3 ni gbogbo awọn pinni ti o kun bi a ti ṣe ni jara QSH/QTH. Niwọn igba ti igbimọ idagbasoke Cyclone VE FPGA kii ṣe igbimọ transceiver, awọn pinni transceiver ti HSMC ko ni asopọ si ẹrọ Cyclone VE FPGA.

olusin 2–8 fihan ifowo akanṣe ti awọn ifihan agbara pẹlu ọwọ si Samtec asopo ká mẹta bèbe.

Olusin 2–8. Ifihan agbara HSMC ati Bank aworan atọka

HSMC ni wiwo ni o ni siseto bi-itọnisọna ti mo ti / Eyin pinni ti o le ṣee lo bi 2.5-V LVCMOS, eyi ti o jẹ 3.3-V LVTTL-ibaramu. Awọn pinni wọnyi tun le ṣee lo bi ọpọlọpọ awọn iṣedede I/O iyatọ pẹlu, ṣugbọn kii ṣe opin si, LVDS, mini-LVDS, ati RSDS pẹlu to awọn ikanni onimeji-meji 17.
Gẹgẹbi a ti ṣe akiyesi ninu Kaadi Iyara Mezzanine giga (HSMC) Iwe-itumọ pato, LVDS ati awọn iṣedede I/O ti o pari-ẹyọkan jẹ iṣeduro lati ṣiṣẹ nigbati o ba dapọ ni ibamu si boya jeneriki pin-opin ẹyọkan tabi pin-jade iyatọ jeneriki.

Tabili 2–21 ṣe atokọ awọn iṣẹ iyansilẹ ni wiwo HSMC, awọn orukọ ifihan, ati awọn iṣẹ.

Tabili 2-21. Awọn iyansilẹ Pin Ni wiwo HSMC, Awọn orukọ Ififihan Sikematiki, ati Awọn iṣẹ (Apá 1 ti 3)

Ọkọ Itọkasi (J7)	Sisọmu Ifihan agbara Oruko	Afẹfẹ V E Pin FPGA Nọmba	I/O Standard	Apejuwe
33	HSMC_SDA	AB22	2.5-V CMOS	Data ni tẹlentẹle isakoso
34	HSMC_SCL	AC22	2.5-V CMOS	Aago ni tẹlentẹle isakoso
35	JTAG_TCK	AC7	2.5-V CMOS	JTAG aago ifihan agbara
36	HSMC_JTAG_TMS	—	2.5-V CMOS	JTAG mode yan ifihan agbara
37	HSMC_JTAG_TDO	—	2.5-V CMOS	JTAG o wu data
38	JTAC_FPGA_TDO_RETIMER	—	2.5-V CMOS	JTAG data igbewọle
39	HSMC_CLK_OUT0	AJ14	2.5-V CMOS	Ifiṣootọ aago CMOS jade
40	HSMC_CLK_IN0	AB16	2.5-V CMOS	Ifiṣootọ aago CMOS ni
41	HSMC_D0	AH10	2.5-V CMOS	Iyasọtọ CMOS I/O bit 0
42	HSMC_D1	AJ10	2.5-V CMOS	Iyasọtọ CMOS I/O bit 1
43	HSMC_D2	Y13	2.5-V CMOS	Iyasọtọ CMOS I/O bit 2
44	HSMC_D3	AA14	2.5-V CMOS	Iyasọtọ CMOS I/O bit 3
47	HSMC_TX_D_P0	AK27	LVDS tabi 2.5-V	LVDS TX bit 0 tabi CMOS bit 4
48	HSMC_RX_D_P0	Y16	LVDS tabi 2.5-V	LVDS RX bit 0 tabi CMOS bit 5
49	HSMC_TX_D_N0	AK28	LVDS tabi 2.5-V	LVDS TX bit 0n tabi CMOS bit 6
50	HSMC_RX_D_N0	AA26	LVDS tabi 2.5-V	LVDS RX bit 0n tabi CMOS bit 7
53	HSMC_TX_D_P1	AJ27	LVDS tabi 2.5-V	LVDS TX bit 1 tabi CMOS bit 8
54	HSMC_RX_D_P1	Y17	LVDS tabi 2.5-V	LVDS RX bit 1 tabi CMOS bit 9
55	HSMC_TX_D_N1	AK26	LVDS tabi 2.5-V	LVDS TX bit 1n tabi CMOS bit 10
56	HSMC_RX_D_N1	Y18	LVDS tabi 2.5-V	LVDS RX bit 1n tabi CMOS bit 11
59	HSMC_TX_D_P2	AG26	LVDS tabi 2.5-V	LVDS TX bit 2 tabi CMOS bit 12
60	HSMC_RX_D_P2	AA18	LVDS tabi 2.5-V	LVDS RX bit 2 tabi CMOS bit 13
61	HSMC_TX_D_N2	AH26	LVDS tabi 2.5-V	LVDS TX bit 2n tabi CMOS bit 14
62	HSMC_RX_D_N2	AA19	LVDS tabi 2.5-V	LVDS RX bit 2n tabi CMOS bit 15
65	HSMC_TX_D_P3	AJ25	LVDS tabi 2.5-V	LVDS TX bit 3 tabi CMOS bit 16
66	HSMC_RX_D_P3	Y20	LVDS tabi 2.5-V	LVDS RX bit 3 tabi CMOS bit 17
67	HSMC_TX_D_N3	AK25	LVDS tabi 2.5-V	LVDS TX bit 3n tabi CMOS bit 18
68	HSMC_RX_D_N3	AA20	LVDS tabi 2.5-V	LVDS RX bit 3n tabi CMOS bit 19
71	HSMC_TX_D_P4	AH24	LVDS tabi 2.5-V	LVDS TX bit 4 tabi CMOS bit 20

Tabili 2-21. Awọn iyansilẹ Pin Ni wiwo HSMC, Awọn orukọ Ififihan Sikematiki, ati Awọn iṣẹ (Apá 2 ti 3)

Ọkọ Itọkasi (J7)	Sisọmu Ifihan agbara Oruko	Afẹfẹ V E Pin FPGA Nọmba	I/O Standard	Apejuwe
72	HSMC_RX_D_P4	AA21	LVDS tabi 2.5-V	LVDS RX bit 4 tabi CMOS bit 21
73	HSMC_TX_D_N4	AJ24	LVDS tabi 2.5-V	LVDS TX bit 4n tabi CMOS bit 22
74	HSMC_RX_D_N4	AB21	LVDS tabi 2.5-V	LVDS RX bit 4n tabi CMOS bit 23
77	HSMC_TX_D_P5	AH21	LVDS tabi 2.5-V	LVDS TX bit 5 tabi CMOS bit 24
78	HSMC_RX_D_P5	AB19	LVDS tabi 2.5-V	LVDS RX bit 5 tabi CMOS bit 25
79	HSMC_TX_D_N5	AJ22	LVDS tabi 2.5-V	LVDS TX bit 5n tabi CMOS bit 26
80	HSMC_RX_D_N5	AC19	LVDS tabi 2.5-V	LVDS RX bit 5n tabi CMOS bit 27
83	HSMC_TX_D_P6	AJ23	LVDS tabi 2.5-V	LVDS TX bit 6 tabi CMOS bit 28
84	HSMC_RX_D_P6	AC21	LVDS tabi 2.5-V	LVDS RX bit 6 tabi CMOS bit 29
85	HSMC_TX_D_N6	AK23	LVDS tabi 2.5-V	LVDS TX bit 6n tabi CMOS bit 30
86	HSMC_RX_D_N6	AD20	LVDS tabi 2.5-V	LVDS RX bit 6n tabi CMOS bit 31
89	HSMC_TX_D_P7	AK21	LVDS tabi 2.5-V	LVDS TX bit 7 tabi CMOS bit 32
90	HSMC_RX_D_P7	AD19	LVDS tabi 2.5-V	LVDS RX bit 7 tabi CMOS bit 33
91	HSMC_TX_D_N7	AK22	LVDS tabi 2.5-V	LVDS TX bit 7n tabi CMOS bit 34
92	HSMC_RX_D_N7	AE20	LVDS tabi 2.5-V	LVDS RX bit 7n tabi CMOS bit 35
95	HSMC_CLK_OUT_P1	AE22	LVDS tabi 2.5-V	LVDS tabi aago CMOS jade 1 tabi CMOS bit 36
96	HSMC_CLK_IN_P1	AB14	LVDS tabi 2.5-V	LVDS tabi aago CMOS ni 1 tabi CMOS bit 37
97	HSMC_CLK_OUT_N1	AF23	LVDS tabi 2.5-V	LVDS tabi aago CMOS jade 1 tabi CMOS bit 38
98	HSMC_CLK_IN_N1	AC14	LVDS tabi 2.5-V	LVDS tabi aago CMOS ni 1 tabi CMOS bit 39
101	HSMC_TX_D_P8	AJ20	LVDS tabi 2.5-V	LVDS TX bit 8 tabi CMOS bit 40
102	HSMC_RX_D_P8	AF21	LVDS tabi 2.5-V	LVDS RX bit 8 tabi CMOS bit 41
103	HSMC_TX_D_N8	AK20	LVDS tabi 2.5-V	LVDS TX bit 8n tabi CMOS bit 42
104	HSMC_RX_D_N8	AG22	LVDS tabi 2.5-V	LVDS RX bit 8n tabi CMOS bit 43
107	HSMC_TX_D_P9	AJ19	LVDS tabi 2.5-V	LVDS TX bit 9 tabi CMOS bit 44
108	HSMC_RX_D_P9	AF20	LVDS tabi 2.5-V	LVDS RX bit 9 tabi CMOS bit 45
109	HSMC_TX_D_N9	AK18	LVDS tabi 2.5-V	LVDS TX bit 9n tabi CMOS bit 46
110	HSMC_RX_D_N9	AG21	LVDS tabi 2.5-V	LVDS RX bit 9n tabi CMOS bit 47
113	HSMC_TX_D_P10	AJ17	LVDS tabi 2.5-V	LVDS TX bit 10 tabi CMOS bit 48
114	HSMC_RX_D_P10	AF18	LVDS tabi 2.5-V	LVDS RX bit 10 tabi CMOS bit 49
115	HSMC_TX_D_N10	AJ18	LVDS tabi 2.5-V	LVDS TX bit 10n tabi CMOS bit 50
116	HSMC_RX_D_N10	AF19	LVDS tabi 2.5-V	LVDS RX bit 10n tabi CMOS bit 51
119	HSMC_TX_D_P11	AK25	LVDS tabi 2.5-V	LVDS TX bit 11 tabi CMOS bit 52
120	HSMC_RX_D_P11	AG18	LVDS tabi 2.5-V	LVDS RX bit 11 tabi CMOS bit 53
121	HSMC_TX_D_N11	AG24	LVDS tabi 2.5-V	LVDS TX bit 11n tabi CMOS bit 54
122	HSMC_RX_D_N11	AG19	LVDS tabi 2.5-V	LVDS RX bit 11n tabi CMOS bit 55
125	HSMC_TX_D_P12	AH19	LVDS tabi 2.5-V	LVDS TX bit 12 tabi CMOS bit 56
126	HSMC_RX_D_P12	AK16	LVDS tabi 2.5-V	LVDS RX bit 12 tabi CMOS bit 57
127	HSMC_TX_D_N12	AH20	LVDS tabi 2.5-V	LVDS TX bit 12n tabi CMOS bit 58

Tabili 2-21. Awọn iyansilẹ Pin Ni wiwo HSMC, Awọn orukọ Ififihan Sikematiki, ati Awọn iṣẹ (Apá 3 ti 3)

Ọkọ Itọkasi (J7)	Sisọmu Ifihan agbara Oruko	Afẹfẹ V E Pin FPGA Nọmba	I/O Standard	Apejuwe
128	HSMC_RX_D_N12	AK17	LVDS tabi 2.5-V	LVDS RX bit 12n tabi CMOS bit 59
131	HSMC_TX_D_P13	AG17	LVDS tabi 2.5-V	LVDS TX bit 13 tabi CMOS bit 60
132	HSMC_RX_D_P13	AF16	LVDS tabi 2.5-V	LVDS RX bit 13 tabi CMOS bit 61
133	HSMC_TX_D_N13	AH17	LVDS tabi 2.5-V	LVDS TX bit 13n tabi CMOS bit 62
134	HSMC_RX_D_N13	AG16	LVDS tabi 2.5-V	LVDS RX bit 13n tabi CMOS bit 63
137	HSMC_TX_D_P14	AJ15	LVDS tabi 2.5-V	LVDS TX bit 14 tabi CMOS bit 64
138	HSMC_RX_D_P14	AE16	LVDS tabi 2.5-V	LVDS RX bit 14 tabi CMOS bit 65
139	HSMC_TX_D_N14	AK15	LVDS tabi 2.5-V	LVDS TX bit 14n tabi CMOS bit 66
140	HSMC_RX_D_N14	AF15	LVDS tabi 2.5-V	LVDS RX bit 14n tabi CMOS bit 67
143	HSMC_TX_D_P15	AH14	LVDS tabi 2.5-V	LVDS TX bit 15 tabi CMOS bit 68
144	HSMC_RX_D_P15	AD17	LVDS tabi 2.5-V	LVDS RX bit 15 tabi CMOS bit 69
145	HSMC_TX_D_N15	AH15	LVDS tabi 2.5-V	LVDS TX bit 15n tabi CMOS bit 70
146	HSMC_RX_D_N15	AE17	LVDS tabi 2.5-V	LVDS RX bit 15n tabi CMOS bit 71
149	HSMC_TX_D_P16	AE15	LVDS tabi 2.5-V	LVDS TX bit 16 tabi CMOS bit 72
150	HSMC_RX_D_P16	AD18	LVDS tabi 2.5-V	LVDS RX bit 16 tabi CMOS bit 73
151	HSMC_TX_D_N16	AF14	LVDS tabi 2.5-V	LVDS TX bit 16n tabi CMOS bit 74
152	HSMC_RX_D_N16	AE18	LVDS tabi 2.5-V	LVDS RX bit 16n tabi CMOS bit 75
155	HSMC_CLK_OUT_P2	AG23	LVDS tabi 2.5-V	LVDS tabi aago CMOS jade 2 tabi CMOS bit 76
156	HSMC_CLK_IN_P2	Y15	LVDS tabi 2.5-V	LVDS tabi aago CMOS ni 2 tabi CMOS bit 77
157	HSMC_CLK_OUT_N2	AH22	LVDS tabi 2.5-V	LVDS tabi aago CMOS jade 2 tabi CMOS bit 78
158	HSMC_CLK_IN_N2	AA15	LVDS tabi 2.5-V	LVDS tabi aago CMOS ni 2 tabi CMOS bit 79
160	HSMC_PRSNTn	AK5	2.5-V CMOS	HSMC ibudo wiwa iwari

RS-232 Serial UART
A obinrin angled DSUB 9-pin asopo ohun pẹlú pẹlu a support RS-232 transceiver pese support fun imulo awon kan boṣewa RS-232 ni tẹlentẹle UART ikanni lori yi ọkọ. Awọn asopo ni o ni kanna pinouts bi a data ebute ẹrọ ati ki o nbeere nikan kan boṣewa USB (ko si asan modẹmu beere fun PC ni wiwo). Ifipamọ ipele-ipinsi ti a ṣe iyasọtọ jẹ lilo lati tumọ laarin LVTTL ati awọn ipele RS-232. Awọn itọkasi igbimọ D23 ati D24 jẹ awọn LED UART ni tẹlentẹle ti o tan imọlẹ lati tọka iṣẹ ṣiṣe RX ati TX.

Tabili 2-24 ṣe atokọ awọn iṣẹ iyansilẹ RS-232 tẹlentẹle UART pin, awọn orukọ ifihan agbara, ati awọn iṣẹ.

Awọn orukọ ifihan ati awọn oriṣi jẹ ibatan si Cyclone VE FPGA ni awọn ofin ti eto I/O ati itọsọna.

Tabili 2-22. RS-232 Serial UART Sikematiki Awọn orukọ ifihan agbara ati awọn iṣẹ

Ọkọ Itọkasi (U20)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
14	UART_TXD	AB9	3.3-V	Firanṣẹ data
15	UART_RTS	AH6	3.3-V	Beere lati firanṣẹ

Tabili 2-22. RS-232 Serial UART Sikematiki Awọn orukọ ifihan agbara ati awọn iṣẹ

Ọkọ Itọkasi (U20)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
16	UART_RXD	AG6	3.3-V	Gba data
13	UART_CTS	AF8	3.3-V	Ko lati firanṣẹ

USB-UART
Igbimọ idagbasoke naa ṣe atilẹyin wiwo UART nipasẹ asopo USB kan nipa lilo afara Silicon Labs CP2104 USB-to-UART Afara. Lati dẹrọ ibaraẹnisọrọ alejo gbigba pẹlu CP2104, o nilo lati lo awọn awakọ USB-to-UART Afara Foju COM Port (VCP).

Awọn awakọ VCP wa ni: www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx

Tabili 2–23 ṣe atokọ awọn iṣẹ iyansilẹ pin USB-UART, awọn orukọ ifihan, ati awọn iṣẹ. Awọn orukọ ifihan ati awọn oriṣi jẹ ibatan si Cyclone VE FPGA ni awọn ofin ti eto I/O ati itọsọna

Tabili 2-23. Awọn orukọ ifihan agbara Sikematiki USB-UART ati Awọn iṣẹ

Ọkọ Itọkasi (U20)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
1	USB_UART_RI	AD12	2.5-V	Iṣagbewọle iṣakoso Atọka oruka (kekere lọwọ)
24	USB_UART_DCD	AD13	2.5-V	Ti ngbe data ṣawari iṣagbewọle iṣakoso (kekere ti nṣiṣẹ)
22	USB_UART_DSR	V12	2.5-V	Iṣagbewọle iṣakoso imurasilẹ ṣeto data (kekere ti nṣiṣe lọwọ)
21	USB_UART_RXD	AF10	2.5-V	Iṣagbewọle data Asynchronous (Gba UART)
19	USB_UART_RTS	AE12	2.5-V	Ṣetan lati firanṣẹ iṣelọpọ iṣakoso (kekere ti nṣiṣe lọwọ)
12	USB_UART_GPIO2	AE13	2.5-V	Iṣagbewọle atunto olumulo tabi iṣẹjade.
23	USB_UART_DTR	AE10	2.5-V	Iṣẹjade iṣakoso imurasilẹ ti ebute data (kekere ti nṣiṣe lọwọ)
20	USB_UART_TXD	W12	2.5-V	Ijade data Asynchronous (gbigbe UART)
18	USB_UART_CTS	AJ1	2.5-V	Ko o lati fi titẹ sii iṣakoso ranṣẹ (kekere ṣiṣẹ)
15	USB_UART_SUSPENDn	—	2.5-V	Pin jẹ kannaa kekere nigbati CP2104 wa ni ipo idaduro USB.
17	USB_UART_SUSPEND	—	2.5-V	Pin jẹ kannaa ga nigbati CP2104 wa ni ipo idaduro USB.
9	USB_UART_RSTn	—	2.5-V	Atunto ẹrọ

Iranti
Abala yii ṣapejuwe atilẹyin wiwo iranti igbimọ igbimọ idagbasoke ati tun awọn orukọ ifihan agbara wọn, awọn oriṣi, ati Asopọmọra ni ibatan si Cyclone VE FPGA. Igbimọ idagbasoke naa ni awọn atọkun iranti wọnyi:

• DDR3 SDRAM
• LPDDR2 SDRAM
• EEPROM
• Amuṣiṣẹpọ SRAM
• Filaṣi amuṣiṣẹpọ

Fun alaye diẹ sii nipa awọn atọkun iranti, tọka si awọn iwe aṣẹ wọnyi:

• Abala Itupalẹ akoko ninu Iwe-itumọ Oju-ọna Iranti Ita Ita.
• DDR, DDR2, ati DDR3 SDRAM Design Tutorial apakan ninu awọn Ita Memory Interface Handbook.

DDR3 SDRAM

• Igbimọ idagbasoke naa ṣe atilẹyin 16Mx16x8 meji ati awọn atọkun SDRAM 16Mx8x8 DDR3 meji fun iraye si iranti iyara iyara pupọ.
• Bosi data 32-bit ni ninu awọn ẹrọ x16 meji ni lilo wiwo oluṣakoso iranti rirọ (SMC). Pẹlu SMC, wiwo iranti yii n ṣiṣẹ ni igbohunsafẹfẹ ibi-afẹde ti 300 MHz fun bandiwidi imọ-jinlẹ ti o pọju ti o ju 9.6 Gbps. Igbohunsafẹfẹ ti o pọju fun ẹrọ DDR3 yii jẹ 800 MHz pẹlu lairi CAS ti 11.
• Tabili 2–24 ṣe atokọ awọn iṣẹ iyansilẹ pin DDR3, awọn orukọ ifihan agbara, ati awọn iṣẹ. Awọn orukọ ifihan ati awọn oriṣi jẹ ibatan si Cyclone VE FPGA ni awọn ofin ti eto I/O ati itọsọna.

Tabili 2-24. Awọn iyansilẹ Pin Ẹrọ Ẹrọ DDR3, Awọn Orukọ Ifihan Iṣeto, ati Awọn iṣẹ (Apá 1 ti 4)

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
DDR3 x16 (U8)
N3	DDR3_A0	A16	1.5-V SSTL Kilasi I	akero adirẹsi
P7	DDR3_A1	G23	1.5-V SSTL Kilasi I	akero adirẹsi
P3	DDR3_A2	E21	1.5-V SSTL Kilasi I	akero adirẹsi
N2	DDR3_A3	E22	1.5-V SSTL Kilasi I	akero adirẹsi
P8	DDR3_A4	A20	1.5-V SSTL Kilasi I	akero adirẹsi
P2	DDR3_A5	A26	1.5-V SSTL Kilasi I	akero adirẹsi
R8	DDR3_A6	A15	1.5-V SSTL Kilasi I	akero adirẹsi
R2	DDR3_A7	B26	1.5-V SSTL Kilasi I	akero adirẹsi
T8	DDR3_A8	H17	1.5-V SSTL Kilasi I	akero adirẹsi
R3	DDR3_A9	D14	1.5-V SSTL Kilasi I	akero adirẹsi
L7	DDR3_A10	E23	1.5-V SSTL Kilasi I	akero adirẹsi

Tabili 2-24. Awọn iyansilẹ Pin Ẹrọ Ẹrọ DDR3, Awọn Orukọ Ifihan Iṣeto, ati Awọn iṣẹ (Apá 2 ti 4)

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
R7	DDR3_A11	E20	1.5-V SSTL Kilasi I	akero adirẹsi
N7	DDR3_A12	C25	1.5-V SSTL Kilasi I	akero adirẹsi
T3	DDR3_A13	B13	1.5-V SSTL Kilasi I	akero adirẹsi
M2	DDR3_BA0	J18	1.5-V SSTL Kilasi I	Bank adirẹsi akero
N8	DDR3_BA1	F20	1.5-V SSTL Kilasi I	Bank adirẹsi akero
M3	DDR3_BA2	D19	1.5-V SSTL Kilasi I	Bank adirẹsi akero
K3	DDR3_CASN	L20	1.5-V SSTL Kilasi I	Adirẹsi ila yan
K9	DDR3_CKE	C11	1.5-V SSTL Kilasi I	Adirẹsi ọwọn yan
J7	DDR3_CLK_P	J20	Iyatọ 1.5-V SSTL Kilasi I	Aago o wu iyatọ
K7	DDR3_CLK_N	H20	Iyatọ 1.5-V SSTL Kilasi I	Aago o wu iyatọ
L2	DDR3_CSN	G17	1.5-V SSTL Kilasi I	Chip yan
E7	DDR3_DM0	D23	1.5-V SSTL Kilasi I	Kọ boju baiti ona
D3	DDR3_DM1	D18	1.5-V SSTL Kilasi I	Kọ boju baiti ona
E3	DDR3_DQ0	A25	1.5-V SSTL Kilasi I	Ona baiti data akero 0
H8	DDR3_DQ1	D22	1.5-V SSTL Kilasi I	Ona baiti data akero 0
F7	DDR3_DQ2	C21	1.5-V SSTL Kilasi I	Ona baiti data akero 0
H7	DDR3_DQ3	C19	1.5-V SSTL Kilasi I	Ona baiti data akero 0
F2	DDR3_DQ4	C20	1.5-V SSTL Kilasi I	Ona baiti data akero 0
G2	DDR3_DQ5	C22	1.5-V SSTL Kilasi I	Ona baiti data akero 0
F8	DDR3_DQ6	D25	1.5-V SSTL Kilasi I	Ona baiti data akero 0
H3	DDR3_DQ7	D20	1.5-V SSTL Kilasi I	Ona baiti data akero 0
A7	DDR3_DQ8	B24	1.5-V SSTL Kilasi I	Ona baiti data akero 1
C3	DDR3_DQ9	A21	1.5-V SSTL Kilasi I	Ona baiti data akero 1
A3	DDR3_DQ10	B21	1.5-V SSTL Kilasi I	Ona baiti data akero 1
D7	DDR3_DQ11	F19	1.5-V SSTL Kilasi I	Ona baiti data akero 1
A2	DDR3_DQ12	C24	1.5-V SSTL Kilasi I	Ona baiti data akero 1
C2	DDR3_DQ13	B23	1.5-V SSTL Kilasi I	Ona baiti data akero 1
B8	DDR3_DQ14	E18	1.5-V SSTL Kilasi I	Ona baiti data akero 1
C8	DDR3_DQ15	A23	1.5-V SSTL Kilasi I	Ona baiti data akero 1
F3	DDR3_DQS_P0	K20	Iyatọ 1.5-V SSTL Kilasi I	Data strobe P baiti ona 0
G3	DDR3_DQS_N0	J19	Iyatọ 1.5-V SSTL Kilasi I	Data strobe N baiti ona 0
C7	DDR3_DQS_P1	L18	Iyatọ 1.5-V SSTL Kilasi I	Data strobe P baiti ona 1
B7	DDR3_DQS_N1	K18	Iyatọ 1.5-V SSTL Kilasi I	Data strobe N baiti ona 1
K1	DDR3_ODT	H19	1.5-V SSTL Kilasi I	Lori-kú ifopinsi jeki

Tabili 2-24. Awọn iyansilẹ Pin Ẹrọ Ẹrọ DDR3, Awọn Orukọ Ifihan Iṣeto, ati Awọn iṣẹ (Apá 3 ti 4)

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
J3	DDR3_RASN	A24	1.5-V SSTL Kilasi I	Adirẹsi ila yan
T2	DDR3_RESETN	L19	1.5-V SSTL Kilasi I	Tunto
L3	DDR3_WEN	B22	1.5-V SSTL Kilasi I	Kọ ṣiṣẹ
L8	DDR3_ZQ01	—	1.5-V SSTL Kilasi I	Isọdiwọn ikọjusi ZQ
DDR3 x16 (U7)
N3	DDR3_A0	A16	1.5-V SSTL Kilasi I	akero adirẹsi
P7	DDR3_A1	G23	1.5-V SSTL Kilasi I	akero adirẹsi
P3	DDR3_A2	E21	1.5-V SSTL Kilasi I	akero adirẹsi
N2	DDR3_A3	E22	1.5-V SSTL Kilasi I	akero adirẹsi
P8	DDR3_A4	A20	1.5-V SSTL Kilasi I	akero adirẹsi
P2	DDR3_A5	A26	1.5-V SSTL Kilasi I	akero adirẹsi
R8	DDR3_A6	A15	1.5-V SSTL Kilasi I	akero adirẹsi
R2	DDR3_A7	B26	1.5-V SSTL Kilasi I	akero adirẹsi
T8	DDR3_A8	H17	1.5-V SSTL Kilasi I	akero adirẹsi
R3	DDR3_A9	D14	1.5-V SSTL Kilasi I	akero adirẹsi
L7	DDR3_A10	E23	1.5-V SSTL Kilasi I	akero adirẹsi
R7	DDR3_A11	E20	1.5-V SSTL Kilasi I	akero adirẹsi
N7	DDR3_A12	C25	1.5-V SSTL Kilasi I	akero adirẹsi
T3	DDR3_A13	B13	1.5-V SSTL Kilasi I	akero adirẹsi
M2	DDR3_BA0	J18	1.5-V SSTL Kilasi I	Bank adirẹsi akero
N8	DDR3_BA1	F20	1.5-V SSTL Kilasi I	Bank adirẹsi akero
M3	DDR3_BA2	D19	1.5-V SSTL Kilasi I	Bank adirẹsi akero
K3	DDR3_CASN	L20	1.5-V SSTL Kilasi I	Adirẹsi ila yan
K9	DDR3_CKE	AK18	1.5-V SSTL Kilasi I	Adirẹsi ọwọn yan
K7	DDR3_CLK_P	J20	1.5-V SSTL Kilasi I	Aago o wu iyatọ
J7	DDR3_CLK_N	H20	1.5-V SSTL Kilasi I	Aago o wu iyatọ
L2	DDR3_CSN	G17	1.5-V SSTL Kilasi I	Chip yan
E7	DDR3_DM2	A19	1.5-V SSTL Kilasi I	Kọ boju baiti ona
D3	DDR3_DM3	B14	1.5-V SSTL Kilasi I	Kọ boju baiti ona
F2	DDR3_DQ16	G18	1.5-V SSTL Kilasi I	Ona baiti data akero 2
F8	DDR3_DQ17	B18	1.5-V SSTL Kilasi I	Ona baiti data akero 2
E3	DDR3_DQ18	A18	1.5-V SSTL Kilasi I	Ona baiti data akero 2
F7	DDR3_DQ19	F18	1.5-V SSTL Kilasi I	Ona baiti data akero 2
H3	DDR3_DQ20	C14	1.5-V SSTL Kilasi I	Ona baiti data akero 2
G2	DDR3_DQ21	C17	1.5-V SSTL Kilasi I	Ona baiti data akero 2
H7	DDR3_DQ22	B17	1.5-V SSTL Kilasi I	Ona baiti data akero 2
H8	DDR3_DQ23	B19	1.5-V SSTL Kilasi I	Ona baiti data akero 2
A2	DDR3_DQ24	C15	1.5-V SSTL Kilasi I	Ona baiti data akero 3

Tabili 2-24. Awọn iyansilẹ Pin Ẹrọ Ẹrọ DDR3, Awọn Orukọ Ifihan Iṣeto, ati Awọn iṣẹ (Apá 4 ti 4)

Ọkọ Itọkasi	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
C2	DDR3_DQ25	D17	1.5-V SSTL Kilasi I	Ona baiti data akero 3
D7	DDR3_DQ26	C12	1.5-V SSTL Kilasi I	Ona baiti data akero 3
A7	DDR3_DQ27	E17	1.5-V SSTL Kilasi I	Ona baiti data akero 3
A3	DDR3_DQ28	C16	1.5-V SSTL Kilasi I	Ona baiti data akero 3
C3	DDR3_DQ29	A14	1.5-V SSTL Kilasi I	Ona baiti data akero 3
B8	DDR3_DQ30	D12	1.5-V SSTL Kilasi I	Ona baiti data akero 3
C8	DDR3_DQ31	A13	1.5-V SSTL Kilasi I	Ona baiti data akero 3
F3	DDR3_DQS_P2	K16	Iyatọ 1.5-V SSTL Kilasi I	Data strobe P baiti ona 2
G3	DDR3_DQS_N2	L16	Iyatọ 1.5-V SSTL Kilasi I	Data strobe N baiti ona 2
C7	DDR3_DQS_P3	K17	Iyatọ 1.5-V SSTL Kilasi I	Data strobe P baiti ona 3
B7	DDR3_DQS_N3	J17	Iyatọ 1.5-V SSTL Kilasi I	Data strobe N baiti ona 3
K1	DDR3_ODT	H19	1.5-V SSTL Kilasi I	Lori-kú ifopinsi jeki
J3	DDR3_RASN	A24	1.5-V SSTL Kilasi I	Adirẹsi ila yan
T2	DDR3_RESETN	L19	1.5-V SSTL Kilasi I	Tunto
L3	DDR3_WEN	B22	1.5-V SSTL Kilasi I	Kọ ṣiṣẹ
L8	DDR3_ZQ2	—	1.5-V SSTL Kilasi I	Isọdiwọn ikọjusi ZQ

LPDDR2 SDRAM
LPDDR2 jẹ ẹrọ alagbeka kekere agbara DDR2 SDRAM ti o nṣiṣẹ ni 1.2 V. Ni wiwo yii sopọ si awọn bèbe I/O petele lori eti oke ti ẹrọ FPGA.
Iyara ẹrọ jẹ 300 MHz. Iṣeto x16 nikan ni a lo botilẹjẹpe LPDDR2 SDRAM lori igbimọ jẹ ẹrọ x32 kan.
Tabili 2–25 ṣe atokọ awọn iṣẹ iyansilẹ pin LPDDR2 SDRAM, awọn orukọ ifihan, ati awọn iṣẹ.
Awọn orukọ ifihan ati awọn oriṣi jẹ ibatan si Cyclone VE FPGA ni awọn ofin ti eto I/O ati itọsọna.

Tabili 2-25. LPDDR2 SDRAM Awọn orukọ ifihan agbara Sikematiki ati Awọn iṣẹ

Ọkọ Itọkasi (U9)	Sisọmu Ifihan agbara Oruko	Cyclone VE Nọmba PIN FPGA	I/O Standard	Apejuwe
AC6	LPDDR2_CA0	Y30	1.2-V HSUL	akero adirẹsi
AB6	LPDDR2_CA1	T30	1.2-V HSUL	akero adirẹsi
AC7	LPDDR2_CA2	W29	1.2-V HSUL	akero adirẹsi
AB8	LPDDR2_CA3	AB29	1.2-V HSUL	akero adirẹsi
AB9	LPDDR2_CA4	W30	1.2-V HSUL	akero adirẹsi
W1	LPDDR2_CA5	U29	1.2-V HSUL	akero adirẹsi
V2	LPDDR2_CA6	AC30	1.2-V HSUL	akero adirẹsi
U1	LPDDR2_CA7	R30	1.2-V HSUL	akero adirẹsi

Tabili 2-25. LPDDR2 SDRAM Awọn orukọ ifihan agbara Sikematiki ati Awọn iṣẹ

Ọkọ Itọkasi (U9)	Sisọmu Ifihan agbara Oruko	Cyclone VE Nọmba PIN FPGA	I/O Standard	Apejuwe
T2	LPDDR2_CA8	T28	1.2-V HSUL	akero adirẹsi
T1	LPDDR2_CA9	T25	1.2-V HSUL	akero adirẹsi
Y2	LPDDR2_CK	V21	Iyatọ 1.2-V HSUL	Aago igbejade iyatọ P
Y1	LPDDR2_CKN	V22	Iyatọ 1.2-V HSUL	Aago igbejade iyatọ N
AC3	LPDDR2_CKE	T29	1.2-V HSUL	Aago ṣiṣẹ
AB3	LPDDR2_CSN	R26	1.2-V HSUL	Chip yan
N23	LPDDR2_DM0	AG29	1.2-V HSUL	Iboju data
L23	LPDDR2_DM1	AB27	1.2-V HSUL	Iboju data
AB20	LPDDR2_DM2	—	1.2-V HSUL	Iboju data
B20	LPDDR2_DM3	—	1.2-V HSUL	Iboju data
AA23	LPDDR2_DQ0	AG28	1.2-V HSUL	Ona baiti data akero 0
Y22	LPDDR2_DQ1	AH30	1.2-V HSUL	Ona baiti data akero 0
W22	LPDDR2_DQ2	AA28	1.2-V HSUL	Ona baiti data akero 0
W23	LPDDR2_DQ3	AH29	1.2-V HSUL	Ona baiti data akero 0
V23	LPDDR2_DQ4	Y28	1.2-V HSUL	Ona baiti data akero 0
U22	LPDDR2_DQ5	AE30	1.2-V HSUL	Ona baiti data akero 0
T22	LPDDR2_DQ6	AJ28	1.2-V HSUL	Ona baiti data akero 0
T23	LPDDR2_DQ7	AD30	1.2-V HSUL	Ona baiti data akero 0
H22	LPDDR2_DQ8	AC29	1.2-V HSUL	Ona baiti data akero 1
H23	LPDDR2_DQ9	AF30	1.2-V HSUL	Ona baiti data akero 1
G23	LPDDR2_DQ10	AA30	1.2-V HSUL	Ona baiti data akero 1
F22	LPDDR2_DQ11	AE28	1.2-V HSUL	Ona baiti data akero 1
E22	LPDDR2_DQ12	AF29	1.2-V HSUL	Ona baiti data akero 1
E23	LPDDR2_DQ13	AD28	1.2-V HSUL	Ona baiti data akero 1
D23	LPDDR2_DQ14	V27	1.2-V HSUL	Ona baiti data akero 1
C22	LPDDR2_DQ15	W28	1.2-V HSUL	Ona baiti data akero 1
AB12	LPDDR2_DQ16	—	1.2-V HSUL	Ona baiti data akero 2
AC13	LPDDR2_DQ17	—	1.2-V HSUL	Ona baiti data akero 2
AB14	LPDDR2_DQ18	—	1.2-V HSUL	Ona baiti data akero 2
AC14	LPDDR2_DQ19	—	1.2-V HSUL	Ona baiti data akero 2
AB15	LPDDR2_DQ20	—	1.2-V HSUL	Ona baiti data akero 2
AC16	LPDDR2_DQ21	—	1.2-V HSUL	Ona baiti data akero 2
AB17	LPDDR2_DQ22	—	1.2-V HSUL	Ona baiti data akero 2
AC17	LPDDR2_DQ23	—	1.2-V HSUL	Ona baiti data akero 2
B17	LPDDR2_DQ24	—	1.2-V HSUL	Ona baiti data akero 3
A17	LPDDR2_DQ25	—	1.2-V HSUL	Ona baiti data akero 3
A16	LPDDR2_DQ26	—	1.2-V HSUL	Ona baiti data akero 3
B15	LPDDR2_DQ27	—	1.2-V HSUL	Ona baiti data akero 3
B14	LPDDR2_DQ28	—	1.2-V HSUL	Ona baiti data akero 3

Tabili 2-25. LPDDR2 SDRAM Awọn orukọ ifihan agbara Sikematiki ati Awọn iṣẹ

Ọkọ Itọkasi (U9)	Sisọmu Ifihan agbara Oruko	Cyclone VE Nọmba PIN FPGA	I/O Standard	Apejuwe
A14	LPDDR2_DQ29	—	1.2-V HSUL	Ona baiti data akero 3
A13	LPDDR2_DQ30	—	1.2-V HSUL	Ona baiti data akero 3
B12	LPDDR2_DQ31	—	1.2-V HSUL	Ona baiti data akero 3
R23	LPDDR2_DQS0	V26	Iyatọ 1.2-V HSUL	Data strobe P baiti ona 0
P22	LPDDR2_DQSN0	U26	Iyatọ 1.2-V HSUL	Data strobe N baiti ona 0
J22	LPDDR2_DQS1	U27	Iyatọ 1.2-V HSUL	Data strobe P baiti ona 1
K23	LPDDR2_DQSN1	U28	Iyatọ 1.2-V HSUL	Data strobe N baiti ona 1
AB18	LPDDR2_DQS2	—	Iyatọ 1.2-V HSUL	Data strobe P baiti ona 2
AC19	LPDDR2_DQSN2	—	Iyatọ 1.2-V HSUL	Data strobe N baiti ona 2
B18	LPDDR2_DQS3	—	Iyatọ 1.2-V HSUL	Data strobe P baiti ona 3
A19	LPDDR2_DQSN4	—	Iyatọ 1.2-V HSUL	Data strobe N baiti ona 3
P1	LPDDR2_ZQ	—	1.2-V	Isọdiwọn ikọjusi ZQ

EEPROM
Igbimọ yii pẹlu ẹrọ EEPROM 64-Kb kan. Yi ẹrọ ni o ni a 2-waya ni tẹlentẹle ni wiwo akero I2C.
Tabili 2–26 ṣe atokọ awọn iṣẹ iyansilẹ pin EEPROM, awọn orukọ ifihan agbara, ati awọn iṣẹ. Awọn orukọ ifihan ati awọn oriṣi jẹ ibatan si Cyclone VE FPGA ni awọn ofin ti eto I/O ati itọsọna.

Tabili 2-26. Awọn orukọ ifihan agbara Sikematiki EEPROM ati Awọn iṣẹ

Ọkọ Itọkasi (U12)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
1	EEPROM_A0	—	3.3-V	Adirẹsi Chip
2	EEPROM_A1	—	3.3-V	Adirẹsi Chip
3	EEPROM_A2	—	3.3-V	Adirẹsi Chip
5	EEPROM_SDA	AH7	3.3-V	Tẹlentẹle adirẹsi tabi data
6	EEPROM_SCL	AG7	3.3-V	Serial aago
7	EEPROM_WP	—	3.3-V	Kọ igbewọle aabo

Amuṣiṣẹpọ SRAM
Igbimọ idagbasoke n ṣe atilẹyin SRAM amuṣiṣẹpọ boṣewa 18-Mb fun itọnisọna ati ibi ipamọ data pẹlu agbara wiwọle lairi-kekere. Ẹrọ naa ni wiwo 1024K x 18-bits. Ẹrọ yii jẹ apakan ti ọkọ akero FSM ti o pin ti o sopọ si iranti filasi, SRAM, ati MAX V CPLD 5M2210 System Adarí. Iyara ẹrọ jẹ 250 MHz iwọn-data-ọkan. Ko si iyara to kere julọ fun ẹrọ yii. Awọn bandiwidi o tumq si ti yi ni wiwo jẹ 4 Gbps fun lemọlemọfún bursts. Lairi kika fun adirẹsi eyikeyi jẹ awọn aago meji lakoko ti airi kikọ jẹ aago kan.

Tabili 2–27 ṣe atokọ awọn iṣẹ iyansilẹ pin SSRAM, awọn orukọ ifihan agbara, ati awọn iṣẹ.

Tabili 2-27. Awọn iṣẹ iyansilẹ Pin SSRAM, Awọn Orukọ Ifihan Iṣeto, ati Awọn iṣẹ (Apá 1 ti 2)

Ọkọ Itọkasi (U11)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
86	SRAM_OEN	E7	2.5-V	O wu jade
87	SRAM_WEN	D6	2.5-V	Kọ ṣiṣẹ
37	FSM_A1	B11	2.5-V	akero adirẹsi
36	FSM_A2	A11	2.5-V	akero adirẹsi
44	FSM_A3	D9	2.5-V	akero adirẹsi
42	FSM_A4	C10	2.5-V	akero adirẹsi
34	FSM_A5	A10	2.5-V	akero adirẹsi
47	FSM_A6	A9	2.5-V	akero adirẹsi
43	FSM_A7	C9	2.5-V	akero adirẹsi
46	FSM_A8	B8	2.5-V	akero adirẹsi
45	FSM_A9	B7	2.5-V	akero adirẹsi
35	FSM_A10	A8	2.5-V	akero adirẹsi
32	FSM_A11	B6	2.5-V	akero adirẹsi
33	FSM_A12	A6	2.5-V	akero adirẹsi
50	FSM_A13	C7	2.5-V	akero adirẹsi
48	FSM_A14	C6	2.5-V	akero adirẹsi
100	FSM_A15	F13	2.5-V	akero adirẹsi
99	FSM_A16	E13	2.5-V	akero adirẹsi
82	FSM_A17	A5	2.5-V	akero adirẹsi
80	FSM_A18	A4	2.5-V	akero adirẹsi
49	FSM_A19	J7	2.5-V	akero adirẹsi
81	FSM_A20	H7	2.5-V	akero adirẹsi
39	FSM_A21	J9	2.5-V	akero adirẹsi
58	FSM_D0	F16	2.5-V	akero data
59	FSM_D1	E16	2.5-V	akero data
62	FSM_D2	M9	2.5-V	akero data
63	FSM_D3	M8	2.5-V	akero data
68	FSM_D4	F15	2.5-V	akero data
69	FSM_D5	E15	2.5-V	akero data

Tabili 2-27. Awọn iṣẹ iyansilẹ Pin SSRAM, Awọn Orukọ Ifihan Iṣeto, ati Awọn iṣẹ (Apá 2 ti 2)

Ọkọ Itọkasi (U11)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
72	FSM_D6	E12	2.5-V	akero data
73	FSM_D7	D13	2.5-V	akero data
23	FSM_D8	J15	2.5-V	akero data
22	FSM_D9	H15	2.5-V	akero data
19	FSM_D10	E11	2.5-V	akero data
18	FSM_D11	D10	2.5-V	akero data
12	FSM_D12	L10	2.5-V	akero data
13	FSM_D13	L9	2.5-V	akero data
8	FSM_D14	G14	2.5-V	akero data
9	FSM_D15	F14	2.5-V	akero data
85	SRAM_ADSCN	E6	2.5-V	Adarí ipo adirẹsi
84	SRAM_ADSPN	J10	2.5-V	isise ipo adirẹsi
83	SRAM_ADVN	G6	2.5-V	Adirẹsi wulo
93	SRAM_BWAN	A3	2.5-V	Kọ baiti yan
94	SRAM_BWBN	A2	2.5-V	Kọ baiti yan
97	SRAM_CE2	—	2.5-V	Chip mu ṣiṣẹ 2
92	SRAM_CE3N	—	2.5-V	Chip mu ṣiṣẹ 3
98	SRAM_CEN	D7	2.5-V	Chip mu ṣiṣẹ 1
89	SRAM_CLK	K10	2.5-V	Aago
88	SRAM_GWN	—	2.5-V	Agbara kikọ agbaye
31	SRAM_MODE	—	2.5-V	Ti nwaye ọkọọkan yiyan
64	SRAM_ZZ	—	2.5-V	Ipo orun agbara

Filaṣi
Igbimọ idagbasoke n ṣe atilẹyin ohun elo filasi amuṣiṣẹpọ ibaramu 512-Mb CFI fun ibi ipamọ ti kii ṣe iyipada ti data iṣeto FPGA, alaye igbimọ, data ohun elo idanwo, ati aaye koodu olumulo. Ẹrọ yii jẹ apakan ti ọkọ akero FSM ti o pin ti o sopọ si iranti filasi, SSRAM, ati MAX V CPLD 5M2210 System Adarí. Ni wiwo iranti data 16-bit yii le ṣe atilẹyin awọn iṣẹ kika kika ti nwaye ni to 52 MHz fun ṣiṣejade ti 832 Mbps fun ẹrọ kan. Iṣe kikọ jẹ 270 μs fun ifipamọ ọrọ kan lakoko ti akoko piparẹ jẹ 800 ms fun bulọọki orun 128K kan. Tabili 2–28 ṣe atokọ awọn iṣẹ iyansilẹ pin filasi, awọn orukọ ifihan agbara, ati awọn iṣẹ. Awọn orukọ ifihan ati awọn oriṣi jẹ ibatan si Cyclone VE FPGA ni awọn ofin ti eto I/O ati itọsọna.

Tabili 2-28. Awọn iṣẹ iyansilẹ Pin Filaṣi, Awọn orukọ Ifiranṣẹ Iṣeto, ati Awọn iṣẹ (Apá 1 ti 3)

Ọkọ Itọkasi (U10)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
F6	FLASH_ADVN	H12	2.5-V	Adirẹsi wulo
B4	FLASH_CEN	H14	2.5-V	Chip jeki

Tabili 2-28. Awọn iṣẹ iyansilẹ Pin Filaṣi, Awọn orukọ Ifiranṣẹ Iṣeto, ati Awọn iṣẹ (Apá 2 ti 3)

Ọkọ Itọkasi (U10)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
E6	FLASH_CLK	N12	2.5-V	Aago
F8	FLASH_OEN	L11	2.5-V	O wu jade
F7	FLASH_RDYBSYN	J12	2.5-V	Ṣetan
D4	FLASH_RESETN	K11	2.5-V	Tunto
G8	FLASH_WEN	P12	2.5-V	Kọ ṣiṣẹ
C6	FLASH_WPN	—	2.5-V	Kọ idaabobo
A1	FSM_A1	B11	2.5-V	akero adirẹsi
B1	FSM_A2	A11	2.5-V	akero adirẹsi
C1	FSM_A3	D9	2.5-V	akero adirẹsi
D1	FSM_A4	C10	2.5-V	akero adirẹsi
D2	FSM_A5	A10	2.5-V	akero adirẹsi
A2	FSM_A6	A9	2.5-V	akero adirẹsi
C2	FSM_A7	C9	2.5-V	akero adirẹsi
A3	FSM_A8	B8	2.5-V	akero adirẹsi
B3	FSM_A9	B7	2.5-V	akero adirẹsi
C3	FSM_A10	A8	2.5-V	akero adirẹsi
D3	FSM_A11	B6	2.5-V	akero adirẹsi
C4	FSM_A12	A6	2.5-V	akero adirẹsi
A5	FSM_A13	C7	2.5-V	akero adirẹsi
B5	FSM_A14	C6	2.5-V	akero adirẹsi
C5	FSM_A15	F13	2.5-V	akero adirẹsi
D7	FSM_A16	E13	2.5-V	akero adirẹsi
D8	FSM_A17	A5	2.5-V	akero adirẹsi
A7	FSM_A18	A4	2.5-V	akero adirẹsi
B7	FSM_A19	J7	2.5-V	akero adirẹsi
C7	FSM_A20	H7	2.5-V	akero adirẹsi
C8	FSM_A21	J9	2.5-V	akero adirẹsi
A8	FSM_A22	H9	2.5-V	akero adirẹsi
G1	FSM_A23	G9	2.5-V	akero adirẹsi
H8	FSM_A24	F8	2.5-V	akero adirẹsi
B6	FSM_A25	E8	2.5-V	akero adirẹsi
B8	FSM_A26	D8	2.5-V	akero adirẹsi
F2	FSM_D0	F16	2.5-V	akero data
E2	FSM_D1	E16	2.5-V	akero data
G3	FSM_D2	M9	2.5-V	akero data
E4	FSM_D3	M8	2.5-V	akero data
E5	FSM_D4	F15	2.5-V	akero data
G5	FSM_D5	E15	2.5-V	akero data
G6	FSM_D6	E12	2.5-V	akero data

Tabili 2-28. Awọn iṣẹ iyansilẹ Pin Filaṣi, Awọn orukọ Ifiranṣẹ Iṣeto, ati Awọn iṣẹ (Apá 3 ti 3)

Ọkọ Itọkasi (U10)	Sisọmu Ifihan agbara Oruko	Cyclone VE FPGA Nọmba PIN	I/O Standard	Apejuwe
H7	FSM_D7	D13	2.5-V	akero data
E1	FSM_D8	J15	2.5-V	akero data
E3	FSM_D9	H15	2.5-V	akero data
F3	FSM_D10	E11	2.5-V	akero data
F4	FSM_D11	D10	2.5-V	akero data
F5	FSM_D12	L10	2.5-V	akero data
H5	FSM_D13	L9	2.5-V	akero data
G7	FSM_D14	G14	2.5-V	akero data
E7	FSM_D15	F14	2.5-V	akero data

Ibi ti ina elekitiriki ti nwa
O le fi agbara soke igbimọ idagbasoke lati inu titẹ agbara DC ti ara laptop kan. Awọn igbewọle voltage gbọdọ wa ni iwọn 14 V si 20 V, lọwọlọwọ ti 4.3 A, ati wat ti o pọjutage ti 65 W. The DC voltage ti wa ni ki o Witoelar si isalẹ lati orisirisi agbara afowodimu lo nipasẹ awọn ọkọ irinše ati fi sori ẹrọ sinu HSMC asopo. Afọwọṣe-ikanni oni-nọmba oni-nọmba oni-iyipada (ADC) lori-ọkọ ṣe iwọn lọwọlọwọ fun ọpọlọpọ awọn afowodimu igbimọ kan pato.

Eto Pinpin Agbara
Nọmba 2-9 fihan eto pinpin agbara lori igbimọ idagbasoke. Awọn ailagbara oluṣakoso ati pinpin jẹ afihan ninu awọn ṣiṣan ti o han, eyiti o jẹ awọn ipele ti o pọju Konsafetifu.

Olusin 2–9. Power Distribution System

Wiwọn Agbara
Awọn afowodimu ipese agbara mẹjọ wa ti o ni awọn agbara ori lọwọlọwọ lori ọkọ nipa lilo awọn ẹrọ ADC iyatọ 24-bit. Awọn alatako oye oye ti pin awọn ẹrọ ADC ati awọn irin-irin lati ọkọ ofurufu ipese akọkọ fun ADC lati wiwọn lọwọlọwọ. Bosi SPI kan so awọn ẹrọ ADC wọnyi pọ si MAX V CPLD 5M2210 Eto Adarí.

Nọmba 2-10 ṣe afihan aworan atọka Àkọsílẹ fun wiwọn wiwọn agbara.

Olusin 2-10. Agbara Idiwọn Circuit

Tabili 2–29 ṣe atokọ awọn irin-ajo ti a fojusi. Oju-iwe ami ami sikematiki pato orukọ ti iṣinipopada ti n wọnwọn nigba ti ọwọn pin ohun elo sọ awọn ẹrọ ti o so mọ iṣinipopada naa.

Tabili 2-29. Awọn afowodimu Iwọn Agbara

ikanni	Sisọmu Ifihan agbara Oruko	Voltage (V)	Ẹrọ Pin	Apejuwe
1	VCC	1.1	VCC	FPGA mojuto agbara
2	VCCAUX	2.5	VCC_AUX	Iranlọwọ
3	VCCA_FPLL	2.5	VCCA_FPLL	PLL afọwọṣe agbara
			VCCPD3B4A,
			VCCPD5A, VCCPD5B, VCCPD6A,	I/O awọn banki iṣaaju awakọ 3B, 4A, 5A, 5B, 6A, 7A, ati 8A
5	VCCIO_VCCPD_2.5V	2.5	VCCPD7A8A
			VCCIO3B,
			VCCIO6A, VCCIO7A,	VCC I/O banki 3B, 6A, 7A, ati 8A
			VCCIO8A
7	VCCIO_1.2V	1.2	VCCIO5A, VCCIO5B,	VCC I/O banki 5A ati 5B (LPDDR2)
8	VCCIO_1.5V	1.5	VCCIO_4A	VCC I/O banki 4A (DDR3)

Board irinše Reference

Ipin yii ṣe apejuwe awọn paati igbimọ idagbasoke Cyclone VE FPGA, alaye iṣelọpọ, ati awọn alaye ibamu igbimọ.

Awọn paati Igbimọ
Tabili ṣe atokọ itọkasi paati ati alaye iṣelọpọ ti gbogbo awọn paati lori igbimọ idagbasoke.

Tabili 3–1. Itọkasi paati ati Alaye iṣelọpọ

Ọkọ Itọkasi	Ẹya ara ẹrọ	Olupese	Ṣiṣe iṣelọpọ Nọmba apakan	Olupese Webojula
U1	FPGA, Cyclone VE F896, 149,500 Les, asiwaju free	Ile-iṣẹ Altera	5CEFA7F31I7N	www.altera.com
U13	MAX V CPLD 5M2210 Eto Adarí	Ile-iṣẹ Altera	5M2210ZF256I5N	www.altera.com
U18	Adarí agbeegbe USB iyara-giga	Cypress	CY7C68013A	www.cypress.com
D1-D16, D18-D31,	Awọn LED alawọ ewe	Lumex Inc.	SML-LXT0805GW-TR	www.lumex.com
D17	LED pupa	Lumex Inc.	SML-LXT0805IW-TR	www.lumex.com
D35	LED bulu	Lumex Inc.	SML-LX0805USBC-TR	www.lumex.com
SW1–SW4	Mẹrin-ipo DIP yipada	Awọn paati C&K / Awọn ile-iṣẹ ITT	TDA04H0SB1	www.ittcannon.com
S1-S8	Awọn bọtini titari	Panasonic	EVQPAC07K	www.panasonic.com
S5	Yipada ifaworanhan	E-yipada	EG2201A	www.e-switch.com
X1	Eto LVDS aago 125M aseku	Silikoni Labs	570FAB000973DG	www.silabs.com
X3	100 MHz oscillator gara, ± 50 ppm, CMOS, 2.5 V	Silikoni Labs	510GBA100M000BAGx	www.silabs.com
X2	50 MHz oscillator gara, ± 50 ppm, CMOS, 2.5 V	Silikoni Labs	510GBA50M0000BAGx	www.silabs.com
J12	Obinrin angled PCB WR-DSUB 9-pin asopo	Wurth Elektronik	618009231121	www.we-online.com
U21	USB-to-UART Afara	Silikoni Labs	CP2104	www.silabs.com
J14	2× 7 pin LCD iho rinhoho	Samtec	TSM-107-07-GD	www.samtec.com
	2× 16 ohun kikọ LCD, 5× 8 aami matrix	Lumex Inc.	LCM-S01602DSR/C	www.lumex.com
U14, U15	Àjọlò PHY BASE-T awọn ẹrọ	Marvell Semikondokito	88E1111-B2- CAA1C000	www.marvell.com
J8, J9	RJ-45 asopọ, 10/100/1000 Mbps	Wurth Elektronik	7499111001A	www.we-online.com
J7	HSMC, aṣa aṣa ti idile QSH-DP iho iyara to ga julọ.	Samtec	ASP-122953-01	www.samtec.com
U20	RS-232 meji transceiver	Imọ-ẹrọ Laini	LTC2803-1	www.linear.com

Tabili 3–1. Itọkasi paati ati Alaye iṣelọpọ

Ọkọ Itọkasi	Ẹya ara ẹrọ	Olupese	Ṣiṣe iṣelọpọ Nọmba apakan	Olupese Webojula
U12	64-Kb EEPROM	Microchip	24AA64	www.microchip.com
J15, J16	2 x 8 awọn akọle yokokoro	Samtec	TSM-108-01-L-DV	www.samtec.com
U7, U8	16M × 16 × 8, 256-MB DDR3 SDRAM	Micron	MT41J128M16	www.micron.com
U9	16M × 32 × 8, 512-MB LPDDR2 SDRAM	Micron	MT42L128M32	www.micron.com
U11	1024K × 18 bit 18-Mb amuṣiṣẹpọ SRAM	Integrated Silicon Solution, Inc.	IS61VPS102418A- 250TQL	www.issi.com
U10	512-Mb amuṣiṣẹpọ filasi	Numonyx	PC28F512P30BF	www.numonyx.com
U35	16-ikanni iyato 24-bit ADC	Imọ-ẹrọ Laini	LTC2418CGN#PBF	www.linear.com

Gbólóhùn ti China-RoHS Ibamu

Tabili 3–2 ṣe atokọ awọn nkan eewu ti o wa pẹlu ohun elo naa.

Tabili 3–2. Tabili ti Orukọ Awọn nkan elewu ati Awọn akọsilẹ Ifọkansi (1), (2)

Apakan Oruko	Asiwaju (Pb)	Cadmium (Cd)	Hexavalent Chromium (Cr6 +)	Makiuri (Hg)	Polybrominated biphenyls (PBB)	Polybrominated diphenyl Ethers (PBDE)
Cyclone VE idagbasoke ọkọ	X*	0	0	0	0	0
15 V ipese agbara	0	0	0	0	0	0
Tẹ AB okun USB	0	0	0	0	0	0
Itọsọna olumulo	0	0	0	0	0	0

Awọn akọsilẹ si Tabili 3–2:

1. 0 tọkasi pe ifọkansi ti nkan ti o lewu ni gbogbo awọn ohun elo isokan ni awọn apakan wa ni isalẹ iloro ti o yẹ ti boṣewa SJ/T11363-2006.
2. X * tọkasi pe ifọkansi ti nkan ti o lewu ti o kere ju ọkan ninu gbogbo awọn ohun elo isokan ninu awọn apakan wa loke iloro ti o yẹ ti boṣewa SJ/T11363-2006, ṣugbọn o jẹ imukuro nipasẹ EU RoHS.

CE EMI Išọra Ibamu
Ohun elo idagbasoke yii jẹ jiṣẹ ni ibamu si awọn iṣedede ti o yẹ ti a fun ni aṣẹ nipasẹ Itọsọna 2004/108/EC. Nitori iru awọn ohun elo ọgbọn ero ti siseto, o ṣee ṣe fun olumulo lati yi ohun elo naa pada ni ọna kan lati ṣe ipilẹṣẹ kikọlu itanna (EMI) ti o kọja awọn opin ti a ṣeto fun ohun elo yii. Eyikeyi EMI ti o ṣẹlẹ bi abajade ti awọn iyipada si ohun elo ti a firanṣẹ jẹ ojuṣe olumulo.

Alaye ni Afikun

Ipin yii n pese alaye ni afikun nipa iwe-ipamọ ati Altera.

Board Àtúnyẹwò History
Tabili ti o tẹle ṣe atokọ awọn ẹya ti gbogbo awọn idasilẹ ti Igbimọ Idagbasoke Cyclone VE FPGA.

Tu silẹ Ọjọ	Ẹya	Apejuwe
Oṣu Kẹta ọdun 2013	Silikoni iṣelọpọ	■ Atunyẹwo igbimọ tuntun. Titun ẹrọ ara nọmba-5CEFA7F31I7N. ■ Igbimọ gba idanwo ibamu CE.
Oṣu kọkanla ọdun 2012	ohun alumọni ẹrọ	Itusilẹ akọkọ.

Iwe Itan Atunyẹwo
Tabili ti o tẹle yii ṣe atokọ itan-akọọlẹ atunyẹwo fun iwe-ipamọ yii.

Ọjọ	Ẹya	Awọn iyipada
Oṣu Kẹjọ ọdun 2017	1.4	Ipo igbimọ ti a ṣe atunṣe fun Asopọ SMA Ijade Aago ni “O pariview ti awọn Cyclone VE FPGA Development Board Awọn ẹya ara ẹrọ” loju iwe 2–2.
Oṣu Kẹta ọdun 2017	1.3	Atunse ENETA_RX_DV nọmba pin sinu Tabili 2–20 loju iwe 2–25.
Oṣu Kẹsan 2015	1.2	■ Fikun ọna asopọ si Ile Itaja Altera in "MAX V CPLD 5M2210 System Adarí" lori ojú ìwé 2–5. ■ Atunse aami ẹrọ ni Ṣe nọmba 2–5 loju iwe 2–15.
Oṣu Kẹta ọdun 2013	1.1	■ Tuntunwo nọmba apakan ẹrọ FPGA fun idasilẹ silikoni iṣelọpọ. ■ Fikun apakan nipa “Iṣọra Ibamu CE EMI” ni oju-iwe 3–2.
Oṣu kọkanla ọdun 2012	1.0	Itusilẹ akọkọ.

Awọn Apejọ Atẹwe
Tabili ti o tẹle n ṣe afihan awọn apejọ iwe-kikọ ti iwe yii nlo.

Awoju Itumọ	Itumo
Irufẹ igboya pẹlu Olu Ibẹrẹ Awọn lẹta	Tọkasi awọn orukọ aṣẹ, awọn akọle apoti ibanisọrọ, awọn aṣayan apoti ibanisọrọ, ati awọn aami GUI miiran. Fun example, Fipamọ Bi apoti ajọṣọ. Fun awọn eroja GUI, capitalization baamu GUI.
igboya iru	Tọkasi awọn orukọ ilana, awọn orukọ iṣẹ akanṣe, awọn orukọ awakọ disk, file awọn orukọ, file awọn amugbooro orukọ, awọn orukọ ohun elo sọfitiwia, ati awọn aami GUI. Fun example, \ q awọn apẹrẹ liana, D: wakọ, ati chiptrip.gdf file.
Italic Iru pẹlu Awọn lẹta Olu Ibẹrẹ	Tọkasi awọn akọle iwe. Fun example, Stratix IV Apẹrẹ Awọn itọnisọna.

Cyclone VE FPGA Development Board

Ilana itọkasi

August 2017 Altera Corporation

Awọn iwe aṣẹ / Awọn orisun

ALTERA Cyclone VE FPGA Development Board [pdf] Afowoyi olumulo Cyclone VE FPGA Igbimọ Idagbasoke, Cyclone, Igbimọ Idagbasoke VE FPGA, Igbimọ Idagbasoke FPGA, Igbimọ Idagbasoke, Igbimọ

Awọn itọkasi

• Itọsọna olumulo