ALTERA Cyclone VE FPGA Boto ea Nts'etsopele
Tlhahisoleseding ya Sehlahiswa
Litlhaloso
- Mohlala oa FPGA: Leholiotsoana VE FPGA (5CEFA7F31I7N)
- Sephutheloana sa FPGA: 896-pin FineLine BGA (FBGA)
- Molaoli: Tokiso ea Flash fast passive parallel (FPP).
- Mohlala oa CPLD: MAX II CPLD (EPM240M100I5N)
- Sephutheloana sa CPLD: 100-pin FBGA
- Jenereithara ea oache e ka hlophisehang bakeng sa ho kenya oache ea litšupiso ea FPGA
- 50-MHz oscillator e sa feleng bakeng sa FPGA le MAX V CPLD ea oache
- 100-MHz oscillator e phethiloeng e le 'ngoe bakeng sa kenyelletso ea tlhophiso ea oache ea MAX V CPLD
- SMA input (LVDS)
- Sehopotso:
- Lisebelisoa tse peli tsa 256-Mbyte (MB) DDR3 SDRAM tse nang le bese ea data ea 16-bit
- E 'ngoe ea 18-Mbit (Mb) SSRAM
- Khanya e le 'ngoe ea 512-Mb e lumellanang
- E 'ngoe ea 512-MB LPDDR2 SDRAM e nang le bese ea data ea 32-bit (ho sebelisoa bese ea data ea 16 feela botong ena)
- PROM e le 'ngoe ea 64-Kb I2C e ka hlakolehang ka motlakase (EEPROM)
- Mechini: Boto ea boholo ba 6.5 x 4.5
Litaelo tsa Tšebeliso ea Sehlahisoa
Khaolo ea 1: Ho fetaview
Tlhaloso e Akaretsang
Boto ea Nts'etsopele ea Leholiotsoana VE FPGA e etselitsoe ho fana ka bokhoni ba meralo e tsoetseng pele ka likarolo tse joalo ka tlhophiso e sa fellang. E fana ka ts'ebetso e potlakileng, tšebeliso e tlase ea matla, le nako e potlakileng ea ho rekisa ha e bapisoa le malapa a fetileng a FPGA.
Lihokelo Tse Molemo
Ho fumana lintlha tse ling ka lihlooho tse latelang, sheba litokomane tse amehang:
- Lelapa la sesebelisoa sa Cyclone V: Leholiotsoana V Buka ea Sesebelisoa
- Litlhaloso tsa HSMC: Tlhaloso ea Karete ea Mezzanine e Phahameng (HSMC).
Khaolo ea 2: Likarolo tsa Boto
Li-block tsa Karolo ea Boto
Boto ea ntlafatso e na le li-block tsa likarolo tse latelang:
- One Cyclone VE FPGA (5CEFA7F31I7N) in a 896-pin FineLine BGA (FBGA)
- Molaoli: Tokiso ea Flash fast passive parallel (FPP).
- MAX II CPLD (EPM240M100I5N) ka har'a sephutheloana sa 100-pin FBGA
- Jenereithara ea oache e ka hlophisehang bakeng sa ho kenya oache ea litšupiso ea FPGA
- 50-MHz oscillator e sa feleng bakeng sa FPGA le MAX V CPLD ea oache
- 100-MHz oscillator e phethiloeng e le 'ngoe bakeng sa kenyelletso ea tlhophiso ea oache ea MAX V CPLD
- SMA input (LVDS)
- Sehopotso:
- Lisebelisoa tse peli tsa 256-Mbyte (MB) DDR3 SDRAM tse nang le bese ea data ea 16-bit
- E 'ngoe ea 18-Mbit (Mb) SSRAM
- Khanya e le 'ngoe ea 512-Mb e lumellanang
- E 'ngoe ea 512-MB LPDDR2 SDRAM e nang le bese ea data ea 32-bit (ho sebelisoa bese ea data ea 16 feela botong ena)
- PROM e le 'ngoe ea 64-Kb I2C e ka hlakolehang ka motlakase (EEPROM)
Mechini
Boto ea nts'etsopele e na le boholo ba 6.5 x 4.5 inches.
Khaolo ea 3: Reference Board Components
Karolo ena e fana ka lintlha tse qaqileng mabapi le karolo ka 'ngoe ea boto le ts'ebetso ea eona. Ka kopo sheba Bukana ea Reference Board ea Leholiotsoana VE FPGA bakeng sa lintlha tse ling.
FAQs
P: Nka fumana li-HSMC tsa morao-rao li fumaneha hokae?
A: Ho bona lenane la li-HSMC tsa morao-rao tse fumanehang kapa ho khoasolla khopi ea litlhaloso tsa HSMC, sheba leqephe la Development Board Daughtercards la Altera. websebaka.
Q: advan ke engtagke Boto ea Nts'etsopele ea Leholiotsoana VE FPGA?
A: Boto ea Nts'etsopele ea Leholiotsoana VE FPGA e fana ka tsoelo-pele ea meralo le lits'ebollo, joalo ka tokiso e sa fellang, e netefatsang ts'ebetso e potlakileng, ts'ebeliso e tlase ea matla, le nako e potlakileng ea 'maraka ha e bapisoa le malapa a fetileng a FPGA.
P: Nka fumana leseli le eketsehileng hokae ka lelapa la sesebelisoa sa Cyclone V?
A: Bakeng sa tlhaiso-leseling e batsi mabapi le lelapa la sesebelisoa sa Leholiotsoana V, sheba Buka ea Leholiotsoana ea Sesebelisoa sa Leholiotsoana.
P: Boholo ba boto ea ntlafatso ke eng?
A: Boto ntshetsopele e na le boholo ba 6.5 x 4.5 lisenthimithara.
101 Boqapi ba popontshwa
San Jose, CA 95134
www.altera.com
MNL-01075-1.4
© 2017 Altera Corporation. Litokelo tsohle li sirelelitsoe. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS le STRATIX mantsoe le li-logo ke matšoao a khoebo a Altera Corporation 'me a ngolisitsoe ho Ofisi ea Patent ea US le Letšoao la Khoebo le linaheng tse ling. Mantswe a mang kaofela le matshwao a tshwaotsweng e le matshwao a kgwebo kapa matshwao a tshebeletso ke thepa ya beng ba ona ka ho fapana jwalo ka ha ho hlalositswe ho www.altera.com/common/legal.html. Altera e fana ka tumello ea ho sebetsa ha lihlahisoa tsa eona tsa semiconductor ho latela litlhaloso tsa hajoale ho latela tiisetso e tloaelehileng ea Altera, empa e na le tokelo ea ho etsa liphetoho lihlahisoa le litšebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Altera ha e nke boikarabelo kapa boikarabelo bo hlahang ka lebaka la kopo kapa tšebeliso ea tlhahisoleseding leha e le efe, sehlahisoa, kapa tšebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Altera. Bareki ba Altera ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
Phato 2017 Altera Corporation Leholiotsoana VE FPGA Board Development
Bukana ea Litšupiso
Tokomane ena e hlalosa likarolo tsa Hardware tsa boto ea nts'etsopele ea Cyclone® VE FPGA, ho kenyeletsoa lintlha tse qaqileng tsa pin-out le lintlha tsa litšupiso tse hlokahalang ho theha meralo ea tloaelo ea FPGA e hokahanyang le likarolo tsohle tsa boto.
Fetileview
Tlhaloso e Akaretsang
Boto ea nts'etsopele ea Leholiotsoana VE FPGA e fana ka sethala sa lisebelisoa bakeng sa ho nts'etsapele le ho hlahisa meralo ea matla a tlase, e sebetsang hantle, le e matla e sebelisang Leholiotsoana la Altera VE FPGA. Boto e fana ka mefuta e mengata e fapaneng ea li-peripherals le li-memory interface ho thusa nts'etsopele ea meralo ea Cyclone VE FPGA. Sehokelo se le seng sa karete ea lebelo le phahameng ea mezzanine (HSMC) se teng ho eketsa ts'ebetso ka mefuta e fapaneng ea li-HSMC tse fumanehang ho tsoa ho Altera® le balekane ba fapaneng.
- Ho bona lethathamo la li-HSMC tsa morao-rao tse fumanehang kapa ho khoasolla khopi ea litlhaloso tsa HSMC, sheba leqephe la "Development Daughtercards" la Altera. websebaka.
Lintlafatso tsa meralo le lits'ebollo, joalo ka tlhophiso e sa fellang, li netefatsa hore meralo e kentsoeng ts'ebetsong ho Leholiotsoana VE FPGAs e sebetsa ka potlako, ka matla a tlase, 'me e na le nako e potlakileng ea ho rekisa ho feta malapa a fetileng a FPGA. - Ho fumana lintlha tse ling ka lihlooho tse latelang, sheba litokomane tse amehang:
- Lelapa la sesebelisoa sa Leholiotsoana V, bua ka Leholiotsoana V Device Handbook.
- HSMC Specification, bua ka High Speed Mezzanine Card (HSMC) Specification.
Li-block tsa Karolo ea Boto
Boto ea ntlafatso e na le li-block tsa likarolo tse latelang:
- Leholiotsoana le le leng la VE FPGA (5CEFA7F31I7N) ka har'a sephutheloana sa 896-pin FineLine BGA (FBGA)
- 149,500 LEs
- 56,480 adaptive logic modules (ALMs)
- 6,860 Kbit (Kb) M10K le 836 KB MLAB memori
- Loops tse supileng tse notletsoeng ka mekhahlelo e supileng (PLLs)
- 312 18×18-bit tse ngatafatsang
- 480 sepheo se akaretsang sa tlhahiso/sephetho (GPIO)
- Karolo ea mantlha ea 1.1-Vtage
- FPGA tlhophiso ea potoloho
- Peakanyo ya Active Serial (AS) x1 kapa AS x4 (EPCQ256SI16N)
- MAX® V CPLD (5M2210ZF256I5N) ka har'a sephutheloana sa FBGA sa 256-pin e le Molaoli oa Tsamaiso
- Tokiso ea Flash fast passive parallel (FPP).
- MAX II CPLD (EPM240M100I5N) ka har'a sephutheloana sa 100-pin FBGA e le karolo ea USB-Blaster TM II e kentsoeng bakeng sa ho sebelisoa le Quartus® II Programmer.
- Ho koala potoloho
- Jenereithara ea oache e ka hlophisehang bakeng sa ho kenya oache ea litšupiso ea FPGA
- 50-MHz oscillator e sa feleng bakeng sa FPGA le MAX V CPLD ea oache
- 100-MHz oscillator e phethiloeng e le 'ngoe bakeng sa kenyelletso ea tlhophiso ea oache ea MAX V CPLD
- SMA input (LVDS)
- Mohopolo
- Lisebelisoa tse peli tsa 256-Mbyte (MB) DDR3 SDRAM tse nang le bese ea data ea 16-bit
- E 'ngoe ea 18-Mbit (Mb) SSRAM
- Khanya e le 'ngoe ea 512-Mb e lumellanang
- E 'ngoe ea 512-MB LPDDR2 SDRAM e nang le bese ea data ea 32-bit (ho sebelisoa bese ea data ea 16 feela botong ena)
- PROM e le 'ngoe ea 64-Kb I2C e ka hlakolehang ka motlakase (EEPROM)
- Kakaretso ya mosebedisi/sephetho
- Li-LED le lipontšo
- Li-LED tse 'nè tsa basebelisi
- Sesebelisoa se le seng sa LED
- Tlhophiso e le 'ngoe e entsoe ka LED
- Phoso e le 'ngoe ea LED
- Litlhophiso tse tharo khetha li-LED
- Li-LED tse 'ne tse kentsoeng tsa boemo ba USB-Blaster II
- Li-LED tse tharo tsa sebopeho sa HSMC
- Li-LED tse leshome tsa Ethernet
- Lintlha tse peli tsa UART li fetisetsa le ho amohela li-LED
- Li-LED tse peli tsa USB-UART TX / RX LEDs
- Matla a le mong ho LED
- Pontšo ea LCD ea litlhaku tse peli
- Sututsa likonopo
- Konopo e le 'ngoe ea ho tsosolosa CPU
- Konopo e le 'ngoe ea MAX V ea ho seta bocha
- Lenaneo le le leng khetha konopo ea push
- Konopo e le 'ngoe ea tlhophiso ea lenaneo
- Likonopo tse 'ne tse akaretsang tsa basebelisi
- Liphetoho tsa DIP
- Li-switches tse 'nè tsa MAX V CPLD System Controller
- Tse peli JTAG li-switches tsa DIP tsa taolo ea ketane
- Fene e le 'ngoe ea taolo ea DIP switch
- Li-switches tse 'ne tsa DIP tse akaretsang
- Phepelo ea motlakase
14–20-V (laptop) e kenang ea DC - Mechini
Boto ea boholo ba 6.5" x 4.5 ″
Setšoantšo sa Block Board ea Nts'etsopele
Setšoantšo sa 1-1 se bonts'a sets'oants'o sa boloko sa boto ea ntlafatso ea Cyclone VE FPGA.
Ho sebetsana le Boto
Ha u sebetsana le boto, ke habohlokoa ho ela hloko mehato e latelang ea ho thibela ho tsoa ha static:
tlhokomediso
Ntle le ts'ebetso e nepahetseng ea anti-static, boto e ka senyeha. Ka hona, sebelisa litemoso tsa anti-static ha u ama boto.
Likarolo tsa Boto
Khaolo ena e hlahisa likarolo tse kholo ho boto ea ntlafatso ea Cyclone VE FPGA. Setšoantšo sa 2-1 se bontša libaka tsa likarolo 'me Lethathamo la 2-1 le fana ka tlhaloso e khutšoanyane ea likarolo tsohle tsa boto.
Lenane le felletseng la meralo, pokello ea lintlha tsa sebopeho, le GERBER files bakeng sa boto ea nts'etsopele e lula bukeng ea litokomane tsa ntlafatso ea Cyclone VE FPGA.
Ho fumana leseli mabapi le ho matlafatsa boto le ho kenya software ea lipontšo, sheba Tataiso ea Mosebelisi ea Cyclone VE FPGA Development Kit.
Khaolo ena e na le likarolo tse latelang:
- “E-ea ho Fetaview”
- "Sesebelisoa se Kenyellelitsoeng: Cyclone VE FPGA" leqepheng la 2-4
- "MAX V CPLD 5M2210 System Controller" leqepheng la 2-5
- "FPGA Configuration" leqepheng la 2-10
- “Potoloho ea Oache” leqepheng la 2–18
- “Tlhahiso/Sephetho sa Mosebelisi Kakaretso” leqepheng la 2–20
- “Likaroloana le Litšebelisano” leqepheng la 2-24
- “Mehopolo” leqepheng la 2–32
- “Phepelo ea Matla” leqepheng la 2–41
Board Overview
Karolo ena e fana ka tlhalosoview ea Boto ea nts'etsopele ea Leholiotsoana VE FPGA, ho kenyeletsoa setšoantšo sa boto e hlalositsoeng le litlhaloso tsa likarolo. Setšoantšo sa 2-1 se bontša ho fetaview ea likarolo tsa boto.
Letlapa la 2-1 le hlalosa likarolo mme le thathamisa litšupiso tsa boto tse tsamaellanang le tsona.
Lethathamo la 2–1. Likarolo tsa Boto (Karolo ea 1 ho tse 3)
| Boto Referense | Mofuta | Tlhaloso |
| Featured Lisebelisoa | ||
| U1 | FPGA | Leholiotsoana VE FPGA, 5CEFA7F31I7N, 896-pin FBGA. |
| U13 | CPLD | MAX V CPLD, 5M2210ZF256I5N, 256-pin FBGA. |
| Tlhophiso, Boemo, le Seta Elements | ||
| J4 | JTAG hlooho ea ketane | E fana ka phihlello ho JTAG chain le ho tima USB-Blaster II e kentsoeng ha u sebelisa thapo ea kantle ea USB-Blaster. |
| SW2 | JTAG taolo ea ketane DIP switjha | Tlosa kapa u kenye lisebelisoa ho J e sebetsangTAG ketane. |
| J10 | Sehokelo sa USB mofuta-B | Sehokelo sa USB bakeng sa lenaneo la FPGA le ho lokisa liphoso ka har'a USB-Blaster II J e kenelletsengTAG ka thapo ya USB ya mofuta-B. |
Lethathamo la 2–1. Likarolo tsa Boto (Karolo ea 2 ho tse 3)
| Boto Referense | Mofuta | Tlhaloso |
|
SW3 |
Litlhophiso tsa DIP switch |
E laola lits'ebetso tsa MAX V CPLD 5M2210 System Controller joalo ka ho nolofalletsa oache, taolo ea ho kenya oache ea SMA, le hore na o ka kenya setšoantšo sefe ho tsoa mohopolong oa flash ha o ntse o matlafatsa. |
| SW1 | Mokhoa oa ho fetola MSEL DIP | E laola leano la tlhophiso letlapeng. MSEL pins 0, 1, 2 le 4 e hokela ho switch ea DIP ha MSEL pin 3 e hokela fatše. |
| S2 | Khetha konopo ea ho tobetsa konopo | E fetola lenaneo ho khetha li-LED, tse khethang setšoantšo sa lenaneo se jarang ho tloha mohopolong oa flash ho ea ho FPGA. |
| S1 | Konopo ea tokiso ea tlhophiso ea lenaneo | Kenya setšoantšo ho tloha mohopolong oa flash ho ea ho FGPA ho latela litlhophiso tsa lenaneo khetha li-LED. |
| D19 | Tlhophiso e entsoe ka LED | E khantša ha FPGA e hlophisoa. |
| D18 | Laela LED | E khantša ha MAX V CPLD 5M2210 System Controller e ntse e lokisa FPGA ka mafolofolo. |
| D17 | Phoso ea LED | E khantša ha tlhophiso ea FPGA e tsoang ho memori ea flash e hloleha. |
| D35 | Matla a LED | E khantša ha matla a 5.0-V a le teng. |
|
D25 ~ D27 |
Lenaneo khetha li-LED |
E khantša ho bonts'a tatellano ea LED e khethollang hore na ke setšoantšo sefe sa memori ea flash se jaroang ho FPGA ha o tobetsa lenaneo khetha konopo ea push. Sheba Tafole 2–6 bakeng sa litlhophiso tsa LED. |
| D1 ~ D10 | Li-LED tsa Ethernet | E khantša ho bontša lebelo la khokahanyo hammoho le ho fetisa kapa ho amohela tšebetso. |
| D20, D21 | Li-LED tsa boema-kepe ba HSMC | U ka hlophisa li-LED tsena ho bonts'a tšebetso ea ho fetisa kapa ho amohela. |
| D22 | Boema-kepe ba HSMC bo hlahisa LED | E bonesa ha karete ea morali e hokeloa boema-kepeng ba HSMC. |
| D15, D16 | Li-LED tsa USB-UART | E khantša ha mochine oa motlakase oa USB-UART le moamoheli li ntse li sebelisoa. |
| D23, D24 | Li-LED tsa serial UART | E bonesa ha transmitter ea UART le moamoheli li ntse li sebelisoa. |
| Tshupanako Potoloho | ||
|
X1 |
Oscillator e hlophisitsoeng |
Oscillator e hlophisitsoeng e nang le maqhubu a kamehla a 125 MHz. Maqhubu a ka lokisoa ho sebelisoa GUI ea taolo ea oache e sebetsang ho MAX V CPLD 5M2210 System Controller. |
| U4 | 50MHz oscillator | 50.000-MHz kristale oscillator bakeng sa mabaka a akaretsang. |
| X3 | 100MHz oscillator | 100.000-MHz kristale oscillator bakeng sa MAX V CPLD 5M2210 System Controller. |
| J2, j3 | Lihokelo tsa SMA tsa oache | Khanna lisebelisoa tsa oache tse lumellanang le LVDS ka har'a buffer ea oache e mengata. |
| J4 | Sehokelo sa SMA se hlahisoang ke nako | Hlakola tlhahiso ea oache ea 2.5-V CMOS ho tsoa ho FPGA. |
| Kakaretso Mosebedisi Kenyeletso/Sehlahisoa | ||
| D28 ~ D31 | Lisebelisoa tsa LED | Li-LED tse 'nè tsa basebelisi. E khantša ha e khanneloa tlaase. |
| SW3 | Sesebelisoa sa DIP sa mosebelisi | Li-switches tsa DIP tsa basebelisi ba Quad. Ha switjha e BUTSE, ho khethoa logic 0. |
| S4 | Konopo ea ho reset ea CPU | Seta bocha mohopolo oa FPGA. |
| S3 | MAX V seta botjha konopo | Seta bocha MAX V CPLD 5M2210 Taolo ea Sisteme. |
| S5 ~ S8 | Likonopo tse tobetsang tsa mosebelisi ka kakaretso | Likonopo tse 'nè tsa basebelisi. E khanneloa tlase ha e hatelloa. |
| Mohopolo Lisebelisoa | ||
| U7, U8 | memori ea DDR3 x32 | Tse peli tsa 256-MB DDR3 SDRAM tse nang le bese ea data ea 16-bit. |
| U9 | LPDDR2 x 16 mohopolo | 512-MB LPDDR 2 SDRAM e nang le bese ea 32-bit, ke bese feela ea 16-bit e sebelisoang botong ena. |
Lethathamo la 2–1. Likarolo tsa Boto (Karolo ea 3 ho tse 3)
| Boto Referense | Mofuta | Tlhaloso |
| U10 | Memori ea Flash x16 | Lisebelisoa tsa flash tsa 512-Mb tse nang le bese ea data ea 16-bit bakeng sa mohopolo o sa fetoheng. |
| U11 | SSRAM x16 mohopolo | RAM e tloaelehileng ea 18-Mb e nang le bese ea data ea 12-bit le 4-bit parity. |
| U12 | EEPROM | 64-Mb I2C serial EEPROM. |
| Puisano Boema-kepe | ||
| J1 | Boema-kepe ba HSMC | E fana ka liteishene tse 84 tsa CMOS kapa tse 17 tsa LVDS ho latela litlhaloso tsa HSMC. |
|
J11 |
Boema-kepe ba Gigabit Ethernet |
Sehokelo sa RJ-45 se fanang ka khokahano ea 10/100/1000 Ethernet ka Marvell 88E1111 PHY le ts'ebetso ea Altera Triple Speed Ethernet MegaCore e thehiloeng ho FPGA ka mokhoa oa RGMII. |
| J12 | Boema-kepe ba serial UART | Sehokelo sa DSUB 9-pin se nang le transceiver ea RS-232 ho kenya tšebetsong mocha oa RS-232 oa serial UART. |
| J13 | Boema-kepe ba USB-UART | Sehokelo sa USB se nang le borokho ba USB-to-UART bakeng sa sehokelo sa serial sa UART. |
| J15, j16 | Hloekisa lihlooho | Lihlooho tse peli tsa 2x8 molemong oa ho lokisa bothata. |
| Video le Pontšo Boema-kepe | ||
| J14 | Sebopeho LCD | Sehokelo se hokahanang le mojule oa LCD oa litlhaku tse 16 × 2 hammoho le li-standoffs tse peli. |
| Matla Phepelo | ||
| J17 | Jack input ea DC | E amohela phepelo ea motlakase ea 14–20-V DC. |
| SW5 | Phetoho ea matla | Fetolela ho kenya kapa ho tima boto ha motlakase o fanoa ho tsoa ho jack input ea DC. |
Sesebelisoa se Kenyellelitsoeng: Cyclone VE FPGA
Boto ea nts'etsopele ea Cyclone VE FPGA e na le Leholiotsoana VE FPGA 5CEFA7F31I7N sesebelisoa (U1) ka har'a sephutheloana sa 896-pin FBGA.
Bakeng sa tlhaiso-leseling e batsi mabapi le lelapa la sesebelisoa sa Leholiotsoana V, sheba Buka ea Leholiotsoana ea Sesebelisoa.
Letlapa la 2-2 le hlalosa likarolo tsa sesebelisoa sa Cyclone VE FPGA 5CEFA7F31I7N.
Lethathamo la 2–2. Litšobotsi tsa Leholiotsoana VE FPGA
| Li-ALM | E lekanang LEs | M10K RAM Li-blocks | Kakaretso ea RAM (Kbits) | 18-bit × 18-bit Ba bangata | Li-PLL | Sephutheloana Mofuta |
| 56,480 | 149,500 | 6,860 | 836 | 312 | 7 | 896-pin FBGA |
Lisebelisoa tsa I/O
Sesebelisoa sa Cyclone VE FPGA 5CEFA7F31I7N se na le kakaretso ea basebelisi ba 480 ba I/O. Lethathamo la 2–3 le thathamisa palo ea lipini tsa Leholiotsoana VE FPGA I/O le tšebeliso ka tšebetso botong.
Lethathamo la 2–3. Leholiotsoana VE FPGA I/O Pin Count
| Mosebetsi | I/O Standard | I/O Bala | E khethehileng Lithako |
| DDR3 | 1.5-V SSTL | 71 | Phapang e le 'ngoe ea x4 DQS pin |
| LPDDR2 | 1.2-V HSUL | 37 | Phapang e le 'ngoe ea x2 DQS pin |
| Flash, SSRAM, EEPROM, le MAX V
FSM bese |
2.5-V CMOS, 3.3-V LVCMOS | 69 | — |
| Boema-kepe ba HSMC | 2.5-V CMOS + LVDS | 79 | 17 LVDS, I2C |
| Boema-kepe ba Gigabit Ethernet | 2.5-V CMOS | 42 | — |
| USB-Blaster II e kentsoeng | 2.5-V CMOS | 20 | — |
| Hlooho ea ho lokisa | 1.5-V, 2.5-V | 20 | — |
| UART | 3.3-V LVTTL | 4 | — |
| USB-UART | 2.5-V CMOS | 12 | — |
| Sututsa likonopo | 2.5-V CMOS | 5 | Pin e le 'ngoe ea DEV_CLRn |
| Liphetoho tsa DIP | 2.5-V CMOS | 4 | — |
| Sebopeho LCD | 2.5-V CMOS | 11 | — |
| Li-LED | 2.5-V CMOS | 9 | — |
| Oache kapa li-oscillator | 2.5-V CMOS + LVDS | 12 | Pini ea oache e le 'ngoe |
| Kakaretso I/O E sebelisitsoeng: | 395 | ||
MAX V CPLD 5M2210 Taolo ea Sisteme
Boto e sebelisa 5M2210 System Controller, Altera MAX V CPLD, ka sepheo se latelang:
- FPGA tlhophiso ho tloha ho flash
- Tekanyo ea matla
- Taolo le lirekoto tsa boemo bakeng sa ntlafatso ea sistimi e hole
Setšoantšo sa 2–2 se bonts'a tšebetso ea MAX V CPLD 5M2210 System Controller le likhokahano tsa potoloho ea kantle joalo ka setšoantšo sa block.\
Setšoantšo sa 2-2. MAX V CPLD 5M2210 Setšoantšo sa Thibelo ea Taolo ea Sisteme
Lethathamo la 2-4 le thathamisa matšoao a I/O a teng ho MAX V CPLD 5M2210 System Controller. Mabitso a matšoao le mesebetsi e amana le sesebelisoa sa MAX V.
U ka khoasolla example moralo o nang le libaka tsa phini le likabelo tse phethiloeng ho latela tafole e latelang ho tsoa ho Altera Design Store. Ka har'a Leholiotsoana VE FPGA Development Kit, tlas'a Design Exampjoalo ka, tobetsa Cyclone VE FPGA Development Kit Baseline Pinout.
Lethathamo la 2–4. MAX V CPLD 5M2210 Molaoli oa Sesebelisoa sa Pin-Out (Karolo ea 1 ea 5)
| Boto Reference (U13) | Leano Letshwao Lebitso | I/O Standard | Tlhaloso |
| N4 | 5M2210_JTAG_TMS | 3.3-V | MAX VJTAG TMS |
| E9 | CLK50_EN | 2.5-V | 50 MHz oscillator thusa |
| H12 | CLK_CONFIG | 2.5-V | 100 MHz ho kenya oache ea tlhophiso |
| A15 | CLK_ENABLE | 2.5-V | DIP switch bakeng sa oscillator oache e nolofalletsa |
| A13 | CLK_SEL | 2.5-V | Switch DIP bakeng sa khetho ea oache—SMA kapa oscillator |
| J12 | CLKIN_50_MAXV | 2.5-V | 50 MHz ho kenya oache |
| D9 | CLOCK_SCL | 2.5-V | Lenaneo la oscillator I2C oache |
| C9 | CLOCK_SDA | 2.5-V | Lintlha tse ka khonehang tsa oscillator I2C |
| D10 | CPU_RESETN | 2.5-V | FPGA seta konopo hape |
| P12 | EXTRA_SIG0 | 2.5-V | Sehokelo se kentsoeng sa USB-Blaster II. E boloketsoe tšebeliso ea nako e tlang |
| T13 | EXTRA_SIG1 | 2.5-V | Sehokelo se kentsoeng sa USB-Blaster II. E boloketsoe tšebeliso ea nako e tlang |
| T15 | EXTRA_SIG2 | 2.5-V | Sehokelo se kentsoeng sa USB-Blaster II. E boloketsoe tšebeliso ea nako e tlang |
| A2 | FACTORY_LOAD | 2.5-V | Phetoho ea DIP ho kenya feme kapa moralo oa mosebelisi ha o matlafatsa |
Lethathamo la 2–4. MAX V CPLD 5M2210 Molaoli oa Sesebelisoa sa Pin-Out (Karolo ea 2 ea 5)
| Boto Reference (U13) | Leano Letshwao Lebitso | I/O Standard | Tlhaloso |
| R14 | FACTORY_REQUEST | 2.5-V | Kopo e kentsoeng ea USB-Blaster II ea ho romela taelo ea FACTORY |
| N12 | FACTORY_STATUS | 2.5-V | Boemo ba taelo ea USB-Blaster II FACTORY e kentsoeng |
| C8 | FAN_FORCE_ON | 2.5-V | DIP ho bulela kapa ho tima fene |
| N7 | FLASH_ADVN | 2.5-V | Aterese ea memori ea bese ea FSM e nepahetse |
| R5 | FLASH_CEN | 2.5-V | FSM bus flash memory chip e thusa |
| R6 | FLASH_CLK | 2.5-V | Oache ea memori ea libese ea FSM |
| M6 | FLASH_OEN | 2.5-V | Tlhahiso ea memori ea libese ea FSM e thusa |
| T5 | FLASH_RDYBSYN | 2.5-V | Memori ea flash ea libese ea FSM e se e loketse |
| P7 | FLASH_RESETN | 2.5-V | Ho tsosolosa memori ea libese ea FSM |
| N6 | FLASH_WEN | 2.5-V | Ho ngola memori ea bese ea FSM e thusa |
| K1 | FPGA_CONF_ETSAHALA | 3.3-V | Phetoho ea FPGA e entsoe ka LED |
| D3 | FPGA_CONFIG_D0 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| C2 | FPGA_CONFIG_D1 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| C3 | FPGA_CONFIG_D2 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| E3 | FPGA_CONFIG_D3 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| D2 | FPGA_CONFIG_D4 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| E4 | FPGA_CONFIG_D5 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| D1 | FPGA_CONFIG_D6 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| E5 | FPGA_CONFIG_D7 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| F3 | FPGA_CONFIG_D8 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| E1 | FPGA_CONFIG_D9 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| F4 | FPGA_CONFIG_D10 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| F2 | FPGA_CONFIG_D11 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| F1 | FPGA_CONFIG_D12 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| F6 | FPGA_CONFIG_D13 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| G2 | FPGA_CONFIG_D14 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| G3 | FPGA_CONFIG_D15 | 3.3-V | Lintlha tsa tlhophiso ea FPGA |
| K4 | FPGA_MAX_DCLK | 3.3-V | Oache ea tlhophiso ea FPGA |
| J3 | FPGA_DCLK | 3.3-V | Oache ea tlhophiso ea FPGA |
| N1 | FPGA_NCONFIG | 3.3-V | Phetoho ea FPGA e sebetsa |
| J4 | FPGA_NSTATUS | 3.3-V | FPGA tlhophiso e loketse |
| H1 | FPGA_PR_DONE | 3.3-V | FPGA e entsoe bocha |
| P2 | FPGA_PR_ERROR | 3.3-V | Phoso ea karolo ea FPGA ea ho lokisa bocha |
| E2 | FPGA_PR_ READY | 3.3-V | FPGA e se e loketse ho hlophisa bocha |
| F5 | FPGA_PR_REQUEST | 3.3-V | Kopo ea FPGA ea ntlafatso e sa fellang |
| L5 | FPGA_MAX_NCS | 3.3-V | FPGA tlhophiso chip khetha |
| E14 | FSM_A1 | 2.5-V | FSM aterese bese |
| C14 | FSM_A2 | 2.5-V | FSM aterese bese |
Lethathamo la 2–4. MAX V CPLD 5M2210 Molaoli oa Sesebelisoa sa Pin-Out (Karolo ea 3 ea 5)
| Boto Reference (U13) | Leano Letshwao Lebitso | I/O Standard | Tlhaloso |
| C15 | FSM_A3 | 2.5-V | FSM aterese bese |
| E13 | FSM_A4 | 2.5-V | FSM aterese bese |
| E12 | FSM_A5 | 2.5-V | FSM aterese bese |
| D15 | FSM_A6 | 2.5-V | FSM aterese bese |
| F14 | FSM_A7 | 2.5-V | FSM aterese bese |
| D16 | FSM_A8 | 2.5-V | FSM aterese bese |
| F13 | FSM_A9 | 2.5-V | FSM aterese bese |
| E15 | FSM_A10 | 2.5-V | FSM aterese bese |
| E16 | FSM_A11 | 2.5-V | FSM aterese bese |
| F15 | FSM_A12 | 2.5-V | FSM aterese bese |
| G14 | FSM_A13 | 2.5-V | FSM aterese bese |
| F16 | FSM_A14 | 2.5-V | FSM aterese bese |
| G13 | FSM_A15 | 2.5-V | FSM aterese bese |
| G15 | FSM_A16 | 2.5-V | FSM aterese bese |
| G12 | FSM_A17 | 2.5-V | FSM aterese bese |
| G16 | FSM_A18 | 2.5-V | FSM aterese bese |
| H14 | FSM_A19 | 2.5-V | FSM aterese bese |
| H20 | FSM_A20 | 2.5-V | FSM aterese bese |
| H13 | FSM_A21 | 2.5-V | FSM aterese bese |
| H16 | FSM_A22 | 2.5-V | FSM aterese bese |
| J13 | FSM_A23 | 2.5-V | FSM aterese bese |
| J16 | FSM_A24 | 2.5-V | FSM aterese bese |
| T2 | FSM_A25 | 2.5-V | FSM aterese bese |
| P5 | FSM_A26 | 2.5-V | FSM aterese bese |
| J14 | FSM_D0 | 2.5-V | Lebese la data la FSM |
| J15 | FSM_D1 | 2.5-V | Lebese la data la FSM |
| K16 | FSM_D2 | 2.5-V | Lebese la data la FSM |
| K13 | FSM_D3 | 2.5-V | Lebese la data la FSM |
| K15 | FSM_D4 | 2.5-V | Lebese la data la FSM |
| K14 | FSM_D5 | 2.5-V | Lebese la data la FSM |
| L16 | FSM_D6 | 2.5-V | Lebese la data la FSM |
| L11 | FSM_D7 | 2.5-V | Lebese la data la FSM |
| L15 | FSM_D8 | 2.5-V | Lebese la data la FSM |
| L12 | FSM_D9 | 2.5-V | Lebese la data la FSM |
| M16 | FSM_D10 | 2.5-V | Lebese la data la FSM |
| L13 | FSM_D11 | 2.5-V | Lebese la data la FSM |
| M15 | FSM_D12 | 2.5-V | Lebese la data la FSM |
| L14 | FSM_D13 | 2.5-V | Lebese la data la FSM |
| N16 | FSM_D14 | 2.5-V | Lebese la data la FSM |
Lethathamo la 2–4. MAX V CPLD 5M2210 Molaoli oa Sesebelisoa sa Pin-Out (Karolo ea 4 ea 5)
| Boto Reference (U13) | Leano Letshwao Lebitso | I/O Standard | Tlhaloso |
| M13 | FSM_D15 | 2.5-V | Lebese la data la FSM |
| B8 | HSMA_PRSNTN | 2.5-V | Boema-kepe ba HSMC bo teng |
| L6 | JTAG_5M2210_TDI | 3.3-V | MAX V CPLD JTAG data ketane |
| M5 | JTAG_5M2210_TDO | 3.3-V | MAX V CPLD JTAG data ketane tsoa |
| P3 | JTAG_TCK | 3.3-V | JTAG oache ea ketane |
| P11 | M570_OCHE | 2.5-V | Oache ea 25-MHz ho kenya USB-Blaster II bakeng sa ho romela taelo ea FACTORY |
| M1 | M570_JTAG_EN | 3.3-V | Letšoao le tlase la ho tima USB-Blaster II e kentsoeng |
| P10 | MAX5_BEN0 | 2.5-V | FSM bese MAX V byte thusa 0 |
| R11 | MAX5_BEN1 | 2.5-V | FSM bese MAX V byte thusa 1 |
| T12 | MAX5_BEN2 | 2.5-V | FSM bese MAX V byte thusa 2 |
| N11 | MAX5_BEN3 | 2.5-V | FSM bese MAX V byte thusa 3 |
| T11 | MAX5_CLK | 2.5-V | FSM bese MAX V oache |
| R10 | MAX5_CSN | 2.5-V | FSM bese MAX V chip khetha |
| M10 | MAX5_OEN | 2.5-V | FSM bese MAX V tlhahiso e thusa |
| N10 | MAX5_WEN | 2.5-V | FSM bese MAX V ngola nolofalletsa |
| E11 | MAX_CONF_DONEN | 2.5-V | Tlhophiso e kenelletseng ea USB-Blaster II e entsoe ka LED |
| A4 | MAX_ERROR | 2.5-V | FPGA phoso ea tlhophiso ea LED |
| A6 | MAX_LOAD | 2.5-V | FPGA tlhophiso ea LED e sebetsang |
| M9 | MAX_RESETN | 2.5-V | MAX V seta botjha konopo |
| B7 | KHABANE | 2.5-V | Fane ea ho hlahloba mocheso e lumella |
| D12 | PGM_CONFIG | 2.5-V | Laola sets'oants'o sa memori ea flash se khethiloeng ke li-LED tsa PGM |
| B14 | PGM_LED0 | 2.5-V | Sesupo sa khetho ea Flash memory PGM 0 |
| C13 | PGM_LED1 | 2.5-V | Sesupo sa khetho ea Flash memory PGM 1 |
| B16 | PGM_LED2 | 2.5-V | Sesupo sa khetho ea Flash memory PGM 2 |
| B13 | PGM_SEL | 2.5-V | E fetola PGM_LED[2:0] tatelano ea LED |
| H4 | PSAS_CSn | 3.3-V | AS tlhophiso chip khetha |
| G1 | PSAS_DCLK | 3.3-V | AS oache ea tlhophiso |
| G4 | PSAS_CONF_ETSAHALA | 3.3-V | tlhophiso ea AS e entsoe |
| H2 | PSAS_CONFIGn | 3.3-V | AS tlhophiso e sebetsa |
| G5 | PSAS_DATA1 | 3.3-V | Lintlha tsa tlhophiso ea AS |
| H3 | PSAS_DATA0_ASD0 | 3.3-V | Lintlha tsa tlhophiso ea AS |
| J1 | PSAS_CEn | 3.3-V | AS tlhophiso chip thusa |
| R12 | SECURITY_MODE | 2.5-V | Sesepa sa DIP bakeng sa USB-Blaster II e kenelletseng ho romella FACTORY taelo ka matla |
| E7 | SENSE_CS0N | 2.5-V | Khetho ea ho beha leihlo la matla |
| A5 | SENSE_SCK | 2.5-V | Oache ea SPI ea ho shebella matla |
| D7 | SENSE_SDI | 2.5-V | Matla a hlokomela lintlha tsa SPI ho |
| B6 | SENSE_SDO | 2.5-V | Matla a ho lekola lintlha tsa SPI li tsoa |
Lethathamo la 2–4. MAX V CPLD 5M2210 Molaoli oa Sesebelisoa sa Pin-Out (Karolo ea 5 ea 5)
| Boto Reference (U13) | Leano Letshwao Lebitso | I/O Standard | Tlhaloso |
| M13 | FSM_D15 | 2.5-V | Lebese la data la FSM |
| B8 | HSMA_PRSNTN | 2.5-V | Boema-kepe ba HSMC bo teng |
| L6 | JTAG_5M2210_TDI | 3.3-V | MAX V CPLD JTAG data ketane |
| M5 | JTAG_5M2210_TDO | 3.3-V | MAX V CPLD JTAG data ketane tsoa |
| P3 | JTAG_TCK | 3.3-V | JTAG oache ea ketane |
| P11 | M570_OCHE | 2.5-V | Oache ea 25-MHz ho kenya USB-Blaster II bakeng sa ho romela taelo ea FACTORY |
| M1 | M570_JTAG_EN | 3.3-V | Letšoao le tlase la ho tima USB-Blaster II e kentsoeng |
| P10 | MAX5_BEN0 | 2.5-V | FSM bese MAX V byte thusa 0 |
| R11 | MAX5_BEN1 | 2.5-V | FSM bese MAX V byte thusa 1 |
| T12 | MAX5_BEN2 | 2.5-V | FSM bese MAX V byte thusa 2 |
| N11 | MAX5_BEN3 | 2.5-V | FSM bese MAX V byte thusa 3 |
| T11 | MAX5_CLK | 2.5-V | FSM bese MAX V oache |
| R10 | MAX5_CSN | 2.5-V | FSM bese MAX V chip khetha |
| M10 | MAX5_OEN | 2.5-V | FSM bese MAX V tlhahiso e thusa |
| N10 | MAX5_WEN | 2.5-V | FSM bese MAX V ngola nolofalletsa |
| E11 | MAX_CONF_DONEN | 2.5-V | Tlhophiso e kenelletseng ea USB-Blaster II e entsoe ka LED |
| A4 | MAX_ERROR | 2.5-V | FPGA phoso ea tlhophiso ea LED |
| A6 | MAX_LOAD | 2.5-V | FPGA tlhophiso ea LED e sebetsang |
| M9 | MAX_RESETN | 2.5-V | MAX V seta botjha konopo |
| B7 | KHABANE | 2.5-V | Fane ea ho hlahloba mocheso e lumella |
| D12 | PGM_CONFIG | 2.5-V | Laola sets'oants'o sa memori ea flash se khethiloeng ke li-LED tsa PGM |
| B14 | PGM_LED0 | 2.5-V | Sesupo sa khetho ea Flash memory PGM 0 |
| C13 | PGM_LED1 | 2.5-V | Sesupo sa khetho ea Flash memory PGM 1 |
| B16 | PGM_LED2 | 2.5-V | Sesupo sa khetho ea Flash memory PGM 2 |
| B13 | PGM_SEL | 2.5-V | E fetola PGM_LED[2:0] tatelano ea LED |
| H4 | PSAS_CSn | 3.3-V | AS tlhophiso chip khetha |
| G1 | PSAS_DCLK | 3.3-V | AS oache ea tlhophiso |
| G4 | PSAS_CONF_ETSAHALA | 3.3-V | tlhophiso ea AS e entsoe |
| H2 | PSAS_CONFIGn | 3.3-V | AS tlhophiso e sebetsa |
| G5 | PSAS_DATA1 | 3.3-V | Lintlha tsa tlhophiso ea AS |
| H3 | PSAS_DATA0_ASD0 | 3.3-V | Lintlha tsa tlhophiso ea AS |
| J1 | PSAS_CEn | 3.3-V | AS tlhophiso chip thusa |
| R12 | SECURITY_MODE | 2.5-V | Sesepa sa DIP bakeng sa USB-Blaster II e kenelletseng ho romella FACTORY taelo ka matla |
| E7 | SENSE_CS0N | 2.5-V | Khetho ea ho beha leihlo la matla |
| A5 | SENSE_SCK | 2.5-V | Oache ea SPI ea ho shebella matla |
| D7 | SENSE_SDI | 2.5-V | Matla a hlokomela lintlha tsa SPI ho |
| B6 | SENSE_SDO | 2.5-V | Matla a ho lekola lintlha tsa SPI li tsoa |
FPGA Configuration
Karolo ena e hlalosa FPGA, flash memory, le MAX V CPLD 5M2210 System Controller mekhoa ea ho etsa lisebelisoa e tšehetsoeng ke Leholiotsoana VE FPGA boto ea ntlafatso.
Boto ea ntlafatso ea Cyclone VE FPGA e ts'ehetsa mekhoa e latelang ea tlhophiso:
- USB-Blaster II e kenelletseng ke mokhoa oa kamehla oa ho hlophisa FPGA o sebelisa Quartus II Programmer ho J.TAG mokhoa o nang le thapo ea USB e fanoeng.
- Khoasollo ea memori ea Flash bakeng sa ho hlophisa FPGA u sebelisa litšoantšo tse bolokiloeng ho tsoa mohopolong oa flash ka matla-up kapa ho tobetsa konopo ea tlhophiso ea lenaneo (S1).
- USB-Blaster ea kantle bakeng sa ho hlophisa FPGA o sebelisa USB-Blaster ea kantle e hokelang ho J.TAG hlooho ea ketane (J4).
- Sesebelisoa sa EPCQ bakeng sa litlhophiso tsa serial kapa quad-serial FPGA tse tšehetsang maano a tlhophiso a AS x1 kapa AS x4.
Lenaneo la FPGA holim'a USB-Blaster II e kentsoeng
Mokhoa ona oa peakanyo o sebelisa sehokelo sa mofuta oa USB (J10), sesebelisoa sa USB 2.0 PHY (U18), le Altera MAX II CPLD EPM570GF100I5N (U16) ho lumella tlhophiso ea FPGA ka thapo ea USB. Thapo ena ea USB e hokela ka kotloloho lipakeng tsa sehokelo sa USB mofuta oa B botong le kou ea USB ea komporo e tsamaisang software ea Quartus II.
USB-Blaster II e kenelletseng ho MAX II CPLD EPM570GF100I5N hangata e laola J.TAG ketane.
Setšoantšo sa 2-3 se bontša JTAG ketane.
Leano la JTAG chain control DIP switch (SW2) e laola li- jumpers tse bontšitsoeng ho Setšoantšo sa 2–3.
Ho hokahanya sesebelisoa kapa segokanyimmediamentsi sa ketane, switch ea bona e ts'oanang e tlameha ho ba maemong a OFF. Tsamaisa li-switches tsohle sebakeng sa ON ho ba le FPGA feela ka ketane.
Taolo ea Sistimi ea MAX V CPLD 5M2210 e tlameha ho ba ho JTAG chain ho sebelisa tse ling tsa li-interface tsa GUI.
Letlapa la 2–5 le thathamisa mabitso a mats'oao a leano la USB 2.0 PHY le linomoro tsa tsona tse tsamaellanang tsa Cyclone VE FPGA.
Lethathamo la 2–5. USB 2.0 PHY Mabitso a Leano la Letšoao le Mesebetsi (Karolo ea 1 ea 2)
| Reference Board (U18) | Leano Letshwao Lebitso | Leholiotsoana VE Nomoro ea Pin ea FPGA | I/O Standard | Tlhaloso |
| C1 | 24M_XTALIN | — | 3.3-V | Kenyelletso ea Crystal oscillator |
| C2 | 24M_XTALOUT | — | 3.3-V | Tlhahiso ea Crystal oscillator |
| E1 | FX2_D_N | — | 3.3-V | USB 2.0 PHY data |
| E2 | FX2_D_P | — | 3.3-V | USB 2.0 PHY data |
| H7 | FX2_FLAGA | — | 3.3-V | Boemo ba tlhahiso ea makhoba FIFO |
Lethathamo la 2–5. USB 2.0 PHY Mabitso a Leano la Letšoao le Mesebetsi (Karolo ea 2 ea 2)
| Reference Board (U18) | Leano Letshwao Lebitso | Leholiotsoana VE Nomoro ea Pin ea FPGA | I/O Standard | Tlhaloso |
| G7 | FX2_FLGB | — | 3.3-V | Boemo ba tlhahiso ea makhoba FIFO |
| H8 | FX2_FLAGC | — | 3.3-V | Boemo ba tlhahiso ea makhoba FIFO |
| G6 | FX2_PA1 | — | 3.3-V | USB 2.0 PHY port A interface |
| F8 | FX2_PA2 | — | 3.3-V | USB 2.0 PHY port A interface |
| F7 | FX2_PA3 | — | 3.3-V | USB 2.0 PHY port A interface |
| F6 | FX2_PA4 | — | 3.3-V | USB 2.0 PHY port A interface |
| C8 | FX2_PA5 | — | 3.3-V | USB 2.0 PHY port A interface |
| C7 | FX2_PA6 | — | 3.3-V | USB 2.0 PHY port A interface |
| C6 | FX2_PA7 | — | 3.3-V | USB 2.0 PHY port A interface |
| H3 | FX2_PB0 | — | 3.3-V | USB 2.0 PHY segokanyimmediamentsi sa sebolokigolo |
| F4 | FX2_PB1 | — | 3.3-V | USB 2.0 PHY segokanyimmediamentsi sa sebolokigolo |
| H4 | FX2_PB2 | — | 3.3-V | USB 2.0 PHY segokanyimmediamentsi sa sebolokigolo |
| G4 | FX2_PB3 | — | 3.3-V | USB 2.0 PHY segokanyimmediamentsi sa sebolokigolo |
| H5 | FX2_PB4 | — | 3.3-V | USB 2.0 PHY segokanyimmediamentsi sa sebolokigolo |
| G5 | FX2_PB5 | — | 3.3-V | USB 2.0 PHY segokanyimmediamentsi sa sebolokigolo |
| F5 | FX2_PB6 | — | 3.3-V | USB 2.0 PHY segokanyimmediamentsi sa sebolokigolo |
| H6 | FX2_PB7 | — | 3.3-V | USB 2.0 PHY segokanyimmediamentsi sa sebolokigolo |
| A8 | FX2_PD0 | — | 3.3-V | USB 2.0 PHY port D interface |
| A7 | FX2_PD1 | — | 3.3-V | USB 2.0 PHY port D interface |
| B6 | FX2_PD2 | — | 3.3-V | USB 2.0 PHY port D interface |
| A6 | FX2_PD3 | — | 3.3-V | USB 2.0 PHY port D interface |
| B3 | FX2_PD4 | — | 3.3-V | USB 2.0 PHY port D interface |
| A3 | FX2_PD5 | — | 3.3-V | USB 2.0 PHY port D interface |
| C3 | FX2_PD6 | — | 3.3-V | USB 2.0 PHY port D interface |
| A2 | FX2_PD7 | — | 3.3-V | USB 2.0 PHY port D interface |
| B8 | FX2_RESETN | V21 | 3.3-V | USB-Blaster e kentsoeng ka thata e seta bocha |
| F3 | FX2_SCL | — | 3.3-V | USB 2.0 PHY oache ea serial |
| G3 | FX2_SDA | — | 3.3-V | USB 2.0 PHY data ea seriale |
| A1 | FX2_SLRDN | — | 3.3-V | Bala strobe bakeng sa lekhoba FIFO |
| B1 | FX2_SLWRN | — | 3.3-V | Ngola strobe bakeng sa lekhoba FIFO |
| B7 | FX2_TSOHA | — | 3.3-V | USB 2.0 PHY lets'oao la ho tsoha |
| G2 | USB_CLK | AA23 | 3.3-V | USB 2.0 PHY 48-MHz segokanyimmediamentsi sa sebolokigolo oache |
FPGA Programming ho tsoa ho Flash Memory
Lenaneo la memori ea Flash le khoneha ka mekhoa e fapaneng. Mokhoa oa kamehla ke oa ho sebelisa moralo oa feme—Board Update Portal. Moqapi ona o kenyelelitsoe webseva, e sebeletsang Board Update Portal web leqephe. The web Leqephe le u lumella ho khetha meralo e mecha ea FPGA ho kenyeletsoa hardware, software, kapa ka bobeli ho S-Record ea maemo a indasteri. File (.flash) 'me u ngole moralo ho leqephe la lisebelisoa tsa mosebelisi (leqephe la 1) la memori ea flash holim'a marang-rang.
Mokhoa oa bobeli ke ho sebelisa moralo o hahiloeng esale pele oa parallel flash loader (PFL) o kenyellelitsoeng setsing sa nts'etsopele. Boto ea nts'etsopele e sebelisa megafunction ea Altera PFL bakeng sa mananeo a memori ea flash. PFL megafunction ke "block of logic" e hlophisitsoeng ho Altera programmable logic device (FPGA kapa CPLD). PFL e sebetsa e le sesebelisoa sa ho ngolla sesebelisoa sa memori se lumellanang. Moralo ona o hahiloeng esale pele o na le megafunction ea PFL e o lumellang ho ngola leqephe la 0, leqephe la 1, kapa libaka tse ling tsa memori ea flash holim'a sebopeho sa USB u sebelisa software ea Quartus II. Mokhoa ona o sebelisoa ho khutlisetsa boto ea nts'etsopele ho litlhophiso tsa eona tsa kamehla tsa feme.
Mekhoa e meng ea ho hlophisa memori ea flash e ka sebelisoa hape, ho kenyeletsoa processor ea Nios® II.
Bakeng sa tlhaiso-leseling e batsi ka processor ea Nios II, sheba leqephe la Nios II processor ea Altera websebaka.
Ka matla-up kapa ka ho tobetsa konopo ea tlhophiso ea lenaneo, PGM_CONFIG (S1), PFL ea MAX V CPLD 5M2210 System Controller e hlophisa FPGA ho tsoa mohopolong oa flash. PFL megafunction e bala data ea 16-bit ho tsoa mohopolong oa flash ebe e e fetolela ho sebopeho sa fast passive parallel (FPP). Lintlha tsena tsa 16-bit li ngolloa ho lithapo tsa tlhophiso tse inehetseng ho FPGA nakong ea tlhophiso.
Ho tobetsa konopo ea PGM_CONFIG (S1) ho laela FPGA ka leqephe la hardware ho latela hore na PGM_LED[2:0] (D25, D26, D27) e bonesa. Lethathamo la 2–6 le thathamisa moralo o belehang ha o tobetsa konopo ea PGM_CONFIG.
Lethathamo la 2–6. Litlhophiso tsa PGM_LED (1)
| PGM_LED0 EA-D25 | PGM_LED1 EA-D26 | PGM_LED2 EA-D27 | Moralo |
| ON | TLOA | TLOA | Lisebelisoa tsa feme |
| TLOA | ON | TLOA | Lisebelisoa tsa mosebelisi 1 |
| TLOA | TLOA | ON | Lisebelisoa tsa mosebelisi 2 |
Setšoantšo sa 2-4 se bontša tlhophiso ea PFL.
Ho fumana lintlha tse ling ka lihlooho tse latelang, sheba litokomane tse amehang:
- Boto ea Phatlalatso ea Portal, moralo oa PFL, le polokelo ea limmapa tsa flash, li bua ka Tataiso ea Mosebelisi ea Leholiotsoana VE FPGA.
- PFL megafunction, bua ka Parallel Flash Loader Megafunction User Guide.
Lenaneo la FPGA holim'a USB-Blaster ea kantle
Leano la JTAG hlooho ea ketane e fana ka mokhoa o mong oa ho hlophisa FPGA o sebelisa sesebelisoa sa kantle sa USB-Blaster se nang le Quartus II Programmer e sebetsang ho PC. Ho thibela likhohlano lipakeng tsa JTAG masters, USB-Blaster e kentsoeng e ea holofala ka bo eona ha o hokela USB-Blaster ea kantle ho J.TAG ketane ka JTAG hlooho ea ketane.
Lenaneo la FPGA le sebelisa EPCQ
Sesebelisoa sa theko e tlase sa ECPQ se nang le memori e sa fetoheng se na le sebopeho se bonolo sa lipini tse tšeletseng le sebopeho se senyenyane. ECPQ e ts'ehetsa mekhoa ea AS x1 le x4. Ka ho sa feleng, boto ena e na le tlhophiso ea moralo oa tlhophiso ea FPP. E le ho beha moralo oa tlhophiso ho mokhoa oa AS, rework rework e tlameha ho etsoa. Beakanya litlhophiso tsa MSEL u sebelisa sesebelisoa sa MSEL DIP (SW1) ho fetola sekema sa tlhophiso.
Setšoantšo sa 2-5 se bontša kamano pakeng tsa EPCQ le Leholiotsoana VE FPGA.
Setšoantšo sa 2-5. Phetoho ea EPCQ
Lintlha tsa Boemo
Boto ea ntlafatso e kenyelletsa li-LED tsa maemo. Karolo ena e hlalosa likarolo tsa boemo.
Lethathamo la 2–7 le thathamisa litšupiso tsa boto ea LED, mabitso le litlhaloso tsa tšebetso.
Lethathamo la 2–7. Li-LED tse Khethehileng tsa Boto (Karolo ea 1 ea 2)
| Boto Referense | Leano Letshwao Lebitso | I/O Standard | Tlhaloso |
| D35 | Matla | 5.0-V | LED e putsoa. E khantša ha matla a 5.0 V a sebetsa. |
| D19 | MAX_CONF_DONEn | 2.5-V | LED e tala. E bonesa ha FPGA e hlophisoa ka katleho. E tsamaisoa ke MAX V CPLD 5M2210 System Controller. |
|
D17 |
MAX_ERROR |
2.5-V |
LED e khubelu. E khantša ha MAX V CPLD 5M2210 System Controller e hlōleha ho lokisa FPGA. E tsamaisoa ke MAX V CPLD 5M2210 System Controller. |
|
D18 |
MAX_LOAD |
2.5-V |
LED e tala. E khantša ha MAX V CPLD 5M2210 System Controller e ntse e lokisa FPGA ka mafolofolo. E tsamaisoa ke MAX V CPLD 5M2210 System Controller. |
| D25
EA-D26 D27 |
PGM_LED[0]
PGM_LED[1] PGM_LED[2] |
2.5-V |
Li-LED tse tala. E khantša ho bontša hore na ke leqephe lefe la hardware le rometsoeng mohopolong oa flash ha u tobetsa konopo ea PGM_SEL. |
Lethathamo la 2–7. Li-LED tse Khethehileng tsa Boto (Karolo ea 2 ea 2)
| Boto Referense | Leano Letshwao Lebitso | I/O Standard | Tlhaloso |
| D11, D12
D13, D14 |
JTAG_RX, JTAG_TX
SC_RX, SC_TX |
2.5-V | Li-LED tse tala. E khantša ho bontša mesebetsi ea USB-Blaster II ea ho amohela le ho fetisa. |
| D1 | EETA_LED_TX | 2.5-V | LED e tala. E khantša ho bontša ts'ebetso ea phetisetso ea Ethernet PHY. E tsamaisoa ke Marvell 88E1111 PHY. |
| D2 | EETA_LED_RX | 2.5-V | LED e tala. E khantša ho bontša ts'ebetso ea ho amohela Ethernet PHY. E tsamaisoa ke Marvell 88E1111 PHY. |
| D5 | EETA_LED_LINK10 | 2.5-V | LED e tala. E khantša ho bonts'a Ethernet e hokahaneng ka lebelo la khokahano ea 10 Mbps. E tsamaisoa ke Marvell 88E1111 PHY. |
| D4 | EETA_LED_LINK100 | 2.5-V | LED e tala. E khantša ho bonts'a Ethernet e hokahaneng ka lebelo la khokahano ea 100 Mbps. E tsamaisoa ke Marvell 88E1111 PHY. |
| D3 | EETA_LED_LINK1000 | 2.5-V | LED e tala. E khantša ho bonts'a Ethernet e hokahaneng ka lebelo la khokahano ea 1000 Mbps. E tsamaisoa ke Marvell 88E1111 PHY. |
| D19 | ENETB_LED_TX | 2.5-V | LED e tala. E khantša ho bontša ts'ebetso ea phetisetso ea Ethernet PHY B. E tsamaisoa ke Marvell 88E1111 PHY. |
| D22 | ENETB_LED_RX | 2.5-V | LED e tala. E khantša ho bontša ts'ebetso ea ho amohela Ethernet PHY B. E tsamaisoa ke Marvell 88E1111 PHY. |
| D24 | ENETB_LED_LINK10 | 2.5-V | LED e tala. E khantša ho bontša Ethernet B e hoketsoeng ka lebelo la khokahanyo la 10 Mbps. E tsamaisoa ke Marvell 88E1111 PHY. |
| D20 | ENETB_LED_LINK100 | 2.5-V | LED e tala. E khantša ho bontša Ethernet B e hoketsoeng ka lebelo la khokahanyo la 100 Mbps. E tsamaisoa ke Marvell 88E1111 PHY. |
| D21 | ENETB_LED_LINK1000 | 2.5-V | LED e tala. E khantša ho bontša Ethernet B e hoketsoeng ka lebelo la khokahanyo la 1000 Mbps. E tsamaisoa ke Marvell 88E1111 PHY. |
| D15, D16 | USB_UART_TX_TOGGLE, USB_UART_RX_TOGGLE | 2.5-V | LED e tala. E khantša ho bontša mesebetsi ea USB_UART ea ho amohela le ho fetisa. |
| D23, D24 | UART_RXD_LED, UART_TXD_LED | 2.5-V | LED e tala. E khantša ho bontša mesebetsi ea UART ea ho amohela le ho fetisa. |
|
D3 |
HSMA_PRSNTn |
3.3-V |
LED e tala. E bonesa ha boema-kepe ba HSMC bo e-na le boto kapa thapo e hoketsoeng hoo pin 160 e leng motheong. E tsamaisoa ke karete ea kenyelletso. |
Seta Elements
Boto ea nts'etsopele e kenyelletsa mefuta e mengata e fapaneng ea lisebelisoa tsa ho seta. Karolo ena e hlalosa likarolo tse latelang tsa ho seta:
- Litlhophiso tsa DIP switch
- JTAG di-setting DIP switjha
- Konopo ea ho reset ea CPU
- MAX V seta botjha konopo
- Konopo ea tokiso ea tlhophiso ea lenaneo
- Khetha konopo ea ho tobetsa konopo
Bakeng sa tlhaiso-leseling e batsi mabapi le li-setting tsa kamehla tsa li-switches tsa DIP, sheba Tataiso ea Mosebelisi ea Cyclone VE FPGA Development Kit.
Litlhophiso tsa Boto DIP Switch
Setlhophiso sa DIP switch (SW4) se laola likarolo tse fapaneng tse ikhethileng ho boto le moralo oa logic oa MAX V CPLD 5M2210 System Controller. Lethathamo la 2–8 le thathamisa li-switches le litlhaloso.
Lethathamo la 2–8. Litlhophiso tsa Boto DIP Switch Controls
| Fetoha | Leano Letshwao Lebitso | Tlhaloso |
| 1 |
CLK_SEL |
ON: Khetha oache ea oscillator e hlophisitsoeng
TIMA: Khetha oache ea ho kenya SMA |
| 2 |
CLK_ENABLE |
ON : Tlosa oscillator e holim'a board
QETELA: Numella oscillator ka botong |
| 3 |
FACTORY_LOAD |
ON : Laola moralo oa mosebelisi ho tloha ho flash ho power up
TIMA: Kenya moralo oa feme ho tloha ho flash ho ea holimo |
|
4 |
SECURITY_MODE |
ON : Embedded USB-Blaster II e romela FACTORY taelo ka matla up.
TIMA: USB-Blaster II e kenyellelitsoeng ha e romele taelo ea FACTORY ka matla. |
JTAG Chain Control DIP Switch
Leano la JTAG chain control DIP switch (SW2) e ka tlosa kapa e kenyelletsa lisebelisoa ho J e sebetsangTAG ketane. Cyclone VE FPGA e lula e le sebakeng sa JTAG ketane. Lethathamo la 2–9 le thathamisa li-switch controls le litlhaloso tsa tsona.
Lethathamo la 2–9. JTAG Chain Control DIP Switch
| Fetoha | Leano Letshwao Lebitso | Tlhaloso |
| 1 |
5M2210_JTAG_EN |
HO TSOSOA: Bypass MAX V CPLD 5M2210 Taolo ea Sisteme
OFF : MAX V CPLD 5M2210 Molaoli oa Sistimi ka ketane |
| 2 |
HSMC_JTAG_EN |
ON : Bypass HSMC port
OFF : HSMC port in-chain |
| 3 |
FAN_FORCE_ON |
ON : Numella fan
OFF : Tlosa fan |
| 4 | RETS'ELISITSOE | Reserved |
CPU Reset Push Button
Konopo ea "CPU" reset, CPU_RESETn (S4), ke kenyelletso ho Leholiotsoana VE FPGA DEV_CLRn pin 'me ke I/O e bulehileng e tsoang ho MAX V CPLD System Controller. Konopo ena ea ho sutumetsa ke mokhoa o hlophisitsoeng oa kamehla oa FPGA le CPLD logic. The MAX V CPLD 5M2210 System Controller e boetse e khanna konopo ena ea push nakong ea matla-on-reset (POR).
MAX V Seta Botjha Konopo ya Push
Konopo ea ho seta bocha ea MAX V, MAX_RESETn (S3), ke kenyelletso ho MAX V CPLD 5M2210 System Controller. Konopo ena ea ho sutumetsa ke mokhoa oa kamehla oa ho tsosolosa mohopolo oa CPLD.
Sebopeho sa Lenaneo Push Button
Konopo ea tlhophiso ea lenaneo, PGM_CONFIG (S1), ke kenyelletso ho MAX V CPLD 5M2210 System Controller. Kenyelletso ena e qobella phetoho ea FPGA ho tsoa mohopolong oa flash. Sebaka sa memori ea flash se ipapisitse le litlhophiso tsaPGM_LED[2:0], tse laoloang ke konopo ea ho tobetsa, PGM_SEL. Litlhophiso tse sebetsang li kenyelletsa PGM_LED0, PGM_LED1, kapa PGM_LED2 maqepheng a mararo a memori ea flash e boloketsoeng meralo ea FPGA.
Lenaneo Khetha Tobetsa Push
Lenaneo khetha konopo ea ho sutumetsa, PGM_SEL (S2), ke kenyelletso ho MAX V CPLD 5M2210 System Controller. Konopo ena e totobatsang e fetola tatellano ea PGM_LED[2:0] e khethang hore na ke sebaka sefe sa memori ea flash se sebelisetsoang ho lokisa FPGA. Sheba Lethathamo la 2–6 bakeng sa litlhaloso tsa tatellano ea PGM_LED[2:0].
Potoloho ea oache
Karolo ena e hlalosa lintho tseo boto e li kenyang le liphetho tsa oache.
Li-oscillator tsa on-Boto
Boto ea nts'etsopele e kenyelletsa li-oscillator tse nang le maqhubu a 50-MHz, 100-MHz, le oscillator e hlophisitsoeng.
Setšoantšo sa 2-6 se bonts'a maqhubu a kamehla a lioache tsohle tsa kantle tse eang boto ea nts'etsopele ea Cyclone VE FPGA.
Setšoantšo sa 2-6. Leholiotsoana VE FPGA Lioache tsa Boto ea Nts'etsopele
Lethathamo la 2–10 le thathamisa li-oscillator, maemo a eona a I/O, le voltage hlokahalang bakeng sa boto ea ntlafatso.
Lethathamo la 2–10. Li-oscillator tsa on-Boto
| Mohloli | Leano Letshwao Lebitso | Khafetsa | I/O Standard | Leholiotsoana VE Nomoro ea Pin ea FPGA | Kopo |
| U4 | CLKIN_50_FPGA_TOP | 50.000 MHz | E le ngoe | L14 | Bokaholimo le ka ho le letona |
| CLKIN_50_FPGA_RIGHT | P22 | ||||
| X3 | CLK_CONFIG | 100.000 MHz | 2.5V CMOS | — | Phetoho e potlakileng ea FPGA |
|
X1 le U3 (buffer) |
DIFF_CLKIN_TOP_125_P |
125.000 MHz |
LVDS |
L15 |
Moeli o ka holimo le o ka tlase |
| DIFF_CLKIN_TOP_125_N | K15 | ||||
| DIFF_CLKIN_BOT_125_P | AB17 | ||||
| DIFF_CLKIN_BOT_125_N | AB18 |
Kenyelletso ea Sets'oants'o sa Oache ea Off-Board
Boto ea nts'etsopele e na le lioache tsa ho kenya le tse hlahisoang tse ka khannoang botong. Lioache tse hlahisoang li ka hlophisoa ho ea maemong a fapaneng le maemo a I/O ho latela sebopeho sa sesebelisoa sa FPGA.
Lethathamo la 2–11 le thathamisa lintlha tsa oache bakeng sa boto ea nts'etsopele.
Lethathamo la 2–11. Lits'oants'o tsa Oache ea Off-Board
|
Mohloli |
Letšoao la Schematic Lebitso |
I/O Standard |
Leholiotsoana V E Setšoantšo sa FPGA
Nomoro |
Tlhaloso |
| SMA | CLKIN_SMA_P | LVDS | — | Kena ho buffer ea fan-out ea LVDS. |
| CLKIN_SMA_N | LVDS | — | ||
| Samtec HSMC | HSMA_CLK_IN0 | 2.5-V | AB16 | Kenyelletso e nang le pheletso e le 'ngoe ho tsoa ho thapo kapa boto e kentsoeng ea HSMC. |
| Samtec HSMC | HSMA_CLK_IN_P1 | LVDS/2.5-V | AB14 | Kenyelletso ea LVDS ho tsoa ho thapo kapa boto e kentsoeng ea HSMC. E ka boela ea tšehetsa 2x LVTTL inputs. |
| HSMA_CLK_IN_N1 | Tlhaloso: LVDS/LVTTL | AC14 | ||
| Samtec HSMC | HSMA_CLK_IN_P2 | Tlhaloso: LVDS/LVTTL | Y15 | Kenyelletso ea LVDS ho tsoa ho thapo kapa boto e kentsoeng ea HSMC. E ka boela ea tšehetsa 2x LVTTL inputs. |
| HSMA_CLK_IN_N2 | Tlhaloso: LVDS/LVTTL | AA15 |
Lethathamo la 2–12 le thathamisa lipoelo tsa oache bakeng sa boto ea nts'etsopele.
Lethathamo la 2–12. Litholoana tsa Oache ea Off-Board
|
Mohloli |
Letšoao la Schematic Lebitso |
I/O Standard |
Leholiotsoana V E Setšoantšo sa FPGA
Nomoro |
Tlhaloso |
| Samtec HSMC | HSMA_CLK_OUT0 | 2.5V CMOS | AJ14 | Tlhahiso ea FPGA CMOS (kapa GPIO) |
| Samtec HSMC | HSMA_CLK_OUT_P1 | LVDS/2.5V CMOS | AE22 | Tlhahiso ea LVDS. E ka ts'ehetsa liphetho tsa 2x CMOS. |
| HSMA_CLK_OUT_N1 | LVDS/2.5V CMOS | AF23 | ||
| Samtec HSMC | HSMA_CLK_OUT_P2 | LVDS/2.5V CMOS | AG23 | Tlhahiso ea LVDS. E ka ts'ehetsa liphetho tsa 2x CMOS. |
| HSMA_CLK_OUT_N2 | LVDS/2.5V CMOS | AH22 | ||
| SMA | CLKOUT_SMA | 2.5V CMOS | F9 | Tlhahiso ea FPGA CMOS (kapa GPIO) |
Kenyelletso e Akaretsang ya Mosebedisi/Output
Karolo ena e hlalosa sebopeho sa mosebelisi sa I/O ho FPGA, ho kenyeletsoa likonopo tse sutumetsang, li-switches tsa DIP, li-LED, le LCD ea sebapali.
Likonopo tsa Push tse hlalosoang ke basebelisi
Boto ea nts'etsopele e kenyelletsa likonopo tse tharo tse hlalosoang ke basebelisi. Bakeng sa tlhahisoleseling mabapi le sistimi le likonopo tsa ho seta bocha ka mokhoa o sireletsehileng, sheba ho "Setup Elements" leqepheng la 2–16. Litšupiso tsa boto S5, S6, S7, le S8 ke li-button tsa ho laola meralo ea FPGA e kenang sesebelisoa sa Leholiotsoana VE FPGA. Ha o tobetsa le ho tšoara switjha, pinana ea sesebelisoa e behiloe ho logic 0; ha o lokolla sesebelisoa, pinana ea sesebelisoa e behiloe ho logic 1. Ha ho na mesebetsi e khethehileng ea boto bakeng sa likonopo tsena tsa basebelisi ba kakaretso.
Lethathamo la 2-13 le thathamisa mabitso a mats'oao a lets'oao a sebelisoang ke mosebelisi le linomoro tsa tsona tse tsamaellanang tsa Cyclone VE FPGA.
Lethathamo la 2–13. Mabitso le Mesebetsi e Hlalositsoeng ea Push Button Schematic Signal Names
| Boto Referense | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Pin Nomoro | I/O Standard |
| S5 | USER_PB0 | AB12 | 2.5-V |
| S6 | USER_PB1 | AB13 | 2.5-V |
| S7 | USER_PB2 | AF13 | 2.5-V |
| S8 | USER_PB3 | AG12 | 2.5-V |
Switch-Defined DIP Switch
Boto ea boto SW3 ke sesebelisoa sa DIP se nang le lintlha tse 'ne. Sesebelisoa sena se hlalosoa ke basebelisi 'me se fana ka taolo e eketsehileng ea ho kenya FPGA. Ha switjha e le maemong a TIMA, ho khethoa logic 1. Ha switjha e le maemong a ON, ho khethoa logic 0. Ha ho na mesebetsi e khethehileng ea boto bakeng sa switjha ena.
Lethathamo la 2–14 le thathamisa mabitso a mats'oao a leano la DIP a hlalosoang ke mosebelisi le linomoro tsa tsona tse tsamaellanang tsa Cyclone VE FPGA.
Lethathamo la 2–14. Mabitso le Mesebetsi e Hlalositsoeng ea DIP Switch Schematic Schematic
| Boto Referense | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Pin Nomoro | I/O Standard |
| S5 | USER_PB0 | AB12 | 2.5-V |
| S6 | USER_PB1 | AB13 | 2.5-V |
| S7 | USER_PB2 | AF13 | 2.5-V |
| S8 | USER_PB3 | AG12 | 2.5-V |
Li-LED tse hlalositsoeng ke basebelisi
Boto ea nts'etsopele e kenyelletsa li-LED tsa kakaretso le tsa HSMC tse hlalosoang ke basebelisi. Karolo ena e hlalosa li-LED tsohle tse hlalosoang ke basebelisi. Bakeng sa lintlha tse mabapi le li-LED tse khethehileng kapa tsa boemo, sheba "Lintlha tsa Boemo" leqepheng la 2–15.
Li-LED tse akaretsang
Litšupiso tsa boto D28 ho isa D31 ke li-LED tse 'ne tse hlalosoang ke basebelisi. Maemo le matšoao a ho lokisa liphoso a khannoa ho li-LED ho tloha meralong e kentsoeng ho Leholiotsoana VE FPGA. Ho khanna logic 0 boema-kepeng ba I/O ho bulela LED ha u ntse u khanna logic 1 ho tima LED. Ha ho na mesebetsi e khethehileng ea boto bakeng sa li-LED tsena.
Letlapa la 2-15 le thathamisa mabitso a mats'oao a leano la LED le linomoro tsa tsona tse tsamaellanang tsa Cyclone VE FPGA.
Lethathamo la 2–15. Kakaretso ea Mabitso a Letšoao la Leano la LED le Mesebetsi
| Boto Referense | Leano Lebitso la Letshwao | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard |
| D28 | USER_LED0 | AK3 | 2.5-V |
| D29 | USER_LED1 | AJ4 | 2.5-V |
| D30 | USER_LED2 | AJ5 | 2.5-V |
| D31 | USER_LED3 | AK6 | 2.5-V |
Li-LED tsa HSMC
Litšupiso tsa boto D20 le D21 ke li-LED tsa boema-kepe ba HSMC. Ha ho na mesebetsi e khethehileng bakeng sa li-LED tsa HSMC. Li-LED li ngotsoe TX le RX, 'me li reretsoe ho bonts'a phallo ea data ho ea le ho tsoa ho likarete tsa morali tse hokahaneng. Li-LED li tsamaisoa ke sesebelisoa sa Cyclone VE FPGA.
Letlapa la 2–16 le thathamisa mabitso a mats'oao a HSMC LED le linomoro tsa tsona tse tsamaellanang tsa Cyclone VE FPGA.
Lethathamo la 2–16. HSMC LED Schematic Signal Mabitso le Mesebetsi
| Boto Referense | Leano Lebitso la Letshwao | Leholiotsoana VE FPGA Pin Nomoro | I/O Standard |
| D1 | HSMC_RX_LED | AH12 | 2.5-V |
| D2 | HSMC_TX_LED | AH11 | 2.5-V |
Sebopeho LCD
Boto ea nts'etsopele e kenyelletsa hlooho e le 'ngoe ea 14-pin 0.1 ″ sekontiri se nang le mela e 'meli se hokahanang le mohala oa 2 × 16 tlhaku ea Lumex ea LCD. Sebopeho sa LCD se na le sekoahelo sa li-pin tse 14 se nyolohelang ka kotloloho hloohong ea li-pin tse 14, kahoo se ka tlosoa habonolo bakeng sa ho fihlella likarolo tse ka tlasa ponts'o. U ka sebelisa hlooho ho lokisa liphoso kapa merero e meng.
Lethathamo la 2–17 le akaretsa likabelo tsa phini tsa LCD. Mabitso a matšoao le litaelo li amana le sesebelisoa sa Cyclone VE FPGA.
Lethathamo la 2–17. Likabelo tsa Pin tsa LCD tsa Sebopeho, Mabitso a Letšoao la Schematic, le Mesebetsi
| Boto Reference (J14) | Lebitso la Letshwao la Schematic | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 7 | LCD_DATA0 | AJ7 | 2.5-V | LCD data bese |
| 8 | LCD_DATA1 | AK7 | 2.5-V | LCD data bese |
| 9 | LCD_DATA2 | AJ8 | 2.5-V | LCD data bese |
| 10 | LCD_DATA3 | AK8 | 2.5-V | LCD data bese |
| 11 | LCD_DATA4 | AF9 | 2.5-V | LCD data bese |
| 12 | LCD_DATA5 | AG9 | 2.5-V | LCD data bese |
| 13 | LCD_DATA6 | AH9 | 2.5-V | LCD data bese |
| 14 | LCD_DATA7 | AJ9 | 2.5-V | LCD data bese |
Lethathamo la 2–17. Likabelo tsa Pin tsa LCD tsa Sebopeho, Mabitso a Letšoao la Schematic, le Mesebetsi
| Boto Reference (J14) | Lebitso la Letshwao la Schematic | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 4 | LCD_D_Cn | AK11 | 2.5-V | LCD data kapa taelo khetha |
| 5 | LCD_WEn | AK10 | 2.5-V | LCD ngola nolofalletsa |
| 6 | LCD_CSn | AJ12 | 2.5-V | LCD chip khetha |
Lethathamo la 2–18 le thathamisa litlhaloso tsa phini ea LCD, 'me ke qotsulo ho tsoa letlapeng la data la Lumex.
Lethathamo la 2–18. LCD Pin Litlhaloso le Mesebetsi
| Pin Nomoro | Letšoao | Boemo | Mosebetsi | |
| 1 | VDD | — |
Phepelo ea motlakase |
5 V |
| 2 | VSS | — | GND (0 V) | |
| 3 | V0 | — | Bakeng sa LCD drive | |
|
4 |
RS |
H/L |
Ngolisa khetha lets'oao H: Kenyelletso ea data
L: Ho kenya litaelo |
|
| 5 | R/W | H/L | H: Lintlha li baloa (mojule ho ea ho MPU)
L: Ngola data (MPU ho module) |
|
| 6 | E | H, H ho L | Thusa | |
| 7–14 | DB0–DB7 | H/L | Data bese - software e ka khethoang ka mokhoa oa 4-bit kapa 8-bit | |
Ho fumana lintlha tse ling joalo ka nako, limmapa tsa libapali, tataiso ea sebopeho, le litokomane tse ling tse amanang, etela www.lumex.com.
Hlooho ea ho lokisa
Boto ena ea ntlafatso e kenyelletsa lihlooho tse peli tsa 2 × 8 bakeng sa merero ea ho lokisa bothata. Tsela ea FPGA I/Os ka kotloloho ho ea hloohong bakeng sa tlhahlobo ea moralo, ho lokisa liphoso, kapa netefatso e potlakileng.
Letlapa la 2–19 le akaretsa likabelo tsa sehlooho sa debug, mabitso a matšoao, le mesebetsi.
Lethathamo la 2–19. Likabelo tsa Hlooho ea Pin, Mabitso a Letšoao a Schematic, le Mesebetsi (Karolo ea 1 ea 2)
| Boto Referense | Letšoao la Schematic Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| Hlakola Hlooho (J15) | ||||
| 1 | HEADER_D0 | H21 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
| 5 | HEADER_D1 | G21 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
| 9 | HEADER_D2 | G22 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
| 13 | HEADER_D3 | E26 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
| 4 | HEADER_D4 | E25 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
| 8 | HEADER_D5 | C27 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
| 12 | HEADER_D6 | C26 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
Lethathamo la 2–19. Likabelo tsa Hlooho ea Pin, Mabitso a Letšoao a Schematic, le Mesebetsi (Karolo ea 2 ea 2)
| Boto Referense | Letšoao la Schematic Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 16 | HEADER_D7 | B27 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
| Hlakola Hlooho (J16) | ||||
| 1 le 2 | HEADER_P0 le HEADER_N0 | H25 le H26 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 3 le 4 | HEADER_P1 le
HEADER_N1 |
P20 le N20 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 7 le 8 | HEADER_P2 le HEADER_N2 | J22 le J23 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 9 le 10 | HEADER_P3 le HEADER_N3 | D28 le D29 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 13 le 14 | HEADER_P4 le HEADER_N4 | E27 le D27 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 15 le 16 | HEADER_P5 le HEADER_N5 | H24 le J25 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
Likaroloana le li-interfaces
Karolo ena e hlalosa likou tsa puisano tsa boto ea nts'etsopele le likarete tsa khokahano tse amanang le sesebelisoa sa Cyclone VE FPGA. Boto ea nts'etsopele e ts'ehetsa likou tse latelang tsa likhokahano:
- RS-232 Serial UART
- 10/100/1000 Ethernet
- HSMC
- USB UART
10/100/1000 Ethernet
Boto ea nts'etsopele e ts'ehetsa tse peli tsa 10/100/1000 base-T Ethernet tse peli tse kantle tsa Marvell 88E1111 PHY le Altera Triple-Speed Ethernet MegaCore MAC ts'ebetso. Khokahano ea PHY-to-MAC e sebelisa sebopeho sa RGMII. Ts'ebetso ea MAC e tlameha ho fanoa ho FPGA bakeng sa lits'ebetso tse tloaelehileng tsa marang-rang. Marvell 88E1111 PHY e sebelisa liporo tsa motlakase tsa 2.5-V le 1.0-V 'me e hloka oache ea litšupiso ea 25-MHz e tsamaisoang ho tsoa ho oscillator e inehetseng. PHY e hokahana le mofuta oa RJ45 o nang le makenete a kahare a ka sebelisoang ho khanna mela ea koporo ka sephethephethe sa Ethernet.
Setšoantšo sa 2-7 se bontša sebopeho sa RGMII pakeng tsa FPGA (MAC) le Marvell 88E1111 PHY.
Setšoantšo sa 2-7. Sehokelo sa RGMII lipakeng tsa FPGA (MAC) le Marvell 88E1111 PHY
Lethathamo la 2–20 le thathamisa likabelo tsa pin interface PHY
Lethathamo la 2–20. Ethernet PHY Pin Assignments, Mabitso a Lipontšo le Mesebetsi (Karolo ea 1 ea 3)
| Boto Referense | Letšoao la Schematic Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 16 | HEADER_D7 | B27 | 1.5-V | Letšoao le nang le pheletso e le 'ngoe molemong oa ho lokisa bothata feela |
| Hlakola Hlooho (J16) | ||||
| 1 le 2 | HEADER_P0 le HEADER_N0 | H25 le H26 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 3 le 4 | HEADER_P1 le
HEADER_N1 |
P20 le N20 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 7 le 8 | HEADER_P2 le HEADER_N2 | J22 le J23 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 9 le 10 | HEADER_P3 le HEADER_N3 | D28 le D29 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 13 le 14 | HEADER_P4 le HEADER_N4 | E27 le D27 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
| 15 le 16 | HEADER_P5 le HEADER_N5 | H24 le J25 | 2.5-V | Matshwao a maiketsetso a fapaneng bakeng sa merero ya ho rarolla bothata feela |
Lethathamo la 2–20. Ethernet PHY Pin Assignments, Mabitso a Lipontšo le Mesebetsi (Karolo ea 2 ea 3)
| Boto Referense | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 33 | EETA_MDI_P1 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 34 | ENETA_MDI_N1 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 39 | EETA_MDI_P2 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 41 | ENETA_MDI_N2 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 42 | EETA_MDI_P3 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 43 | ENETA_MDI_N3 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| Ethernet PHY B (U11) | ||||
| 8 | ENETB_GTX_CLK | E28 | 2.5-V CMOS | 125-MHz RGMII e fetisa oache |
| 23 | ENETB_INTN | K22 | 2.5-V CMOS | Batsamaisi ba sitisa libese |
| 60 | ENETB_LED_DUPLEX | — | 2.5-V CMOS | Duplex kapa ho thulana ha LED. Ha e sebelisoe |
| 70 | ENETB_LED_DUPLEX | — | 2.5-V CMOS | Duplex kapa ho thulana ha LED. Ha e sebelisoe |
| 76 | ENETB_LED_LINK10 | — | 2.5-V CMOS | 10-Mb sehokelo sa LED |
| 74 | ENETB_LED_LINK100 | — | 2.5-V CMOS | 100-Mb sehokelo sa LED |
| 73 | ENETB_LED_LINK1000 | — | 2.5-V CMOS | 1000-Mb sehokelo sa LED |
| 58 | ENETB_LED_RX | — | 2.5-V CMOS | RX data e sebetsang ea LED |
| 69 | ENETB_LED_RX | — | 2.5-V CMOS | RX data e sebetsang ea LED |
| 68 | ENETB_LED_TX | — | 2.5-V CMOS | TX data e sebetsang ea LED |
| 25 | ENETB_MDC | A29 | 2.5-V CMOS | Tsamaiso ea data ea libese oache |
| 24 | ENETB_MDIO | L23 | 2.5-V CMOS | Tsamaiso ea data ea libese |
| 28 | ENETB_RESETN | M21 | 2.5-V CMOS | Seta sesebelisoa bocha |
| 2 | ENETB_RX_CLK | R23 | 2.5-V CMOS | RGMII amohela oache |
| 95 | ENETB_RX_D0 | F25 | 2.5-V CMOS | RGMII fumana bese ea data |
| 92 | ENETB_RX_D1 | F26 | 2.5-V CMOS | RGMII fumana bese ea data |
| 93 | ENETB_RX_D2 | R20 | 2.5-V CMOS | RGMII fumana bese ea data |
| 91 | ENETB_RX_D3 | T21 | 2.5-V CMOS | RGMII fumana bese ea data |
| 94 | ENETB_RX_DV | L24 | 2.5-V CMOS | RGMII fumana data e sebetsang |
| 11 | ENETB_TX_D0 | F29 | 2.5-V CMOS | RGMII e fetisetsa bese ea data |
| 12 | ENETB_TX_D1 | D30 | 2.5-V CMOS | RGMII e fetisetsa bese ea data |
| 14 | ENETB_TX_D2 | C30 | 2.5-V CMOS | RGMII e fetisetsa bese ea data |
| 16 | ENETB_TX_D3 | F28 | 2.5-V CMOS | RGMII e fetisetsa bese ea data |
| 9 | ENETB_TX_EN | B29 | 2.5-V CMOS | Sesebelisoa sa phetisetso ea RGMII |
| 55 | ENETB_XTAL_25MHZ | — | 2.5-V CMOS | 25-MHz RGMII e fetisa oache |
| 29 | ENETB_MDI_P0 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 31 | ENETB_MDI_N0 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 33 | ENETB_MDI_P1 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 34 | ENETB_MDI_N1 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 39 | ENETB_MDI_P2 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 41 | ENETB_MDI_N2 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
Lethathamo la 2–20. Ethernet PHY Pin Assignments, Mabitso a Lipontšo le Mesebetsi (Karolo ea 3 ea 3)
| Boto Referense | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 42 | ENETB_MDI_P3 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
| 43 | ENETB_MDI_N3 | — | 2.5-V CMOS | Sehokelo se itšetlehileng ka mecha ea litaba |
HSMC
- Boto ea nts'etsopele e ts'ehetsa sebopeho sa HSMC. Khokahano ea HSMC e ts'ehetsa sebopeho se felletseng sa SPI4.2 (liteishene tse 17 tsa LVDS), lioache tse tharo tsa ho kenya le ho tsoa, hammoho le J.TAG le matshwao a SMB. Liteishene tsa LVDS li ka sebelisoa bakeng sa lipontšo tsa CMOS kapa LVDS.
- HSMC ke tlhaloso e bulehileng e ntlafalitsoeng ea Altera, e u lumellang ho holisa ts'ebetso ea boto ea nts'etsopele ka ho eketsoa ha li- daughtercards (HSMCs).
- Bakeng sa tlhaiso-leseling e batsi mabapi le litlhaloso tsa HSMC joalo ka litekanyetso tsa matšoao, botšepehi ba matšoao, lihokelo tse tsamaellanang, le tlhaiso-leseling ea mochini, sheba bukana ea Litlhaloso tsa High Speed Mezzanine Card (HSMC).
- Sehokelo sa HSMC se na le kakaretso ea lithakhisa tse 172, ho kenyeletsoa lithakhisa tse 120, lithakhisa tse 39 tsa matla, le lithakhisa tse 13 tsa fatše. Lithako tsa fatše li pakeng tsa mela e 'meli ea lipontšo le lithakhisa tsa matla, tse sebetsang ka bobeli e le thebe le tšupiso. Sehokelo sa moamoheli sa HSMC se ipapisitse le lelapa la 0.5 mm-pitch QSH/QTH la lihokelo tsa lebelo le holimo, tsa board-to-board ho tloha Samtec. Ho na le libanka tse tharo sehokelong sena. Bank 1 e tlosa phini e 'ngoe le e 'ngoe ea boraro joalo ka ha e etsoa letotong la QSH-DP/QTH-DP. Bank 2 le bank 3 li na le li-pins tse ngata joalo ka ha li entsoe letotong la QSH/QTH. Kaha boto ea nts'etsopele ea Cyclone VE FPGA ha se boto ea transceiver, li-transceiver pins tsa HSMC ha li kopane le sesebelisoa sa Cyclone VE FPGA.
Setšoantšo sa 2–8 se bontša tlhophiso ea banka ea matšoao mabapi le libanka tse tharo tsa sehokelo sa Samtec.
Setšoantšo sa 2-8. Letšoao la HSMC le Setšoantšo sa Banka
HSMC segokanyimmediamentsi sa sebolokigolo na le programmable bi-directional I/O pins tse ka sebelisoang e le 2.5-V LVCMOS, e leng 3.3-V LVTTL-e lumellana. Lithakhisa tsena li ka sebelisoa hape e le litekanyetso tse fapaneng tsa I/O tse fapaneng ho kenyeletsoa, empa li sa felle feela, LVDS, mini-LVDS, le RSDS tse nang le likanale tse fihlang ho tse 17 tse felletseng.
Joalokaha ho boletsoe bukeng ea Tlhaloso ea High Speed Mezzanine Card (HSMC), LVDS le litekanyetso tsa I / O tse sa feleng li tiisetsoa feela hore li tla sebetsa ha li kopane ho ea ka pin-out ea generic single-ended single-out kapa generic differential pin-out.
Lethathamo la 2–21 le thathamisa mesebetsi ea HSMC, mabitso a matšoao le mesebetsi.
Lethathamo la 2–21. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Karolo 1 ea 3)
| Boto Reference (J7) |
Leano Letshwao Lebitso |
Leholiotsoana V E Setšoantšo sa FPGA
Nomoro |
I/O Standard |
Tlhaloso |
| 33 | HSMC_SDA | AB22 | 2.5-V CMOS | Tsamaiso ya data ya seriale |
| 34 | HSMC_SCL | AC22 | 2.5-V CMOS | Tsamaiso ea serial oache |
| 35 | JTAG_TCK | AC7 | 2.5-V CMOS | JTAG lets'oao la oache |
| 36 | HSMC_JTAG_TMS | — | 2.5-V CMOS | JTAG mokgwa wa ho kgetha letshwao |
| 37 | HSMC_JTAG_TDO | — | 2.5-V CMOS | JTAG tlhahiso ya data |
| 38 | JTAC_FPGA_TDO_RETIMER | — | 2.5-V CMOS | JTAG ho kenya data |
| 39 | HSMC_CLK_OUT0 | AJ14 | 2.5-V CMOS | Oache ea CMOS e inehetseng e felile |
| 40 | HSMC_CLK_IN0 | AB16 | 2.5-V CMOS | Oache e inehetseng ea CMOS ho |
| 41 | HSMC_D0 | AH10 | 2.5-V CMOS | CMOS I/O e inehetseng hanyane 0 |
| 42 | HSMC_D1 | AJ10 | 2.5-V CMOS | CMOS I/O e inehetseng hanyane 1 |
| 43 | HSMC_D2 | Y13 | 2.5-V CMOS | CMOS I/O e inehetseng hanyane 2 |
| 44 | HSMC_D3 | AA14 | 2.5-V CMOS | CMOS I/O e inehetseng hanyane 3 |
| 47 | HSMC_TX_D_P0 | AK27 | LVDS kapa 2.5-V | LVDS TX bit 0 kapa CMOS bit 4 |
| 48 | HSMC_RX_D_P0 | Y16 | LVDS kapa 2.5-V | LVDS RX bit 0 kapa CMOS bit 5 |
| 49 | HSMC_TX_D_N0 | AK28 | LVDS kapa 2.5-V | LVDS TX bit 0n kapa CMOS bit 6 |
| 50 | HSMC_RX_D_N0 | AA26 | LVDS kapa 2.5-V | LVDS RX bit 0n kapa CMOS bit 7 |
| 53 | HSMC_TX_D_P1 | AJ27 | LVDS kapa 2.5-V | LVDS TX bit 1 kapa CMOS bit 8 |
| 54 | HSMC_RX_D_P1 | Y17 | LVDS kapa 2.5-V | LVDS RX bit 1 kapa CMOS bit 9 |
| 55 | HSMC_TX_D_N1 | AK26 | LVDS kapa 2.5-V | LVDS TX bit 1n kapa CMOS bit 10 |
| 56 | HSMC_RX_D_N1 | Y18 | LVDS kapa 2.5-V | LVDS RX bit 1n kapa CMOS bit 11 |
| 59 | HSMC_TX_D_P2 | AG26 | LVDS kapa 2.5-V | LVDS TX bit 2 kapa CMOS bit 12 |
| 60 | HSMC_RX_D_P2 | AA18 | LVDS kapa 2.5-V | LVDS RX bit 2 kapa CMOS bit 13 |
| 61 | HSMC_TX_D_N2 | AH26 | LVDS kapa 2.5-V | LVDS TX bit 2n kapa CMOS bit 14 |
| 62 | HSMC_RX_D_N2 | AA19 | LVDS kapa 2.5-V | LVDS RX bit 2n kapa CMOS bit 15 |
| 65 | HSMC_TX_D_P3 | AJ25 | LVDS kapa 2.5-V | LVDS TX bit 3 kapa CMOS bit 16 |
| 66 | HSMC_RX_D_P3 | Y20 | LVDS kapa 2.5-V | LVDS RX bit 3 kapa CMOS bit 17 |
| 67 | HSMC_TX_D_N3 | AK25 | LVDS kapa 2.5-V | LVDS TX bit 3n kapa CMOS bit 18 |
| 68 | HSMC_RX_D_N3 | AA20 | LVDS kapa 2.5-V | LVDS RX bit 3n kapa CMOS bit 19 |
| 71 | HSMC_TX_D_P4 | AH24 | LVDS kapa 2.5-V | LVDS TX bit 4 kapa CMOS bit 20 |
Lethathamo la 2–21. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Karolo 2 ea 3)
| Boto Reference (J7) |
Leano Letshwao Lebitso |
Leholiotsoana V E Setšoantšo sa FPGA
Nomoro |
I/O Standard |
Tlhaloso |
| 72 | HSMC_RX_D_P4 | AA21 | LVDS kapa 2.5-V | LVDS RX bit 4 kapa CMOS bit 21 |
| 73 | HSMC_TX_D_N4 | AJ24 | LVDS kapa 2.5-V | LVDS TX bit 4n kapa CMOS bit 22 |
| 74 | HSMC_RX_D_N4 | AB21 | LVDS kapa 2.5-V | LVDS RX bit 4n kapa CMOS bit 23 |
| 77 | HSMC_TX_D_P5 | AH21 | LVDS kapa 2.5-V | LVDS TX bit 5 kapa CMOS bit 24 |
| 78 | HSMC_RX_D_P5 | AB19 | LVDS kapa 2.5-V | LVDS RX bit 5 kapa CMOS bit 25 |
| 79 | HSMC_TX_D_N5 | AJ22 | LVDS kapa 2.5-V | LVDS TX bit 5n kapa CMOS bit 26 |
| 80 | HSMC_RX_D_N5 | AC19 | LVDS kapa 2.5-V | LVDS RX bit 5n kapa CMOS bit 27 |
| 83 | HSMC_TX_D_P6 | AJ23 | LVDS kapa 2.5-V | LVDS TX bit 6 kapa CMOS bit 28 |
| 84 | HSMC_RX_D_P6 | AC21 | LVDS kapa 2.5-V | LVDS RX bit 6 kapa CMOS bit 29 |
| 85 | HSMC_TX_D_N6 | AK23 | LVDS kapa 2.5-V | LVDS TX bit 6n kapa CMOS bit 30 |
| 86 | HSMC_RX_D_N6 | AD20 | LVDS kapa 2.5-V | LVDS RX bit 6n kapa CMOS bit 31 |
| 89 | HSMC_TX_D_P7 | AK21 | LVDS kapa 2.5-V | LVDS TX bit 7 kapa CMOS bit 32 |
| 90 | HSMC_RX_D_P7 | AD19 | LVDS kapa 2.5-V | LVDS RX bit 7 kapa CMOS bit 33 |
| 91 | HSMC_TX_D_N7 | AK22 | LVDS kapa 2.5-V | LVDS TX bit 7n kapa CMOS bit 34 |
| 92 | HSMC_RX_D_N7 | AE20 | LVDS kapa 2.5-V | LVDS RX bit 7n kapa CMOS bit 35 |
| 95 | HSMC_CLK_OUT_P1 | AE22 | LVDS kapa 2.5-V | LVDS kapa CMOS e tima 1 kapa CMOS bit 36 |
| 96 | HSMC_CLK_IN_P1 | AB14 | LVDS kapa 2.5-V | Oache ea LVDS kapa CMOS ho 1 kapa CMOS bit 37 |
| 97 | HSMC_CLK_OUT_N1 | AF23 | LVDS kapa 2.5-V | LVDS kapa CMOS e tima 1 kapa CMOS bit 38 |
| 98 | HSMC_CLK_IN_N1 | AC14 | LVDS kapa 2.5-V | Oache ea LVDS kapa CMOS ho 1 kapa CMOS bit 39 |
| 101 | HSMC_TX_D_P8 | AJ20 | LVDS kapa 2.5-V | LVDS TX bit 8 kapa CMOS bit 40 |
| 102 | HSMC_RX_D_P8 | AF21 | LVDS kapa 2.5-V | LVDS RX bit 8 kapa CMOS bit 41 |
| 103 | HSMC_TX_D_N8 | AK20 | LVDS kapa 2.5-V | LVDS TX bit 8n kapa CMOS bit 42 |
| 104 | HSMC_RX_D_N8 | AG22 | LVDS kapa 2.5-V | LVDS RX bit 8n kapa CMOS bit 43 |
| 107 | HSMC_TX_D_P9 | AJ19 | LVDS kapa 2.5-V | LVDS TX bit 9 kapa CMOS bit 44 |
| 108 | HSMC_RX_D_P9 | AF20 | LVDS kapa 2.5-V | LVDS RX bit 9 kapa CMOS bit 45 |
| 109 | HSMC_TX_D_N9 | AK18 | LVDS kapa 2.5-V | LVDS TX bit 9n kapa CMOS bit 46 |
| 110 | HSMC_RX_D_N9 | AG21 | LVDS kapa 2.5-V | LVDS RX bit 9n kapa CMOS bit 47 |
| 113 | HSMC_TX_D_P10 | AJ17 | LVDS kapa 2.5-V | LVDS TX bit 10 kapa CMOS bit 48 |
| 114 | HSMC_RX_D_P10 | AF18 | LVDS kapa 2.5-V | LVDS RX bit 10 kapa CMOS bit 49 |
| 115 | HSMC_TX_D_N10 | AJ18 | LVDS kapa 2.5-V | LVDS TX bit 10n kapa CMOS bit 50 |
| 116 | HSMC_RX_D_N10 | AF19 | LVDS kapa 2.5-V | LVDS RX bit 10n kapa CMOS bit 51 |
| 119 | HSMC_TX_D_P11 | AK25 | LVDS kapa 2.5-V | LVDS TX bit 11 kapa CMOS bit 52 |
| 120 | HSMC_RX_D_P11 | AG18 | LVDS kapa 2.5-V | LVDS RX bit 11 kapa CMOS bit 53 |
| 121 | HSMC_TX_D_N11 | AG24 | LVDS kapa 2.5-V | LVDS TX bit 11n kapa CMOS bit 54 |
| 122 | HSMC_RX_D_N11 | AG19 | LVDS kapa 2.5-V | LVDS RX bit 11n kapa CMOS bit 55 |
| 125 | HSMC_TX_D_P12 | AH19 | LVDS kapa 2.5-V | LVDS TX bit 12 kapa CMOS bit 56 |
| 126 | HSMC_RX_D_P12 | AK16 | LVDS kapa 2.5-V | LVDS RX bit 12 kapa CMOS bit 57 |
| 127 | HSMC_TX_D_N12 | AH20 | LVDS kapa 2.5-V | LVDS TX bit 12n kapa CMOS bit 58 |
Lethathamo la 2–21. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Karolo 3 ea 3)
| Boto Reference (J7) |
Leano Letshwao Lebitso |
Leholiotsoana V E Setšoantšo sa FPGA
Nomoro |
I/O Standard |
Tlhaloso |
| 128 | HSMC_RX_D_N12 | AK17 | LVDS kapa 2.5-V | LVDS RX bit 12n kapa CMOS bit 59 |
| 131 | HSMC_TX_D_P13 | AG17 | LVDS kapa 2.5-V | LVDS TX bit 13 kapa CMOS bit 60 |
| 132 | HSMC_RX_D_P13 | AF16 | LVDS kapa 2.5-V | LVDS RX bit 13 kapa CMOS bit 61 |
| 133 | HSMC_TX_D_N13 | AH17 | LVDS kapa 2.5-V | LVDS TX bit 13n kapa CMOS bit 62 |
| 134 | HSMC_RX_D_N13 | AG16 | LVDS kapa 2.5-V | LVDS RX bit 13n kapa CMOS bit 63 |
| 137 | HSMC_TX_D_P14 | AJ15 | LVDS kapa 2.5-V | LVDS TX bit 14 kapa CMOS bit 64 |
| 138 | HSMC_RX_D_P14 | AE16 | LVDS kapa 2.5-V | LVDS RX bit 14 kapa CMOS bit 65 |
| 139 | HSMC_TX_D_N14 | AK15 | LVDS kapa 2.5-V | LVDS TX bit 14n kapa CMOS bit 66 |
| 140 | HSMC_RX_D_N14 | AF15 | LVDS kapa 2.5-V | LVDS RX bit 14n kapa CMOS bit 67 |
| 143 | HSMC_TX_D_P15 | AH14 | LVDS kapa 2.5-V | LVDS TX bit 15 kapa CMOS bit 68 |
| 144 | HSMC_RX_D_P15 | AD17 | LVDS kapa 2.5-V | LVDS RX bit 15 kapa CMOS bit 69 |
| 145 | HSMC_TX_D_N15 | AH15 | LVDS kapa 2.5-V | LVDS TX bit 15n kapa CMOS bit 70 |
| 146 | HSMC_RX_D_N15 | AE17 | LVDS kapa 2.5-V | LVDS RX bit 15n kapa CMOS bit 71 |
| 149 | HSMC_TX_D_P16 | AE15 | LVDS kapa 2.5-V | LVDS TX bit 16 kapa CMOS bit 72 |
| 150 | HSMC_RX_D_P16 | AD18 | LVDS kapa 2.5-V | LVDS RX bit 16 kapa CMOS bit 73 |
| 151 | HSMC_TX_D_N16 | AF14 | LVDS kapa 2.5-V | LVDS TX bit 16n kapa CMOS bit 74 |
| 152 | HSMC_RX_D_N16 | AE18 | LVDS kapa 2.5-V | LVDS RX bit 16n kapa CMOS bit 75 |
| 155 | HSMC_CLK_OUT_P2 | AG23 | LVDS kapa 2.5-V | LVDS kapa CMOS e tima 2 kapa CMOS bit 76 |
| 156 | HSMC_CLK_IN_P2 | Y15 | LVDS kapa 2.5-V | Oache ea LVDS kapa CMOS ho 2 kapa CMOS bit 77 |
| 157 | HSMC_CLK_OUT_N2 | AH22 | LVDS kapa 2.5-V | LVDS kapa CMOS e tima 2 kapa CMOS bit 78 |
| 158 | HSMC_CLK_IN_N2 | AA15 | LVDS kapa 2.5-V | Oache ea LVDS kapa CMOS ho 2 kapa CMOS bit 79 |
| 160 | HSMC_PRSNTn | AK5 | 2.5-V CMOS | Sebono sa boteng ba boema-kepe ba HSMC |
RS-232 Serial UART
Sehokelo sa li-angled DSUB 9-pin hammoho le transceiver e tšehetsang RS-232 e fana ka ts'ehetso bakeng sa ho kenya tšebetsong mocha o tloaelehileng oa RS-232 serial UART botong ena. Sehokelo se na le li-pinouts tse tšoanang le sesebelisoa sa terminal sa data mme se hloka thapo e tloaelehileng feela (ha ho na modem e se nang letho e hlokahalang bakeng sa sebopeho sa PC). Sebaka se inehetseng sa ho feto-fetoha ha maemo se sebelisoa ho fetolela lipakeng tsa maemo a LVTTL le RS-232. Litšupiso tsa boto D23 le D24 ke li-LED tsa serial tsa UART tse khantšang ho bontša ts'ebetso ea RX le TX.
Lethathamo la 2–24 le thathamisa likabelo tsa serial tsa UART tsa RS-232, mabitso a matšoao, le mesebetsi.
Mabitso le mefuta ea matšoao li amana le Leholiotsoana VE FPGA ho latela maemo le tataiso ea I/O.
Lethathamo la 2–22. RS-232 Serial UART Schematic Signal Mabitso le Mesebetsi
| Boto Reference (U20) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 14 | UART_TXD | AB9 | 3.3-V | Fetisetsa data |
| 15 | UART_RTS | AH6 | 3.3-V | Kopa ho romela |
Lethathamo la 2–22. RS-232 Serial UART Schematic Signal Mabitso le Mesebetsi
| Boto Reference (U20) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 16 | UART_RXD | AG6 | 3.3-V | Amohela ya data |
| 13 | UART_CTS | AF8 | 3.3-V | E hlakile ho romella |
USB-UART
Boto ea nts'etsopele e ts'ehetsa sebopeho sa UART ka sehokelo sa USB se sebelisang borokho ba Silicon Labs CP2104 USB-to-UART. Ho nolofatsa puisano ea moamoheli le CP2104, o kopuoa ho sebelisa likhanni tsa borokho tsa USB-to-UART Virtual COM Port (VCP).
Bakhanni ba VCP ba fumaneha ho: www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx
Lethathamo la 2–23 le thathamisa likabelo tsa phini tsa USB-UART, mabitso a matšoao, le mesebetsi. Mabitso le mefuta ea matšoao li amana le Leholiotsoana VE FPGA ho latela maemo le tataiso ea I/O
Lethathamo la 2–23. USB-UART Schematic Signal Mabitso le Mesebetsi
| Boto Reference (U20) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 1 | USB_UART_RI | AD12 | 2.5-V | Kenyelletso ea taolo ea selikalikoe (e sebetsang e tlase) |
| 24 | USB_UART_DCD | AD13 | 2.5-V | Mofani oa data o lemoha tlhahiso ea taolo (e sebetsa e tlase) |
| 22 | USB_UART_DSR | V12 | 2.5-V | Kenyelletso ea taolo ea sete ea data (e sebetsa e tlase) |
| 21 | USB_UART_RXD | AF10 | 2.5-V | Asynchronous data input (UART fumana) |
| 19 | USB_UART_RTS | AE12 | 2.5-V | E itokiselitse ho romela tlhahiso ea taolo (tlase e sebetsang) |
| 12 | USB_UART_GPIO2 | AE13 | 2.5-V | Kenyelletso kapa tlhahiso e ka lokisoang ke mosebelisi. |
| 23 | USB_UART_DTR | AE10 | 2.5-V | Sephetho se lokiselitsoeng ho laola terminal ea data (e tlase e sebetsang) |
| 20 | USB_UART_TXD | W12 | 2.5-V | Asynchronous data output (UART transmit) |
| 18 | USB_UART_CTS | AJ1 | 2.5-V | Hlakola ho romella tlhahiso ea taolo (e sebetsa e tlase) |
| 15 | USB_UART_SUSPENDn | — | 2.5-V | Pin e tlase haholo ha CP2104 e le maemong a ho emisa ha USB. |
| 17 | USB_UART_SUSPEND | — | 2.5-V | Pin e holimo ha CP2104 e le maemong a ho emisa ha USB. |
| 9 | USB_UART_RSTn | — | 2.5-V | Seta sesebelisoa bocha |
Mohopolo
Karolo ena e hlalosa tšehetso ea memori ea boto ea nts'etsopele le mabitso a bona a matšoao, mefuta, le khokahano e amanang le Leholiotsoana VE FPGA. Boto ea nts'etsopele e na le li-interfaces tse latelang tsa memori:
- DDR3 SDRAM
- LPDDR2 SDRAM
- EEPROM
- Synchronous SRAM
- Flash e tsamaisanang
Bakeng sa tlhaiso-leseling e batsi ka li-interface tsa memori, sheba litokomane tse latelang:
- Karolo ea Tlhahlobo ea Nako ho Buka ea External Memory Interface Handbook.
- DDR, DDR2, le DDR3 SDRAM Design Tutorials karolo ho Buka ea External Memory Interface Handbook.
DDR3 SDRAM
- Boto ea nts'etsopele e ts'ehetsa li-interfaces tse peli tsa 16Mx16x8 le tse peli tsa 16Mx8x8 DDR3 SDRAM bakeng sa phihlello ea memori e latellanang ka lebelo le holimo haholo.
- Bese ea data ea 32-bit e na le lisebelisoa tse peli tsa x16 tse sebelisang sebopeho sa "Soft memory controller" (SMC). Ka SMC, segokanyimmediamentsi sa sebolokigolo sena se sebetsa ka lebelo le lebisitsweng la 300 MHz bakeng sa bandwidth e phahameng ya theory e fetang 9.6 Gbps. Maqhubu a phahameng a sesebelisoa sena sa DDR3 ke 800 MHz ka CAS latency ea 11.
- Lethathamo la 2–24 le thathamisa likabelo tsa DDR3, mabitso a matšoao le mesebetsi. Mabitso le mefuta ea matšoao li amana le Leholiotsoana VE FPGA ho latela maemo le tataiso ea I/O.
Lethathamo la 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Karolo ea 1 ea 4)
| Boto Referense | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| DDR3 x16 (U8) | ||||
| N3 | DDR3_A0 | A16 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| P7 | DDR3_A1 | G23 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| P3 | DDR3_A2 | E21 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| N2 | DDR3_A3 | E22 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| P8 | DDR3_A4 | A20 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| P2 | DDR3_A5 | A26 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| R8 | DDR3_A6 | A15 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| R2 | DDR3_A7 | B26 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| T8 | DDR3_A8 | H17 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| R3 | DDR3_A9 | D14 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| L7 | DDR3_A10 | E23 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
Lethathamo la 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Karolo ea 2 ea 4)
| Boto Referense | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| R7 | DDR3_A11 | E20 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| N7 | DDR3_A12 | C25 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| T3 | DDR3_A13 | B13 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| M2 | DDR3_BA0 | J18 | 1.5-V SSTL Sehlopha sa I | bese ea aterese ea banka |
| N8 | DDR3_BA1 | F20 | 1.5-V SSTL Sehlopha sa I | bese ea aterese ea banka |
| M3 | DDR3_BA2 | D19 | 1.5-V SSTL Sehlopha sa I | bese ea aterese ea banka |
| K3 | DDR3_CASN | L20 | 1.5-V SSTL Sehlopha sa I | Khetha aterese ea mola |
| K9 | DDR3_CKE | C11 | 1.5-V SSTL Sehlopha sa I | Khetha aterese ea kholomo |
| J7 | DDR3_CLK_P | J20 | Phapang ea 1.5-V SSTL Sehlopha sa I | Oache ea tlhahiso e fapaneng |
| K7 | DDR3_CLK_N | H20 | Phapang ea 1.5-V SSTL Sehlopha sa I | Oache ea tlhahiso e fapaneng |
| L2 | DDR3_CSN | G17 | 1.5-V SSTL Sehlopha sa I | Khetho ea chip |
| E7 | DDR3_DM0 | D23 | 1.5-V SSTL Sehlopha sa I | Ngola mask byte lane |
| D3 | DDR3_DM1 | D18 | 1.5-V SSTL Sehlopha sa I | Ngola mask byte lane |
| E3 | DDR3_DQ0 | A25 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 0 |
| H8 | DDR3_DQ1 | D22 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 0 |
| F7 | DDR3_DQ2 | C21 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 0 |
| H7 | DDR3_DQ3 | C19 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 0 |
| F2 | DDR3_DQ4 | C20 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 0 |
| G2 | DDR3_DQ5 | C22 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 0 |
| F8 | DDR3_DQ6 | D25 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 0 |
| H3 | DDR3_DQ7 | D20 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 0 |
| A7 | DDR3_DQ8 | B24 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 1 |
| C3 | DDR3_DQ9 | A21 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 1 |
| A3 | DDR3_DQ10 | B21 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 1 |
| D7 | DDR3_DQ11 | F19 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 1 |
| A2 | DDR3_DQ12 | C24 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 1 |
| C2 | DDR3_DQ13 | B23 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 1 |
| B8 | DDR3_DQ14 | E18 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 1 |
| C8 | DDR3_DQ15 | A23 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 1 |
| F3 | DDR3_DQS_P0 | K20 | Phapang ea 1.5-V SSTL Sehlopha sa I | Data strobe P byte lane 0 |
| G3 | DDR3_DQS_N0 | J19 | Phapang ea 1.5-V SSTL Sehlopha sa I | Data strobe N byte lane 0 |
| C7 | DDR3_DQS_P1 | L18 | Phapang ea 1.5-V SSTL Sehlopha sa I | Data strobe P byte lane 1 |
| B7 | DDR3_DQS_N1 | K18 | Phapang ea 1.5-V SSTL Sehlopha sa I | Data strobe N byte lane 1 |
| K1 | DDR3_ODT | H19 | 1.5-V SSTL Sehlopha sa I | Ho felloa ke nako hoa khoneha |
Lethathamo la 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Karolo ea 3 ea 4)
| Boto Referense | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| J3 | DDR3_RASN | A24 | 1.5-V SSTL Sehlopha sa I | Khetha aterese ea mola |
| T2 | DDR3_RESETN | L19 | 1.5-V SSTL Sehlopha sa I | Seta bocha |
| L3 | DDR3_WEN | B22 | 1.5-V SSTL Sehlopha sa I | Ngola nolofalletsa |
| L8 | DDR3_ZQ01 | — | 1.5-V SSTL Sehlopha sa I | ZQ impedance calibration |
| DDR3 x16 (U7) | ||||
| N3 | DDR3_A0 | A16 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| P7 | DDR3_A1 | G23 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| P3 | DDR3_A2 | E21 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| N2 | DDR3_A3 | E22 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| P8 | DDR3_A4 | A20 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| P2 | DDR3_A5 | A26 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| R8 | DDR3_A6 | A15 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| R2 | DDR3_A7 | B26 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| T8 | DDR3_A8 | H17 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| R3 | DDR3_A9 | D14 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| L7 | DDR3_A10 | E23 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| R7 | DDR3_A11 | E20 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| N7 | DDR3_A12 | C25 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| T3 | DDR3_A13 | B13 | 1.5-V SSTL Sehlopha sa I | Aterese bese |
| M2 | DDR3_BA0 | J18 | 1.5-V SSTL Sehlopha sa I | bese ea aterese ea banka |
| N8 | DDR3_BA1 | F20 | 1.5-V SSTL Sehlopha sa I | bese ea aterese ea banka |
| M3 | DDR3_BA2 | D19 | 1.5-V SSTL Sehlopha sa I | bese ea aterese ea banka |
| K3 | DDR3_CASN | L20 | 1.5-V SSTL Sehlopha sa I | Khetha aterese ea mola |
| K9 | DDR3_CKE | AK18 | 1.5-V SSTL Sehlopha sa I | Khetha aterese ea kholomo |
| K7 | DDR3_CLK_P | J20 | 1.5-V SSTL Sehlopha sa I | Oache ea tlhahiso e fapaneng |
| J7 | DDR3_CLK_N | H20 | 1.5-V SSTL Sehlopha sa I | Oache ea tlhahiso e fapaneng |
| L2 | DDR3_CSN | G17 | 1.5-V SSTL Sehlopha sa I | Khetho ea chip |
| E7 | DDR3_DM2 | A19 | 1.5-V SSTL Sehlopha sa I | Ngola mask byte lane |
| D3 | DDR3_DM3 | B14 | 1.5-V SSTL Sehlopha sa I | Ngola mask byte lane |
| F2 | DDR3_DQ16 | G18 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 2 |
| F8 | DDR3_DQ17 | B18 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 2 |
| E3 | DDR3_DQ18 | A18 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 2 |
| F7 | DDR3_DQ19 | F18 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 2 |
| H3 | DDR3_DQ20 | C14 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 2 |
| G2 | DDR3_DQ21 | C17 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 2 |
| H7 | DDR3_DQ22 | B17 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 2 |
| H8 | DDR3_DQ23 | B19 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 2 |
| A2 | DDR3_DQ24 | C15 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 3 |
Lethathamo la 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Karolo ea 4 ea 4)
| Boto Referense | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| C2 | DDR3_DQ25 | D17 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 3 |
| D7 | DDR3_DQ26 | C12 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 3 |
| A7 | DDR3_DQ27 | E17 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 3 |
| A3 | DDR3_DQ28 | C16 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 3 |
| C3 | DDR3_DQ29 | A14 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 3 |
| B8 | DDR3_DQ30 | D12 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 3 |
| C8 | DDR3_DQ31 | A13 | 1.5-V SSTL Sehlopha sa I | Data bus byte lane 3 |
| F3 | DDR3_DQS_P2 | K16 | Phapang ea 1.5-V SSTL Sehlopha sa I | Data strobe P byte lane 2 |
| G3 | DDR3_DQS_N2 | L16 | Phapang ea 1.5-V SSTL Sehlopha sa I | Data strobe N byte lane 2 |
| C7 | DDR3_DQS_P3 | K17 | Phapang ea 1.5-V SSTL Sehlopha sa I | Data strobe P byte lane 3 |
| B7 | DDR3_DQS_N3 | J17 | Phapang ea 1.5-V SSTL Sehlopha sa I | Data strobe N byte lane 3 |
| K1 | DDR3_ODT | H19 | 1.5-V SSTL Sehlopha sa I | Ho felloa ke nako hoa khoneha |
| J3 | DDR3_RASN | A24 | 1.5-V SSTL Sehlopha sa I | Khetha aterese ea mola |
| T2 | DDR3_RESETN | L19 | 1.5-V SSTL Sehlopha sa I | Seta bocha |
| L3 | DDR3_WEN | B22 | 1.5-V SSTL Sehlopha sa I | Ngola nolofalletsa |
| L8 | DDR3_ZQ2 | — | 1.5-V SSTL Sehlopha sa I | ZQ impedance calibration |
LPDDR2 SDRAM
LPDDR2 ke sesebelisoa sa DDR2 SDRAM se nang le matla a tlaase se sebetsang ho 1.2 V. Khokahano ena e hokahana le libanka tsa I/O tse tšekaletseng moeling o ka holimo oa sesebelisoa sa FPGA.
Lebelo la sesebelisoa ke 300 MHz. Ho sebelisoa tlhophiso ea x16 feela leha LPDDR2 SDRAM e botong e le sesebelisoa sa x32.
Lethathamo la 2–25 le thathamisa likabelo tsa phini ea LPDDR2 SDRAM, mabitso a matšoao le mesebetsi.
Mabitso le mefuta ea matšoao li amana le Leholiotsoana VE FPGA ho latela maemo le tataiso ea I/O.
Lethathamo la 2–25. LPDDR2 SDRAM Schematic Signal Mabitso le Mesebetsi
| Boto Reference (U9) | Leano Letshwao Lebitso | Leholiotsoana VE Nomoro ea Pin ea FPGA | I/O Standard | Tlhaloso |
| AC6 | LPDDR2_CA0 | Y30 | 1.2-V HSUL | Aterese bese |
| AB6 | LPDDR2_CA1 | T30 | 1.2-V HSUL | Aterese bese |
| AC7 | LPDDR2_CA2 | W29 | 1.2-V HSUL | Aterese bese |
| AB8 | LPDDR2_CA3 | AB29 | 1.2-V HSUL | Aterese bese |
| AB9 | LPDDR2_CA4 | W30 | 1.2-V HSUL | Aterese bese |
| W1 | LPDDR2_CA5 | U29 | 1.2-V HSUL | Aterese bese |
| V2 | LPDDR2_CA6 | AC30 | 1.2-V HSUL | Aterese bese |
| U1 | LPDDR2_CA7 | R30 | 1.2-V HSUL | Aterese bese |
Lethathamo la 2–25. LPDDR2 SDRAM Schematic Signal Mabitso le Mesebetsi
| Boto Reference (U9) | Leano Letshwao Lebitso | Leholiotsoana VE Nomoro ea Pin ea FPGA | I/O Standard | Tlhaloso |
| T2 | LPDDR2_CA8 | T28 | 1.2-V HSUL | Aterese bese |
| T1 | LPDDR2_CA9 | T25 | 1.2-V HSUL | Aterese bese |
| Y2 | LPDDR2_CK | V21 | Phapang 1.2-V HSUL | Oache e fapaneng ea tlhahiso ea P |
| Y1 | LPDDR2_CKN | V22 | Phapang 1.2-V HSUL | Oache e fapaneng ea tlhahiso N |
| AC3 | LPDDR2_CKE | T29 | 1.2-V HSUL | Oache e nolofalletsa |
| AB3 | LPDDR2_CSN | R26 | 1.2-V HSUL | Khetho ea chip |
| N23 | LPDDR2_DM0 | AG29 | 1.2-V HSUL | Mask ea data |
| L23 | LPDDR2_DM1 | AB27 | 1.2-V HSUL | Mask ea data |
| AB20 | LPDDR2_DM2 | — | 1.2-V HSUL | Mask ea data |
| B20 | LPDDR2_DM3 | — | 1.2-V HSUL | Mask ea data |
| AA23 | LPDDR2_DQ0 | AG28 | 1.2-V HSUL | Data bus byte lane 0 |
| Y22 | LPDDR2_DQ1 | AH30 | 1.2-V HSUL | Data bus byte lane 0 |
| W22 | LPDDR2_DQ2 | AA28 | 1.2-V HSUL | Data bus byte lane 0 |
| W23 | LPDDR2_DQ3 | AH29 | 1.2-V HSUL | Data bus byte lane 0 |
| V23 | LPDDR2_DQ4 | Y28 | 1.2-V HSUL | Data bus byte lane 0 |
| U22 | LPDDR2_DQ5 | AE30 | 1.2-V HSUL | Data bus byte lane 0 |
| T22 | LPDDR2_DQ6 | AJ28 | 1.2-V HSUL | Data bus byte lane 0 |
| T23 | LPDDR2_DQ7 | AD30 | 1.2-V HSUL | Data bus byte lane 0 |
| H22 | LPDDR2_DQ8 | AC29 | 1.2-V HSUL | Data bus byte lane 1 |
| H23 | LPDDR2_DQ9 | AF30 | 1.2-V HSUL | Data bus byte lane 1 |
| G23 | LPDDR2_DQ10 | AA30 | 1.2-V HSUL | Data bus byte lane 1 |
| F22 | LPDDR2_DQ11 | AE28 | 1.2-V HSUL | Data bus byte lane 1 |
| E22 | LPDDR2_DQ12 | AF29 | 1.2-V HSUL | Data bus byte lane 1 |
| E23 | LPDDR2_DQ13 | AD28 | 1.2-V HSUL | Data bus byte lane 1 |
| D23 | LPDDR2_DQ14 | V27 | 1.2-V HSUL | Data bus byte lane 1 |
| C22 | LPDDR2_DQ15 | W28 | 1.2-V HSUL | Data bus byte lane 1 |
| AB12 | LPDDR2_DQ16 | — | 1.2-V HSUL | Data bus byte lane 2 |
| AC13 | LPDDR2_DQ17 | — | 1.2-V HSUL | Data bus byte lane 2 |
| AB14 | LPDDR2_DQ18 | — | 1.2-V HSUL | Data bus byte lane 2 |
| AC14 | LPDDR2_DQ19 | — | 1.2-V HSUL | Data bus byte lane 2 |
| AB15 | LPDDR2_DQ20 | — | 1.2-V HSUL | Data bus byte lane 2 |
| AC16 | LPDDR2_DQ21 | — | 1.2-V HSUL | Data bus byte lane 2 |
| AB17 | LPDDR2_DQ22 | — | 1.2-V HSUL | Data bus byte lane 2 |
| AC17 | LPDDR2_DQ23 | — | 1.2-V HSUL | Data bus byte lane 2 |
| B17 | LPDDR2_DQ24 | — | 1.2-V HSUL | Data bus byte lane 3 |
| A17 | LPDDR2_DQ25 | — | 1.2-V HSUL | Data bus byte lane 3 |
| A16 | LPDDR2_DQ26 | — | 1.2-V HSUL | Data bus byte lane 3 |
| B15 | LPDDR2_DQ27 | — | 1.2-V HSUL | Data bus byte lane 3 |
| B14 | LPDDR2_DQ28 | — | 1.2-V HSUL | Data bus byte lane 3 |
Lethathamo la 2–25. LPDDR2 SDRAM Schematic Signal Mabitso le Mesebetsi
| Boto Reference (U9) | Leano Letshwao Lebitso | Leholiotsoana VE Nomoro ea Pin ea FPGA | I/O Standard | Tlhaloso |
| A14 | LPDDR2_DQ29 | — | 1.2-V HSUL | Data bus byte lane 3 |
| A13 | LPDDR2_DQ30 | — | 1.2-V HSUL | Data bus byte lane 3 |
| B12 | LPDDR2_DQ31 | — | 1.2-V HSUL | Data bus byte lane 3 |
| R23 | LPDDR2_DQS0 | V26 | Phapang 1.2-V HSUL | Data strobe P byte lane 0 |
| P22 | LPDDR2_DQSN0 | U26 | Phapang 1.2-V HSUL | Data strobe N byte lane 0 |
| J22 | LPDDR2_DQS1 | U27 | Phapang 1.2-V HSUL | Data strobe P byte lane 1 |
| K23 | LPDDR2_DQSN1 | U28 | Phapang 1.2-V HSUL | Data strobe N byte lane 1 |
| AB18 | LPDDR2_DQS2 | — | Phapang 1.2-V HSUL | Data strobe P byte lane 2 |
| AC19 | LPDDR2_DQSN2 | — | Phapang 1.2-V HSUL | Data strobe N byte lane 2 |
| B18 | LPDDR2_DQS3 | — | Phapang 1.2-V HSUL | Data strobe P byte lane 3 |
| A19 | LPDDR2_DQSN4 | — | Phapang 1.2-V HSUL | Data strobe N byte lane 3 |
| P1 | LPDDR2_ZQ | — | 1.2-V | ZQ impedance calibration |
EEPROM
Boto ena e kenyelletsa sesebelisoa sa 64-Kb EEPROM. Sesebelisoa sena se na le 2-wire serial interface bese I2C.
Lethathamo la 2–26 le thathamisa likabelo tsa phini tsa EEPROM, mabitso a matšoao, le mesebetsi. Mabitso le mefuta ea matšoao li amana le Leholiotsoana VE FPGA ho latela maemo le tataiso ea I/O.
Lethathamo la 2–26. EEPROM Schematic Signal Mabitso le Mesebetsi
| Boto Reference (U12) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 1 | EEPROM_A0 | — | 3.3-V | Aterese ea Chip |
| 2 | EEPROM_A1 | — | 3.3-V | Aterese ea Chip |
| 3 | EEPROM_A2 | — | 3.3-V | Aterese ea Chip |
| 5 | EEPROM_SDA | AH7 | 3.3-V | Aterese ea serial kapa data |
| 6 | EEPROM_SCL | AG7 | 3.3-V | Oache ea serial |
| 7 | EEPROM_WP | — | 3.3-V | Ngola tšireletso |
Synchronous SRAM
Boto ea nts'etsopele e ts'ehetsa SRAM e tloaelehileng ea 18-Mb bakeng sa taeo le polokelo ea data e nang le bokhoni bo tlase ba ho fihlella ka tšohanyetso. Sesebelisoa se na le sebopeho sa 1024K x 18-bits. Sesebelisoa sena ke karolo ea bese ea FSM e arolelanoang e hokahanyang le memori ea flash, SRAM, le MAX V CPLD 5M2210 System Controller. Lebelo la sesebelisoa ke 250 MHz ea data e le 'ngoe. Ha ho na lebelo le tlase la sesebelisoa sena. Theoretical bandwidth ea sebopeho sena ke 4 Gbps bakeng sa ho phatloha ho tsoelang pele. The read latency bakeng sa aterese efe kapa efe ke lioache tse peli ha nako ea ho ngola e le oache e le 'ngoe.
Lethathamo la 2–27 le thathamisa likabelo tsa phini tsa SSRAM, mabitso a matšoao, le mesebetsi.
Lethathamo la 2–27. Likabelo tsa Pin tsa SSRAM, Mabitso a Letšoao la Sekema, le Mesebetsi (Karolo ea 1 ea 2)
| Boto Reference (U11) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 86 | SRAM_OEN | E7 | 2.5-V | Output nolofalletsa |
| 87 | SRAM_WEN | D6 | 2.5-V | Ngola nolofalletsa |
| 37 | FSM_A1 | B11 | 2.5-V | Aterese bese |
| 36 | FSM_A2 | A11 | 2.5-V | Aterese bese |
| 44 | FSM_A3 | D9 | 2.5-V | Aterese bese |
| 42 | FSM_A4 | C10 | 2.5-V | Aterese bese |
| 34 | FSM_A5 | A10 | 2.5-V | Aterese bese |
| 47 | FSM_A6 | A9 | 2.5-V | Aterese bese |
| 43 | FSM_A7 | C9 | 2.5-V | Aterese bese |
| 46 | FSM_A8 | B8 | 2.5-V | Aterese bese |
| 45 | FSM_A9 | B7 | 2.5-V | Aterese bese |
| 35 | FSM_A10 | A8 | 2.5-V | Aterese bese |
| 32 | FSM_A11 | B6 | 2.5-V | Aterese bese |
| 33 | FSM_A12 | A6 | 2.5-V | Aterese bese |
| 50 | FSM_A13 | C7 | 2.5-V | Aterese bese |
| 48 | FSM_A14 | C6 | 2.5-V | Aterese bese |
| 100 | FSM_A15 | F13 | 2.5-V | Aterese bese |
| 99 | FSM_A16 | E13 | 2.5-V | Aterese bese |
| 82 | FSM_A17 | A5 | 2.5-V | Aterese bese |
| 80 | FSM_A18 | A4 | 2.5-V | Aterese bese |
| 49 | FSM_A19 | J7 | 2.5-V | Aterese bese |
| 81 | FSM_A20 | H7 | 2.5-V | Aterese bese |
| 39 | FSM_A21 | J9 | 2.5-V | Aterese bese |
| 58 | FSM_D0 | F16 | 2.5-V | Data bese |
| 59 | FSM_D1 | E16 | 2.5-V | Data bese |
| 62 | FSM_D2 | M9 | 2.5-V | Data bese |
| 63 | FSM_D3 | M8 | 2.5-V | Data bese |
| 68 | FSM_D4 | F15 | 2.5-V | Data bese |
| 69 | FSM_D5 | E15 | 2.5-V | Data bese |
Lethathamo la 2–27. Likabelo tsa Pin tsa SSRAM, Mabitso a Letšoao la Sekema, le Mesebetsi (Karolo ea 2 ea 2)
| Boto Reference (U11) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| 72 | FSM_D6 | E12 | 2.5-V | Data bese |
| 73 | FSM_D7 | D13 | 2.5-V | Data bese |
| 23 | FSM_D8 | J15 | 2.5-V | Data bese |
| 22 | FSM_D9 | H15 | 2.5-V | Data bese |
| 19 | FSM_D10 | E11 | 2.5-V | Data bese |
| 18 | FSM_D11 | D10 | 2.5-V | Data bese |
| 12 | FSM_D12 | L10 | 2.5-V | Data bese |
| 13 | FSM_D13 | L9 | 2.5-V | Data bese |
| 8 | FSM_D14 | G14 | 2.5-V | Data bese |
| 9 | FSM_D15 | F14 | 2.5-V | Data bese |
| 85 | SRAM_ADSCN | E6 | 2.5-V | Selaoli sa maemo a aterese |
| 84 | SRAM_ADSPN | J10 | 2.5-V | Sesebelisoa sa boemo ba aterese |
| 83 | SRAM_ADVN | G6 | 2.5-V | Aterese e nepahetse |
| 93 | SRAM_BWAN | A3 | 2.5-V | Byte ngola khetha |
| 94 | SRAM_BWBN | A2 | 2.5-V | Byte ngola khetha |
| 97 | SRAM_CE2 | — | 2.5-V | Chip e nolofalletsa 2 |
| 92 | SRAM_CE3N | — | 2.5-V | Chip e nolofalletsa 3 |
| 98 | SRAM_CEN | D7 | 2.5-V | Chip e nolofalletsa 1 |
| 89 | SRAM_CLK | K10 | 2.5-V | Tshupanako |
| 88 | SRAM_GWN | — | 2.5-V | Global ngola nolofalletsa |
| 31 | SRAM_MODE | — | 2.5-V | Khetho ea tatellano e phatlohileng |
| 64 | SRAM_ZZ | — | 2.5-V | Mokhoa oa ho robala oa matla |
Khanya
Boto ea nts'etsopele e ts'ehetsa sesebelisoa sa Flash se lumellanang sa 512-Mb CFI bakeng sa polokelo e sa fetoheng ea data ea tlhophiso ea FPGA, tlhaiso-leseling ea boto, data ea kopo ea liteko, le sebaka sa khoutu ea mosebelisi. Sesebelisoa sena ke karolo ea bese ea FSM e arolelanoang e hokahanyang le memori ea flash, SSRAM, le MAX V CPLD 5M2210 System Controller. Khokahano ena ea memori ea 16-bit e ka boloka ts'ebetso ea ho bala ho fihla ho 52 MHz bakeng sa phallo ea 832 Mbps ka sesebelisoa. Mosebetsi oa ho ngola ke 270 μs bakeng sa buffer ea lentsoe le le leng ha nako ea ho hlakola e le 800 ms bakeng sa boloko ba 128 K. Lethathamo la 2–28 le thathamisa likabelo tsa phini ea flash, mabitso a matšoao, le mesebetsi. Mabitso le mefuta ea matšoao li amana le Leholiotsoana VE FPGA ho latela maemo le tataiso ea I/O.
Lethathamo la 2–28. Likabelo tsa Flash Pin, Mabitso a Letšoao a Schematic, le Mesebetsi (Karolo ea 1 ea 3)
| Boto Reference (U10) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| F6 | FLASH_ADVN | H12 | 2.5-V | Aterese e nepahetse |
| B4 | FLASH_CEN | H14 | 2.5-V | Chip nolofalletsa |
Lethathamo la 2–28. Likabelo tsa Flash Pin, Mabitso a Letšoao a Schematic, le Mesebetsi (Karolo ea 2 ea 3)
| Boto Reference (U10) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| E6 | FLASH_CLK | N12 | 2.5-V | Tshupanako |
| F8 | FLASH_OEN | L11 | 2.5-V | Output nolofalletsa |
| F7 | FLASH_RDYBSYN | J12 | 2.5-V | E lokile |
| D4 | FLASH_RESETN | K11 | 2.5-V | Seta bocha |
| G8 | FLASH_WEN | P12 | 2.5-V | Ngola nolofalletsa |
| C6 | FLASH_WPN | — | 2.5-V | Ngola tšireletso |
| A1 | FSM_A1 | B11 | 2.5-V | Aterese bese |
| B1 | FSM_A2 | A11 | 2.5-V | Aterese bese |
| C1 | FSM_A3 | D9 | 2.5-V | Aterese bese |
| D1 | FSM_A4 | C10 | 2.5-V | Aterese bese |
| D2 | FSM_A5 | A10 | 2.5-V | Aterese bese |
| A2 | FSM_A6 | A9 | 2.5-V | Aterese bese |
| C2 | FSM_A7 | C9 | 2.5-V | Aterese bese |
| A3 | FSM_A8 | B8 | 2.5-V | Aterese bese |
| B3 | FSM_A9 | B7 | 2.5-V | Aterese bese |
| C3 | FSM_A10 | A8 | 2.5-V | Aterese bese |
| D3 | FSM_A11 | B6 | 2.5-V | Aterese bese |
| C4 | FSM_A12 | A6 | 2.5-V | Aterese bese |
| A5 | FSM_A13 | C7 | 2.5-V | Aterese bese |
| B5 | FSM_A14 | C6 | 2.5-V | Aterese bese |
| C5 | FSM_A15 | F13 | 2.5-V | Aterese bese |
| D7 | FSM_A16 | E13 | 2.5-V | Aterese bese |
| D8 | FSM_A17 | A5 | 2.5-V | Aterese bese |
| A7 | FSM_A18 | A4 | 2.5-V | Aterese bese |
| B7 | FSM_A19 | J7 | 2.5-V | Aterese bese |
| C7 | FSM_A20 | H7 | 2.5-V | Aterese bese |
| C8 | FSM_A21 | J9 | 2.5-V | Aterese bese |
| A8 | FSM_A22 | H9 | 2.5-V | Aterese bese |
| G1 | FSM_A23 | G9 | 2.5-V | Aterese bese |
| H8 | FSM_A24 | F8 | 2.5-V | Aterese bese |
| B6 | FSM_A25 | E8 | 2.5-V | Aterese bese |
| B8 | FSM_A26 | D8 | 2.5-V | Aterese bese |
| F2 | FSM_D0 | F16 | 2.5-V | Data bese |
| E2 | FSM_D1 | E16 | 2.5-V | Data bese |
| G3 | FSM_D2 | M9 | 2.5-V | Data bese |
| E4 | FSM_D3 | M8 | 2.5-V | Data bese |
| E5 | FSM_D4 | F15 | 2.5-V | Data bese |
| G5 | FSM_D5 | E15 | 2.5-V | Data bese |
| G6 | FSM_D6 | E12 | 2.5-V | Data bese |
Lethathamo la 2–28. Likabelo tsa Flash Pin, Mabitso a Letšoao a Schematic, le Mesebetsi (Karolo ea 3 ea 3)
| Boto Reference (U10) | Leano Letshwao Lebitso | Leholiotsoana VE FPGA Nomoro ea Pin | I/O Standard | Tlhaloso |
| H7 | FSM_D7 | D13 | 2.5-V | Data bese |
| E1 | FSM_D8 | J15 | 2.5-V | Data bese |
| E3 | FSM_D9 | H15 | 2.5-V | Data bese |
| F3 | FSM_D10 | E11 | 2.5-V | Data bese |
| F4 | FSM_D11 | D10 | 2.5-V | Data bese |
| F5 | FSM_D12 | L10 | 2.5-V | Data bese |
| H5 | FSM_D13 | L9 | 2.5-V | Data bese |
| G7 | FSM_D14 | G14 | 2.5-V | Data bese |
| E7 | FSM_D15 | F14 | 2.5-V | Data bese |
Phepelo ea motlakase
O ka matlafatsa boto ea nts'etsopele ho tsoa ho sesebelisoa sa motlakase sa DC sa mofuta oa laptop. Kenyelletso voltage tlameha ho ba maemong a 14 V ho isa ho 20 V, ea hajoale ea 4.3 A, le boholo ba wattage ea 65 W. The DC voltage ntan'o theoleloa liporong tse fapaneng tsa motlakase tse sebelisoang ke likarolo tsa boto ebe li kengoa lihokelong tsa HSMC. Sefetoleli sa analog-to-digital (ADC) se ka har'a board se lekanya hajoale bakeng sa liporo tse 'maloa tse ikhethileng.
Sisteme ea Kabo ea Matla
Setšoantšo sa 2-9 se bontša tsamaiso ea kabo ea matla botong ea ntlafatso. Ho se sebetse hantle ha taolo le ho arolelana ho bonts'oa maqhubu a bonts'itsoeng, e leng maemo a phahameng ka ho fetesisa.
Setšoantšo sa 2-9. Sistimi ea Kabo ea Matla
Tekanyo ea Matla
Ho na le liporo tse robeli tsa phepelo ea motlakase tse nang le bokhoni ba hona joale ba kutlo tse sebelisang lisebelisoa tse fapaneng tsa 24-bit tsa ADC. Li-resistant sensor tse nepahetseng li arola lisebelisoa tsa ADC le liporo ho tloha sefofaneng sa mantlha sa phepelo bakeng sa ADC ho lekanya hajoale. Bese ea SPI e hokahanya lisebelisoa tsena tsa ADC le MAX V CPLD 5M2210 System Controller.
Setšoantšo sa 2-10 se bontša setšoantšo sa "block" bakeng sa potoloho ea tekanyo ea matla.
Setšoantšo sa 2-10. Potoloho ea Tekanyo ea Matla
Lethathamo la 2–29 le thathamisa liporo tse shebiloeng. Kholomo ea lebitso la lets'oao la schematic e totobatsa lebitso la terene e lekantsoeng ha kholomo ea phini ea sesebelisoa e totobatsa lisebelisoa tse khomaretsoeng tereneng.
Lethathamo la 2–29. Mela ea Tekanyo ea Matla
| Channel | Leano Letshwao Lebitso | Moqtage (V) | Sesebelisoa Pin | Tlhaloso |
| 1 | VCC | 1.1 | VCC | Matla a mantlha a FPGA |
| 2 | VCCAUX | 2.5 | VCC_AUX | Motlatsi |
| 3 | VCCA_FPLL | 2.5 | VCCA_FPLL | Matla a analog ea PLL |
| VCCPD3B4A, | ||||
| VCCPD5A,
VCCPD5B, VCCPD6A, |
Libanka tsa pele tsa I/O 3B, 4A, 5A, 5B, 6A, 7A, le 8A | |||
| 5 | VCCIO_VCPPD_2.5V | 2.5 | VCCPD7A8A | |
| VCCIO3B, | ||||
| VCCIO6A, VCCIO7A, | VCC I/O libanka 3B, 6A, 7A, le 8A | |||
| VCCIO8A | ||||
| 7 | VCCIO_1.2V | 1.2 | VCCIO5A, VCCIO5B, | Libanka tsa VCC I/O 5A le 5B (LPDDR2) |
| 8 | VCCIO_1.5V | 1.5 | VCCIO_4A | VCC I/O bank 4A (DDR3) |
Reference Board Components
Khaolo ena e hlalosa likarolo tsa boto ea nts'etsopele ea Leholiotsoana VE FPGA, tlhaiso-leseling ea tlhahiso, le lipolelo tsa boitlamo ba boto.
Likarolo tsa Boto
Lethathamo le thathamisa litšupiso tsa karolo le tlhaiso-leseling ea tlhahiso ea likarolo tsohle ho boto ea nts'etsopele.
Lethathamo la 3–1. Litšupiso tsa Karolo le Boitsebiso ba Tlhahiso
| Boto Referense | Karolo | Moetsi | Tlhahiso Nomoro ea Karolo | Moetsi Websebaka |
| U1 | FPGA, Leholiotsoana VE F896, 149,500
LEs, e se nang lead |
Mokhatlo oa Altera | 5CEFA7F31I7N | www.altera.com |
| U13 | Sistimi ea MAX V CPLD 5M2210
Molaoli |
Mokhatlo oa Altera | 5M2210ZF256I5N | www.altera.com |
| U18 | Selaoli sa peripheral sa USB sa lebelo le phahameng | Cypress | CY7C68013A | www.cypress.com |
| D1-D16, D18-D31, | Li-LED tse tala | Likhamphani tsa Lumex Inc. | Setšoantšo sa SML-LXT0805GW-TR | www.lumex.com |
| D17 | LED e khubelu | Likhamphani tsa Lumex Inc. | Setšoantšo sa SML-LXT0805IW-TR | www.lumex.com |
| D35 | LED e putsoa | Likhamphani tsa Lumex Inc. | SML-LX0805USBC-TR | www.lumex.com |
| SW1–SW4 | Li-switches tsa DIP tsa maemo a mane | Likarolo tsa C&K / ITT Industries | TDA04H0SB1 | www.ittcannon.com |
| S1-S8 | Sututsa likonopo | Panasonic | EVQPAC07K | Www.panasonic.com |
| S5 | Slide switjha | E-switch | EG2201A | www.e-switch.com |
| X1 | Oache ea LVDS e ka khonehang ea 125M e sa sebetse | Li-Labs tsa silicon | 570FAB000973DG | www.silabs.com |
| X3 | 100 MHz kristale oscillator, ± 50 ppm,
CMOS, 2.5 V |
Li-Labs tsa silicon | 510GBA100M000BAGx | www.silabs.com |
| X2 | 50 MHz kristale oscillator, ± 50 ppm,
CMOS, 2.5 V |
Li-Labs tsa silicon | 510GBA50M0000BAGx | www.silabs.com |
| J12 | Sehokelo sa 9-pin se tšehali sa PCB WR-DSUB | Wurth Elektronik | 618009231121 | www.we-online.com |
| U21 | USB-to-UART borokho | Li-Labs tsa silicon | CP2104 | www.silabs.com |
| J14 | 2 × 7 pin LCD socket strip | Samtec | TSM-107-07-GD | www.samtec.com |
| LCD ea sebopeho sa 2x16, matrix a matheba a 5x8 | Likhamphani tsa Lumex Inc. | LCM-S01602DSR/C | www.lumex.com | |
| U14, U15 | Lisebelisoa tsa Ethernet PHY BASE-T | Marvell Semiconductor | 88E1111-B2- CAA1C000 | www.marvell.com |
| J8, j9 | Lihokelo tsa RJ-45, 10/100/1000 Mbps | Wurth Elektronik | 7499111001A | www.we-online.com |
| J7 | HSMC, mofuta oa tloaelo oa sokete ea lelapa la QSH-DP e phahameng haholo. | Samtec | ASP-122953-01 | www.samtec.com |
| U20 | RS-232 transceiver tse peli | Linear Technology | LTC2803-1 | www.linear.com |
Lethathamo la 3–1. Litšupiso tsa Karolo le Boitsebiso ba Tlhahiso
| Boto Referense | Karolo | Moetsi | Tlhahiso Nomoro ea Karolo | Moetsi Websebaka |
| U12 | 64-Kb EEPROM | Microchip | 24AA64 | www.microchip.com |
| J15, j16 | 2 x 8 lihlooho tsa ho lokisa bothata | Samtec | TSM-108-01-L-DV | www.samtec.com |
| U7, U8 | 16M × 16 × 8, 256-MB DDR3 SDRAM | Micron | MT41J128M16 | www.micron.com |
| U9 | 16M × 32 × 8, 512-MB LPDDR2 SDRAM | Micron | MT42L128M32 | www.micron.com |
| U11 | 1024K × 18 bit 18-Mb e lumellanang ea SRAM | Litlhaloso tsa likarolo tsa Integrated Silicon Solution, Inc. | Setšoantšo sa IS61VPS102418A-250TQL | www.issi.com |
| U10 | 512-Mb e lumellanang le flash | Numonyx | Setšoantšo sa PC28F512P30BF | www.numonyx.com |
| U35 | Phapang ea likanale tse 16 24-bit ADC | Linear Technology | LTC2418CGN#PBF | www.linear.com |
Polelo ea Tumellano ea China-RoHS
Lethathamo la 3–2 le thathamisa lintho tse kotsi tse kenyellelitsoeng khiti.
Lethathamo la 3–2. Lethathamo la Mabitso a Lintho Tse Kotsi le Lintlha tsa Maemo (1), (2)
|
Karolo Lebitso |
Ketapele (Pb) | Cadmium (Cd) | Hexavalent Chromium (Cr6 +) | Mercury (HG) | E kopantsoe haholo li-biphenyls (PBB) | E kopantsoe haholo diphenyl Ethers (PBDE) |
| Boto ea ntlafatso ea Cyclone VE | X* | 0 | 0 | 0 | 0 | 0 |
| 15 V phepelo ea motlakase | 0 | 0 | 0 | 0 | 0 | 0 |
| Tlanya thapo ea USB ea AB | 0 | 0 | 0 | 0 | 0 | 0 |
| Tataiso ea mosebelisi | 0 | 0 | 0 | 0 | 0 | 0 |
Lintlha ho Lethathamo la 3–2:
- 0 e bontša hore mahloriso a ntho e kotsi linthong tsohle tse homogeneous likarolong tse ka tlase ho moeli o loketseng oa SJ/T11363-2006 standard.
- X* e bonts'a hore bongata ba ntho e kotsi ea bonyane e le 'ngoe ea lisebelisoa tsohle tse homogeneous likarolong e ka holimo ho moeli o amehang oa SJ/T11363-2006 standard, empa e lokollotsoe ke EU RoHS.
CE EMI Conformity Tlhokomeliso
Setsi sena sa nts'etsopele se fanoa ho latela maemo a nepahetseng a laetsoeng ke Directive 2004/108/EC. Ka lebaka la mofuta oa lisebelisoa tsa logic tse hlophisehang, hoa khonahala hore mosebelisi a fetole khiti ka tsela ea ho hlahisa tšitiso ea motlakase (EMI) e fetang meeli e behiloeng bakeng sa sesebelisoa sena. EMI efe kapa efe e bakiloeng ka lebaka la liphetoho ho thepa e fanoeng ke boikarabello ba mosebelisi.
Tlhahisoleseling e 'Ngoe
Khaolo ena e fana ka tlhahisoleseding e eketsehileng mabapi le tokomane le Altera.
Nalane ea Phetoho ea Boto
Tafole e latelang e thathamisa mefuta ea likhatiso tsohle tsa Leholiotsoana VE FPGA Development Board.
| Lokolla Letsatsi | Phetolelo | Tlhaloso |
| Hlakubele 2013 | Silicone ea tlhahiso | ■ Phetoho e ncha ea boto. Nomoro ea karolo e ncha ea sesebelisoa—5CEFA7F31I7N.
■ Boto e fetisitse tlhahlobo ea ho latela melao ea CE. |
| La 2012 Pulungoana XNUMX | Silicone ea boenjiniere | Tokollo ea pele. |
Nalane ea Phetoho ea Litokomane
Lethathamo le latelang le thathamisa nalane ea ntlafatso ea tokomane ena.
| Letsatsi | Phetolelo | Liphetoho |
| Phato 2017 | 1.4 | Sebaka se nepahetseng sa boto bakeng sa Clock Output SMA Connector in “Ho fetaview tsa Likarolo tsa Boto ea Nts'etsopele ea Leholiotsoana VE FPGA” leqepheng la 2–2. |
| Pherekhong 2017 | 1.3 | Nomoro ea phini ea EETA_RX_DV e nepahetseng Lethathamo la 2–20 leqepheng la 2–25. |
|
Loetse 2015 |
1.2 |
■ Sehokelo se kentsoeng ho Altera Design Store in "MAX V CPLD 5M2210 System Controller" ho leqepheng la 2–5.
■ Leibole ea sesebelisoa e lokisitsoeng ho Setšoantšo sa 2–5 leqepheng la 2–15. |
| Hlakubele 2013 | 1.1 | ■ E ntlafalitse nomoro ea karolo ea sesebelisoa sa FPGA bakeng sa ho lokolloa ha silicon.
■ E kentse karolo e mabapi le “CE EMI Conformity Caution” leqepheng la 3–2. |
| La 2012 Pulungoana XNUMX | 1.0 | Tokollo ea pele. |
Likopano tsa Typographic
Tafole e latelang e bonts'a litumellano tsa typographic eo tokomane ena e e sebelisang.
| E bonoang Cue | Tlhaloso |
| Mofuta oa Bold o nang le Capital ea Pele Mangolo | Hlahisa mabitso a litaelo, lihlooho tsa lebokose la puisano, likhetho tsa lebokose la puisano, le li-label tse ling tsa GUI. Bakeng sa mohlalaample, Boloka Joalo ka lebokose la puisano. Bakeng sa likarolo tsa GUI, capitalization e tsamaisana le GUI. |
|
sebete mofuta |
E bontša mabitso a li-directory, mabitso a morero, mabitso a disk drive, file mabitso, file li-extensions tsa mabitso, mabitso a lisebelisoa tsa software, le li-label tsa GUI. Bakeng sa mohlalaample, \qmeqapi bukana, D: khanna, le chiptrip.gdf file. |
| Mofuta oa Italic o nang le Litlhaku tsa Pele tsa Capital | Bontša lihlooho tsa litokomane. Bakeng sa mohlalaample, Stratix IV Moralo Tataiso. |
Leholiotsoana VE FPGA Board Development
Bukana ea Litšupiso
Phato 2017 Altera Corporation
Litokomane / Lisebelisoa
 |
ALTERA Cyclone VE FPGA Boto ea Nts'etsopele [pdf] Bukana ea Mosebelisi Leholiotsoana VE FPGA Boto ea Nts'etsopele, Leholiotsoana, Boto ea Nts'etsopele ea VE FPGA, Boto ea Nts'etsopele ea FPGA, Boto ea Nts'etsopele, Boto |
