ʻO Microsemi IGLOO2 HPMS DDR Configuration
Hoʻolauna
Loaʻa i ka IGLOO2 HPMS kahi mana DDR i hoʻopili ʻia (HPMS DDR). Hoʻolālā ʻia kēia mea hoʻoponopono DDR e kāohi i kahi hoʻomanaʻo DDR off-chip. Hiki ke kiʻi ʻia ka mea hoʻoponopono HPMS DDR mai ka HPMS (me ka HPDMA) a me ka lole FPGA.
Ke hoʻohana ʻoe i ka System Builder e kūkulu i kahi poloka ʻōnaehana me kahi HPMS DDR, hoʻonohonoho ʻo System Builder i ka mea hoʻoponopono HPMS DDR no ʻoe ma muli o kāu mau helu a me nā koho.
ʻAʻole pono ka hoʻonohonoho ʻokoʻa HPMS DDR e ka mea hoʻohana. No nā kikoʻī, e ʻoluʻolu e nānā i ka IGLOO2 System Builder User's Guide.
Mea Hana Pūnaewele
Mea Hana Pūnaewele
Ma em Builder e hoʻonohonoho aunoa i ka HPMS DDR.
- Ma ka ʻaoʻao ʻaoʻao Device Features of System Builder, e nānā i ka HPMS External DDR Memory (HPMS DDR).
- Ma ka papa Memories, koho i ka DDR Memory Type:
- DDR2
- DDR3
- LPDDR
- E koho i ka laulā o ka DDR Memory: 8, 16 a i ʻole 32
- E nānā iā ECC inā makemake ʻoe e loaʻa iā ECC no ka DDR.
- E komo i ka manawa hoʻonohonoho hoʻomanaʻo DDR. ʻO kēia ka manawa e pono ai ka hoʻomanaʻo DDR e hoʻomaka.
- Kaomi i ka Import Register Configuration e hoʻokomo i nā waiwai Kākau no ka FDDR mai kahi kikokikona i loaʻa file loaʻa nā waiwai hoʻopaʻa inoa. E nānā i ka Papa 1 no ka hoʻonohonoho hoʻopaʻa inoa file huaʻōlelo.
Mālama ʻo Libero i kēia ʻikepili hoʻonohonoho ma ka eNVM. Ma ka hoʻoponopono hou ʻana o FPGA, e kope kope ʻia kēia ʻikepili hoʻonohonoho i loko o ka HPMS DDR.
Kiʻi 1 • Mea Hana Pūnaewele a me HPMS DDR
Papa 1 • Kakau inoa File Syntax
- ddrc_dyn_soft_reset_CR 0x00 ;
- ddrc_dyn_refresh_1_CR 0x27DE ;
- ddrc_dyn_refresh_2_CR 0x30F ;
- ddrc_dyn_powerdown_CR 0x02 ;
- ddrc_dyn_debug_CR 0x00 ;
- ddrc_ecc_data_mask_CR 0x0000 ;
- ddrc_addr_map_col_1_CR 0x3333 ;
Hoʻonohonoho hoʻoponopono HPMS DDR
Ke hoʻohana ʻoe i ka HPMS DDR Controller e komo i kahi DDR Memory waho, pono e hoʻomaka ka DDR Controller i ka wā holo. Hana ʻia kēia ma ke kākau ʻana i ka ʻikepili hoʻonohonoho i nā papa inoa hoʻonohonoho hoʻonohonoho DDR controller. Ma IGLOO2, mālama ka eNVM i ka ʻikepili hoʻonohonoho hoʻopaʻa inoa a ma hope o ka hoʻonohonoho hou ʻana o FPGA, kope ʻia ka ʻikepili hoʻonohonoho mai ka eNVM a i nā papa inoa hoʻolaʻa a HPMS DDR no ka hoʻomaka ʻana.
HPMS DDR Mana Hoʻopaʻa inoa
Loaʻa i ka HPMS DDR Controller kahi papa inoa e pono e hoʻonohonoho i ka wā holo. Hōʻike nā koina hoʻonohonoho no kēia mau papa inoa i nā ʻāpana like ʻole, e like me ke ʻano DDR, ka laulā PHY, ke ʻano burst, a me ka ECC. No nā kikoʻī piha e pili ana i nā papa inoa hoʻonohonoho DDR controller e ʻoluʻolu e nānā i ka Microsemi IGLOO2 User's Guide
Hoʻopaʻa inoa HPMS MDDR
No ka wehewehe ʻana i nā waiwai DDR Register:
- E hoʻohana i ka mea hoʻoponopono kikokikona ma waho o Libero SoC, e hoʻomākaukau i kahi kikokikona file Aia nā inoa a me nā waiwai, e like me ke kiʻi 1-1.
- Mai ka ʻaoʻao hoʻomanaʻo ʻo System Builder, kaomi i ka Import Register Configuration.
- E hoʻokele i kahi o ka kikokikona hoʻonohonoho hoʻopaʻa inoa file ua hoʻomākaukau ʻoe ma ka ʻanuʻu 1 a koho i ka file e lawe mai.
Kiʻi 1-1 • Hoʻopaʻa inoa i ka ʻikepili hoʻonohonoho - Hōʻano kikokikona
Hoʻomaka HPMS DDR
Hoʻokomo ʻia ka ʻikepili hoʻonohonoho hoʻopaʻa inoa āu e lawe mai ai no ka HPMS DDR i loko o ka eNVM a kope ʻia i nā papa inoa hoʻonohonoho HPMS DDR ma ka hoʻonohonoho hou ʻana o FPGA. ʻAʻohe mea hoʻohana e koi ʻia e hoʻomaka i ka HPMS DDR i ka wā holo. Hoʻohālike pū ʻia kēia hoʻomaka ʻana ma ka simulation.
Wehewehe Awa
DDR PHY Interface
Hōʻike ʻia kēia mau awa ma ka pae kiʻekiʻe o ka poloka i hana ʻia e System Builder. No nā kikoʻī, e nānā i ka IGLOO2 System Builder User Guide. Hoʻohui i kēia mau awa i kāu hoʻomanaʻo DDR.
Papa 2-1 • DDR PHY Interface
| inoa awa | Kuhikuhi | wehewehe |
| MDDR_CAS_N | Iwaho | DRAM CASN |
| MDDR_CKE | Iwaho | DRAM CKE |
| MDDR_CLK | Iwaho | Uaki, aoao P |
| MDDR_CLK_N | Iwaho | Uaki, N aoao |
| MDDR_CS_N | Iwaho | DRAM CSN |
| MDDR_ODT | Iwaho | DRAM ODT |
| MDDR_RAS_N | Iwaho | DRAM RASN |
| MDDR_RESET_N | Iwaho | Hoʻoponopono hou DRAM no DDR3 |
| MDDR_WE_N | Iwaho | DRAM WEN |
| MDDR_ADDR[15:0] | Iwaho | Dram Address bits |
| MDDR_BA[2:0] | Iwaho | ʻO Dram Bank Address |
| MDDR_DM_RDQS ([3:0]/[1:0]/[0]) | INOUT | Dram Data Mask |
| MDDR_DQS ([3:0]/[1:0]/[0]) | INOUT | Dram Data Strobe Input / Output – ʻaoʻao P |
| MDDR_DQS_N ([3:0]/[1:0]/[0]) | INOUT | Dram Data Strobe Input / Output - N ʻaoʻao |
| MDDR_DQ ([31:0]/[15:0]/[7:0]) | INOUT | Hoʻokomo/Hanaʻike DRAM |
| MDDR_DQS_TMATCH_0_IN | IN | FIFO ma ka hoailona |
| MDDR_DQS_TMATCH_0_OUT | Iwaho | FIFO waho hōʻailona |
| MDDR_DQS_TMATCH_1_IN | IN | FIFO ma ka hōʻailona (32-bit wale nō) |
| MDDR_DQS_TMATCH_1_OUT | Iwaho | FIFO waho hōʻailona (32-bit wale nō) |
| MDDR_DM_RDQS_ECC | INOUT | Dram ECC Ikepili Mask |
| MDDR_DQS_ECC | INOUT | Dram ECC Data Strobe Input / Output - P ʻaoʻao |
| MDDR_DQS_ECC_N | INOUT | Dram ECC ʻIkepili Strobe Hoʻokomo/Hanaʻana – N ʻaoʻao |
| MDDR_DQ_ECC ([3:0]/[1:0]/[0]) | INOUT | DRAM ECC ʻIkepili Hoʻokomo/Hana |
| MDDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO ma ka hōʻailona |
| MDDR_DQS_TMATCH_ECC_OUT | Iwaho | ECC FIFO hōʻailona waho (32-bit wale nō) |
Hoʻololi nā laula awa no kekahi mau awa ma muli o ke koho ʻana o ka laula PHY. Hoʻohana ʻia ka hōʻailona “[a:0]/[b:0]/[c:0]” e hōʻike i kēlā mau awa, kahi i kapa ʻia ai ʻo “[a:0]” i ka laula awa ke koho ʻia kahi laula PHY 32-bit. , “[b:0]” pili i ka 16-bit PHY laula, a “[c:0]” pili i ka 8-bit PHY laula.
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ʻO Microsemi IGLOO2 HPMS DDR Configuration [pdf] Ke alakaʻi hoʻohana IGLOO2 HPMS DDR Mea Mana Mana, IGLOO2, HPMS DDR Mana Mana Mana, DDR Mana Mana Mana, Mana Manawa. |
