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1 Xilinx DDR2 MIG 7 Performance Estimation Guide
2 Nhanganyaya
3 Inoshanda bandwidth
4 MIG Dhizaini Generation
5 Performance Simulation RTL gadziriso
6 Kutevedzera Performance Traffic Generator
7 General nzira dzekunatsiridza Performance
8 Memory nguva iri pamusoro
9 Controller Overheads
10 References
11 References
12 Related Posts

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Xilinx DDR2 MIG 7 Performance Estimation Guide

Xilinx_DDR2_MIG_7_Performance-Estimation-chigadzirwa

Chiziviso Chakakosha: Iyi PDF inodhaunirodha yeRekodhi Rekodhi inopihwa kuti iwedzere kushandiswa kwayo uye kuverenga kwayo. Zvakakosha kuziva kuti Mhinduro Records ndeiyi Web-yakavakirwa zvemukati izvo zvinogara zvichigadziridzwa sezvo ruzivo rutsva runowanikwa. Unoyeuchidzwa kushanyira Xilinx Technical Support Websaiti uye review (Xilinx Mhinduro 63234) yeshanduro yazvino yeMhinduro iyi.

Nhanganyaya

Nekuda kwenzira iyo DDR2 uye DDR3 ndangariro dzakagadzirwa uye iyo MIG 7 inoteedzera controller yakagadzirwa, kuita hakuna kunanga kumberi.
Zvinoda kunzwisiswa kweakasiyana Jedec Nguva maparamendi uye controller Architecture, uye iwe uchafanirwa kumhanyisa simulations kuti uwane fungidziro.
Nheyo yakajairika yekuona mashandiro akafanana asi gwaro iri rinopa nzira iri nyore yekuwana hunyanzvi uchishandisa iyo MIG example dhizaini nerubatsiro rwebhenji rekuyedza uye kukurudzira fileyakabatanidzwa pano.

Inoshanda bandwidth

Iyo DRAM data bhazi inowana padhuze-peak bandwidth chete panguva yekuputika kwekuverenga nekunyora uye pamusoro payo inodzikisa inoshanda data data.
Vashoma exampzvishoma zvepamusoro ndezvi:

  • precharge nguva yekuwana mitsara mubhangi rimwechete (Access address not in the same row-peji hit)
  • nyora kudzoreredza nguva yekuchinja kubva pakunyora kuenda kuverenga kuverenga
  • nguva yebhazi yekuchinja kubva pakuverenga kuenda pakunyora

Xilinx DDR2 MIG 7 Performance Estimation-fig-28
Inoshanda Bandwidth = Peak Bandwidth * Kushanda 

MIG Dhizaini Generation

Tarisa kuUG586 Chitsauko 1 kune nhanho-nhanho ruzivo paMIG IP uye example design generation.
Usati wamhanya MIG 7 Series performance simulation, ita zvinotevera kuti uve nechokwadi chekuti nzvimbo yako yekufananidza yakanaka. Vhura iyo MIG example dhizaini uye mepu maraibhurari akakodzera, mhanyisa simulation, uye ive nechokwadi chekuti unogona kuona meseji "bvunzo yakapfuura" mune yakanyorwa.
Kuratidza kuyerera ini ndakagadzira MIG IP ye xc7vx690tffg1761-2 uye ndakakumbira iyo yekare.ample design.
Zvinhu zviviri zvinofanirwa kucherechedzwa ndezvokuti ndangariro kero bits uye ndangariro kero mepu sarudzo.
For example, ini ndasarudza MT41J128M8XX-125 pasi pechikamu chekudonha pasi sarudzo.Xilinx DDR2 MIG-7-Performance-Estimation-fig-1

Kune yakasarudzwa ndangariro chikamu kubva Mufananidzo-1, mutsara = 14, column = 10 uye bhangi = 3, saka app_addr_width = mutsara + column + bhangi + chinzvimbo = 28 Xilinx DDR2 MIG 7 Performance Estimation-fig-2

Unogona kusarudza BANK_ROW_COLUMN kana ROW BANK Column.
Ndasiya ROW BANK Column inova iyo yekumisikidza kero mepu.

Example dhizaini Simulation ine synthesizable test bhenji

Pasi peSimulation marongero, sarudza QuestaSim/ModelSim Simulator uye bhurawuza kunzvimbo yakaunganidzwa yemaraibhurari.
Kuti uwane ruzivo rwekunongedza kune yechitatu-bato maturusi ekuisa nzira, kusarudza iyo inotarirwa simulator, uye kuunganidza uye mepu maraibhurari, unogona kureva (UG900) Vivado Dhizaini Suite Mushandisi Yekushandisa Logic Simulation.Xilinx DDR2 MIG 7 Performance Estimation-fig-3

Mhanya iyo simulation kuburikidza neGUI (Dzvanya iyo Run Simulation Tab mune maneja weprojekiti) uye ita shuwa kuti unoona "test yakapfuura" meseji mune yakanyorwa.

Performance Simulation RTL gadziriso

  1. Tinya-kurudyi kune masosi tab, sarudza "wedzera kana gadzira zvinyorwa zvekutevedzera", uye bhurawuza kune mig7_perfsim_traffic_generator.sv file uye tinya finish kuti uwedzere.
  2. Tinya-kurudyi kwezvinobva tab, sarudza “wedzera kana gadzira manyuko ekuenzanisa”, tsvaga ku perfsim_stimulus.txt, wobva wadzvanya finish kuti uwedzere.
  3. Comment out the example_top instantiation mu sim_tb_top.v file.
  4. Wedzera iri pazasi RTL mitsetse kune sim_tb_top,v
  • localparam APP_ADDR_WIDTH = 28;
  • localparam APP_DATA_WIDTH = 64;
  • localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
  • localparam MEM_ADDR_ORDER = “BANK_ROW_COLUMN”;
  • localparam BANK_WIDTH = 3;
  • localparam RANK_WIDTH = 1;
  • waya [APP_ADDR_WIDTH-1:0] c0_ddr3_app_addr;
  • waya [2:0] c0_ddr3_app_cmd;
  • waya c0_ddr3_app_en;
  • waya [APP_DATA_WIDTH-1:0] c0_ddr3_app_wdf_data;
  • waya c0_ddr3_app_wdf_end;
  • waya [APP_MASK_WIDTH-1:0] c0_ddr3_app_wdf_mask;
  • waya c0_ddr3_app_wdf_wren;
  • waya [APP_DATA_WIDTH-1:0] c0_ddr3_app_rd_data;
  • waya c0_ddr3_app_rd_data_end;
  • waya c0_ddr3_app_rd_data_valid;
  • waya c0_ddr3_app_rdy;
  • waya c0_ddr3_app_wdf_rdy;
  • waya c0_data_compare_error;
  • waya ui_clk;
  • waya ui_clk_sync_rst;
  • waya app_sr_req = 0;
  • waya app_ref_req = 0;
  • waya app_zq_req =0;
  • waya c0_app_wdf_mask =0;

FPGA Memory Controller instantiation

mig_7series_0_mig u_mig_7series_0_mig (
// Memory interface ports

  • .ddr3_addr (ddr3_addr_fpga),
  • .ddr3_ba (ddr3_ba_fpga),
  • .ddr3_cas_n (ddr3_cas_n_fpga),
  • .ddr3_ck_n (ddr3_ck_n_fpga),
  • .ddr3_ck_p (ddr3_ck_p_fpga),
  • .ddr3_cke (ddr3_cke_fpga),
  • .ddr3_ras_n (ddr3_ras_n_fpga),
  • .ddr3_reset_n (ddr3_reset_n),
  • .ddr3_we_n (ddr3_we_n_fpga),
  • .ddr3_dq (ddr3_dq_fpga),
  • .ddr3_dqs_n (ddr3_dqs_n_fpga),
  • .ddr3_dqs_p (ddr3_dqs_p_fpga),
  • .init_calib_complete (init_calib_complete),
  • .ddr3_cs_n (ddr3_cs_n_fpga),
  • .ddr3_dm (ddr3_dm_fpga),
  • .ddr3_odt (ddr3_odt_fpga),

// Application interface ports

  • .app_addr (c0_ddr3_app_addr),
  • .app_cmd (c0_ddr3_app_cmd),
  • .app_en (c0_ddr3_app_en),
  • .app_wdf_data (c0_ddr3_app_wdf_data),
  • .app_wdf_end (c0_ddr3_app_wdf_end),
  • .app_wdf_wren (c0_ddr3_app_wdf_wren),
  • .app_rd_data (c0_ddr3_app_rd_data),
  • .app_rd_data_end (app_rd_data_end),
  • .app_rd_data_valid (c0_ddr3_app_rd_data_valid),
  • .app_rdy (c0_ddr3_app_rdy),
  • .app_wdf_rdy (c0_ddr3_app_wdf_rdy),
  • .app_sr_req (app_sr_req),
  • .app_ref_req (app_ref_req),
  • .app_zq_req (app_zq_req),
  • .app_sr_active (app_sr_active),
  • .app_ref_ack (app_ref_ack),
  • .app_zq_ack (app_zq_ack),
  • .ui_clk (ui_clk),
  • .ui_clk_sync_rst (ui_clk_sync_rst),
  • .app_wdf_mask (c0_ddr3_app_wdf_mask),

// System Clock Ports

  • .sys_clk_i (sys_clk_i),

// Reference Clock Ports

  • .clk_ref_i (clk_ref_i),
  • .sys_rst (sys_rst)
  • );

Kuita traffic jenareta instantiation

mig7_perfsim_traffic_generator#
(
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.tCK (tCK),
.ADDR_WIDTH (APP_ADDR_WIDTH)
)

u_traffic_gen
(
.clk (ui_clk ),
.rst (ui_clk_sync_rst ),
.init_calib_complete (init_calib_complete),
.cmp_error (c0_data_compare_error),
.app_wdf_rdy (c0_ddr3_app_wdf_rdy ),
.app_rd_data_valid (c0_ddr3_app_rd_data_valid),
.app_rd_data (c0_ddr3_app_rd_data ),
.app_rdy (c0_ddr3_app_rdy),
.app_cmd (c0_ddr3_app_cmd ),
.app_addr (c0_ddr3_app_addr ),
.app_en (c0_ddr3_app_en ),
.app_wdf_mask (c0_ddr3_app_wdf_mask),
.app_wdf_data (c0_ddr3_app_wdf_data),
.app_wdf_end (c0_ddr3_app_wdf_end ),
.app_wdf_wren (c0_ddr3_app_wdf_wren)
);

  • 5. Shandura APP_ADDR_WIDTH, APP_DATA_WIDTH, RANK_WIDTH uye BANK_WIDTH zvichienderana nesarudzo yako yechikamu chendangariro.
    Values ​​inogona kuwanikwa kubva kune _mig.v file.
  • Iyo yero yakaratidza instantiation zita mig_7series_0_mig inogona kusiyana zvichienderana nezita rechikamu chako panguva yekugadzira IP, simbisa kana wasarudza rimwe zita uye worishandura zvinoenderana.Xilinx DDR2 MIG 7 Performance Estimation-fig-4
  • Kana iyo IP yagadzirwa vhura iyo _mig.v file uye yambuka-tarisa kune chero misiyano mumazita echiratidzo cheLHS uye ugadzirise.
  • app_sr_req, app_ref_req uye app_zq_req inofanira kutanga kusvika 0.
  • Sezvo example_top.v inotsanangurwa kunze uye itsva files akawedzerwa, iwe uchaona "?" kunze kwe
    mig_7series_0_mig.v file pasi pekutevedzera masosi.
    Kutora mepu chaiyo file, tinya kurudyi mig_7series_0_mig.v, sarudza "Wedzera Nzvimbo", Bhurawuza ku
    /mig_7series_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl
    wowedzera mig_7series_0_mig_sim.v file.
  • Kana ukaona "?" nokuda kwezviri pasi files, wedzera zvese RTL files mune wachi, controller, ip_top, phy uye UI maforodha.
  • Kana iyo RTL shanduko yaitwa uye zvese zvinodiwa files inowedzerwa kune yako Simulation Source, Hierarchy inofanira kufanana neFigure 5.
    The files akaiswa mutsvuku achangowedzerwa, uye "?" inotarisirwa paECC ine hukama mamodule sezvo yakasarudzwa ndangariro gadziriso ine ECC sarudzo yakadzimwa.Xilinx DDR2 MIG 7 Performance Estimation-fig-5

Stimulus File Tsanangudzo
Imwe neimwe yekusimudzira maitiro ndeye 48 bits uye fomati inotsanangurwa muFigure 6-1 kuburikidza 6-4.Xilinx DDR2 MIG 7 Performance Estimation-fig-6

Kero Encoding (Kero [35:0])

Iyo kero yakavharwa mukukurudzira senge Figure 7-1 kusvika Figure 7-6. Yese minda yekero inoda kuiswa muiyo hexadecimal fomati. Yese yenzvimbo dzekero hupamhi hunopatsanurwa neina kuti upinde mumhando yehexadecimal. Bhenji rekuyedza rinongotumira mabheti anodiwa endima yekero kune Memory Controller.
For example, mukugadzirisa kwebhangi sere, mabhiti ebhangi chete [2:0] anotumirwa kuMemory Controller uye mabheti akasara anofuratirwa. Mamwe mabhiti endima yekero anopiwa kuti iwe uise kero mune hexadecimal fomati.
Iwe unofanirwa kusimbisa kukosha kwakapinda kunoenderana nehupamhi hwekugadziriswa kwakapihwa.Xilinx DDR2 MIG 7 Performance Estimation-fig-7

  • Kero yeKoramu (Koramu[11:0]) - Column Kero mune yekukurudzira inopihwa kune inokwana gumi nemaviri bits, asi iwe unofanirwa kugadzirisa izvi zvichibva pane iyo column wide parameter yakaiswa mudhizaini yako.
  • Kero yeRow (Row[15:0]) - Row kero mune yekukurudzira inopihwa kune inokwana gumi nematanhatu bits, asi iwe unofanirwa kugadzirisa izvi zvichibva pamutsara wehupamhi paramende yakaiswa mudhizaini yako.
  • Kero yeBhangi (Bhangi[3:0]) - Kero yebhangi mune yekukurudzira inopiwa kune inokwana mabhiti mana, asi iwe unofanirwa kugadzirisa izvi zvichibva pabhangi upamhi paramende yakaiswa mudhizaini yako.
  • Kero yenzvimbo (Chinzvimbo[3:0]) - Kero yekero mukusimudzira inopihwa kune inokwana mabhiti mana, asi iwe unofanirwa kugadzirisa izvi zvichibva pane renji upamhi paramende yakaiswa mudhizaini yako.
    Kero inounganidzwa zvichienderana nepamusoro-soro MEM_ADDR_ORDER parameter uye inotumirwa kune mushandisi interface.

Raira Dzokorora (Raira Dzokorora [7:0])
Murairo wekudzokorora kuverenga ndiyo nhamba yenguva iyo murairo unodzokororwa kuMushandisi Interface. Kero yekudzokorora kwega kwega inowedzerwa ne 8. Iyo yakawanda yekudzokorora kuverenga ndeye 128.
Bhenji rekuyedza haritarise muganhu wekoramu uye rinoputira kutenderedza kana iyo yakanyanya mbiru muganho wasvika panguva yekuwedzera.
Mitemo 128 inozadza peji. Kune chero kero yekoramu kunze kwe0, nhamba yekudzokorora ye128 inoguma yayambuka muganho wekoramu uye nekupeta kusvika panotangira kero yekoramu.

Bus Utilization
Iko kushandiswa kwebhazi kunoverengerwa kuMushandisi Interface ichitora huwandu hwekuverenga uye Kunyora mukufunga uye inotevera equation inoshandiswa:

Xilinx DDR2 MIG 7 Performance Estimation-fig-8

  • BL8 inotora mana ndangariro wachi kutenderera
  • end_of_stimulus ndiyo nguva iyo mirairo yese yaitwa.
  • calib_done ndiyo nguva iyo calibration yaitwa.

Example Patterns
Izvi exampzvishoma zvinobva paMEM_ADDR_ORDER yakaiswa kuBANK_ROW_COLUMN.

Single Read Pattern
00_0_2_000F_00A_1 - Iyi pateni inoverengwa kamwe chete kubva pachikamu chegumi, mutsara wechigumi neshanu, uye bhangi rechipiri.Xilinx DDR2 MIG 7 Performance Estimation-fig-9Imwe Nyora Pateni
00_0_1_0040_010_0 - Iyi pateni nyora imwe chete kune iyo 32nd column, 128th row, uye yekutanga bhangi.Xilinx DDR2 MIG 7 Performance Estimation-fig-10Nyora Imwechete uye Verenga kune Kero Yakafanana
00_0_2_000F_00A_0 – Iyi pateni ndeyekunyorera ku10th column, 15th row, uye yechipiri bhangi.
00_0_2_000F_00A_1 – Iyi pateni ndeyekuverenga kamwe chete kubva ku10th column, 15th row, uye yechipiri bhangiXilinx DDR2 MIG 7 Performance Estimation-fig-11

Akawanda Anonyora uye Anoverenga ane Kero Yakafanana
0A_0_0_0010_000_0 – Izvi zvinoenderana negumi anonyora nekero inotangira kubva pa10 kusvika pa0 iyo inogona kuonekwa muchikamu.Xilinx DDR2 MIG 7 Performance Estimation-fig-12

0A_0_0_0010_000_1 – Izvi zvinoenderana ne10 kuverenga nekero inotangira kubva pa0 kusvika pa80 iyo inogona kuonekwa muchikamu.Xilinx DDR2 MIG 7 Performance Estimation-fig-13

Peji Yekupeta Panguva Yekunyora
0A_0_2_000F_3F8_0 – Izvi zvinoenderana negumi anonyora nekero yekoramu yakaputirwa panotangira peji mushure mekunyora kumwe chete.Xilinx DDR2 MIG 7 Performance Estimation-fig-14

Kutevedzera Performance Traffic Generator

Panguva ino wapedza neMIG example design simulation. Izvi zvinoreva kuti simulation yako yekumisikidza yakagadzirira, waita maitiro ekuenzanisa RTL gadziriso, iyo itsva simulation hierarchy ndeyechokwadi uye wanzwisisa maitiro ekusimudzira. Mhanya kuenzanisa zvakare ne16 anonyora uye anoverenga mu perfsim_stimulus.txt.Xilinx DDR2 MIG 7 Performance Estimation-fig-15

Ita-mhanya-zvese, mirira kusvika iyo init_calib_complete chiratidzo ichisimbiswa, uye iwe uchakwanisa kuona nhamba yakatsanangurwa yekunyora uye kuverenga. The simulation inobva yamira. Xilinx DDR2 MIG 7 Performance Estimation-fig-16

Paunenge uchinge wakumbirwa kuti usiye simulation, sarudza Kwete uye enda kuhwindo rekunyora uko iwe unozokwanisa kuona maitiro ekuita. Xilinx DDR2 MIG 7 Performance Estimation-fig-17

Kana ukasarudza "siya simulation" nhamba dzekushanda dzichanyorwa kune a file zita mig_band_width_output.txt iri mu sim_1/behave folder.

Exampnzira yedhairekitori: -
/mig_7series_0_example_perf_sim\mig_7series_0_example.sim/sim_1/behavXilinx DDR2 MIG 7 Performance Estimation-fig-18

Unogona kushamisika kuti sei muzanatage bus utilization is ony 29. Dzokorora simulation nemasettings eIP akafanana asi uchingoshandura kukurudzira file kusvika 256 anonyora uye 256 anoverenga

ff_0_0_0000_000_0
ff_0_0_0000_000_1

Iwe zvino uchaona muzanatage se85, izvo zvinoreva kuti DDR3 inopa kushandiswa kuri nani kwebhazi kwenguva refu kutevedzana kwekunyora uye kuverenga kuputika. Xilinx DDR2 MIG 7 Performance Estimation-fig-19

General nzira dzekunatsiridza Performance

Zvinhu zvinopesvedzera kushanda zvakanaka zvinogona kukamurwa kuita zvikamu zviviri:

  1. Memory Specific
  2. Controller SpecificXilinx DDR2 MIG 7 Performance Estimation-fig-20

Mufananidzo 9 unokupa iwe pamusoroview yematemu anonangana nendangariro.
Kusiyana neSRAMs neBlock Memories DDR2 kana DDR3 kuita haisiriyo yakakwira data reti.

Izvo zvinoenderana nezvakawanda zvenguva zvinhu, zvinosanganisira:

  • tRCD: Row Command Kunonoka (kana ras to cas delay).
  • tCAS(CL): Column address strobe latency.
  • tRP: Row precharge kunonoka.
  • tRAS: Row Active Time (activate kuti uchinje).
  • tRC: Row cycle time. tRC = tRAS + tRP
  • tRAC: Kunonoka kuwana kunonoka. tRAC = tRCD + tCAS
  • tCWL: Cas nyora latency.
  • tZQ: ZQ calibration nguva.
  • tRFC: Row Refresh Cycle Time
  • tWTR: Nyora kuverenga kunonoka. Pakupedzisira kunyora kutengeserana kuKuverenga nguva yekuraira.
  • tWR: Nyora Recovery nguva. Pakupedzisira kunyora kutengeserana kuPrecharge nguva

Nguva yeese maparamita akanyorwa zvinoenderana nerudzi rwendangariro inoshandiswa uye ndangariro chikamu chekumhanya giredhi.
Rumwe ruzivo nezve tsananguro uye nguva yakatarwa inogona kuwanikwa muDDR2 DDR3 JEDEC kana mune chero memori mudziyo wedata.

Kunyatsoshanda kunoenderana nekuti ndangariro inowanikwa sei. Mhando dzekero dzakasiyana dzinopa mhedzisiro dzakasiyana.

Memory nguva iri pamusoro

  1. Activation nguva uye Precharge nguva paunochinja kune mabhangi matsva / mitsara kana kuchinja mitsara ine mubhangi rimwechete.- Saka kana iwe ukaderedza kuchinja kwemutsara, izvi zvinogona kubvisa tRCD uye tRP.
  2. Tumira kuenderera mberi kunyora kana kuverenga mirairo -Kuchengetedza tCCD nguva.
  3. Deredza kunyora kuti uverenge uye uverenge kunyora kuraira shanduko - Nyora kudzoreredza nguva yekuchinja kuti uverenge masvikiro, bhazi rekuchinja nguva yekuchinja kubva pakuverenga kuenda kunyora.
  4. Seta nguva yekuvandudza yakakodzera.
    • DDR3 SDRAM inoda Refresh cycles paavhareji periodic interval ye tREFI.
    • Iyo yakawanda ye8 yekuwedzera Refresh mirairo inogona kupihwa pachine nguva ("kudhonzerwa mukati"). Izvi hazvideredze huwandu hwekuzorodza, asi iyo yakanyanya nguva pakati pemirairo miviri yakatenderedza Refresh inogumira ku9 × tREFI.Xilinx DDR2 MIG 7 Performance Estimation-fig-21
  • Shandisa mabhanga ese - Nzira yekutaura yakakodzera inodiwa.
    • Row-Bank-Column: Kune kutengeserana kunoitika pamusoro peyakatevedzana kero nzvimbo, musimboti unovhura otomatiki mutsetse mumwechete mubhangi rinotevera remudziyo weDRAM kuti uenderere mberi nekutengeserana kana kupera kwemutsara uripo kwasvika. Yakanyatso kuenderana nemashandisirwo anoda kuputika kwemapaketi makuru edata kunzvimbo dzakatevedzana kero.
    • Bank-Row-Column: Paunenge uchiyambuka muganhu wemutsara, mutsara wezvino uchavharwa uye mumwe mutsara uchavhurwa mukati mebhangi rimwechete. MSB ikero yebhangi, iyo inogona kushandiswa kuchinja kubva kumabhangi akasiyana. Inokodzera kupfupika, kwakawanda kusarudzika kutengeserana kune imwe bhuroka yendangariro kwenguva yenguva uyezve kusvetukira kune imwe block (bhangi)
  • Kuputika Kureba
    • BL 8 inotsigirwa DDR3 pa7 akatevedzana. BC4 ine yakaderera kwazvo kushanda iri pasi pe50%. Izvi zvinodaro nekuti nguva yekuuraya yeBC4 yakafanana neBL8. Iyo data inongovharwa mukati mechikamu.
    • Muzviitiko zvausingade kunyora yakazara kuputika, ingave data mask kana kunyora-pashure-kuverenga inogona kutariswa.
  • Seta nguva yakakodzera yeZQ (DDR3 Chete)
    Iyo controller inotumira zvese ZQ Short (ZQCS) uye ZQ Long (ZQCL) Calibration mirairo.
    • Teerera kuDDR3 Jedec Standard
    • ZQ Calibration inokurukurwa muchikamu 5.5 cheJEDEC Spec JESD79-3 DDR3 SDRAM Standard.
    • ZQ Calibration inogadzirisa On Die Termination (ODT) nguva nenguva kuverengera mutsauko muVT.
    • Logic iri mubank_common.v/vhd
    • Parameter Tzqcs inosarudza chiyero icho ZQ Calibration command inotumirwa kundangariro
    • t zvinokwanisika kudzima counter uye nemaoko kutumira uchishandisa app_zq_req, Zvakafanana nekutumira nemaoko Refresh.
      Tarisa ku (Xilinx Mhinduro 47924) kuti uwane ruzivo.Xilinx DDR2 MIG 7 Performance Estimation-fig-22

Controller Overheads

  1. Periodic Reads - Tarisa kune (Xilinx Mhinduro 43344) kuti uwane ruzivo.
    • Usashandura nguva yekuverenga
    • Svetuka kuverenga nguva nenguva panguva yekunyora uye wopa nhamba yewakapotsa kuverenga pamberi pekuverenga kwechokwadi
  2. Kuronga patsva - Refer (Xilinx Mhinduro 34392) kuti uwane ruzivo.
    Kune Mushandisi uye AXI Interface dhizaini zviri nani kuti izvi zvigoneswe.
    • Reorder ndiyo pfungwa inotarisa kumberi mirairo yakati wandei uye inoshandura mushandisi yekuraira odha kuita isiri-yendangariro mirairo isingagare inoshanda bandwidth. Kuita kwacho kunoenderana neiyo chaiyo traffic pateni.
    • Zvichienderana nemaitiro ekero, kurodha kunobatsira kusvetuka precharge uye kumisikidza mirairo uye inoita kuti tRCD uye tRP isatore data bhendi upamhi.Xilinx DDR2 MIG 7 Performance Estimation-fig-23
  3. Edza kuwedzera nhamba yeBank Machines.
    • Mazhinji emutongi wepfungwa anogara mumakina ebhangi uye anoenderana nemabhangi eDRAM
    • Muchina webhangi wakapihwa unobata bhangi rimwe reDRAM chero nguva.
    • Bank machine assignment ine simba saka hazvikodzeri kuve nemuchina webhangi kubhengi rega rega remuviri.
    • Michina yebhangi inogona kugadzirwa, asi ndeye tradeoff pakati penzvimbo nekuita.
    • Nhamba inobvumirwa yemakina emabhangi inotangira pa2-8.
    • Nekutadza, 4 Bank Machines inogadziriswa kuburikidza neRTL paramita.
    • Kuti uchinje Bank Machines, funga parameter nBANK_MACHS = 8 iri mukati memc_ui_top Ex.ample ye8 Bank Machines - nBANK_MACHS = 8

Wava kuziva zvinhu zvinopesvedzera kuita basa.
Funga nezve application yekukwira iyo inokupa 512 data byte packet uye iwe unofanirwa kuichengeta kune dzakasiyana nzvimbo dzekurangarira. Sezvo 512 data bytes yakaenzana ne64 DDR3 data bursts, mhanyisa ex.ample dhizaini ine kukurudzira file ine 512 inonyora, 512 inoverenga uye mutsara switching kune yega 64 inonyora kana kuverenga:

  • 3f_0_0_0000_000_0
  • 3f_0_0_0001_000_0
  • 3f_0_0_0002_000_0
  • 3f_0_0_0003_000_0
  • 3f_0_0_0004_000_0
  • 3f_0_0_0005_000_0
  • 3f_0_0_0006_000_0
  • 3f_0_0_0007_000_0
  • 3f_0_0_0000_000_1
  • 3f_0_0_0001_000_1
  • 3f_0_0_0002_000_1
  • 3f_0_0_0003_000_1
  • 3f_0_0_0004_000_1
  • 3f_0_0_0005_000_1
  • 3f_0_0_0006_000_1
  • 3f_0_0_0007_000_1

Pakupera kwekufananidza iwe uchaona kuti kushandiswa kwebhazi kuri pa77 muzana. Xilinx DDR2 MIG 7 Performance Estimation-fig-24

Mufananidzo 11: Performance Statistics ye512 inonyora uye 512 inoverenga - Row switching ye64 inonyora kana kuverenga. 

Iwe zvino unogona kushandisa ruzivo rwakadzidzwa muchikamu chekutanga kuvandudza kushanda. With a view pakushandisa mabhanga ese pachinzvimbo chekuchinja mutsara, shandura kero patani kuti uchinje bhangi sezvakaratidzwa pasi apa.
Izvi zvakaenzana nekuseta ROW_BANK_Column mumepu yemepu yekero muMIG GUI.

  • 3f_0_0_0000_000_0
  • 3f_0_1_0000_000_0
  • 3f_0_2_0000_000_0
  • 3f_0_3_0000_000_0
  • 3f_0_4_0000_000_0
  • 3f_0_5_0000_000_0
  • 3f_0_6_0000_000_0
  • 3f_0_7_0000_000_0
  • 3f_0_0_0000_000_1
  • 3f_0_1_0000_000_1
  • 3f_0_2_0000_000_1
  • 3f_0_3_0000_000_1
  • 3f_0_4_0000_000_1
  • 3f_0_5_0000_000_1
  • 3f_0_6_0000_000_1
  • 3f_0_7_0000_000_1

Pakupera kwekufananidza iwe uchaona kuti yekutanga 77 Percent Bhazi Kushandisa ikozvino 87! Xilinx DDR2 MIG 7 Performance Estimation-fig-25

Kana iwe uchiri kuda hunyanzvi hwepamusoro, unogona kuenda kune akakura mapaketi saizi e1024 kana 2048 bytes, kana kufunga bhuku rekuvandudza.

Cherechedza: Xilinx haikurudzire kupfuudza controller kuzorodza sezvo isu tisina chokwadi kana iwe uchizokwanisa kusangana neJedec auto refresh nguva iyo inokanganisa kuvimbika kwedata.
Kubva kudivi rekutonga unogona kuchinja nBANk_MACH woona kuvandudzwa kwekuita.
Nekudaro, izvi zvinogona kukanganisa dhizaini yako nguva, ndapota tarisa kune (Xilinx Mhinduro 36505) kuti uwane ruzivo panBANk_MACHXilinx DDR2 MIG 7 Performance Estimation-fig-26

Vhura iyo core_name_mig_sim.v file uye shandura parameters nBANK_MACHS kubva pa4 kusvika ku8 uye shandisa zvakare simulation. Kuti uwane kukosha kweparameta muhardware, unofanirwa kugadzirisa iyo core_name_mig.v file.
Ndakashandisa nzira imwechete yatakawana 87% kushandiswa kwebhazi (mufananidzo -12).
NenBANK_MACHS yakaiswa ku8, kushanda zvakanaka kwave 90%. Xilinx DDR2 MIG 7 Performance Estimation-fig-27

Nyorawo chinyorwa kuti ½ uye ¼ controller inokanganisa kushanda zvakanaka nekuda kwekunonoka kwavo.
For example, sezvo isu tichingokwanisa kutumira mirairo yega yega 4 CK matenderedzwa pane dzimwe nguva yakawedzera padding kana uchiomerera kune shoma DRAM nguva yakatarwa, iyo inogona kuderedza kushanda zvakanaka kubva kune theoretical.
Edza ma controller akasiyana kuti uwane iyo inoenderana nezvinodiwa zvako zvakanaka.

References

  1. Zynq-7000 AP SoC uye 7 Series FPGAs MIS v2.3 [UG586]
  2. Xilinx MIG Solution Center http://www.xilinx.com/support/answers/34243.html

Revision History
13/03/2015 - Kuburitswa kwekutanga

Dhawunirodha PDF: Xilinx DDR2 MIG 7 Performance Estimation Guide

References

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