Xilinx DDR2 MIG 7 Tataiso ea Tekanyetso ea Ts'ebetso
Keletso ea Bohlokoa: PDF ena e jarollotsoeng ea Rekoto ea Karabo e fanoe ho ntlafatsa ts'ebeliso ea eona le ho baloa ha eona. Ho bohlokoa ho hlokomela hore Litlaleho tsa Karabo li Web-ka litaba tse nchafalitsoeng khafetsa ha litaba tse ncha li fumaneha. U hopotsoa ho etela Tšehetso ea Tekheniki ea Xilinx Websebaka le botjhaview (Xilinx Answer 63234) bakeng sa phetolelo ea morao-rao ea Karabo ena.
Selelekela
Ka lebaka la tsela eo mehopolo ea DDR2 le DDR3 e raliloeng ka eona le taolo ea letoto la MIG 7 e entsoe, ts'ebetso ha e ea pele.
E hloka kutloisiso ea mekhahlelo e fapaneng ea Jedec Timing le Architecture ea taolo, 'me u tla hloka ho etsa lipapiso ho fumana likhakanyo.
Molao-motheo o akaretsang oa ho khetholla ts'ebetso o ts'oana empa tokomane ena e fana ka mokhoa o bonolo oa ho fumana katleho ka ho sebelisa MIG example moralo ka thuso ea benche ea liteko le ts'usumetso filee khomaretsoe mona.
Bandwidth e sebetsang
Bese ea data ea DRAM e fihlella bandwidth e haufi le tlhoro feela nakong ea ho bala le ho ngola, 'me bokaholimo ba eona bo theola sekhahla se sebetsang sa data.
Ba seng bakae examplintlha tse ka sehloohong ke:
- nako ea ho kena ka har'a bankeng e le 'ngoe (Aterese ea ho kena ha e molaong o tšoanang oa leqephe)
- ngola nako ea ho khutlisa ho fetola ho tloha ho ngola ho ea ho phihlello ea ho bala
- nako ea ho fetola libese ho tloha ho bala ho ea ho phihlello ea ho ngola
Bophahamo bo Sebetsang = Bophahamo ba Sehlohlolong * Bokhabane
Moloko oa Moqapi oa MIG
Sheba UG586 Khaolo ea 1 bakeng sa lintlha tsa mohato ka mohato ho MIG IP le example moralo moloko.
Pele o sebelisa papiso ea ts'ebetso ea MIG 7 Series, etsa se latelang ho etsa bonnete ba hore tikoloho ea hau ea papiso e ntle. Bula MIG example rala le ho etsa 'mapa oa lilaebrari tse nepahetseng, tsamaisa papiso,' me u netefatse hore u ka bona molaetsa "teko e fetisitsoeng" sengolong.
Ho bonts'a phallo ke hlahisitse MIG IP bakeng sa xc7vx690tffg1761-2 mme ke kopa ex.ampmoralo.
Lintho tse peli tse lokelang ho hlokomeloa ke likaroloana tsa aterese ea memori le khetho ea 'mapa oa aterese ea memori.
Bakeng sa mohlalaample, ke khethile MT41J128M8XX-125 tlas'a khetho ea ho theoha ea memori.
Bakeng sa karolo e khethiloeng ea memori ho tsoa ho Setšoantšo-1, mola = 14, kholomo = 10 le banka = 3, kahoo app_addr_width = row + column + bank + rank= 28 
O ka khetha BANK_ROW_COLUMN kapa ROW BANK Kholomo.
Ke tlohetse Kholomo ea ROW BANK e leng 'mapa oa aterese ea kamehla.
Example moralo Ketsiso e nang le benche ea tlhahlobo ea synthesizeble
Tlas'a Litlhophiso tsa Simulation, khetha QuestaSim/ModelSim Simulator 'me u shebelle sebakeng sa lilaebrari tse hlophisitsoeng.
Bakeng sa lintlha tse mabapi le ho supa mokhoa oa ho kenya lisebelisoa tsa motho oa boraro, ho khetha simulator eo u e batlang, le ho hlophisa le ho etsa lilaebrari, u ka sheba (UG900) Vivado Design Suite User Guide Logic Simulation.
Etsa papiso ka GUI (Tobetsa Run Simulation Tab ho mookameli oa morero) 'me u netefatse hore u bona molaetsa oa "teko e fetile" ho sengoloa.
Performance Simulation RTL diphetolo
- Tobetsa ka ho le letona ho tab ea mehloli, khetha "eketsa kapa u thehe mehloli ea papiso", 'me u shebe ho mig7_perfsim_traffic_generator.sv file ebe o tobetsa finish ho e eketsa.
- Tobetsa ka ho le letona ho tab ea mehloli, khetha "eketsa kapa u thehe mehloli ea papiso", sheba ho perfsim_stimulus.txt, 'me u tobetse qetellong ho e eketsa.
- Hlalosa maikutlo a example_top instantiation ho sim_tb_top.v file.
- Kenya mela e ka tlase ea RTL ho sim_tb_top,v
- localparam APP_ADDR_WIDTH = 28;
- localparam APP_DATA_WIDTH = 64;
- localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
- localparam MEM_ADDR_ORDER = “BANK_ROW_COLUMN”;
- localparam BANK_WIDTH = 3;
- localparam RANK_WIDTH = 1;
- terata [APP_ADDR_WIDTH-1:0] c0_ddr3_app_addr;
- terata [2:0] c0_ddr3_app_cmd;
- terata c0_ddr3_app_en;
- terata [APP_DATA_WIDTH-1:0] c0_ddr3_app_wdf_data;
- terata c0_ddr3_app_wdf_end;
- terata [APP_MASK_WIDTH-1:0] c0_ddr3_app_wdf_mask;
- terata c0_ddr3_app_wdf_wren;
- terata [APP_DATA_WIDTH-1:0] c0_ddr3_app_rd_data;
- terata c0_ddr3_app_rd_data_end;
- terata c0_ddr3_app_rd_data_valid;
- terata c0_ddr3_app_rdy;
- terata c0_ddr3_app_wdf_rdy;
- terata c0_data_compare_error;
- terata ui_clk;
- terata ui_clk_sync_rst;
- terata app_sr_req = 0;
- terata app_ref_req = 0;
- terata app_zq_req =0;
- terata c0_app_wdf_mask =0;
FPGA Memory Controller instatation
mig_7series_0_mig u_mig_7series_0_mig (
// Boema-kepe ba memori
- .ddr3_addr (ddr3_addr_fpga),
- .ddr3_ba (ddr3_ba_fpga),
- .ddr3_cas_n (ddr3_cas_n_fpga),
- .ddr3_ck_n (ddr3_ck_n_fpga),
- .ddr3_ck_p (ddr3_ck_p_fpga),
- .ddr3_cke (ddr3_cke_fpga),
- .ddr3_ras_n (ddr3_ras_n_fpga),
- .ddr3_reset_n (ddr3_reset_n),
- .ddr3_we_n (ddr3_we_n_fpga),
- .ddr3_dq (ddr3_dq_fpga),
- .ddr3_dqs_n (ddr3_dqs_n_fpga),
- .ddr3_dqs_p (ddr3_dqs_p_fpga),
- .init_calib_feletseng (init_calib_feletseng),
- .ddr3_cs_n (ddr3_cs_n_fpga),
- .ddr3_dm (ddr3_dm_fpga),
- .ddr3_odt (ddr3_odt_fpga),
// Boema-kepe ba sebopeho sa kopo
- .app_addr (c0_ddr3_app_addr),
- .app_cmd (c0_ddr3_app_cmd),
- .app_en (c0_ddr3_app_en),
- .app_wdf_data (c0_ddr3_app_wdf_data),
- .app_wdf_end (c0_ddr3_app_wdf_end),
- .app_wdf_wren (c0_ddr3_app_wdf_wren),
- .app_rd_data (c0_ddr3_app_rd_data),
- .app_rd_data_end (app_rd_data_end),
- .app_rd_data_valid (c0_ddr3_app_rd_data_valid),
- .app_rdy (c0_ddr3_app_rdy),
- .app_wdf_rdy (c0_ddr3_app_wdf_rdy),
- .app_sr_req (app_sr_req),
- .app_ref_req (app_ref_req),
- .app_zq_req (app_zq_req),
- .app_sr_active (app_sr_active),
- .app_ref_ack (app_ref_ack),
- .app_zq_ack (app_zq_ack),
- .ui_clk (ui_clk),
- .ui_clk_sync_rst (ui_clk_sync_rst),
- .app_wdf_mask (c0_ddr3_app_wdf_mask),
// System Clock Ports
- .sys_clk_i (sys_clk_i),
// Reference Clock Ports
- .clk_ref_i (clk_ref_i),
- .sys_rst (sys_rst)
- );
Ts'ebetso ea jenereithara ea sephethephethe
mig7_perfsim_traffic_generator#
(
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.tCK (tCK),
.ADDR_WIDTH (APP_ADDR_WIDTH)
)
u_traffic_gen
(
.clk (ui_clk ),
.rst (ui_clk_sync_rst ),
.init_calib_feletseng (init_calib_feletseng),
.cmp_error (c0_data_compare_error),
.app_wdf_rdy (c0_ddr3_app_wdf_rdy ),
.app_rd_data_valid (c0_ddr3_app_rd_data_valid),
.app_rd_data (c0_ddr3_app_rd_data ),
.app_rdy (c0_ddr3_app_rdy),
.app_cmd (c0_ddr3_app_cmd ),
.app_addr (c0_ddr3_app_addr ),
.app_en (c0_ddr3_app_en ),
.app_wdf_mask (c0_ddr3_app_wdf_mask),
.app_wdf_data (c0_ddr3_app_wdf_data),
.app_wdf_end (c0_ddr3_app_wdf_end ),
.app_wdf_wren (c0_ddr3_app_wdf_wren)
);
- 5. Fetola APP_ADDR_WIDTH, APP_DATA_WIDTH, RANK_WIDTH le BANK_WIDTH ho latela khetho ea memori ea hau.
Litekanyetso li ka fumanoa ho _mig.v file. - Lebitso la instantiation le mosehla mig_7series_0_mig le ka fapana ho latela lebitso la karolo ea hau nakong ea tlhahiso ea IP, netefatsa hore na u khethile lebitso le fapaneng 'me u le fetole ka nepo.
- Hang ha IP e hlahisoa, bula file ea _mig.v file 'me u hlahlobe liphapang life kapa life tsa mabitso a matšoao a LHS ebe u li lokisa.
- app_sr_req, app_ref_req le app_zq_req li lokela ho qalisoa ho 0.
- Joalo ka mohlalaample_top.v e hlalositsoe ebile e ncha files li kenyellelitsoe, mohlomong u tla bona "?" haufi le
mig_7series_0_mig.v file tlas'a mehloli ea ketsiso.
Ho etsa 'mapa o nepahetseng file, tobetsa ka ho le letona mig_7series_0_mig.v, khetha "Kenya Mehloli", Batla ho
/mig_7series_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl
ebe o kenya mig_7series_0_mig_sim.v file. - Haeba u bona "?" bakeng sa motheo files, eketsa RTL kaofela files ho li-wache, molaoli, ip_top, phy le lifoldara tsa UI.
- Hang ha liphetoho tsa RTL li entsoe le tsohle tse hlokahalang files li kenyellelitsoe mehloling ea hau ea Simulation, Hierarchy e lokela ho tšoana le Setšoantšo sa 5.
The filetse totobalitsoeng ka bofubelu li sa tsoa eketsoa, le “?” e lebelletsoe ho li-module tse amanang le ECC kaha tlhophiso ea memori e khethiloeng e na le khetho ea ECC e holofalitsoeng.
Khothatso File Tlhaloso
Mokhoa o mong le o mong oa ts'usumetso ke li-bits tse 48 mme sebopeho se hlalositsoe ho Lipapiso 6-1 ho isa ho 6-4.
Khouto ea Aterese (Aterese [35:0])
Aterese e kentsoe ka har'a tšusumetso joalo ka Sets'oants'o sa 7-1 ho Figure 7-6. Likarolo tsohle tsa liaterese li hloka ho kenngoa ka sebopeho sa hexadecimal. Likarolo tsohle tsa liaterese ke bophara bo aroloang ka tse 'ne ho kenya sebopeho sa hexadecimal. Benche ea teko e romela feela likarolo tse hlokahalang tsa sebaka sa aterese ho Mookameli oa Memori.
Bakeng sa mohlalaample, ka tlhophiso ea libanka tse robeli, ke li-Bits tsa banka feela [2:0] tse romeloang ho Mookameli oa Memori mme likarolo tse setseng li hlokomolohuoa. Li-bits tse ling bakeng sa sebaka sa aterese li fanoe hore u kenye aterese ka sebopeho sa hexadecimal.
U tlameha ho netefatsa hore boleng bo kentsoeng bo lumellana le bophara ba tlhophiso e fanoeng.
- Aterese ea Kholomo (Kholomo[11:0]) - Aterese ea Kholomo ka har'a tšusumetso e fanoe ho isa ho li-bits tse 12, empa o hloka ho sebetsana le sena ho ipapisitse le paramethara ea bophara ba kholomo e behiloeng moralong oa hau.
- Aterese ea Mola (Mola[15:0]) - Aterese ea mola ka har'a stimulus e fanoa ho fihla ho li-bits tse 16, empa o hloka ho sebetsana le sena ho ipapisitse le bophara ba mela e behiloeng moralong oa hau.
- Aterese ea Banka (Banka[3:0]) - Aterese ea banka ka har'a stimulus e fanoa ho fihla ho li-bits tse 'ne, empa u lokela ho sebetsana le sena ho latela parameter ea bophara ba banka e behiloeng moralong oa hau.
- Aterese ea Boemo (Boemo[3:0]) - Aterese ea maemo ho ts'usumetso e fanoa ho isa ho li-bits tse 'ne, empa o hloka ho sebetsana le sena ho ipapisitse le paramethara ea bophara bo behiloeng moralong oa hau.
Aterese e kopanngoa ho ipapisitsoe le maemo a holimo a MEM_ADDR_ORDER 'me a romelloa ho sebopeho sa mosebelisi.
Pheta-taelo (Laela Pheta-pheta [7:0])
Palo ea ho pheta-pheta taelo ke palo ea nako eo taelo e fapaneng e phetoang ka eona ho User Interface. Aterese bakeng sa pheta-pheto e 'ngoe le e' ngoe e eketsoa ka 8. Palo e phahameng ea ho pheta-pheta ke 128.
Benche ea teko ha e hlahlobe moeli oa litšiea 'me e pota-pota haeba moeli o moholo oa kholomo o fihletsoe nakong ea li-increments.
Litaelo tse 128 li tlatsa leqephe. Bakeng sa aterese efe kapa efe ea kholomo ntle le 0, palo ea ho pheta-pheta ea 128 e qetella e tšela moeli oa kholomo ebe e phuthela ho fihlela qalong ea aterese.
Tšebeliso ea Libese
Ts'ebeliso ea libese e baloa ho Sehokelo sa Basebelisi ho nka palo eohle ea Tse Baloang le Tse Ngola li nahaneloa 'me ho sebelisoa equation e latelang:
- BL8 e nka lipotoloho tse 'ne tsa oache ea memori
- end_of_stimulus ke nako eo litaelo tsohle li etsoang ka eona.
- calib_done ke nako eo ka eona calibration e etsoang.
Example Mekhoa
Tsena examptse ling li ipapisitse le MEM_ADDR_ORDER e behiloeng ho BANK_ROW_COLUMN.
Mokhoa oa ho Bala o le Mong
00_0_2_000F_00A_1 - Paterone ena ke palo e le 'ngoe e baloang ho tloha kholomong ea 10, mola oa 15, le bankeng ea bobeli.
Mokhoa oa ho Ngola o le Mong
00_0_1_0040_010_0 - Paterone ena ke mongolo o le mong ho ea karolong ea 32, mola oa 128, le banka ea pele.
Ngola U le Mong 'me U Balle ho Aterese e Tšoanang
00_0_2_000F_00A_0 – Mokhoa ona ke mongolo o le mong ho ea ho karolo ea 10, mola oa 15, le banka ea bobeli.
00_0_2_000F_00A_1 – Paterone ena ke palo e le 'ngoe e baloang ho tloha kholomong ea 10, mola oa 15, le banka ea bobeli
Bangata ba Ngola le ho Bala ka Aterese e Tšoanang
0A_0_0_0010_000_0 – Sena se lumellana le 10 e ngola ka aterese e qalang ho tloha ho 0 ho isa ho 80 e ka bonoang kholomong.
0A_0_0_0010_000_1 – Sena se tsamaisana le lipalo tse 10 tse nang le aterese ho tloha ho 0 ho isa ho 80 tse ka bonoang kholomong.
Qetella Maqephe Nakong ea ho Ngola
0A_0_2_000F_3F8_0 – Sena se lumellana le 10 e ngola ka aterese ea kholomo e phuthetsoeng qalong ea leqephe ka mor'a ho ngola.
Ho etsisa Performance Traffic Generator
Mothating ona u se u qetile ka MIG example moralo ketsiso. Sena se fana ka maikutlo a hore ketsiso ea hau e se e lokile, u entse liphetoho tsa RTL tsa papiso ea ts'ebetso, sehlopha se secha sa papiso se nepahetse 'me u utloisisa mekhoa ea khothatso. Etsa papiso hape ka ho ngola tse 16 'me u bale ho perfsim_stimulus.txt.
Etsa tsohle, ema ho fihlela letšoao la init_calib_complete le tiisitsoe, 'me u tla khona ho bona palo e reriloeng ea ho ngola le ho bala. Ketsiso e tla emisa. 
Ha o khothalletsoa ho tlohela papiso, khetha Che 'me u ee fensetereng ea sengoloa moo u tla khona ho bona lipalo-palo tsa ts'ebetso. 
Haeba u khetha "tlohela papiso" lipalo-palo tsa tšebetso li tla ngolloa ho a file bitsetsoe mig_band_width_output.txt e fumaneha ho sim_1/behave foldara.
Examptsela ea directory: -
/mig_7series_0_example_perf_sim\mig_7series_0_example.sim/sim_1/behav
U ka 'na ua ipotsa hore na ke hobane'ng ha palo e joalotagts'ebeliso ea libese ke ony 29. Etsa hape papiso ka li-setting tse tšoanang tsa IP empa u fetole feela tšusumetso. file ho 256 ba ngola le 256 bala
ff_0_0_0000_000_0
ff_0_0_0000_000_1
Joale u tla bona palotage le 85, ho bolelang hore DDR3 e fana ka ts'ebeliso e ntle ea libese bakeng sa tatellano e telele ea ho ngola le ho bala ho phatloha. 
Mekhoa e akaretsang ea ho Ntlafatsa Ts'ebetso
Lintlha tse susumetsang katleho li ka aroloa ka likarolo tse peli:
- Mehopolo e Ikhethileng
- Taolo e Khethehileng
Setšoantšo sa 9 se u fa ho fetaview ya mareo a tobileng mohopolo.
Ho fapana le SRAMs le Block Memories DDR2 kapa DDR3 tshebetso ha se feela tekanyo e phahameng ea data.
E ipapisitse le lintlha tse ngata tsa nako, ho kenyelletsa:
- tRCD: Row Command Delay (kapa ras to cas delay).
- tCAS(CL): Kholomo ea aterese ea strobe latency.
- tRP: Ho lieha ho chacha.
- TRAS: Row Active Time (kenya tshebetsong ho fetola).
- tRC: Nako ea potoloho ea mela. tRC = tRAS + tRP
- TRAC: Ho lieha ho fihlella ka tšohanyetso. tRAC = tRCD + tCAS
- tCWL: Cas ngola latency.
- tZQ: Nako ea ho lekanya ZQ.
- tRFC: Row Refresh Cycle Nako
- tWTR: Ngola ho Bala tieho. Qetela ho ngola transaction ho Bala nako ea taelo.
- tWR: Ngola Nako ea Pholiso. Qetela ho ngola transaction ho Precharge time
Nako ea li-parameter tsohle tse thathamisitsoeng e ipapisitse le mofuta oa memori o sebelisitsoeng le kereiti ea lebelo la karolo ea memori.
Lintlha tse ling mabapi le litlhaloso le lintlha tsa nako li ka fumanoa ho DDR2 DDR3 JEDEC kapa database efe kapa efe ea sesebelisoa sa memori.
Ho sebetsa hantle haholo ho itšetlehile ka hore na memori e fihlella joang. Mekhoa e fapaneng ea liaterese e fana ka liphetho tse fapaneng tse sebetsang hantle.
Ho boloka nako ea memori
- Nako ea ts'ebetso le nako ea Precharge ha u fetohela libankeng tse ncha / mela kapa ho fetola mela le bankeng e le 'ngoe.- Kahoo haeba u fokotsa phetoho ea mela, sena se ka tlosa tRCD le tRP.
- Romella litaelo tse tsoelang pele tsa ho ngola kapa ho bala -Ho boloka nako ea tCCD.
- Fokotsa ho ngola ho bala le ho bala ho ngola phetoho ea taelo - Ngola nako ea ho khutlisa ho fetola ho bala phihlello, nako ea ho fetola libese ho tloha ho bala ho ea ho ngola
- Beha nako e nepahetseng ea ho khatholla.
- DDR3 SDRAM e hloka lipotoloho tsa Nchafatso ka nako e tloaelehileng ea tREFI.
- Litaelo tse ling tse 8 tsa ho nchafatsa li ka fanoa esale pele ("ho huleloa"). Sena ha se fokotse palo ea likhathollo, empa nako e telele pakeng tsa litaelo tse peli tse potolohileng Refresh e lekanyelitsoe ho 9 × tREFI.
- Sebelisa libanka tsohle - Mokhoa o nepahetseng oa ho bua o molemo.
- Mola-Bank-Column: Bakeng sa transaction e etsahalang sebakeng se latellanang sa aterese, mantlha e bula mola o le mong bankeng e latelang ea sesebelisoa sa DRAM ho ntšetsa pele transaction ha pheletso ea mola o teng o fihla. E loketse lits'ebetso tse hlokang ho phatloha ha lipakete tse kholo tsa data ho ea libakeng tse latellanang tsa aterese.
- Bank-Row-Column: Ha u tšela moeli oa mola, mola oa hona joale o tla koaloa 'me mola o mong o tla buloa ka har'a banka e tšoanang. MSB ke aterese ea banka, e ka sebelisoang ho fetola libanka tse fapaneng. E loketse ts'ebetso e khuts'oane, e sa reroang ho sebaka se le seng sa memori ka nako e itseng ebe o tlolela block e 'ngoe (banka)
- Bolelele ba ho phatloha
- BL 8 e tšehetsoa bakeng sa DDR3 ho lihlopha tse 7. BC4 e na le ts'ebetso e tlase haholo e ka tlase ho 50%. Sena se bakoa ke hore nako ea ts'ebetso ea BC4 e tšoana le BL8. Lintlha li patiloe feela ka har'a karolo.
- Maemong ao u sa batleng ho ngola ka botlalo, ho ka nahanoa maske ea data kapa ho ngola-kamora ho bala.
- Beha nako e nepahetseng ea ZQ (DDR3 Feela)
Molaoli o romela litaelo tsa Calibration tsa ZQ Short (ZQCS) le ZQ Long (ZQCL).- Khomarela DDR3 Jedec Standard
- ZQ Calibration e tšohloa karolong ea 5.5 ea JEDEC Spec JESD79-3 DDR3 SDRAM Standard
- ZQ Calibration e lekanya On Die Termination (ODT) nako le nako ho ikarabella bakeng sa mefuta e fapaneng ea VT.
- Monahano o teng ho bank_common.v/vhd
- Parameter Tzqcs e etsa qeto ea hore na taelo ea ZQ Calibration e romelloa hakae mohopolong
- Hoa khoneha ho tima k'haontareng le ho romella ka letsoho u sebelisa app_zq_req, hoa tšoana le ho romella Refresh ka letsoho.
Sheba (Xilinx Karabo 47924) bakeng sa lintlha.
Likarolo tsa Molaoli
- Ho bala ka Nako le Nako - Sheba ho (Xilinx Karabo 43344) bakeng sa lintlha.
- U se ke ua fetola nako ea ho bala
- Tlohela ho bala nako le nako nakong ea ho ngola 'me u fane ka palo ea lintho tse baloang pele u bala' nete
- Ho hlophisa bocha - Sheba (Xilinx Karabo 34392) bakeng sa lintlha.
Bakeng sa meralo ea Mosebelisi le AXI Interface ho molemo hore sena se khonehe.- Reorder ke mohopolo o shebileng pele litaelo tse 'maloa mme o fetola taelo ea mosebelisi ho etsa hore litaelo tseo e seng tsa memori li se ke tsa nka bandwidth e nepahetseng. Ts'ebetso e boetse e amana le mokhoa oa 'nete oa sephethephethe.
- Ho ipapisitsoe le mokhoa oa aterese, ho hlophisa bocha ho thusa ho tlola tefiso ea pele le ho kenya litaelo mme e etsa hore tRCD le tRP li se ke tsa nka bophara ba sehlopha sa data.
- Leka ho eketsa palo ea Mechini ea Banka.
- Boholo ba lintlha tsa molaoli li lula ka har'a mechini ea banka mme li lumellana le libanka tsa DRAM
- Mochini o fanoeng oa banka o laola banka e le 'ngoe ea DRAM ka nako efe kapa efe.
- Mosebetsi oa mochini oa banka o matla ka hona ha ho hlokahale ho ba le mochini oa banka bakeng sa banka e 'ngoe le e' ngoe ea 'mele.
- Mechini ea banka e ka hlophisoa, empa ke khoebo pakeng tsa sebaka le ts'ebetso.
- Palo e lumelletsoeng ea mechini ea banka e tloha ho 2-8.
- Ka mokhoa o ikhethileng, Mechini e 4 ea Banka e hlophisoa ka liparamente tsa RTL.
- Ho fetola Mechini ea Banka, nahana ka paramethara nBANK_MACHS = 8 e fumanehang ho memc_ui_top Ex.ample bakeng sa Mechini e 8 ea Banka - nBANK_MACHS = 8
Hona joale u tseba lintlha tse susumetsang ts'ebetso.
Nahana ka sesebelisoa se holimo se u fang li-byte tsa data tse 512 pakete ka 'ngoe mme u hloka ho li boloka libakeng tse fapaneng tsa memori. Ha li-byte tsa data tse 512 li lekana le ho phatloha ha data tse 64 DDR3, tsamaisa ea pele hape.ample moralo ka ts'usumetso file e nang le 512 e ngola, 512 e baloa le ho fetola mela bakeng sa tse ling le tse ling tse 64 tse ngolang kapa tse baloang:
- 3f_0_0_0000_000_0
- 3f_0_0_0001_000_0
- 3f_0_0_0002_000_0
- 3f_0_0_0003_000_0
- 3f_0_0_0004_000_0
- 3f_0_0_0005_000_0
- 3f_0_0_0006_000_0
- 3f_0_0_0007_000_0
- 3f_0_0_0000_000_1
- 3f_0_0_0001_000_1
- 3f_0_0_0002_000_1
- 3f_0_0_0003_000_1
- 3f_0_0_0004_000_1
- 3f_0_0_0005_000_1
- 3f_0_0_0006_000_1
- 3f_0_0_0007_000_1
Qetellong ea papiso u tla bona hore ts'ebeliso ea libese ke karolo ea 77 lekholong. 
Setšoantšo sa 11: Lipalo-palo tsa Ts'ebetso bakeng sa 512 e ngola le 512 e bala - Ho fetola mela bakeng sa 64 ho ngola kapa ho bala.
Hona joale o ka sebelisa tsebo eo u ithutileng eona karolong e fetileng ho ntlafatsa ts'ebetso. Ka a view ho sebelisa libanka tsohle ho e-na le ho fetola mola, fetola mokhoa oa aterese ho fetola banka joalokaha ho bontšitsoe ka tlase.
Sena se lekana le ho seta ROW_BANK_Column ho tlhophiso ea 'mapa ea aterese ea memori ho MIG GUI.
- 3f_0_0_0000_000_0
- 3f_0_1_0000_000_0
- 3f_0_2_0000_000_0
- 3f_0_3_0000_000_0
- 3f_0_4_0000_000_0
- 3f_0_5_0000_000_0
- 3f_0_6_0000_000_0
- 3f_0_7_0000_000_0
- 3f_0_0_0000_000_1
- 3f_0_1_0000_000_1
- 3f_0_2_0000_000_1
- 3f_0_3_0000_000_1
- 3f_0_4_0000_000_1
- 3f_0_5_0000_000_1
- 3f_0_6_0000_000_1
- 3f_0_7_0000_000_1
Qetellong ea papiso u tla bona hore Ts'ebeliso ea Libese ea 77% ea pejana e se e le 87! 
Haeba o ntse o hloka ts'ebetso e phahameng, o ka reka lipakete tse kholo tsa 1024 kapa 2048 byte, kapa u nahane ka ho khatholla ka letsoho.
Hlokomela: Xilinx ha e khothaletse ho khatholla taolo ea ho feta kaha ha re na bonnete ba hore na u tla khona ho kopana le nako ea ho khatholla koloi ea Jedec e amang ts'epo ea data.
Ka lehlakoreng la molaoli u ka fetola nBANk_MACH 'me u bone ntlafatso ea ts'ebetso.
Leha ho le joalo, sena se ka ama nako ea moralo oa hau, ka kopo sheba ho (Xilinx Karabo 36505) bakeng sa lintlha tse mabapi le nBANk_MACH
Bula core_name_mig_sim.v file 'me u fetole li-parameter nBANK_MACHS ho tloha ho 4 ho ea ho 8' me u sebelise papiso hape. Ho etsa hore boleng ba parametha bo sebetse ho hardware, o hloka ho nchafatsa core_name_mig.v file.
Ke sebelisitse mokhoa o tšoanang moo re ileng ra fumana 87% ea tšebeliso ea libese (setšoantšo -12).
Ha nBANK_MACHS e behiloe ho 8, katleho e se e le 90%. 
Hape hlokomela hore balaoli ba ½ le ¼ ba ama ts'ebetso hampe ka lebaka la ho lieha ha bona.
Bakeng sa mohlalaample, kaha re ka romella feela litaelo ka nako e 'ngoe le e' ngoe ea 4 CK ka linako tse ling ho na le padding e eketsehileng ha ho latela lintlha tse fokolang tsa nako ea DRAM, tse ka fokotsang katleho ho tsoa ho theory.
Leka balaoli ba fapaneng ho fumana e lumellanang le tlhoko ea hau ea ts'ebetso.
Litšupiso
- Zynq-7000 AP SoC le 7 Series FPGAs MIS v2.3 [UG586]
- Xilinx MIG Setsi sa Tharollo http://www.xilinx.com/support/answers/34243.html
Nalane ea Phetoho
13/03/2015 - Tokollo ea pele
Khoasolla PDF: Xilinx DDR2 MIG 7 Tataiso ea Tekanyetso ea Ts'ebetso
