Xilinx DDR2 MIG 7 Performance Estimation Guide

Chidziwitso chofunikira: PDF yotsitsa iyi ya Rekodi Yankho imaperekedwa kuti ipititse patsogolo kugwiritsidwa ntchito kwake komanso kuwerengeka. Ndikofunika kuzindikira kuti Mayankho Records ndi Web-zotengera zomwe zimasinthidwa pafupipafupi pomwe zatsopano zikupezeka. Mukukumbutsidwa kuti mupite ku Xilinx Technical Support Webtsamba ndi review (Xilinx Yankho 63234) pamtundu waposachedwa wa Yankho ili.

Mawu Oyamba

Chifukwa cha momwe kukumbukira kwa DDR2 ndi DDR3 kumapangidwira komanso chowongolera cha MIG 7 chimapangidwira, magwiridwe antchito siwolunjika patsogolo.
Zimafunika kumvetsetsa kwamitundu yosiyanasiyana ya Jedec Timing ndi Zomangamanga zowongolera, ndipo mudzafunika kuyendetsa zofananira kuti mupeze zowerengera.
Mfundo yodziwika bwino yodziwira magwiridwe antchito ndi yofanana koma chikalatachi chimapereka njira yosavuta yopezera bwino pogwiritsa ntchito MIG example kupanga mothandizidwa ndi benchi yoyesera ndi chilimbikitso filezaphatikizidwa pano.

Kugwiritsira Ntchito Kwabwino

Mabasi a data a DRAM amafika pachimake bandwidth pokhapokha powerenga ndi kulemba ndipo mutu wake umachepetsa kuchuluka kwa data.
Ochepa exampZolemba zapamwamba ndi izi:

• nthawi yopezeratu mizere mu banki yomweyo (Adilesi yolowera siili pamzere womwewo wamasamba)
• lembani nthawi yobwezeretsa kuti musinthe kuchoka polemba kupita ku kuwerenga
• nthawi yosinthira basi kuti isinthe kuchoka ku kuwerenga kupita ku kulemba

Bandwidth Yogwira Ntchito = Chiŵerengero Chapamwamba * Chokwanira 

MIG Design Generation

Onani UG586 Chaputala 1 kuti mudziwe zambiri za MIG IP ndi exampndi kupanga mapangidwe.
Musanagwiritse ntchito kayesedwe ka MIG 7 Series, chitani zotsatirazi kuti muwonetsetse kuti malo anu oyerekeza ali bwino. Tsegulani MIG examplengani ndi kupanga mapu a malaibulale oyenerera, yendetsani kayeseleledwe kake, ndikuwonetsetsa kuti mukuwona uthenga woti "mayeso adutsa" muzolembazo.
Kuti ndiwonetse mayendedwe ndapanga MIG IP ya xc7vx690tffg1761-2 ndikuyitanitsa ex.ampkupanga.
Zinthu ziwiri zomwe ziyenera kuzindikirika ndi ma adilesi okumbukira ndikusankha mapu a ma adilesi.
Za example, ndasankha MT41J128M8XX-125 pansi pa gawo la kukumbukira zomwe mungasankhe.

Pa gawo la kukumbukira lomwe lasankhidwa kuchokera pa Chithunzi-1, mzere = 14, gawo = 10 ndi banki = 3, kotero app_addr_width = mzere + mzere + banki + udindo = 28

Mutha kusankha BANK_ROW_COLUMN kapena ROW BANK Mgawo.
Ndasiya ROW BANK Column yomwe ndi mapu okhazikika.

Exampkamangidwe ka Simulation yokhala ndi benchi yoyeserera yoyeserera

Pansi pa zoikamo Zoyeserera, sankhani QuestaSim/ModelSim Simulator ndikusakatula komwe kuli malaibulale ophatikizidwa.
Kuti mumve zambiri pakulozera zida za chipani chachitatu kukhazikitsa njira, kusankha choyimira chandamale, ndikulemba ndi kupanga malaibulale, mutha kuloza ku (UG900) Vivado Design Suite User Guide Logic Simulation.

Thamangani kayeseleledwe kudzera mu GUI (Dinani Thamangani Kuyerekeza Tab mu woyang'anira polojekiti) ndipo onetsetsani kuti mukuwona uthenga wa "mayeso wadutsa" muzolembazo.

Zosintha za Performance Simulation RTL

1. Dinani kumanja kwa magwero, sankhani "onjezani kapena pangani magwero oyerekeza", ndikusakatula mig7_perfsim_traffic_generator.sv file ndikudina kumaliza kuti muwonjezere.
2. Dinani kumanja kwa magwero, sankhani "onjezani kapena pangani magwero oyerekeza", sakatulani ku perfsim_stimulus.txt, ndikudina malizitsani kuti muwonjezere.
3. Ndemanga za example_top instantiation mu sim_tb_top.v file.
4. Onjezani mizere pansipa ya RTL ku sim_tb_top,v

• localparam APP_ADDR_WIDTH = 28;
• localparam APP_DATA_WIDTH = 64;
• localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
• localparam MEM_ADDR_ORDER = “BANK_ROW_COLUMN”;
• localparam BANK_WIDTH = 3;
• localparam RANK_WIDTH = 1;
• waya [APP_ADDR_WIDTH-1:0] c0_ddr3_app_addr;
• waya [2:0] c0_ddr3_app_cmd;
• waya c0_ddr3_app_en;
• waya [APP_DATA_WIDTH-1:0] c0_ddr3_app_wdf_data;
• waya c0_ddr3_app_wdf_end;
• waya [APP_MASK_WIDTH-1:0] c0_ddr3_app_wdf_mask;
• waya c0_ddr3_app_wdf_wren;
• waya [APP_DATA_WIDTH-1:0] c0_ddr3_app_rd_data;
• waya c0_ddr3_app_rd_data_end;
• waya c0_ddr3_app_rd_data_valid;
• waya c0_ddr3_app_rdy;
• waya c0_ddr3_app_wdf_rdy;
• waya c0_data_compare_error;
• waya ui_clk;
• waya ui_clk_sync_rst;
• waya app_sr_req = 0;
• waya app_ref_req = 0;
• waya app_zq_req =0;
• waya c0_app_wdf_mask =0;

FPGA Memory Controller instantiation

mig_7series_0_mig u_mig_7series_0_mig (
// Madoko a Memory

• .ddr3_addr (ddr3_addr_fpga),
• .ddr3_ba (ddr3_ba_fpga),
• .ddr3_cas_n (ddr3_cas_n_fpga),
• .ddr3_ck_n (ddr3_ck_n_fpga),
• .ddr3_ck_p (ddr3_ck_p_fpga),
• .ddr3_cke (ddr3_cke_fpga),
• .ddr3_ras_n (ddr3_ras_n_fpga),
• .ddr3_reset_n (ddr3_reset_n),
• .ddr3_we_n (ddr3_we_n_fpga),
• .ddr3_dq (ddr3_dq_fpga),
• .ddr3_dqs_n (ddr3_dqs_n_fpga),
• .ddr3_dqs_p (ddr3_dqs_p_fpga),
• .init_calib_complete (init_calib_complete),
• .ddr3_cs_n (ddr3_cs_n_fpga),
• .ddr3_dm (ddr3_dm_fpga),
• .ddr3_odt (ddr3_odt_fpga),

// Madoko ogwiritsira ntchito

• .app_addr (c0_ddr3_app_addr),
• .app_cmd (c0_ddr3_app_cmd),
• .app_en (c0_ddr3_app_en),
• .app_wdf_data (c0_ddr3_app_wdf_data),
• .app_wdf_end (c0_ddr3_app_wdf_end),
• .app_wdf_wren (c0_ddr3_app_wdf_wren),
• .app_rd_data (c0_ddr3_app_rd_data),
• .app_rd_data_end (app_rd_data_end),
• .app_rd_data_valid (c0_ddr3_app_rd_data_valid),
• .app_rdy (c0_ddr3_app_rdy),
• .app_wdf_rdy (c0_ddr3_app_wdf_rdy),
• .app_sr_req (app_sr_req),
• .app_ref_req (app_ref_req),
• .app_zq_req (app_zq_req),
• .app_sr_active (app_sr_active),
• .app_ref_ack (app_ref_ack),
• .app_zq_ack (app_zq_ack),
• .ui_clk (ui_clk),
• .ui_clk_sync_rst (ui_clk_sync_rst),
• .app_wdf_mask (c0_ddr3_app_wdf_mask),

// Madoko a System Clock

• .sys_clk_i (sys_clk_i),

// Reference Clock Ports

• .clk_ref_i (clk_ref_i),
• .sys_rst (sys_rst)
• );

Kukhazikika kwa jenereta yamagalimoto

mig7_perfsim_traffic_generator#
(
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.tCK (tCK),
.ADDR_WIDTH (APP_ADDR_WIDTH)
)

u_traffic_gen
(
.clk (ui_clk),
.rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.cmp_error (c0_data_compare_error),
.app_wdf_rdy (c0_ddr3_app_wdf_rdy),
.app_rd_data_valid (c0_ddr3_app_rd_data_valid),
.app_rd_data (c0_ddr3_app_rd_data),
.app_rdy (c0_ddr3_app_rdy),
.app_cmd (c0_ddr3_app_cmd),
.app_addr (c0_ddr3_app_addr ),
.app_en (c0_ddr3_app_en ),
.app_wdf_mask (c0_ddr3_app_wdf_mask),
.app_wdf_data (c0_ddr3_app_wdf_data),
.app_wdf_end (c0_ddr3_app_wdf_end ),
.app_wdf_wren (c0_ddr3_app_wdf_wren)
);

• 5. Sinthani APP_ADDR_WIDTH, APP_DATA_WIDTH, RANK_WIDTH ndi BANK_WIDTH molingana ndi zomwe mwasankha.
  Makhalidwe angapezeke kuchokera ku _mig.v file.
• Dzina lachikaso lachikaso mig_7series_0_mig limatha kusiyanasiyana kutengera dzina lachigawo chanu mukupanga IP, onetsetsani ngati mwasankha dzina lina ndikulisintha moyenera.
• Mukangopanga adilesi ya IP, tsegulani _mig.v file ndikuwunikanso kusiyana kulikonse kwa mayina a siginecha a LHS ndikuwongolera.
• app_sr_req, app_ref_req ndi app_zq_req ziyenera kukhazikitsidwa ku 0.
• Monga example_top.v ndi ndemanga komanso zatsopano files akuwonjezeredwa, mwina mudzawona "?" pambali pa
  mig_7series_0_mig.v file pansi kayeseleledwe magwero.
  Kupanga mapu olondola file, dinani kumanja mig_7series_0_mig.v, sankhani "Add Sources", Sakatulani ku
  /mig_7series_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl
  ndi kuwonjezera mig_7series_0_mig_sim.v file.
• Ngati mwawona "?" kwa maziko files, onjezani RTL yonse files mu clocking, controller, ip_top, phy ndi UI zikwatu.
• Zosintha za RTL zikachitika komanso zonse zofunika files amawonjezedwa ku Zoyeserera zanu, Utsogoleri uyenera kukhala wofanana ndi Chithunzi 5.
  The filezowonetsedwa zofiira ndizongowonjezeredwa kumene, ndi "?" akuyembekezeka pa ma module okhudzana ndi ECC popeza kasinthidwe ka kukumbukira kosankhidwa kamakhala ndi njira ya ECC yolephereka.

Zolimbikitsa File Kufotokozera
Njira iliyonse yolimbikitsira ndi 48 bits ndipo mawonekedwe ake akufotokozedwa mu Zithunzi 6-1 mpaka 6-4.

Kuyika Maadiresi (Adilesi [35:0])

Adilesiyo imasungidwa muzolimbikitsa monga pa Chithunzi 7-1 mpaka Chithunzi 7-6. Magawo onse adilesi akuyenera kulowetsedwa mumtundu wa hexadecimal. Magawo onse a ma adilesi ndi m'lifupi mwake omwe amagawidwa ndi anayi kuti alowe mumtundu wa hexadecimal. Benchi yoyeserera imangotumiza ma bits ofunikira a gawo la adilesi kwa Memory Controller.
Za example, mu kachitidwe ka banki eyiti, mabanki a banki okha [2:0] amatumizidwa kwa Memory Controller ndipo zotsalirazo zimanyalanyazidwa. Zowonjezera za gawo la adilesi zaperekedwa kuti mulowetse adilesi mumtundu wa hexadecimal.
Muyenera kutsimikizira mtengo womwe walowa ukufanana ndi m'lifupi mwa kasinthidwe koperekedwa.

• Adilesi ya Mzati (Mgawo[11:0]) - Adilesi ya Column muzolimbikitsa imaperekedwa mpaka ma bits 12, koma muyenera kuthana ndi izi kutengera gawo la m'lifupi mwake lomwe lakhazikitsidwa pamapangidwe anu.
• Adilesi ya Mzere (Mzere[15:0]) - Adilesi ya mzere muzolimbikitsa imaperekedwa mpaka ma bits 16, koma muyenera kuthana ndi izi potengera kuchuluka kwa mizere yomwe yakhazikitsidwa pamapangidwe anu.
• Adiresi Yakubanki (Banki[3:0]) - Adilesi ya banki muzolimbikitsa imaperekedwa mpaka ma bits anayi, koma muyenera kuthana ndi izi potengera kuchuluka kwa banki komwe kumapangidwira.
• Adilesi (Maudindo[3:0]) - Ma adilesi muzolimbikitsa amaperekedwa mpaka ma bits anayi, koma muyenera kuthana ndi izi potengera kuchuluka kwa kuchuluka kwazomwe mwapanga.
  Adilesiyi imapangidwa kutengera gawo lapamwamba la MEM_ADDR_ORDER ndikutumizidwa kwa ogwiritsa ntchito.

Lamulo Kubwereza (Lamulani Bwerezani [7:0])
Kuwerengera kubwereza kwa lamulo ndi kuchuluka kwa nthawi yomwe lamulo lomwe limabwerezedwa libwerezedwa pa User Interface. Adilesi ya kubwereza kulikonse imawonjezeredwa ndi 8. Chiwerengero chobwerezabwereza ndi 128.
Benchi yoyesera simayang'ana malire a mzati ndipo imazungulira ngati malire apamwamba afika panthawi yowonjezereka.
Malamulo 128 amadzaza tsamba. Pa adilesi ina iliyonse kupatula 0, chiwerengero chobwerezabwereza cha 128 chimatha kudutsa malire ndi kuzungulira mpaka kumayambiriro kwa adilesi.

Kugwiritsa Ntchito Mabasi
Kugwiritsiridwa ntchito kwa basi kumawerengedwera pa User Interface kutenga chiwerengero chonse cha Zowerenga ndi Kulemba ndikuganizira ndipo zotsatirazi zimagwiritsidwa ntchito:

• BL8 imatenga mawotchi anayi okumbukira
• end_of_stimulus ndi nthawi yomwe malamulo onse achitidwa.
• calib_done ndi nthawi yomwe kuwongolera kwachitika.

Example Patterns
Izi exampLes adatengera MEM_ADDR_ORDER yokhazikitsidwa ku BANK_ROW_COLUMN.

Single Read Pattern
00_0_2_000F_00A_1 - Chitsanzochi ndi chowerengedwa chimodzi kuchokera pa chigawo cha 10, mzere wa 15, ndi banki yachiwiri.Single Lembani Chitsanzo
00_0_1_0040_010_0 - Njira iyi ndi yolembera ku gawo la 32, mzere wa 128, ndi banki yoyamba.Lembani Pamodzi Ndi Kuwerengera Ku Adilesi Yomweyi
00_0_2_000F_00A_0 – Chitsanzochi ndi cholembera chimodzi ku chigawo cha 10, mzere wa 15, ndi banki yachiwiri.
00_0_2_000F_00A_1 – Chitsanzochi ndi chowerengedwa chimodzi kuchokera ku gawo la 10, mzere wa 15, ndi banki yachiwiri

Angapo Amalemba ndi Kuwerenga ndi Adilesi Yomweyi
0A_0_0_0010_000_0 – Izi zikufanana ndi 10 amalemba ndi adilesi yoyambira 0 mpaka 80 yomwe imawoneka pamndandanda.

0A_0_0_0010_000_1 – Izi zikufanana ndi 10 zowerengedwa ndi adilesi yoyambira 0 mpaka 80 yomwe ikuwoneka pamndandanda.

Manga Masamba Polemba
0A_0_2_000F_3F8_0 – Izi zimagwirizana ndi zolemba 10 zokhala ndi adilesi yomwe idakulungidwa poyambira tsamba pambuyo polemba.

Kutengera Performance Traffic Generator

Pakadali pano mwamaliza ndi MIG wakaleampndi mapangidwe kayeseleledwe. Izi zikutanthawuza kuti kukhazikitsidwa kwanu koyerekeza ndikokonzeka, mwapanga zosintha za RTL zofananira, mawonekedwe atsopano oyeserera ndi olondola ndipo mwamvetsetsa njira zolimbikitsira. Yambitsaninso kayesedwe kake ndi zolemba 16 ndikuwerenga mu perfsim_stimulus.txt.

Chitani zonse, dikirani mpaka chizindikiro cha init_calib_complete chitsimikizidwe, ndipo mudzatha kuwona chiwerengero chomwe mukufuna kulemba ndikuwerenga. The kayeseleledwe ndiye kusiya.

Mukauzidwa kuti musiye kuyerekezera, sankhani Ayi ndipo pitani pawindo lazolemba komwe mudzatha kuwona ziwerengero zantchito.

Ngati mungasankhe “siyani kayesedwe” ziwerengero zantchito zidzalembedwa ku a file dzina mig_band_width_output.txt yomwe ili mu sim_1/behave chikwatu.

Example directory njira: -
/mig_7series_0_example_perf_sim\mig_7series_0_example.sim/sim_1/behav

Mwina mungadabwe kuti n’chifukwa chiyani zili chonchotagkugwiritsa ntchito mabasi ndi ony 29. Yambitsaninso kuyerekezera ndi ma IP omwewo koma kungosintha kolimbikitsa file mpaka 256 amalemba ndipo 256 amawerenga

ff_0_0_0000_000_0
ff_0_0_0000_000_1

Tsopano muwona kuchuluka kwaketage monga 85, zomwe zikutanthauza kuti DDR3 imapereka kugwiritsa ntchito bwino mabasi pamalemba ambiri ndikuwerengera.

Njira Zowonjezera Zowonjezera Magwiridwe

Zinthu zomwe zimakhudza kugwira ntchito bwino zitha kugawidwa m'magawo awiri:

1. Kukumbukira Mwachindunji
2. Wowongolera Wachindunji

Chithunzi 9 imakupatsani kupitiliraview za mawu omwe ali okhudzana ndi kukumbukira.
Mosiyana ndi ma SRAMs ndi Block Memories DDR2 kapena DDR3 magwiridwe antchito sikuti amangokhala kuchuluka kwa data.

Zimatengera nthawi zambiri, kuphatikizapo:

• tRCD: Row Command Delay (kapena ras to cas delay).
• tCAS(CL): Adilesi yagawo lazambiri strobe latency.
• tRP: Kuchedwerako kochapira mizere.
• TRAS: Row Active Time (yambitsani kuti musinthe).
• tRC: Nthawi yozungulira mzere. tRC = tRAS + tRP
• TRAC: Kuchedwa kupeza mwachisawawa. tRAC = tRCD + tCAS
• tCWL: Cas kulemba latency.
• tZQ: Kusintha kwa nthawi yayitali kwa ZQ.
• tRFC: Nthawi Yotsitsimutsa Mzere
• tWTR: Lembani kuchedwa kwa kuwerenga. Kulemba komaliza kuchita kuti Werengani nthawi yolamula.
• tWR: Lembani Kubwezeretsa nthawi. Kulemba komaliza kutengera nthawi ya Precharge

Nthawi ya magawo onse omwe atchulidwawo amatengera mtundu wa kukumbukira komwe kumagwiritsidwa ntchito komanso gawo la liwiro la kukumbukira.
Zambiri pamatanthauzidwe ndi nthawi yake zitha kupezeka mu DDR2 DDR3 JEDEC kapena pachida chilichonse chokumbukira.

Kuchita bwino kumadalira momwe kukumbukira kumafikira. Ma adilesi osiyanasiyana amapereka zotsatira zosiyana.

Kuchuluka kwa kukumbukira nthawi

1. Nthawi yoyambitsa ndi Precharge nthawi mukusintha ku mabanki atsopano / mizere kapena kusintha mizere ndi banki yomweyo.- Kotero ngati muchepetse kusintha kwa mzere, izi zikhoza kuchotsa tRCD ndi tRP.
2. Tumizani kulemba mosalekeza kapena kuwerenga malamulo -Kusunga nthawi ya tCCD.
3. Chepetsani kulemba kuti muwerenge ndikuwerenga kuti mulembe kusintha kwa lamulo - Lembani nthawi yobwezeretsa kuti musinthe kuti muwerenge zofikira, nthawi yosinthira mabasi kuti musinthe kuchoka pakuwerenga kupita kulemba
4. Khazikitsani nthawi yoyenera yotsitsimutsa.
   • DDR3 SDRAM imafuna mizunguliro yotsitsimutsa nthawi ndi nthawi ya tREFI.
   • Malamulo opitilira 8 owonjezera a Refresh atha kuperekedwa pasadakhale ("kukokera mkati"). Izi sizichepetsa kuchuluka kwa zotsitsimutsa, koma nthawi yayitali pakati pa malamulo awiri ozungulira Otsitsimutsa ndi 9 × tREFI.

• Gwiritsani ntchito mabanki onse - Njira yoyenera yoyankhulirana ndi yabwino.
  • Mzere-Banki-Chigawo: Pakugulitsa komwe kukuchitika pamalo otsatizana adilesi, pachimake chimangotsegula mzere womwewo mu banki yotsatira ya chipangizo cha DRAM kuti mupitilize kugulitsako kukafika kumapeto kwa mzere womwe ulipo. Ndizoyenerana ndi mapulogalamu omwe amafunikira kuphulika kwa mapaketi akuluakulu a data kumadera otsatizana.
  • Bank-Row-Column: Mukadutsa malire a mzere, mzere wamakono udzatsekedwa ndipo mzere wina udzatsegulidwa mkati mwa banki yomweyo. MSB ndi adilesi yakubanki, yomwe ingagwiritsidwe ntchito kusinthana ndi mabanki osiyanasiyana. Ndioyenera kuchita zinthu zazifupi, zongochitika mwachisawawa ku chipika chimodzi cha kukumbukira kwakanthawi kenako kudumpha kupita ku chipika china (banki)
• Utali Wophulika
  • BL 8 imathandizidwa ndi DDR3 pa mndandanda wa 7. BC4 ili ndi mphamvu yochepa kwambiri yomwe ili yochepera 50%. Izi ndichifukwa choti nthawi yophedwa ya BC4 ndi yofanana ndi BL8. Deta imangobisika mkati mwa chigawocho.
  • Muzochitika zomwe simukufuna kulemba kuphulika kwathunthu, mwina chigoba cha data kapena kulemba-pambuyo-kuwerenga kungaganizidwe.
• Khazikitsani nthawi yoyenera ya ZQ (DDR3 Only)
  Wowongolera amatumiza malamulo onse a ZQ Short (ZQCS) ndi ZQ Long (ZQCL) Calibration.
  • Tsatirani DDR3 Jedec Standard
  • ZQ Calibration ikukambidwa mu gawo 5.5 la JEDEC Spec JESD79-3 DDR3 SDRAM Standard
  • ZQ Calibration imayang'anira On Die Termination (ODT) pafupipafupi kuti awerengere zamitundu yosiyanasiyana mu VT.
  • Logic ili mu bank_common.v/vhd
  • Parameter Tzqcs imatsimikizira mlingo womwe lamulo la ZQ Calibration limatumizidwa kukumbukira
  • t ndizotheka kuletsa kauntala ndikutumiza pamanja pogwiritsa ntchito app_zq_req, ndizofanana ndi kutumiza pamanja Kutsitsimutsa.
    Onani (Xilinx Answer 47924) kuti mudziwe zambiri.

Zowongolera Zowongolera

1. Kuwerenga Kwanthawi - Onani (Yankho la Xilinx 43344) zatsatanetsatane.
   • Osasintha nthawi yowerengera
   • Dumphani zowerengera nthawi ndi nthawi polemba ndikupereka chiwerengero cha zomwe mwaphonya musanawerenge zoona
2. Kukonzanso - Onani (Yankho la Xilinx 34392) zatsatanetsatane.
   Pamapangidwe a User ndi AXI Interface ndikwabwino kuti izi zitheke.
   • Reorder ndi lingaliro lomwe limayang'ana patsogolo malamulo angapo ndikusintha dongosolo la ogwiritsira ntchito kuti apange malamulo osakumbukira kukumbukira kuti asakhale ndi bandwidth yovomerezeka. Ntchitoyi ikugwirizananso ndi ndondomeko yeniyeni ya magalimoto.
   • Kutengera mawonekedwe a ma adilesi, kuyitanitsanso kumathandizira kulumpha kuyitanitsa ndi kuyambitsa malamulo ndikupanga tRCD ndi tRP kuti zisakhale m'lifupi mwa data band.
3. Yesani kuwonjezera kuchuluka kwa Makina a Banki.
   • Malingaliro ambiri a owongolera amakhala m'makina akubanki ndipo amafanana ndi mabanki a DRAM
   • Makina akubanki opatsidwa amayang'anira banki imodzi ya DRAM nthawi iliyonse.
   • Kugawa kwamakina akubanki ndikokhazikika kotero sikofunikira kukhala ndi makina aku banki ku banki iliyonse.
   • Makina a banki akhoza kukhazikitsidwa, koma ndi mgwirizano pakati pa dera ndi ntchito.
   • Chiwerengero chovomerezeka cha makina a banki ndi 2-8.
   • Mwachikhazikitso, Makina 4 a Banki amapangidwa kudzera mu magawo a RTL.
   • Kuti musinthe Makina a Banki, ganizirani za nBANK_MACHS = 8 zomwe zili mu memc_ui_top Ex.ample kwa 8 Bank Machines – nBANK_MACHS = 8

Tsopano mukudziwa zinthu zomwe zimakhudza magwiridwe antchito.
Ganizirani za pulogalamu yam'mwamba yomwe imakupatsani ma data 512 pa paketi iliyonse ndipo muyenera kuwasungira kumalo osiyanasiyana okumbukira. Popeza 512 ma data byte ndi ofanana ndi 64 DDR3 kuphulika kwa data, yambitsaninso zakale.ample kupanga ndi stimulus file okhala ndi zolemba 512, 512 amawerenga ndikusintha mizere pa 64 iliyonse yolemba kapena kuwerenga:

• 3f_0_0_0000_000_0
• 3f_0_0_0001_000_0
• 3f_0_0_0002_000_0
• 3f_0_0_0003_000_0
• 3f_0_0_0004_000_0
• 3f_0_0_0005_000_0
• 3f_0_0_0006_000_0
• 3f_0_0_0007_000_0
• 3f_0_0_0000_000_1
• 3f_0_0_0001_000_1
• 3f_0_0_0002_000_1
• 3f_0_0_0003_000_1
• 3f_0_0_0004_000_1
• 3f_0_0_0005_000_1
• 3f_0_0_0006_000_1
• 3f_0_0_0007_000_1

Pamapeto pa kuyerekezera muwona kuti kugwiritsa ntchito mabasi kuli pa 77 peresenti.

Chithunzi 11: Ziwerengero za Magwiridwe a 512 amalemba ndi 512 amawerenga - Kusintha kwa mzere kwa 64 kulemba kapena kuwerenga. 

Tsopano mutha kugwiritsa ntchito zomwe mwaphunzira m'gawo lapitalo kuti muwongolere bwino. Ndi a view kugwiritsa ntchito mabanki onse m'malo mosintha mzere, sinthani ma adilesi kuti musinthe banki monga momwe zilili pansipa.
Izi zikufanana ndi kukhazikitsa ROW_BANK_Column muzosunga zokumbukira adilesi mu MIG GUI.

• 3f_0_0_0000_000_0
• 3f_0_1_0000_000_0
• 3f_0_2_0000_000_0
• 3f_0_3_0000_000_0
• 3f_0_4_0000_000_0
• 3f_0_5_0000_000_0
• 3f_0_6_0000_000_0
• 3f_0_7_0000_000_0
• 3f_0_0_0000_000_1
• 3f_0_1_0000_000_1
• 3f_0_2_0000_000_1
• 3f_0_3_0000_000_1
• 3f_0_4_0000_000_1
• 3f_0_5_0000_000_1
• 3f_0_6_0000_000_1
• 3f_0_7_0000_000_1

Pamapeto pa kuyerekezera muwona kuti 77 Peresenti Yogwiritsa Ntchito Mabasi tsopano ili 87!

Ngati mukufunikirabe kuchita bwino kwambiri, mutha kupita pamapaketi akuluakulu a 1024 kapena 2048 byte, kapena lingalirani zotsitsimutsa pamanja.

Zindikirani: Xilinx sichilimbikitsa kutsitsimula kwa owongolera chifukwa sitikutsimikiza ngati mudzatha kukumana ndi nthawi yotsitsimutsa ya Jedec yomwe imakhudza kudalirika kwa data.
Kuchokera kumbali yowongolera mutha kusintha nBANk_MACH ndikuwona kusintha kwa magwiridwe antchito.
Komabe, izi zitha kukhudza nthawi yanu yopangira, chonde onani (Yankho la Xilinx 36505) kuti mudziwe zambiri pa nBANk_MACH

Tsegulani core_name_mig_sim.v file ndikusintha magawo nBANK_MACHS kuchokera ku 4 mpaka 8 ndikuyambiranso kuyerekezera. Kuti mtengo wa parameter uyambe kugwira ntchito mu hardware, muyenera kusintha core_name_mig.v file.
Ndidagwiritsa ntchito njira yomweyi pomwe tidapeza 87% mabasi (chithunzi -12).
Ndi nBANK_MACHS yokhazikitsidwa ku 8, kugwira ntchito bwino tsopano ndi 90%.

Komanso dziwani kuti owongolera ½ ndi ¼ amasokoneza magwiridwe antchito chifukwa chakuchedwa kwawo.
Za example, popeza titha kutumiza malamulo pamayendedwe aliwonse a 4 CK nthawi zina pamakhala zowonjezera potsatira zochepa za nthawi ya DRAM, zomwe zingachepetse magwiridwe antchito kuchokera kumalingaliro.
Yesani zowongolera zosiyanasiyana kuti mupeze zomwe zikugwirizana ndi zomwe mukufuna.

Maumboni

1. Zynq-7000 AP SoC ndi 7 Series FPGAs MIS v2.3 [UG586]
2. Xilinx MIG Solution Center http://www.xilinx.com/support/answers/34243.html

Mbiri Yobwereza
13/03/2015 - Kutulutsidwa koyamba

Tsitsani PDF: Xilinx DDR2 MIG 7 Performance Estimation Guide

Maumboni

• Buku Logwiritsa Ntchito