Cov ntsiab lus zais
1 Xilinx DDR2 MIG 7 Performance Estimation Guide
2 Taw qhia
3 Kev Siv Tau Bandwidth
4 MIG Design Generation
5 Kev Ua Haujlwm Simulation RTL hloov kho
6 Simulating lub Performance Traffic Generator
7 Txoj hauv kev los txhim kho kev ua tau zoo
8 Memory timeing overheads
9 Controller Overheads
10 Cov ntaub ntawv
11 Cov ntaub ntawv
12 Related Posts

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Xilinx DDR2 MIG 7 Performance Estimation Guide

Xilinx_DDR2_MIG_7_Performance-Estimation-product

Lus Cim Tseem Ceeb: No downloadable PDF ntawm Cov Lus Teb Cov Ntaub Ntawv yog muab los txhim kho nws cov kev siv tau thiab nyeem tau. Nws yog ib qho tseem ceeb kom nco ntsoov tias Cov Lus Teb Cov Ntaub Ntawv yog Web-raws li cov ntsiab lus uas nquag hloov kho raws li cov ntaub ntawv tshiab muaj. Nco ntsoov mus xyuas Xilinx Technical Support Website thiab review (Xilinx Teb 63234) rau qhov tseeb version ntawm Cov Lus Teb no.

Taw qhia

Vim tias txoj kev DDR2 thiab DDR3 nco tau raug tsim kho thiab MIG 7 series tswj tau tsim, kev ua haujlwm tsis ncaj nraim.
Nws yuav tsum muaj kev nkag siab txog ntau yam Jedec Timing tsis thiab tswj Architecture, thiab koj yuav tsum tau khiav simulations kom tau txais kev kwv yees.
Lub hauv paus ntsiab lus dav dav rau kev txiav txim siab kev ua tau zoo yog tib yam tab sis cov ntaub ntawv no muab txoj hauv kev yooj yim kom tau txais txiaj ntsig siv MIG example tsim nrog kev pab ntawm lub rooj ntev zaum thiab stimulus files txuas ntawm no.

Kev Siv Tau Bandwidth

Lub tsheb npav DRAM tau ua tiav nyob ze-peak bandwidth tsuas yog thaum tawg ntawm kev nyeem thiab sau ntawv thiab nws cov nyiaj siv ua haujlwm txo qis cov ntaub ntawv zoo.
Ob peb examples of overhead yog:

  • precharge lub sij hawm nkag mus rau kab hauv tib lub txhab nyiaj (Access chaw nyob tsis nyob rau tib kab-nplooj ntaus)
  • sau rov qab lub sij hawm hloov los ntawm kev sau ntawv mus nyeem ntawv
  • lub tsheb npav tig lub sijhawm hloov los ntawm kev nyeem ntawv mus sau ntawv

Xilinx DDR2 MIG 7 Performance Estimation-fig-28
Siv tau Bandwidth = Peak Bandwidth * Efficiency 

MIG Design Generation

Xa mus rau UG586 Tshooj 1 rau cov lus qhia ua ntu zus ntawm MIG IP thiab example tsim tiam.
Ua ntej khiav MIG 7 Series kev ua tau zoo simulation, ua cov hauv qab no kom paub tseeb tias koj qhov chaw simulation zoo. Qhib MIG example tsim thiab qhia cov tsev qiv ntawv tsim nyog, khiav qhov simulation, thiab xyuas kom meej tias koj tuaj yeem pom cov lus "kuaj dhau" hauv cov ntawv sau tseg.
Txhawm rau ua kom pom qhov ntws Kuv tau tsim MIG IP rau xc7vx690tffg1761-2 thiab hu rau tus example design.
Ob yam uas yuav tsum tau muab sau tseg yog nco chaw nyob me ntsis thiab nco chaw nyob xaiv xaiv.
Rau example, Kuv tau xaiv MT41J128M8XX-125 nyob rau hauv lub cim xeeb ib feem poob kev xaiv.Xilinx DDR2 MIG-7-Performance-Estimation-fig-1

Rau qhov xaiv nco ib feem ntawm daim duab-1, kab = 14, kem = 10 thiab bank = 3, yog li app_addr_width = kab + kem + bank + qib = 28 Xilinx DDR2 MIG 7 Performance Estimation-fig-2

Koj tuaj yeem xaiv BANK_ROW_COLUMN lossis ROW BANK Kem.
Kuv tau tawm ntawm ROW BANK Kem uas yog qhov chaw nyob pib ua haujlwm.

Example tsim simulation nrog synthesizable xeem lub rooj ntev zaum

Nyob rau hauv Simulation nqis, xaiv QuestaSim/ModelSim Simulator thiab xauj mus rau cov tsev qiv ntawv muab tso ua ke 'qhov chaw.
Yog xav paub meej txog kev taw qhia rau cov cuab yeej thib peb teeb tsa txoj hauv kev, xaiv lub hom phiaj simulator, thiab muab tso ua ke thiab kos duab cov tsev qiv ntawv, koj tuaj yeem xa mus rau (UG900) Vivado Design Suite User Guide Logic SimulationXilinx DDR2 MIG 7 Performance Estimation-fig-3

Khiav qhov simulation los ntawm GUI (Nias lub Khiav Simulation Tab hauv qhov project manager) thiab xyuas kom tseeb tias koj pom cov lus "kuaj dhau" hauv cov ntawv sau tseg.

Kev Ua Haujlwm Simulation RTL hloov kho

  1. Txoj cai-nias ntawm qhov chaw tab, xaiv "ntxiv lossis tsim cov peev txheej simulation", thiab xauj rau mig7_perfsim_traffic_generator.sv file thiab nyem tas mus ntxiv.
  2. Txoj cai-nias ntawm qhov chaw tab, xaiv "ntxiv lossis tsim cov peev txheej simulation", xauj rau perfsim_stimulus.txt, thiab nyem tas mus ntxiv.
  3. Comment out tus example_top instantiation hauv sim_tb_top.v file.
  4. Ntxiv cov kab hauv qab RTL rau sim_tb_top, v
  • localparam APP_ADDR_WIDTH = 28;
  • localparam APP_DATA_WIDTH = 64;
  • localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
  • localparam MEM_ADDR_ORDER = “BANK_ROW_COLUMN”;
  • localparam BANK_WIDTH = 3;
  • localparam RANK_WIDTH = 1;
  • xaim [APP_ADDR_WIDTH-1:0] c0_ddr3_app_addr;
  • xaim [2:0] c0_ddr3_app_cmd;
  • xaim c0_ddr3_app_en;
  • xaim [APP_DATA_WIDTH-1:0] c0_ddr3_app_wdf_data;
  • xaim c0_ddr3_app_wdf_end;
  • xaim [APP_MASK_WIDTH-1:0] c0_ddr3_app_wdf_mask;
  • xaim c0_ddr3_app_wdf_wren;
  • xaim [APP_DATA_WIDTH-1:0] c0_ddr3_app_rd_data;
  • xaim c0_ddr3_app_rd_data_end;
  • xaim c0_ddr3_app_rd_data_valid;
  • xaim c0_ddr3_app_rdy;
  • xaim c0_ddr3_app_wdf_rdy;
  • xaim c0_data_compare_error;
  • xov ui_clk;
  • xov ui_clk_sync_rst;
  • xaim app_sr_req = 0;
  • xaim app_ref_req = 0;
  • xaim app_zq_req = 0;
  • xaim c0_app_wdf_mask = 0;

FPGA Memory Controller instantiation

mig_7series_0_mig u_mig_7series_0_mig (
// Nco interface ports

  • .ddr3_addr (ddr3_addr_fpga),
  • .ddr3_ba (ddr3_ba_fpga),
  • .ddr3_cas_n (ddr3_cas_n_fpga),
  • .ddr3_ck_n (ddr3_ck_n_fpga),
  • .ddr3_ck_p (ddr3_ck_p_fpga),
  • .ddr3_cke (ddr3_cke_fpga),
  • .ddr3_ras_n (ddr3_ras_n_fpga),
  • .ddr3_reset_n (ddr3_reset_n),
  • .ddr3_we_n (ddr3_we_n_fpga),
  • .ddr3_dq (ddr3_dq_fpga),
  • .ddr3_dqs_n (ddr3_dqs_n_fpga),
  • .ddr3_dqs_p (ddr3_dqs_p_fpga),
  • .init_calib_complete (init_calib_complete),
  • .ddr3_cs_n (ddr3_cs_n_fpga),
  • .ddr3_dm (ddr3_dm_fpga),
  • .ddr3_odt (ddr3_odt_fpga),

// Daim ntawv thov interface ports

  • .app_addr (c0_ddr3_app_addr),
  • .app_cmd (c0_ddr3_app_cmd),
  • .app_en (c0_ddr3_app_en),
  • .app_wdf_data (c0_ddr3_app_wdf_data),
  • .app_wdf_end (c0_ddr3_app_wdf_end),
  • .app_wdf_wren (c0_ddr3_app_wdf_wren),
  • .app_rd_data (c0_ddr3_app_rd_data),
  • .app_rd_data_end (app_rd_data_end),
  • .app_rd_data_valid (c0_ddr3_app_rd_data_valid),
  • .app_rdy (c0_ddr3_app_rdy),
  • .app_wdf_rdy (c0_ddr3_app_wdf_rdy),
  • .app_sr_req (app_sr_req),
  • .app_ref_req (app_ref_req),
  • .app_zq_req (app_zq_req),
  • .app_sr_active (app_sr_active),
  • .app_ref_ack (app_ref_ack),
  • .app_zq_ack (app_zq_ack),
  • .ui_clk (ui_clk),
  • .ui_clk_sync_rst (ui_clk_sync_rst),
  • .app_wdf_mask (c0_ddr3_app_wdf_mask),

// System Clock Ports

  • .sys_clk_i (sys_clk_i),

// Siv Clock Ports

  • .clk_ref_i (clk_ref_i),
  • .sys_rst (sys_rst)
  • );

Performance tsheb generator instantiation

mig7_perfsim_traffic_generator#
(
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.tCK (tCK),
.ADDR_WIDTH (APP_ADDR_WIDTH)
)

ua_traffic_gen
(
.clk (ui_clk ),
.rst (ui_clk_sync_rst ),
.init_calib_complete (init_calib_complete),
.cmp_error (c0_data_compare_error),
.app_wdf_rdy (c0_ddr3_app_wdf_rdy ),
.app_rd_data_valid (c0_ddr3_app_rd_data_valid),
.app_rd_data (c0_ddr3_app_rd_data ),
.app_rdy (c0_ddr3_app_rdy),
.app_cmd (c0_ddr3_app_cmd ),
.app_addr (c0_ddr3_app_addr ),
.app_en (c0_ddr3_app_en ),
.app_wdf_mask (c0_ddr3_app_wdf_mask),
.app_wdf_data (c0_ddr3_app_wdf_data),
.app_wdf_end (c0_ddr3_app_wdf_end ),
.app_wdf_wren (c0_ddr3_app_wdf_wren)
);

  • 5. Hloov kho APP_ADDR_WIDTH, APP_DATA_WIDTH, RANK_WIDTH thiab BANK_WIDTH raws li koj lub cim xeeb xaiv.
    Cov nqi tuaj yeem tau txais los ntawm _mig.v file.
  • Lub npe daj tseem ceeb instantiation lub npe mig_7series_0_mig tuaj yeem sib txawv raws li koj lub npe tivthaiv thaum lub sijhawm tsim IP, txheeb xyuas yog tias koj tau xaiv lwm lub npe thiab hloov nws raws li.Xilinx DDR2 MIG 7 Performance Estimation-fig-4
  • Thaum tus IP yog generated qhib lub _mig.v file thiab txheeb xyuas qhov kev hloov pauv hauv LHS cov npe teeb liab thiab kho lawv.
  • app_sr_req, app_ref_req thiab app_zq_req yuav tsum tau pib rau 0.
  • Raws li example_top.v yog commented tawm thiab tshiab files ntxiv, tej zaum koj yuav pom "?" ib sab ntawm
    mig_7series_0_mig.v file nyob rau hauv qhov chaw simulation.
    Daim duab qhia qhov tseeb file, txoj nyem rau mig_7series_0_mig.v, xaiv "Add Sources", Xa mus rau
    /mig_7series_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl
    thiab ntxiv mig_7series_0_mig_sim.v file.
  • Yog koj pom "?" rau lub hauv paus files, ntxiv tag nrho RTL files hauv clocking, maub los, ip_top, phy thiab UI folders.
  • Thaum RTL hloov pauv tiav thiab tag nrho cov yuav tsum tau ua files tau ntxiv rau koj qhov Simulation Sources, Hierarchy yuav tsum zoo ib yam li daim duab 5.
    Cov files highlighted nyob rau hauv liab yog ntxiv tshiab, thiab "?" yuav tsum nyob rau ntawm ECC cov modules uas muaj feem xyuam nrog kev xaiv lub cim xeeb teeb tsa muaj qhov kev xaiv ECC tsis ua haujlwm.Xilinx DDR2 MIG 7 Performance Estimation-fig-5

Kev txhawb siab File Kev piav qhia
Txhua tus qauv stimulus yog 48 khoom thiab cov hom tau piav qhia hauv Daim duab 6-1 txog 6-4.Xilinx DDR2 MIG 7 Performance Estimation-fig-6

Chaw nyob Encoding (Address [35:0])

Qhov chaw nyob yog encoded nyob rau hauv lub stimulus raws li ib daim duab 7-1 rau daim duab 7-6. Txhua qhov chaw nyob yuav tsum tau nkag mus rau hauv hom hexadecimal. Txhua qhov chaw nyob yog qhov dav uas faib los ntawm plaub kom nkag mus rau hauv hom hexadecimal. Lub rooj zaum xeem tsuas yog xa cov khoom yuav tsum tau ntawm qhov chaw nyob mus rau Memory Controller.
Rau example, nyob rau hauv yim lub txhab nyiaj configuration, tsuas yog bank Bits [2:0] raug xa mus rau Memory Controller thiab cov khoom seem tsis quav ntsej. Cov khoom ntxiv rau qhov chaw nyob yog muab rau koj nkag mus rau qhov chaw nyob hauv hom hexadecimal.
Koj yuav tsum paub meej tias tus nqi nkag mus rau qhov dav ntawm qhov muab teeb tsa.Xilinx DDR2 MIG 7 Performance Estimation-fig-7

  • Kem Chaw Nyob (Kem[11:0]) – Kem Chaw Nyob hauv qhov kev txhawb nqa yog muab rau qhov siab tshaj plaws ntawm 12 cov khoom, tab sis koj yuav tsum tau hais txog qhov no raws li cov kab dav dav hauv koj tus qauv tsim.
  • Kab Chaw Nyob (Kaw[15:0]) – Kab chaw nyob hauv qhov kev txhawb nqa yog muab rau qhov siab tshaj plaws ntawm 16 cov khoom, tab sis koj yuav tsum tau hais txog qhov no raws li kab dav parameter teeb tsa hauv koj tus qauv tsim.
  • Lub txhab nyiaj chaw nyob (Bank[3:0]) – Lub txhab nyiaj chaw nyob hauv qhov kev txhawb nqa yog muab rau qhov siab tshaj plaws ntawm plaub qhov, tab sis koj yuav tsum tau hais txog qhov no raws li lub txhab nyiaj dav qhov ntsuas tau teev tseg hauv koj tus qauv tsim.
  • Rank Chaw Nyob (Rank[3:0]) – Qhov chaw nyob qib nyob rau hauv qhov kev txhawb nqa yog muab rau qhov siab tshaj plaws ntawm plaub yam khoom, tab sis koj yuav tsum tau hais txog qhov no raws li qhov ntsuas qhov dav hauv koj tus qauv tsim.
    Qhov chaw nyob yog sib sau ua ke raws li theem saum toj kawg nkaus MEM_ADDR_ORDER parameter thiab xa mus rau tus neeg siv interface

Hais kom rov hais dua (Command Repeat [7:0])
Cov lus txib rov suav yog tus naj npawb ntawm lub sijhawm cov lus txib rov ua dua ntawm Tus Neeg Siv Khoom. Qhov chaw nyob rau txhua qhov kev rov ua dua yog nce los ntawm 8. Qhov siab tshaj qhov rov ua dua yog 128.
Lub rooj ntev zaum sim tsis kuaj rau kab ciam teb thiab nws qhwv ib ncig yog tias qhov siab kawg kab txwv tau mus txog thaum lub sijhawm nce ntxiv.
128 Cov Lus txib sau rau nplooj ntawv. Rau txhua qhov chaw nyob uas tsis yog 0, qhov rov ua dua ntawm 128 xaus mus hla kab ciam teb thiab qhwv ib ncig mus rau qhov pib ntawm qhov chaw nyob.

Kev siv tsheb npav
Kev siv tsheb thauj mus los yog xam ntawm Tus Neeg Siv Khoom Siv Khoom Siv tag nrho ntawm Kev Nyeem thiab Sau rau hauv kev txiav txim siab thiab siv cov kab zauv hauv qab no:

Xilinx DDR2 MIG 7 Performance Estimation-fig-8

  • BL8 siv plaub lub cim xeeb moos
  • end_of_stimulus yog lub sijhawm thaum tag nrho cov lus txib ua tiav.
  • calib_done yog lub sijhawm thaum lub calibration tiav.

Example Patterns
Cov examples yog raws li MEM_ADDR_ORDER teem rau BANK_ROW_COLUMN.

Ib Leeg Nyeem Ntawv
00_0_2_000F_00A_1 – Cov qauv no yog ib qho nyeem los ntawm 10th kem, 15th kab, thiab lub txhab nyiaj thib ob.Xilinx DDR2 MIG 7 Performance Estimation-fig-9Ib Leeg Sau Tus Qauv
00_0_1_0040_010_0 – Cov qauv no yog ib daim ntawv sau rau sab 32nd, 128th kab, thiab thawj lub txhab nyiaj.Xilinx DDR2 MIG 7 Performance Estimation-fig-10Ib Leeg Sau thiab Nyeem rau tib qhov chaw nyob
00_0_2_000F_00A_0 – Cov qauv no yog ib qho sau rau 10th kab, 15th kab, thiab lub txhab nyiaj thib ob.
00_0_2_000F_00A_1 – Cov qauv no yog ib qho nyeem los ntawm 10th kem, 15th kab, thiab lub txhab nyiaj thib obXilinx DDR2 MIG 7 Performance Estimation-fig-11

Ntau Sau thiab nyeem nrog tib qhov chaw nyob
0A_0_0_0010_000_0 – Qhov no sib raug rau 10 sau nrog qhov chaw nyob pib ntawm 0 txog 80 uas tuaj yeem pom hauv kab.Xilinx DDR2 MIG 7 Performance Estimation-fig-12

0A_0_0_0010_000_1 – Qhov no sib raug rau 10 nyeem nrog qhov chaw nyob pib ntawm 0 txog 80 uas tuaj yeem pom hauv kab.Xilinx DDR2 MIG 7 Performance Estimation-fig-13

Page Wrap Thaum Sau
0A_0_2_000F_3F8_0 – Qhov no sib raug rau 10 sau nrog kab ntawv chaw nyob qhwv rau qhov pib ntawm nplooj ntawv tom qab ib qho sau.Xilinx DDR2 MIG 7 Performance Estimation-fig-14

Simulating lub Performance Traffic Generator

Ntawm no koj tau ua tiav nrog MIG example design simulation. Qhov no txhais tau hais tias koj simulation teeb tsa tau npaj txhij, koj tau ua tiav kev ua haujlwm simulation RTL hloov kho, qhov simulation tshiab hierarchy yog qhov tseeb thiab koj tau nkag siab cov qauv kev txhawb nqa. Khiav qhov simulation ib zaug ntxiv nrog 16 sau thiab nyeem hauv perfsim_stimulus.txt.Xilinx DDR2 MIG 7 Performance Estimation-fig-15

Ua khiav-tag nrho, tos kom txog thaum lub teeb liab init_calib_complete tau lees paub, thiab koj yuav tuaj yeem pom cov ntawv thov thiab nyeem. Tom qab ntawd lub simulation yuav nres. Xilinx DDR2 MIG 7 Performance Estimation-fig-16

Thaum koj raug kev tshoov siab kom txiav tawm simulation, xaiv Tsis yog thiab mus rau lub qhov rais transcript uas koj yuav tuaj yeem pom cov kev txheeb xyuas kev ua tau zoo. Xilinx DDR2 MIG 7 Performance Estimation-fig-17

Yog koj xaiv "Tawm simulation" kev ua haujlwm txheeb cais yuav raug sau rau a file npe mig_band_width_output.txt nyob rau hauv lub sim_1/behave nplaub tshev.

Example directory path:-
/mig_7series_0_example_perf_sim\mig_7series_0_example.sim/sim_1/behavXilinx DDR2 MIG 7 Performance Estimation-fig-18

Tej zaum koj yuav xav tias yog vim li cas tus percentage kev siv tsheb npav yog nyob ntawm 29. Rov ua dua qhov simulation nrog tib qhov chaw IP tab sis tsuas yog hloov qhov kev txhawb nqa. file rau 256 sau thiab 256 nyeem

ff_0_0_0000_000_0
ff_0_0_0000_000_1

Tam sim no koj yuav pom tus percentage raws li 85, uas txhais tau hais tias DDR3 muaj kev siv tsheb npav zoo dua rau qhov ntev ntawm kev sau thiab nyeem ntawv tawg. Xilinx DDR2 MIG 7 Performance Estimation-fig-19

Txoj hauv kev los txhim kho kev ua tau zoo

Cov yam ntxwv uas cuam tshuam rau kev ua tau zoo tuaj yeem muab faib ua ob ntu:

  1. Nco tshwj xeeb
  2. Tswj tshwj xeebXilinx DDR2 MIG 7 Performance Estimation-fig-20

Daim duab 9 muab rau kojview ntawm cov ntsiab lus uas yog kev nco tshwj xeeb.
Tsis zoo li SRAMs thiab Block Memories DDR2 lossis DDR3 kev ua tau zoo tsis yog cov ntaub ntawv siab tshaj plaws xwb.

Nws nyob ntawm ntau lub sijhawm, suav nrog:

  • tRCD: Kab Command Delay (los yog ras mus rau cas ncua).
  • CAS (CL): Kem chaw nyob strobe latency.
  • tRP: Kab precharge ncua.
  • TRAS: Kab Lub Sijhawm Ua Haujlwm (nrawm rau kev hloov pauv).
  • tRC: Kab lub sij hawm. tRC = TRAS + tRP
  • tRAC: Radom nkag ncua sijhawm. tRAC = tRCD + tCAS
  • tCWL: Cas sau latency.
  • tZQ: ZQ calibration lub sij hawm.
  • tRFC: Row Refresh Cycle Sijhawm
  • tWTR: Sau kom Nyeem ncua. Kev sau ntawv kawg rau Read command time.
  • tWR: Sau sijhawm rov qab. Kev sau ntawv kawg rau lub sijhawm them ua ntej

Lub sij hawm ntawm tag nrho cov kev teev tseg yog nyob ntawm hom kev nco siv thiab nco ib feem ceev qib.
Cov ntsiab lus ntxiv ntawm cov lus txhais thiab lub sijhawm tshwj xeeb tuaj yeem pom hauv DDR2 DDR3 JEDEC lossis hauv ib daim ntawv teev cov khoom siv nco.

Kev ua tau zoo feem ntau yog nyob ntawm seb lub cim xeeb nkag mus li cas. Cov qauv chaw nyob sib txawv muab cov txiaj ntsig sib txawv.

Memory timeing overheads

  1. Lub sij hawm qhib thiab them ua ntej thaum hloov mus rau cov tsev txhab nyiaj tshiab / kab lossis hloov kab nrog hauv tib lub txhab nyiaj.- Yog li yog tias koj txo cov kab hloov pauv, qhov no tuaj yeem tshem tawm tRCD thiab tRP.
  2. Xa ntawv txuas ntxiv lossis nyeem cov lus txib -Tswj lub sijhawm tCCD.
  3. Txo kev sau ntawv kom nyeem thiab nyeem kom sau cov lus txib hloov pauv - Sau lub sijhawm rov qab los hloov mus nyeem cov ntawv nkag, lub sijhawm caij tsheb npav hloov pauv los ntawm kev nyeem los sau
  4. Teem lub ncua ncua sij hawm kom zoo.
    • DDR3 SDRAM xav kom rov ua dua tshiab ntawm qhov nruab nrab lub sijhawm ntawm tREFI.
    • Qhov siab tshaj plaws ntawm 8 ntxiv Refresh commands tuaj yeem muab tso ua ntej ("rub"). Qhov no tsis txo tus naj npawb ntawm refreshes, tab sis qhov siab tshaj plaws ncua sij hawm ntawm ob puag ncig Refresh commands yog txwv rau 9 × tREFIXilinx DDR2 MIG 7 Performance Estimation-fig-21
  • Siv tag nrho cov tsev txhab nyiaj - Ib qho kev hais lus tsim nyog yog qhov zoo dua.
    • Kab-Bank-Kem: Rau qhov kev sib pauv tshwm sim dhau qhov chaw nyob sib txuas, cov tub ntxhais yuav qhib tib kab hauv lub txhab nyiaj tom ntej ntawm DRAM ntaus ntawv mus txuas ntxiv qhov kev hloov pauv thaum kawg ntawm kab uas twb muaj lawm. Nws yog qhov zoo rau cov ntawv thov uas yuav tsum tau tawg ntawm cov ntaub ntawv loj rau cov chaw nyob sib txuas.
    • Bank-Row-Kem: Thaum hla ib tus ciam teb, kab tam sim no yuav raug kaw thiab lwm kab yuav qhib rau hauv tib lub txhab nyiaj. MSB yog qhov chaw nyob hauv txhab nyiaj, uas tuaj yeem siv los hloov los ntawm ntau lub tsev txhab nyiaj. Nws yog tsim rau luv luv, ntau random muas rau ib lub cim xeeb rau ib lub sij hawm ntawm lub sij hawm thiab ces dhia mus rau lwm lub block (bank)
  • Npog Length
    • BL 8 tau txais kev txhawb nqa rau DDR3 ntawm 7 series. BC4 muaj qhov ua tau zoo heev uas tsawg dua 50%. Qhov no yog vim lub sijhawm ua tiav ntawm BC4 yog tib yam li BL8. Cov ntaub ntawv tsuas yog npog hauv cov khoom.
    • Nyob rau hauv rooj plaub uas koj tsis xav sau tag nrho tawg, cov ntaub ntawv npog lossis sau-tom qab-nyeem tuaj yeem txiav txim siab.
  • Teem lub sijhawm ZQ kom zoo (DDR3 nkaus xwb)
    Tus maub los xa ob ZQ Short (ZQCS) thiab ZQ Ntev (ZQCL) Calibration commands.
    • Ua raws li DDR3 Jedec Standard
    • ZQ Calibration tau tham hauv ntu 5.5 ntawm JEDEC Spec JESD79-3 DDR3 SDRAM Standard
    • ZQ Calibration calibrates On Die Termination (ODT) ntawm ib ntus kom suav rau kev hloov pauv thoob VT
    • Logic muaj nyob rau hauv bank_common.v/vhd
    • Parameter Tzqcs txiav txim siab tus nqi ntawm ZQ Calibration hais kom xa mus rau lub cim xeeb
    • t yog ua tau los lov tes taw lub txee thiab manually xa siv app_zq_req, nws zoo ib yam li manually xa ib tug Refresh.
      Xa mus rau (Xilinx Teb 47924) kom paub meej.Xilinx DDR2 MIG 7 Performance Estimation-fig-22

Controller Overheads

  1. Lub Sijhawm Nyeem Ntawv - Xa mus rau (Xilinx Teb 43344) kom paub meej.
    • Tsis txhob hloov lub sijhawm nyeem ntawv
    • Hla cov ntawv nyeem ib ntus thaum sau ntawv thiab muab cov lej nyeem tsis tau ua ntej nyeem qhov tseeb
  2. Reordering - Xa mus (Xilinx Teb 34392) kom paub meej.
    Rau cov neeg siv thiab AXI Interface tsim nws yog qhov zoo dua kom muaj qhov no.
    • Reorder yog lub logic uas saib ua ntej ntau cov lus txib thiab hloov cov neeg siv cov lus txib kom ua cov lus txib tsis nco tsis nyob hauv bandwidth siv tau. Qhov kev ua tau zoo kuj muaj feem xyuam rau cov qauv tsheb tiag tiag.
    • Raws li tus qauv chaw nyob, reorder pab hla precharge thiab qhib cov lus txib thiab ua rau tRCD thiab tRP tsis nyob hauv cov ntaub ntawv band dav.Xilinx DDR2 MIG 7 Performance Estimation-fig-23
  3. Sim ua kom tus lej ntawm Lub Txhab Nyiaj Txiag.
    • Feem ntau ntawm tus maub los lub logic nyob hauv lub tshuab txhab nyiaj thiab lawv sib raug rau DRAM cov tsev txhab nyiaj
    • Lub tshuab txhab nyiaj muab tswj hwm ib lub txhab nyiaj DRAM ib lub sijhawm twg los tau.
    • Lub txhab nyiaj lub tshuab ua haujlwm yog qhov muaj zog yog li nws tsis tas yuav muaj lub tshuab txhab nyiaj rau txhua lub txhab nyiaj lub cev.
    • Lub tshuab txhab nyiaj tuaj yeem teeb tsa, tab sis nws yog kev sib pauv ntawm thaj chaw thiab kev ua haujlwm.
    • Tus naj npawb tso cai ntawm lub txhab nyiaj tshuab yog li ntawm 2-8.
    • Los ntawm lub neej ntawd, 4 Lub Tuam Txhab Nyiaj Txiag tau teeb tsa los ntawm RTL tsis.
    • Txhawm rau hloov lub tshuab txhab nyiaj, xav txog qhov ntsuas nBANK_MACHS = 8 muaj nyob rau hauv memc_ui_top Example for 8 Bank Machines – nBANK_MACHS = 8

Tam sim no koj paub txog yam uas cuam tshuam rau kev ua haujlwm.
Xav txog ib daim ntawv thov nce toj uas muab rau koj 512 cov ntaub ntawv bytes ib pob ntawv thiab koj yuav tsum khaws lawv mus rau qhov chaw nco sib txawv. Raws li 512 cov ntaub ntawv bytes yog sib npaug rau 64 DDR3 cov ntaub ntawv tawg, rov ua dua tus example tsim nrog stimulus file muaj 512 sau, 512 nyeem thiab kab hloov pauv rau txhua 64 sau lossis nyeem:

  • 3f_0_0_0000_000_0
  • 3f_0_0_0001_000_0
  • 3f_0_0_0002_000_0
  • 3f_0_0_0003_000_0
  • 3f_0_0_0004_000_0
  • 3f_0_0_0005_000_0
  • 3f_0_0_0006_000_0
  • 3f_0_0_0007_000_0
  • 3f_0_0_0000_000_1
  • 3f_0_0_0001_000_1
  • 3f_0_0_0002_000_1
  • 3f_0_0_0003_000_1
  • 3f_0_0_0004_000_1
  • 3f_0_0_0005_000_1
  • 3f_0_0_0006_000_1
  • 3f_0_0_0007_000_1

Thaum kawg ntawm qhov simulation koj yuav pom tias kev siv tsheb npav yog nyob ntawm 77 feem pua. Xilinx DDR2 MIG 7 Performance Estimation-fig-24

Daim duab 11: Performance Statistics rau 512 sau thiab 512 nyeem – Kab hloov rau 64 sau los yog nyeem. 

Tam sim no koj tuaj yeem siv cov kev paub uas tau kawm hauv ntu ua ntej los txhim kho qhov ua tau zoo. Nrog ib view siv tag nrho cov tsev txhab nyiaj es tsis txhob hloov cov kab, hloov qhov chaw nyob qauv hloov lub txhab nyiaj raws li qhia hauv qab no.
Qhov no yog sib npaug rau qhov teeb tsa ROW_BANK_Column hauv lub cim xeeb chaw nyob chaw nyob hauv MIG GUI.

  • 3f_0_0_0000_000_0
  • 3f_0_1_0000_000_0
  • 3f_0_2_0000_000_0
  • 3f_0_3_0000_000_0
  • 3f_0_4_0000_000_0
  • 3f_0_5_0000_000_0
  • 3f_0_6_0000_000_0
  • 3f_0_7_0000_000_0
  • 3f_0_0_0000_000_1
  • 3f_0_1_0000_000_1
  • 3f_0_2_0000_000_1
  • 3f_0_3_0000_000_1
  • 3f_0_4_0000_000_1
  • 3f_0_5_0000_000_1
  • 3f_0_6_0000_000_1
  • 3f_0_7_0000_000_1

Thaum kawg ntawm kev simulation koj yuav pom tias yav dhau los 77 feem pua ​​​​tsheb npav siv tam sim no yog 87! Xilinx DDR2 MIG 7 Performance Estimation-fig-25

Yog tias koj tseem xav tau kev ua haujlwm siab dua, koj tuaj yeem mus rau cov pob ntawv loj ntawm 1024 lossis 2048 bytes, lossis xav txog phau ntawv hloov tshiab.

Nco tseg: Xilinx tsis txhawb kom bypassing controller refresh raws li peb tsis paub tseeb tias koj yuav tuaj yeem ua tau raws li Jedec nws pib refresh lub sijhawm uas cuam tshuam rau cov ntaub ntawv kev ntseeg siab.
Los ntawm tus maub los sab koj tuaj yeem hloov nBANk_MACH thiab pom kev txhim kho hauv kev ua haujlwm.
Txawm li cas los xij, qhov no yuav cuam tshuam rau koj lub sijhawm tsim, thov xa mus rau (Xilinx Teb 36505) rau cov ntsiab lus ntawm nBANk_MACHXilinx DDR2 MIG 7 Performance Estimation-fig-26

Qhib lub core_name_mig_sim.v file thiab hloov cov tsis nBANK_MACHS los ntawm 4 mus rau 8 thiab rov ua dua qhov simulation. Yuav kom muaj tus nqi parameter coj los siv rau hauv kho vajtse, koj yuav tsum hloov kho core_name_mig.v file.
Kuv siv tib tus qauv uas peb tau txais 87% kev siv tsheb npav (daim duab-12).
Nrog nBANK_MACHS teem rau 8, qhov ua tau zoo yog tam sim no 90%. Xilinx DDR2 MIG 7 Performance Estimation-fig-27

Kuj ua kom nco ntsoov tias ½ thiab ¼ cov tswj tsis zoo cuam tshuam rau kev ua haujlwm vim lawv latencies.
Rau example, txij li thaum peb tsuas tuaj yeem xa cov lus txib txhua 4 CK cycles muaj qee zaum ntxiv padding thaum ua raws li qhov tsawg kawg nkaus DRAM sij hawm specs, uas tuaj yeem txo qhov ua tau zoo ntawm qhov kev xav.
Sim tawm cov maub los sib txawv kom pom ib qho uas haum rau koj qhov kev ua tau zoo.

Cov ntaub ntawv

  1. Zynq-7000 AP SoC thiab 7 Series FPGAs MIS v2.3 [UG586]
  2. Xilinx MIG Solution Center http://www.xilinx.com/support/answers/34243.html

Kev kho keeb kwm
13/03/2015 – Thawj tso tawm

Rub tawm PDF: Xilinx DDR2 MIG 7 Performance Estimation Guide

Cov ntaub ntawv

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