Xilinx DDR2 MIG 7 Ta'iala Fa'atatau o Galuega
Fa'amatalaga Taua: O lenei PDF e mafai ona la'u mai o se Fa'amaumauga o Tali ua tu'uina atu e fa'aleleia atili ai lona fa'aogaina ma le faitau. E taua le matauina o Tali Faamaumauga e Web-fa'avae mataupu e fa'afou fa'afou pe a maua fa'amatalaga fou. Ua faamanatu atu ia te oe e asiasi i le Xilinx Technical Support Webnofoaga ma toeview (Xilinx Tali 63234) mo le lomiga lata mai o lenei Tali.
Folasaga
Ona o le auala e fausia ai le DDR2 ma le DDR3 manatuaga ma le MIG 7 faʻasologa o le pule, e le saʻo le faʻatinoga.
E manaʻomia se malamalama i le tele o Jedec Timing parameters ma le controller Architecture, ma e te manaʻomia le faʻatinoina o faʻataʻitaʻiga e maua ai faʻatatau.
O le mataupu faavae lautele mo le fuafuaina o le faatinoga e tutusa ae o lenei pepa e maua ai se auala faigofie e maua ai le lelei e faʻaaoga ai le MIG example mamanu ma le fesoasoani a le nofoa suʻega ma faʻamalosi files fa'apipi'i iinei.
Fua lelei Bandwidth
O le pasi fa'amaumauga a le DRAM e na'o le pa'u o le faitau ma le tusitusi e na'o le fa'ato'a fa'ato'a pito i luga ma fa'aitiitia ai le fua fa'atatau o fa'amaumauga.
O nai example tau o luga o le:
- taimi muamua totogi e maua ai laina i le faletupe lava e tasi (Access address e le o i le laina tutusa-itulau hit)
- tusi le taimi toe faaleleia e sui mai le tusitusi i le faitau avanoa
- le taimi e liliu ai pasi e sui mai le faitau i le tusitusi avanoa
Lelei Bandwidth = Peak Bandwidth * Lelei
MIG Design Generation
Va'ai ile UG586 Mataupu 1 mo fa'amatalaga la'asaga ta'itasi ile MIG IP ma example fausiaina o mamanu.
A'o le'i faia le MIG 7 Series performance simulation, fai mea nei ina ia mautinoa o lo'o lelei lau si'osi'omaga fa'atusa. Tatala le MIG exampLe mamanu ma faʻafanua faletusi talafeagai, faʻatautaia le faʻataʻitaʻiga, ma faʻamautinoa e mafai ona e vaʻai i le feʻau "ua pasia le suʻega" i le tusitusiga.
Ina ia faʻaalia le tafe ua ou faia se MIG IP mo xc7vx690tffg1761-2 ma faʻaogaina le exampmamanu.
E lua mea e tatau ona maitauina o fa'amatalaga tuatusi manatua ma fa'asologa o fa'afanua o tuatusi manatua.
Mo example, ua ou filifilia MT41J128M8XX-125 i lalo o le vaega manatua e toulu i lalo filifiliga.
Mo le vaega manatua filifilia mai le Ata-1, laina = 14, koluma = 10 ma faletupe = 3, o lea app_addr_width = laina + koluma + faletupe + tulaga = 28 
E mafai ona e filifilia le BANK_ROW_COLUMN po'o le ROW BANK Column.
Ua ou tuua le ROW BANK Column o le fa'asologa o tuatusi fa'aletonu.
Example mamanu Fa'ata'ita'iga fa'atasi ma le nofoa su'ega synthesizable
I lalo o le faʻatulagaina o faʻataʻitaʻiga, filifili QuestaSim/ModelSim Simulator ma suʻesuʻe ile nofoaga o faletusi tuʻufaʻatasia.
Mo faʻamatalaga e uiga i le faʻasino atu i se vaega lona tolu o meafaigaluega faʻapipiʻi ala, filifilia o le simulator sini, ma faʻapipiʻiina ma faʻafanua faletusi, e mafai ona e vaʻai ile (UG900) Vivado Design Suite User Guide Logic Simulation
Faʻataʻitaʻi le faʻataʻitaʻiga e ala i le GUI (Kiliki le Run Simulation Tab i le pule o le poloketi) ma ia mautinoa e te vaʻai i le savali "suʻega pasi" i le tusitusiga.
Fa'ata'ita'iga Fa'atinoga RTL suiga
- Kiliki taumatau i le puna puna, filifili "faʻaopoopo pe fatuina puna faʻataʻitaʻiga", ma suʻesuʻe i le mig7_perfsim_traffic_generator.sv file ma kiliki uma e faaopoopo ai.
- Kiliki taumatau i le puna puna, filifili "faʻaopoopo pe fatuina puna faʻataʻitaʻiga", suʻesuʻe i le perfsim_stimulus.txt, ma kiliki le maeʻa e faʻaopoopo ai.
- Fa'amatala le example_top instantiation i le sim_tb_top.v file.
- Faʻaopoopo i lalo laina RTL ile sim_tb_top,v
- localparam APP_ADDR_WIDTH = 28;
- localparam APP_DATA_WIDTH = 64;
- localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
- localparam MEM_ADDR_ORDER = “BANK_ROW_COLUMN”;
- localparam BANK_WIDTH = 3;
- localparam RANK_WIDTH = 1;
- uaea [APP_ADDR_WIDTH-1:0] c0_ddr3_app_addr;
- uaea [2:0] c0_ddr3_app_cmd;
- uaea c0_ddr3_app_en;
- uaea [APP_DATA_WIDTH-1:0] c0_ddr3_app_wdf_data;
- uaea c0_ddr3_app_wdf_end;
- uaea [APP_MASK_WIDTH-1:0] c0_ddr3_app_wdf_mask;
- uaea c0_ddr3_app_wdf_wren;
- uaea [APP_DATA_WIDTH-1:0] c0_ddr3_app_rd_data;
- uaea c0_ddr3_app_rd_data_end;
- uaea c0_ddr3_app_rd_data_valid;
- uaea c0_ddr3_app_rdy;
- uaea c0_ddr3_app_wdf_rdy;
- uaea c0_data_compare_error;
- uaea ui_clk;
- uaea ui_clk_sync_rst;
- uaea app_sr_req = 0;
- uaea app_ref_req = 0;
- uaea app_zq_req =0;
- uaea c0_app_wdf_mask =0;
FPGA Memory Controller instantiation
mig_7series_0_mig u_mig_7series_0_mig (
// Taulaga fa'aoga mafaufau
- .ddr3_addr (ddr3_addr_fpga),
- .ddr3_ba (ddr3_ba_fpga),
- .ddr3_cas_n (ddr3_cas_n_fpga),
- .ddr3_ck_n (ddr3_ck_n_fpga),
- .ddr3_ck_p (ddr3_ck_p_fpga),
- .ddr3_cke (ddr3_cke_fpga),
- .ddr3_ras_n (ddr3_ras_n_fpga),
- .ddr3_reset_n (ddr3_reset_n),
- .ddr3_we_n (ddr3_we_n_fpga),
- .ddr3_dq (ddr3_dq_fpga),
- .ddr3_dqs_n (ddr3_dqs_n_fpga),
- .ddr3_dqs_p (ddr3_dqs_p_fpga),
- .init_calib_complete (init_calib_complete),
- .ddr3_cs_n (ddr3_cs_n_fpga),
- .ddr3_dm (ddr3_dm_fpga),
- .ddr3_odt (ddr3_odt_fpga),
// Taulaga fa'aoga fa'aoga
- .app_addr (c0_ddr3_app_addr),
- .app_cmd (c0_ddr3_app_cmd),
- .app_en (c0_ddr3_app_en),
- .app_wdf_data (c0_ddr3_app_wdf_data),
- .app_wdf_end (c0_ddr3_app_wdf_end),
- .app_wdf_wren (c0_ddr3_app_wdf_wren),
- .app_rd_data (c0_ddr3_app_rd_data),
- .app_rd_data_end (app_rd_data_end),
- .app_rd_data_valid (c0_ddr3_app_rd_data_valid),
- .app_rdy (c0_ddr3_app_rdy),
- .app_wdf_rdy (c0_ddr3_app_wdf_rdy),
- .app_sr_req (app_sr_req),
- .app_ref_req (app_ref_req),
- .app_zq_req (app_zq_req),
- .app_sr_active (app_sr_active),
- .app_ref_ack (app_ref_ack),
- .app_zq_ack (app_zq_ack),
- .ui_clk (ui_clk),
- .ui_clk_sync_rst (ui_clk_sync_rst),
- .app_wdf_mask (c0_ddr3_app_wdf_mask),
// Taulaga Uati System
- .sys_clk_i (sys_clk_i),
// Taulaga Uati Fa'asino
- .clk_ref_i (clk_ref_i),
- .sys_rst (sys_rst)
- );
Fa'atinoga o feoaiga afi afi instantiation
mig7_perfsim_traffic_generator#
(
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.tCK (tCK ),
.ADDR_WIDTH (APP_ADDR_WIDTH)
)
u_traffic_gen
(
.clk (ui_clk ),
.rst (ui_clk_sync_rst ),
.init_calib_complete (init_calib_complete),
.cmp_error (c0_data_compare_error),
.app_wdf_rdy (c0_ddr3_app_wdf_rdy ),
.app_rd_data_valid (c0_ddr3_app_rd_data_valid),
.app_rd_data (c0_ddr3_app_rd_data ),
.app_rdy (c0_ddr3_app_rdy),
.app_cmd (c0_ddr3_app_cmd ),
.app_addr (c0_ddr3_app_addr ),
.app_en (c0_ddr3_app_en ),
.app_wdf_mask (c0_ddr3_app_wdf_mask),
.app_wdf_data (c0_ddr3_app_wdf_data),
.app_wdf_end (c0_ddr3_app_wdf_end ),
.app_wdf_wren (c0_ddr3_app_wdf_wren)
);
- 5. Suia APP_ADDR_WIDTH, APP_DATA_WIDTH, RANK_WIDTH ma BANK_WIDTH e tusa ai ma lau filifiliga vaega manatua.
E mafai ona maua tau mai le _mig.v file. - Ole igoa fa'ailoga lanu samasama mig_7series_0_mig e mafai ona fesuia'i e fa'atatau ile igoa ole vaega ile taimi ole fa'atupuina ole IP, fa'amaonia pe ua e filifilia se isi igoa ma suia e tusa ai.
- O le taimi lava e maua ai le IP tatala le _mig.v file ma su'esu'e so'o se fesuiaiga i igoa faailo LHS ma faasa'o.
- app_sr_req, app_ref_req ma app_zq_req e tatau ona amata i le 0.
- E pei o example_top.v o loʻo faʻaalia ma fou files ua faaopoopo, masalo o le ae vaai i le "?" i tafatafa o le
mig_7series_0_mig.v file i lalo o punaoa faʻataʻitaʻiga.
Ia faafanua le sa'o file, kiliki taumatau mig_7series_0_mig.v, filifili "Add Sources", Su'esu'e i
/mig_7series_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl
ma fa'aopoopo le mig_7series_0_mig_sim.v file. - Afai e te vaʻai "?" mo le faavae files, fa'aopoopo uma RTL files i le uati, pule, ip_top, phy ma UI faila.
- A uma loa suiga RTL ma mea uma e mana'omia files ua fa'aopoopoina i lau Simulation Sources, E tatau ona tutusa le Fa'atonu ma le Ata 5.
O le files fa'ailoga i le mumu e fou fa'aopoopo, ma le "?" o lo'o fa'amoemoeina ile fa'aogaina ole ECC ona ole fa'atonuga manatua ua filifilia ua fa'aletonu le filifiliga ECC.
Fa'aosofia File Fa'amatalaga
O faʻataʻitaʻiga taʻitasi e 48 bits ma o loʻo faʻamatalaina i Ata 6-1 e oʻo i le 6-4.
Fa'ailoga o le tuatusi (Tuafa [35:0])
O le tuatusi o loʻo faʻailogaina i le faʻaosofia e pei o le Ata 7-1 i le Ata 7-6. E mana'omia uma ona fa'aulu i totonu ole fa'ailoga hexadecimal. O fanua tuatusi uma o se lautele e vaevae i le fa e ulufale ai i le faʻasologa o le hexadecimal. O le nofoa su'ega e na'o le auina atu o vaega mana'omia o se fanua tuatusi i le Pule Fa'amanatu.
Mo exampO lea, i se faatulagaga e valu faletupe, e na'o Bank Bits [2:0] e auina atu i le Pule Fa'amanatu ma e le amana'ia vaega o totoe. O vaega fa'aopoopo mo se fa'afanua tuatusi ua tu'uina atu mo oe e tu'u ai le tuatusi i se fa'asologa o le hexadecimal.
E tatau ona e fa'amaonia le tau o lo'o tu'uina e fetaui ma le lautele o se fa'atonuga.
- Tulaga o le Koluma (Koluma[11:0]) – O le tuatusi o le Column i le faʻaosofia e tuʻuina atu i le maualuga o le 12 bits, ae e tatau ona e faʻatalanoaina lenei mea e faʻatatau i le laina lautele o le koluma faʻatulagaina i lau mamanu.
- Tuatusi o Laila (Laula[15:0]) – O le tuatusi laina i le faʻaosofia e tuʻuina atu i le maualuga o le 16 bits, ae e tatau ona e faʻatalanoaina lenei mea e faʻavae i luga o le laina laina laina faʻatulagaina i lau mamanu.
- tuatusi o le Faletupe (Bank[3:0]) – O le tuatusi faletupe i totonu o le faʻamalosi e tuʻuina atu i le maualuga o le fa bits, ae e tatau ona e faʻatalanoaina lenei mea e faʻavae i luga o le faletupe lautele parakalafa seti i lau mamanu.
- Tulaga Tulaga (Fa'ailoga[3:0]) – Tulaga tulaga i le stimulus e tuʻuina atu i le maualuga o le fa bits, ae e tatau ona e faʻatalanoaina lenei mea e faʻavae i luga o le faʻasologa o le lautele lautele seti i lau mamanu.
O le tuatusi o loʻo faʻapipiʻiina e faʻavae i luga o le pito i luga MEM_ADDR_ORDER parameter ma auina atu i le faʻaoga faʻaoga
Toe fai Poloaiga (Toe Poloaiga [7:0])
Ole fa'atonuga toe fai ole numera ole taimi e toe fai ai le fa'atonuga ile User Interface. O le tuatusi mo ta'i fai ta'itasi e fa'aopoopo i le 8. O le aofa'i maualuga o le toe fai e 128.
E le siakiina e le nofoa su'ega le tuaoi o koluma ma e afifi pe a o'o i le pito maualuga o le koluma i le taimi o fa'aopoopoga.
O le 128 Poloaiga e faʻatumu ai le itulau. Mo so'o se tuatusi koluma e ese mai i le 0, o le toe faia o le numera o le 128 e iu ina laasia le tuaoi o koluma ma afifi solo i le amataga o le tuatusi koluma.
Fa'aoga pasi
Ole fa'aogaina ole pasi e fa'atatau ile User Interface e fa'atatau ile aofa'iga ole Faitau ma Tusitusi ma fa'aaoga le fa'atusa lea:
- BL8 e fa fa'asologa o le uati manatua
- end_of_stimulus o le taimi e faia uma ai poloaiga.
- calib_done o le taimi lea e fai ai le faʻavasegaina.
Example Mamanu
O nei exampe fa'avae ile MEM_ADDR_ORDER seti ile BANK_ROW_COLUMN.
Mamanu Faitau Tasi
00_0_2_000F_00A_1 – O lenei mamanu o se faitauga tasi mai le koluma lona 10, laina lona 15, ma le faletupe lona lua.
Mamanu Tusitala Tasi
00_0_1_0040_010_0 – O le mamanu lenei o se tusi e tasi i le koluma lona 32, laina lona 128, ma le faletupe muamua.
Nofofua Tusi ma Faitau i le tuatusi e tasi
00_0_2_000F_00A_0 – O lenei mamanu o se tusi tasi i le koluma 10, laina 15, ma le faletupe lona lua.
00_0_2_000F_00A_1 – O lenei mamanu o se faitauga tasi mai koluma lona 10, laina lona 15, ma le faletupe lona lua
Tele Tusitusi ma Faitau ma Tuatusi Tusa
0A_0_0_0010_000_0 – E fetaui lea ma le 10 tusitusiga ma le tuatusi e amata mai le 0 i le 80 lea e mafai ona vaʻaia i le koluma.
0A_0_0_0010_000_1 – E fetaui lea ma le 10 faitau ma le tuatusi e amata mai le 0 i le 80 lea e mafai ona vaʻaia i le koluma.
A'ai Itulau A'o Tusitala
0A_0_2_000F_3F8_0 – E fetaui lea ma le 10 tusitusiga ma le tuatusi koluma ua afifi i le amataga o le itulau pe a uma le tasi tusi.
Fa'ata'ita'iina o le Fa'atinoga o Ta'avale Ta'avale
I le taimi nei ua maeʻa oe ile MIG example mamanu fa'atusa. O lona uiga ua sauni lau faʻatulagaina faʻataʻitaʻiga, ua e faia faʻataʻitaʻiga faʻataʻitaʻiga suiga RTL, o le faʻasologa fou o faʻataʻitaʻiga e saʻo ma ua e malamalama i mamanu faʻaosofia. Toe tamoʻe le faʻataʻitaʻiga ma le 16 tusitusi ma faitau ile perfsim_stimulus.txt.
Fai tamo'e uma, fa'atali se'ia fa'ailoa mai le fa'ailoga init_calib_complete, ma o le a mafai ona e va'ai i le numera fa'atulagaina o tusi ma faitau. Ona taofi lea o le simulation. 
A faʻamalosia oe e tuʻu le faʻataʻitaʻiga, filifili Leai ma alu i le faʻamalama faʻamatalaga e mafai ai ona e vaʻai i fuainumera faʻatinoga. 
Afai e te filifilia "tuu le fa'ata'ita'iga" o le a tusia fa'amaumauga o fa'atinoga i a file igoa mig_band_width_output.txt o loʻo i totonu o le sim_1/behave faila.
Example ala fa'atonu:-
/mig_7series_0_example_perf_sim\mig_7series_0_example.sim/sim_1/behav
Atonu e te taumānatu pe aisea ua fai ai le pasenetage fa'aoga pasi o so'o se 29. Toe fa'asolo le fa'ata'ita'iga fa'atasi ma tulaga tutusa IP ae na'o le suia o le fa'aosofia. file i le 256 tusitusi ma le 256 faitau
ff_0_0_0000_000_0
ff_0_0_0000_000_1
O le a e va'ai nei i le pasenetage pei o le 85, o lona uiga o le DDR3 e sili atu le faʻaogaina o pasi mo le umi o le faasologa o tusitusiga ma faitau faʻalavelave. 
Auala lautele e Fa'aleleia ai Fa'atinoga
O mea e aʻafia ai le lelei e mafai ona vaevaeina i ni vaega se lua:
- Manatu Fa'apitoa
- Pule Fa'apitoa
Fa'ata 9 e tu'uina atu ia te oe se fa'asiliview o faaupuga e manatua faapitoa.
E le pei o SRAMs ma Block Memories DDR2 poʻo le DDR3 faʻatinoga e le naʻo le maualuga o faʻamaumauga.
E fa'alagolago i le tele o taimi, e aofia ai:
- tRCD: Fa'atuai o Poloaiga (po'o le tuai i le tuai).
- tCAS(CL): Tu'u le fa'aupuga o le koluma.
- tRP: Fa'atuai o le laina muamua.
- tRAS: Row Active Time (faagaioi e muai sui).
- tRC: Taimi ta'amilosaga laina. tRC = tRAS + tRP
- tRAC: Fa'atuai le avanoa o Radom. tRAC = tRCD + tCAS
- tCWL: Cas tusitusi leo.
- tZQ: ZQ taimi fa'avasega.
- tRFC: Taimi Ta'amilosaga Fa'afou laina
- tWTR: Tusi e Faitau le tuai. Fa'asologa tusitusi mulimuli e Faitau le taimi o le poloaiga.
- tWR: Tusi le Taimi Toe Fa'aleleia. Fa'amatalaga tusitusia mulimuli i le taimi o le Precharge
Ole taimi ole lisi uma e fa'atatau ile ituaiga manatua e fa'aaogaina ma le vaega ole manatua ole vasega saoasaoa.
E mafai ona maua nisi fa'amatalaga i fa'amatalaga ma taimi fa'apitoa i le DDR2 DDR3 JEDEC po'o so'o se fa'amaumauga o masini manatua.
E fa'alagolago tele le lelei ile auala e maua ai le manatua. O fa'asologa o tuatusi eseese e maua ai i'uga lelei eseese.
Fa'asili taimi ole manatua
- Taimi fa'agaoioia ma le taimi muamua pe a sui i faletupe fou / laina po'o le suia o laina i totonu o le faletupe e tasi.- O lea afai e te fa'aitiitia le suiga o laina, e mafai ona aveese tRCD ma tRP.
- Auina atu fa'aauau le tusitusi pe faitau fa'atonuga - Fa'atumauina taimi tCCD.
- Fa'aitiiti le tusitusi e faitau ma faitau e tusi le suiga o le poloaiga - Tusi le taimi toe faʻaleleia e sui ai le faitau avanoa, taimi liliu pasi e sui mai le faitau i le tusitusi
- Seti se vaitaimi fa'afou talafeagai.
- E mana'omia e DDR3 SDRAM ta'amilosaga Fa'afou i se vaeluaga fa'avaitaimi o tREFI.
- Ole maualuga ole 8 fa'atonuga Fa'afouina e mafai ona tu'uina atu muamua ("toso i totonu"). E le fa'aitiitia ai le aofa'i o fa'afouga, ae o le va'ava'a maualuga i le va o fa'atonuga Fa'afouina e lua e fa'atapula'aina i le 9 × tREFI.
- Fa'aaoga uma faletupe - E sili ona lelei se faiga fa'afeso'ota'i talafeagai.
- laina-Bank-Koluma: Mo se fefaʻatauaiga o loʻo tupu i luga o se avanoa faʻasologa faʻasologa, e otometi lava ona tatalaina e le autu le laina tutusa i le isi faletupe o le masini DRAM e faʻaauau ai le fefaʻatauaiga pe a oʻo i le pito o se laina o loʻo i ai nei. E fetaui lelei i talosaga e mana'omia ai le fa'asa'oina o fa'amaumauga lapopo'a i fa'asologa fa'asologa o nofoaga.
- Faletupe-Laula-Koluma: A laasia se tuaoi laina, o le laina o loʻo i ai nei o le a tapunia ma o le a tatalaina le isi laina i totonu o le faletupe lava e tasi. MSB ose tuatusi faletupe, e mafai ona fa'aoga e fesuia'i mai faletupe eseese. E talafeagai mo fefaʻatauaiga pupuu, sili atu faʻafuaseʻi i le tasi poloka o manatua mo se vaitaimi ona oso ai lea i le isi poloka (faletupe)
- Pa'u Umi
- BL 8 o loʻo lagolagoina mo le DDR3 ile 7 faʻasologa. BC4 o loʻo i ai se tulaga maualalo maualalo e itiiti ifo i le 50%. E mafua ona o le taimi o le faʻatinoina o le BC4 e tutusa ma le BL8. O faʻamatalaga e naʻo le ufiufi i totonu o le vaega.
- I tulaga e te le mana'o e tusi atoa le pa'u, e mafai ona mafaufau i le mask data po'o le tusitusi-ina ua uma ona faitau.
- Seti se vaeluaga ZQ talafeagai (DDR3 Na'o)
E auina atu e le pule le ZQ Short (ZQCS) ma le ZQ Long (ZQCL) Poloaiga Fa'atonu.- Mulimuli i le DDR3 Jedec Standard
- ZQ Calibration o loʻo talanoaina i le vaega 5.5 o le JEDEC Spec JESD79-3 DDR3 SDRAM Standard
- O le ZQ Calibration e fa'avasega le On Die Termination (ODT) i taimi masani e fa'atatau mo suiga i VT.
- O lo'o iai le fa'atatau ile bank_common.v/vhd
- Parameter Tzqcs e fuafua le fua o le faʻatonuga o le ZQ Calibration e lafo i le manatua
- e mafai ona fa'amalo le fata ma lafo ma le lima e fa'aaoga ai le app_zq_req, e tutusa ma le lafo ma le lima o le Refresh.
Va'ai ile (Xilinx Tali 47924) mo fa'amatalaga.
Pule Sili
- Faitau Fa'avaitaimi - Va'ai ile (Tali Xilinx 43344) mo fa'amatalaga.
- Aua le suia le vaitaimi o le faitau
- Fa'ase'e faitauga fa'avaitaimi a'o tusitusi ma tu'u atu le aofa'i o faitauga na misi a'o le'i faitau moni
- Toe fa'atonu - Fa'asino (Tali Xilinx 34392) mo fa'amatalaga.
Mo le User ma le AXI Interface designs e sili atu le fa'aogaina o lenei mea.- Toe fa'atonu o le fa'atonuga lea e va'ava'ai atu i luma le tele o fa'atonuga ma suia le fa'atonuga o le fa'atonuga a le tagata fa'aoga e fai ai tulafono e le manatua e le fa'aogaina le bandwidth aoga. O le fa'atinoga e feso'ota'i fo'i ma le fa'asologa moni o feoaiga.
- Fa'avae i luga o le fa'asologa o le tuatusi, toe fa'atonu e fesoasoani e fa'ase'e le totogi muamua ma fa'aagaoioia fa'atonuga ma fa'au'u ai le tRCD ma le tRP i le lautele o fa'amaumauga.
- Taumafai e fa'aopoopo le numera o Mesinia Faletupe.
- O le tele o fa'atonuga a le pule o lo'o i totonu o masini faletupe ma e fetaui ma faletupe DRAM
- O se masini faletupe tu'uina atu e pulea se faletupe DRAM e tasi i so'o se taimi.
- O le fa'atonuina o masini faletupe e malosi ma e le mana'omia le i ai o se masini faletupe mo faletupe fa'aletino taitasi.
- E mafai ona fa'atulagaina masini faletupe, ae o se fefa'ataua'iga i le va o le eria ma le fa'atinoga.
- Ole numera fa'atagaina o masini faletupe e mai le 2-8.
- Ona o le faaletonu, 4 Bank Machines ua faʻapipiʻiina e ala i le RTL parameters.
- Ina ia suia Bank Machines, mafaufau i le parakalafa nBANK_MACHS = 8 o loʻo i totonu memc_ui_top Example mo 8 Bank Machines – nBANK_MACHS = 8
Ua e nofouta nei i mea e aafia ai le faatinoga.
Mafaufau i se talosaga i luga e avatu ia te oe le 512 data bytes i le pepa ma e te manaʻomia e teu i latou i nofoaga eseese manatua. E pei o 512 data bytes e tutusa ma 64 DDR3 faʻamaumauga faʻafuaseʻi, toe taʻavale le example mamanu ma se faaosofiaga file o lo'o i ai le 512 tusi, 512 faitau ma laina fesuia'i mo 64 tusitusiga pe faitau:
- 3f_0_0_0000_000_0
- 3f_0_0_0001_000_0
- 3f_0_0_0002_000_0
- 3f_0_0_0003_000_0
- 3f_0_0_0004_000_0
- 3f_0_0_0005_000_0
- 3f_0_0_0006_000_0
- 3f_0_0_0007_000_0
- 3f_0_0_0000_000_1
- 3f_0_0_0001_000_1
- 3f_0_0_0002_000_1
- 3f_0_0_0003_000_1
- 3f_0_0_0004_000_1
- 3f_0_0_0005_000_1
- 3f_0_0_0006_000_1
- 3f_0_0_0007_000_1
I le faaiuga o le faʻataʻitaʻiga o le a e vaʻaia ai o le faʻaaogaina o pasi e 77 pasene. 
Ata 11: Fa'amaumauga o Fa'atinoga mo le 512 tusitusi ma le 512 faitau - Suiga laina mo le 64 tusitusi pe faitau.
E mafai nei ona e faʻaogaina le malamalama na aʻoaʻoina i le vaega muamua e faʻaleleia ai le lelei. Faatasi ai ma le a view i le fa'aogaina o faletupe uma nai lo le suia o le laina, sui le mamanu tuatusi e sui ai le faletupe e pei ona fa'aalia i lalo.
E tutusa lea ma le setiina o le ROW_BANK_Column i le faafanua o le tuatusi manatua i le MIG GUI.
- 3f_0_0_0000_000_0
- 3f_0_1_0000_000_0
- 3f_0_2_0000_000_0
- 3f_0_3_0000_000_0
- 3f_0_4_0000_000_0
- 3f_0_5_0000_000_0
- 3f_0_6_0000_000_0
- 3f_0_7_0000_000_0
- 3f_0_0_0000_000_1
- 3f_0_1_0000_000_1
- 3f_0_2_0000_000_1
- 3f_0_3_0000_000_1
- 3f_0_4_0000_000_1
- 3f_0_5_0000_000_1
- 3f_0_6_0000_000_1
- 3f_0_7_0000_000_1
I le faaiuga o le faʻataʻitaʻiga o le a e vaʻaia o le 77 Percent Bus Utilization muamua ua 87 nei! 
Afai e te manaʻomia pea le faʻaleleia atili, e mafai ona e alu mo lapoʻa lapoa o le 1024 poʻo le 2048 bytes, pe mafaufau i se faʻafouina tusi.
Fa'aaliga: E le fa'amalosia e Xilinx le fa'amalo o le fa'afouina o le pule aua matou te le mautinoa pe o le a mafai ona e fa'afeiloa'i i le taimi o le fa'afouina o le ta'avale a Jedec e a'afia ai le fa'atuatuaina o fa'amaumauga.
Mai le itu pule e mafai ona e suia le nBANk_MACH ma vaʻai i le faʻaleleia atili o le faʻatinoga.
Peita'i, e ono a'afia ai lau taimi fa'atulagaina, fa'amolemole va'ai (Tali Xilinx 36505) mo fa'amatalaga ile nBANk_MACH
Tatala le core_name_mig_sim.v file ma suia le tapulaʻa nBANK_MACHS mai le 4 i le 8 ma toe faʻatautaia le faʻataʻitaʻiga. Ina ia faʻaaogaina le tau faʻamaufaʻailoga i meafaigaluega, e tatau ona e faʻafouina le core_name_mig.v file.
Na ou faʻaogaina le mamanu tutusa lea na matou maua ai le 87% faʻaoga pasi (ata -12).
Faatasi ai ma le nBANK_MACHS ua seti i le 8, o le lelei ua 90% nei. 
Fa'ailoa fo'i e fa'apea o le ½ ma le ¼ fa'atonu e a'afia le lelei ona o latou fa'aletonu.
Mo example, talu ai e mafai ona tatou auina atu poloaiga uma 4 CK taamilosaga o loʻo i ai i nisi taimi faʻaopoopoga faʻapipiʻi pe a pipii i le DRAM taimi faʻapitoa faʻamatalaga, lea e mafai ona faʻaitiitia ai le lelei mai le faʻataʻitaʻiga.
Fa'ata'ita'i isi fa'atonu e su'e le mea e fetaui ma lou mana'oga lelei.
Fa'asinomaga
- Zynq-7000 AP SoC ma 7 Fa'asologa FPGA MIS v2.3 [UG586]
- Xilinx MIG Solution Center http://www.xilinx.com/support/answers/34243.html
Toe Iloilo Tala'aga
13/03/2015 – Fa'asalalauga muamua
La'uina le PDF: Xilinx DDR2 MIG 7 Ta'iala Fa'atatau o Galuega
